[PATCH 00/11] drm/i915/cdclk: Declutter CDCLK code

[PATCH 00/11] drm/i915/cdclk: Declutter CDCLK code

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Declutter the CDCLK code a bit by moving a all the
foo_min_cdclk() things out into their respective files.

And I also reworked the "pixels per clock" and
guardband handling so that we don't have to repeat
essentially the same platform if-ladder two times.

TODO: the dsi and audio min_cdclk stuff could perhaps
      be more cleanly abstracted into some kind of
      encoder->min_cdlk() thing, but haven't really
      given this more than a cursory thought...

Ville Syrjälä (11):
  drm/i915: Introduce HAS_DOUBLE_WIDE()
  drm/i915/cdclk: Extract intel_cdclk_guardband() and intel_cdclk_ppc()
  drm/i915/cdclk: Extract hsw_ips_min_cdclk()
  drm/i915/cdclk: Extract intel_audio_min_cdclk()
  drm/i915/cdclk: Factor out has_audio check in intel_audio_min_cdclk()
  drm/i915/cdclk: Extract vlv_dsi_min_cdclk()
  drm/i915/cdclk: Factor out INTEL_OUTPUT_DSI check in
    vlv_dsi_min_cdclk()
  drm/i915/cdclk: Suck the compression_enable check into
    intel_vdsc_min_cdclk()
  drm/i915/cdclk: Drop pointles max_t() usage in intel_vdsc_min_cdclk()
  drm/i915/cdclk: Relocate intel_vdsc_min_cdclk()
  drm/i915/cdclk: Unify cdclk max() parameter order

 drivers/gpu/drm/i915/display/hsw_ips.c        |  16 +-
 drivers/gpu/drm/i915/display/hsw_ips.h        |   6 +-
 drivers/gpu/drm/i915/display/intel_audio.c    |  47 +++++
 drivers/gpu/drm/i915/display/intel_audio.h    |   1 +
 drivers/gpu/drm/i915/display/intel_bw.c       |   2 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    | 175 ++++--------------
 drivers/gpu/drm/i915/display/intel_display.c  |   4 +-
 .../drm/i915/display/intel_display_device.h   |   1 +
 drivers/gpu/drm/i915/display/intel_vdsc.c     |  46 +++++
 drivers/gpu/drm/i915/display/intel_vdsc.h     |   1 +
 drivers/gpu/drm/i915/display/vlv_dsi.c        |  25 +++
 drivers/gpu/drm/i915/display/vlv_dsi.h        |   8 +
 12 files changed, 187 insertions(+), 145 deletions(-)

-- 
2.45.2

[PATCH 01/11] drm/i915: Introduce HAS_DOUBLE_WIDE()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make the code a bit more self documenting by adding
HAS_DOUBLE_WIDE().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c          | 2 +-
 drivers/gpu/drm/i915/display/intel_display.c        | 4 ++--
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 96523526a2c3..6cef3ca3a069 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3462,7 +3462,7 @@ static int intel_compute_max_dotclk(struct intel_display *display)
 		return max_cdclk_freq;
 	else if (IS_CHERRYVIEW(dev_priv))
 		return max_cdclk_freq*95/100;
-	else if (DISPLAY_VER(display) < 4)
+	else if (HAS_DOUBLE_WIDE(display))
 		return 2*max_cdclk_freq*90/100;
 	else
 		return max_cdclk_freq*90/100;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0e6d6c8354ef..9a5102224c59 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2371,7 +2371,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
 	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	/* GDG double wide on either pipe, otherwise pipe A only */
-	return DISPLAY_VER(dev_priv) < 4 &&
+	return HAS_DOUBLE_WIDE(dev_priv) &&
 		(crtc->pipe == PIPE_A || IS_I915G(dev_priv));
 }
 
@@ -3207,7 +3207,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 
 	intel_color_get_config(pipe_config);
 
-	if (DISPLAY_VER(dev_priv) < 4)
+	if (HAS_DOUBLE_WIDE(dev_priv))
 		pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
 
 	intel_get_transcoder_timings(crtc, pipe_config);
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 410f8b33a8a1..ae7a35cf44ca 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -129,6 +129,7 @@ enum intel_display_subplatform {
 #define HAS_DISPLAY(i915)		(DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
 #define HAS_DMC(i915)			(DISPLAY_RUNTIME_INFO(i915)->has_dmc)
 #define HAS_DOUBLE_BUFFERED_M_N(i915)	(DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
+#define HAS_DOUBLE_WIDE(i915)		(DISPLAY_VER(i915) < 4)
 #define HAS_DP_MST(i915)		(DISPLAY_INFO(i915)->has_dp_mst)
 #define HAS_DP20(i915)			(IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
 #define HAS_DPT(i915)			(DISPLAY_VER(i915) >= 13)
-- 
2.45.2

[PATCH 02/11] drm/i915/cdclk: Extract intel_cdclk_guardband() and intel_cdclk_ppc()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We are duplicating the CDCLK guardband and "pixels per clock"
figures in two places. Pull those out into small helpers that
can be used by both places.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 50 +++++++++++-----------
 1 file changed, 26 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 6cef3ca3a069..977fcdaa7372 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2761,23 +2761,34 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
 			"Post changing CDCLK to");
 }
 
+/* pixels per CDCLK */
+static int intel_cdclk_ppc(struct intel_display *display, bool double_wide)
+{
+	return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1;
+}
+
+/* max pixel rate as % of CDCLK (not accounting for PPC) */
+static int intel_cdclk_guardband(struct intel_display *display)
+{
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
+
+	if (DISPLAY_VER(display) >= 9 ||
+	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+		return 100;
+	else if (IS_CHERRYVIEW(dev_priv))
+		return 95;
+	else
+		return 90;
+}
+
 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	struct drm_i915_private *dev_priv = to_i915(display->drm);
+	int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
+	int guardband = intel_cdclk_guardband(display);
 	int pixel_rate = crtc_state->pixel_rate;
 
-	if (DISPLAY_VER(display) >= 10)
-		return DIV_ROUND_UP(pixel_rate, 2);
-	else if (DISPLAY_VER(display) == 9 ||
-		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
-		return pixel_rate;
-	else if (IS_CHERRYVIEW(dev_priv))
-		return DIV_ROUND_UP(pixel_rate * 100, 95);
-	else if (crtc_state->double_wide)
-		return DIV_ROUND_UP(pixel_rate * 100, 90 * 2);
-	else
-		return DIV_ROUND_UP(pixel_rate * 100, 90);
+	return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc);
 }
 
 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
@@ -3452,20 +3463,11 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
 
 static int intel_compute_max_dotclk(struct intel_display *display)
 {
-	struct drm_i915_private *dev_priv = to_i915(display->drm);
+	int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display));
+	int guardband = intel_cdclk_guardband(display);
 	int max_cdclk_freq = display->cdclk.max_cdclk_freq;
 
-	if (DISPLAY_VER(display) >= 10)
-		return 2 * max_cdclk_freq;
-	else if (DISPLAY_VER(display) == 9 ||
-		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
-		return max_cdclk_freq;
-	else if (IS_CHERRYVIEW(dev_priv))
-		return max_cdclk_freq*95/100;
-	else if (HAS_DOUBLE_WIDE(display))
-		return 2*max_cdclk_freq*90/100;
-	else
-		return max_cdclk_freq*90/100;
+	return ppc * max_cdclk_freq * guardband / 100;
 }
 
 /**
-- 
2.45.2

[PATCH 03/11] drm/i915/cdclk: Extract hsw_ips_min_cdclk()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pull the whole BDW IPS min CDCLK stuff into the IPS code
so that all the details around IPS are contained in once
place.

Note that while
- min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
vs.
+ min_cdclk = max(DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95), min_cdclk)
may look different, they are in fact the same because
min_cdclk==crtc_state->pixel_rate at this point in
intel_crtc_compute_min_cdclk() on BDW.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/hsw_ips.c     | 16 +++++++++++++++-
 drivers/gpu/drm/i915/display/hsw_ips.h     |  6 +++---
 drivers/gpu/drm/i915/display/intel_cdclk.c |  5 +----
 3 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index c571c6e76d4a..5a0fc9f2bd6f 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -186,7 +186,7 @@ bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
 	return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
 }
 
-bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
+static bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
@@ -215,6 +215,20 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
 	return true;
 }
 
+int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+
+	if (!IS_BROADWELL(i915))
+		return 0;
+
+	if (!hsw_crtc_state_ips_capable(crtc_state))
+		return 0;
+
+	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
+	return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95);
+}
+
 int hsw_ips_compute_config(struct intel_atomic_state *state,
 			   struct intel_crtc *crtc)
 {
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.h b/drivers/gpu/drm/i915/display/hsw_ips.h
index 35364228e1c1..7af12f88a8ce 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.h
+++ b/drivers/gpu/drm/i915/display/hsw_ips.h
@@ -19,7 +19,7 @@ bool hsw_ips_pre_update(struct intel_atomic_state *state,
 void hsw_ips_post_update(struct intel_atomic_state *state,
 			 struct intel_crtc *crtc);
 bool hsw_crtc_supports_ips(struct intel_crtc *crtc);
-bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
+int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state);
 int hsw_ips_compute_config(struct intel_atomic_state *state,
 			   struct intel_crtc *crtc);
 void hsw_ips_get_config(struct intel_crtc_state *crtc_state);
@@ -42,9 +42,9 @@ static inline bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
 {
 	return false;
 }
-static inline bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
+static inline int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)
 {
-	return false;
+	return 0;
 }
 static inline int hsw_ips_compute_config(struct intel_atomic_state *state,
 					 struct intel_crtc *crtc)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 977fcdaa7372..3103ecab980c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2857,10 +2857,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 		return 0;
 
 	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
-
-	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-	if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
-		min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
+	min_cdclk = max(hsw_ips_min_cdclk(crtc_state), min_cdclk);
 
 	/* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
 	 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
-- 
2.45.2

[PATCH 04/11] drm/i915/cdclk: Extract intel_audio_min_cdclk()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pull the audio min cdclk calculation into a helper and hide
it inside intel_audio.c in order to keep most audio related
details in one place.

The one audio related thing that remains in intel_cdclk.c
is commit 451eaa1a614c ("drm/i915: Bump GLK CDCLK frequency when
driving multiple pipes") but given that's implemented in terms
of the cdclk_state I think it should stay put.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_audio.c | 45 ++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_audio.h |  1 +
 drivers/gpu/drm/i915/display/intel_cdclk.c | 37 +-----------------
 3 files changed, 47 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 32aa9ec1a204..82c45b24417a 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -978,6 +978,51 @@ static void glk_force_audio_cdclk(struct drm_i915_private *i915,
 	drm_modeset_acquire_fini(&ctx);
 }
 
+int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct drm_i915_private *dev_priv = to_i915(display->drm);
+	int min_cdclk = 0;
+
+	/* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
+	 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
+	 * there may be audio corruption or screen corruption." This cdclk
+	 * restriction for GLK is 316.8 MHz.
+	 */
+	if (intel_crtc_has_dp_encoder(crtc_state) &&
+	    crtc_state->has_audio &&
+	    crtc_state->port_clock >= 540000 &&
+	    crtc_state->lane_count == 4) {
+		if (DISPLAY_VER(display) == 10) {
+			/* Display WA #1145: glk */
+			min_cdclk = max(316800, min_cdclk);
+		} else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) {
+			/* Display WA #1144: skl,bxt */
+			min_cdclk = max(432000, min_cdclk);
+		}
+	}
+
+	/*
+	 * According to BSpec, "The CD clock frequency must be at least twice
+	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
+	 */
+	if (crtc_state->has_audio && DISPLAY_VER(display) >= 9)
+		min_cdclk = max(2 * 96000, min_cdclk);
+
+	/*
+	 * "For DP audio configuration, cdclk frequency shall be set to
+	 *  meet the following requirements:
+	 *  DP Link Frequency(MHz) | Cdclk frequency(MHz)
+	 *  270                    | 320 or higher
+	 *  162                    | 200 or higher"
+	 */
+	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
+	    intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
+		min_cdclk = max(crtc_state->port_clock, min_cdclk);
+
+	return min_cdclk;
+}
+
 static unsigned long i915_audio_component_get_power(struct device *kdev)
 {
 	struct intel_display *display = to_intel_display(kdev);
diff --git a/drivers/gpu/drm/i915/display/intel_audio.h b/drivers/gpu/drm/i915/display/intel_audio.h
index 576c061d72a4..1bafc155434a 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.h
+++ b/drivers/gpu/drm/i915/display/intel_audio.h
@@ -27,6 +27,7 @@ void intel_audio_codec_get_config(struct intel_encoder *encoder,
 				  struct intel_crtc_state *crtc_state);
 void intel_audio_cdclk_change_pre(struct drm_i915_private *dev_priv);
 void intel_audio_cdclk_change_post(struct drm_i915_private *dev_priv);
+int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state);
 void intel_audio_init(struct drm_i915_private *dev_priv);
 void intel_audio_register(struct drm_i915_private *i915);
 void intel_audio_deinit(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 3103ecab980c..89d12c521411 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2858,42 +2858,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 
 	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
 	min_cdclk = max(hsw_ips_min_cdclk(crtc_state), min_cdclk);
-
-	/* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
-	 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
-	 * there may be audio corruption or screen corruption." This cdclk
-	 * restriction for GLK is 316.8 MHz.
-	 */
-	if (intel_crtc_has_dp_encoder(crtc_state) &&
-	    crtc_state->has_audio &&
-	    crtc_state->port_clock >= 540000 &&
-	    crtc_state->lane_count == 4) {
-		if (DISPLAY_VER(display) == 10) {
-			/* Display WA #1145: glk */
-			min_cdclk = max(316800, min_cdclk);
-		} else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) {
-			/* Display WA #1144: skl,bxt */
-			min_cdclk = max(432000, min_cdclk);
-		}
-	}
-
-	/*
-	 * According to BSpec, "The CD clock frequency must be at least twice
-	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
-	 */
-	if (crtc_state->has_audio && DISPLAY_VER(display) >= 9)
-		min_cdclk = max(2 * 96000, min_cdclk);
-
-	/*
-	 * "For DP audio configuration, cdclk frequency shall be set to
-	 *  meet the following requirements:
-	 *  DP Link Frequency(MHz) | Cdclk frequency(MHz)
-	 *  270                    | 320 or higher
-	 *  162                    | 200 or higher"
-	 */
-	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
-	    intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
-		min_cdclk = max(crtc_state->port_clock, min_cdclk);
+	min_cdclk = max(intel_audio_min_cdclk(crtc_state), min_cdclk);
 
 	/*
 	 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
-- 
2.45.2

[PATCH 05/11] drm/i915/cdclk: Factor out has_audio check in intel_audio_min_cdclk()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

All the if statements in intel_audio_min_cdclk() check for
has_audio==true. Check that once ahead of time to make
things a bit simpler.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_audio.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 82c45b24417a..af0bfdc44072 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -984,13 +984,15 @@ int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	int min_cdclk = 0;
 
+	if (!crtc_state->has_audio)
+		return 0;
+
 	/* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
 	 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
 	 * there may be audio corruption or screen corruption." This cdclk
 	 * restriction for GLK is 316.8 MHz.
 	 */
 	if (intel_crtc_has_dp_encoder(crtc_state) &&
-	    crtc_state->has_audio &&
 	    crtc_state->port_clock >= 540000 &&
 	    crtc_state->lane_count == 4) {
 		if (DISPLAY_VER(display) == 10) {
@@ -1006,7 +1008,7 @@ int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state)
 	 * According to BSpec, "The CD clock frequency must be at least twice
 	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
 	 */
-	if (crtc_state->has_audio && DISPLAY_VER(display) >= 9)
+	if (DISPLAY_VER(display) >= 9)
 		min_cdclk = max(2 * 96000, min_cdclk);
 
 	/*
@@ -1017,7 +1019,7 @@ int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state)
 	 *  162                    | 200 or higher"
 	 */
 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
-	    intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
+	    intel_crtc_has_dp_encoder(crtc_state))
 		min_cdclk = max(crtc_state->port_clock, min_cdclk);
 
 	return min_cdclk;
-- 
2.45.2

[PATCH 06/11] drm/i915/cdclk: Extract vlv_dsi_min_cdclk()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pull the DSI min cdclk calculation into a helper and hide
it inside vlv_dsi.c in order to keep most DSI related
details in one place.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 23 ++------------------
 drivers/gpu/drm/i915/display/vlv_dsi.c     | 25 ++++++++++++++++++++++
 drivers/gpu/drm/i915/display/vlv_dsi.h     |  8 +++++++
 3 files changed, 35 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 89d12c521411..e10378744607 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -46,6 +46,7 @@
 #include "intel_vdsc.h"
 #include "skl_watermark.h"
 #include "skl_watermark_regs.h"
+#include "vlv_dsi.h"
 #include "vlv_sideband.h"
 
 /**
@@ -2849,8 +2850,6 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
 
 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
-	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	int min_cdclk;
 
 	if (!crtc_state->hw.enable)
@@ -2859,25 +2858,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
 	min_cdclk = max(hsw_ips_min_cdclk(crtc_state), min_cdclk);
 	min_cdclk = max(intel_audio_min_cdclk(crtc_state), min_cdclk);
-
-	/*
-	 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
-	 * than 320000KHz.
-	 */
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
-	    IS_VALLEYVIEW(dev_priv))
-		min_cdclk = max(320000, min_cdclk);
-
-	/*
-	 * On Geminilake once the CDCLK gets as low as 79200
-	 * picture gets unstable, despite that values are
-	 * correct for DSI PLL and DE PLL.
-	 */
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
-	    IS_GEMINILAKE(dev_priv))
-		min_cdclk = max(158400, min_cdclk);
-
-	/* Account for additional needs from the planes */
+	min_cdclk = max(vlv_dsi_min_cdclk(crtc_state), min_cdclk);
 	min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
 
 	if (crtc_state->dsc.compression_enable)
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 9383eedee2d4..49a895589150 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -1760,6 +1760,31 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
 	intel_dsi_log_params(intel_dsi);
 }
 
+int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	int min_cdclk = 0;
+
+	/*
+	 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
+	 * than 320000KHz.
+	 */
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
+	    IS_VALLEYVIEW(dev_priv))
+		min_cdclk = max(320000, min_cdclk);
+
+	/*
+	 * On Geminilake once the CDCLK gets as low as 79200
+	 * picture gets unstable, despite that values are
+	 * correct for DSI PLL and DE PLL.
+	 */
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
+	    IS_GEMINILAKE(dev_priv))
+		min_cdclk = max(158400, min_cdclk);
+
+	return min_cdclk;
+}
+
 typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi);
 
 /*
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.h b/drivers/gpu/drm/i915/display/vlv_dsi.h
index cf9d7b82f288..5f99059b4c48 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.h
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.h
@@ -8,13 +8,17 @@
 
 #include <linux/types.h>
 
+#include <drm/drm_mipi_dsi.h>
+
 enum port;
 struct drm_i915_private;
+struct intel_crtc_state;
 struct intel_dsi;
 
 #ifdef I915
 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
+int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state);
 void vlv_dsi_init(struct drm_i915_private *dev_priv);
 #else
 static inline void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
@@ -24,6 +28,10 @@ static inline enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt
 {
 	return 0;
 }
+static inline int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+	return 0;
+}
 static inline void vlv_dsi_init(struct drm_i915_private *dev_priv)
 {
 }
-- 
2.45.2

[PATCH 07/11] drm/i915/cdclk: Factor out INTEL_OUTPUT_DSI check in vlv_dsi_min_cdclk()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

All the if statements in vlv_dsi_min_cdclk() check for
INTEL_OUTPUT_DSI. Make life simpler by checking that just
once at the start.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/vlv_dsi.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 49a895589150..708639178e29 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -1763,26 +1763,26 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
 int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-	int min_cdclk = 0;
+
+	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+		return 0;
 
 	/*
 	 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
 	 * than 320000KHz.
 	 */
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
-	    IS_VALLEYVIEW(dev_priv))
-		min_cdclk = max(320000, min_cdclk);
+	if (IS_VALLEYVIEW(dev_priv))
+		return 320000;
 
 	/*
 	 * On Geminilake once the CDCLK gets as low as 79200
 	 * picture gets unstable, despite that values are
 	 * correct for DSI PLL and DE PLL.
 	 */
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
-	    IS_GEMINILAKE(dev_priv))
-		min_cdclk = max(158400, min_cdclk);
+	if (IS_GEMINILAKE(dev_priv))
+		return 158400;
 
-	return min_cdclk;
+	return 0;
 }
 
 typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi);
-- 
2.45.2

[PATCH 08/11] drm/i915/cdclk: Suck the compression_enable check into intel_vdsc_min_cdclk()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Declutter intel_crtc_compute_min_cdclk() by moving the
crtc_state->dsc.compression_enable check into
intel_vdsc_min_cdclk().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index e10378744607..989607c0b35d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2812,6 +2812,9 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
 	int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
 	int min_cdclk = 0;
 
+	if (!crtc_state->dsc.compression_enable)
+		return 0;
+
 	/*
 	 * When we decide to use only one VDSC engine, since
 	 * each VDSC operates with 1 ppc throughput, pixel clock
@@ -2860,9 +2863,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 	min_cdclk = max(intel_audio_min_cdclk(crtc_state), min_cdclk);
 	min_cdclk = max(vlv_dsi_min_cdclk(crtc_state), min_cdclk);
 	min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
-
-	if (crtc_state->dsc.compression_enable)
-		min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
+	min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
 
 	return min_cdclk;
 }
-- 
2.45.2

[PATCH 09/11] drm/i915/cdclk: Drop pointles max_t() usage in intel_vdsc_min_cdclk()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

min_cdclk==0 when intel_vdsc_min_cdclk() calls max_t() on it.
Drop the redundant max_t().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 989607c0b35d..d376f7bccf21 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2810,7 +2810,7 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_display *display = to_intel_display(crtc);
 	int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
-	int min_cdclk = 0;
+	int min_cdclk;
 
 	if (!crtc_state->dsc.compression_enable)
 		return 0;
@@ -2822,8 +2822,7 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
 	 * If there 2 VDSC engines, then pixel clock can't be higher than
 	 * VDSC clock(cdclk) * 2 and so on.
 	 */
-	min_cdclk = max_t(int, min_cdclk,
-			  DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances));
+	min_cdclk = DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances);
 
 	if (crtc_state->joiner_pipes) {
 		int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
-- 
2.45.2

[PATCH 10/11] drm/i915/cdclk: Relocate intel_vdsc_min_cdclk()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Move intel_vdsc_min_cdclk() into intel_vdsc.c from intel_cdclk.c
so that details about DSC are better contained.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 46 ----------------------
 drivers/gpu/drm/i915/display/intel_vdsc.c  | 46 ++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vdsc.h  |  1 +
 3 files changed, 47 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d376f7bccf21..9f38dd14b2d8 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -37,7 +37,6 @@
 #include "intel_cdclk.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
-#include "intel_dp.h"
 #include "intel_display_types.h"
 #include "intel_mchbar_regs.h"
 #include "intel_pci_config.h"
@@ -2805,51 +2804,6 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
 	return min_cdclk;
 }
 
-static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct intel_display *display = to_intel_display(crtc);
-	int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
-	int min_cdclk;
-
-	if (!crtc_state->dsc.compression_enable)
-		return 0;
-
-	/*
-	 * When we decide to use only one VDSC engine, since
-	 * each VDSC operates with 1 ppc throughput, pixel clock
-	 * cannot be higher than the VDSC clock (cdclk)
-	 * If there 2 VDSC engines, then pixel clock can't be higher than
-	 * VDSC clock(cdclk) * 2 and so on.
-	 */
-	min_cdclk = DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances);
-
-	if (crtc_state->joiner_pipes) {
-		int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
-
-		/*
-		 * According to Bigjoiner bw check:
-		 * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
-		 *
-		 * We have already computed compressed_bpp, so now compute the min CDCLK that
-		 * is required to support this compressed_bpp.
-		 *
-		 * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
-		 *
-		 * Since PPC = 2 with bigjoiner
-		 * => CDCLK >= compressed_bpp * Pixel clock  / 2 * Bigjoiner Interface bits
-		 */
-		int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24;
-		int min_cdclk_bj =
-			(fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
-			 pixel_clock) / (2 * bigjoiner_interface_bits);
-
-		min_cdclk = max(min_cdclk, min_cdclk_bj);
-	}
-
-	return min_cdclk;
-}
-
 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 {
 	int min_cdclk;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 40525f5c4c42..e6cb712373a9 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -14,6 +14,7 @@
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
+#include "intel_dp.h"
 #include "intel_dsi.h"
 #include "intel_qp_tables.h"
 #include "intel_vdsc.h"
@@ -1003,3 +1004,48 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent,
 	intel_vdsc_dump_state(p, indent, crtc_state);
 	drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);
 }
+
+int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct intel_display *display = to_intel_display(crtc);
+	int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
+	int min_cdclk;
+
+	if (!crtc_state->dsc.compression_enable)
+		return 0;
+
+	/*
+	 * When we decide to use only one VDSC engine, since
+	 * each VDSC operates with 1 ppc throughput, pixel clock
+	 * cannot be higher than the VDSC clock (cdclk)
+	 * If there 2 VDSC engines, then pixel clock can't be higher than
+	 * VDSC clock(cdclk) * 2 and so on.
+	 */
+	min_cdclk = DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances);
+
+	if (crtc_state->joiner_pipes) {
+		int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
+
+		/*
+		 * According to Bigjoiner bw check:
+		 * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
+		 *
+		 * We have already computed compressed_bpp, so now compute the min CDCLK that
+		 * is required to support this compressed_bpp.
+		 *
+		 * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
+		 *
+		 * Since PPC = 2 with bigjoiner
+		 * => CDCLK >= compressed_bpp * Pixel clock  / 2 * Bigjoiner Interface bits
+		 */
+		int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24;
+		int min_cdclk_bj =
+			(fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
+			 pixel_clock) / (2 * bigjoiner_interface_bits);
+
+		min_cdclk = max(min_cdclk, min_cdclk_bj);
+	}
+
+	return min_cdclk;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 290b2e9b3482..9e2812f99dd7 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -31,5 +31,6 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
 			    const struct intel_crtc_state *crtc_state);
 void intel_vdsc_state_dump(struct drm_printer *p, int indent,
 			   const struct intel_crtc_state *crtc_state);
+int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_VDSC_H__ */
-- 
2.45.2

[PATCH 11/11] drm/i915/cdclk: Unify cdclk max() parameter order

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

In some places we do
 min_cdclk = max(min_cdclk, other_min_cdclk)
and in other places we have the arguments swapped as
 min_cdclk = max(other_min_cdclk, min_cdclk)

Unify everyone to use the first order of arguments, because
it looks cleaner, especially within intel_crtc_compute_min_cdclk()
which is doing a lot of these back-to-back.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_audio.c |  8 ++++----
 drivers/gpu/drm/i915/display/intel_bw.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +++++++++---------
 3 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index af0bfdc44072..047cc5a2ef1f 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -997,10 +997,10 @@ int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state)
 	    crtc_state->lane_count == 4) {
 		if (DISPLAY_VER(display) == 10) {
 			/* Display WA #1145: glk */
-			min_cdclk = max(316800, min_cdclk);
+			min_cdclk = max(min_cdclk, 316800);
 		} else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) {
 			/* Display WA #1144: skl,bxt */
-			min_cdclk = max(432000, min_cdclk);
+			min_cdclk = max(min_cdclk, 432000);
 		}
 	}
 
@@ -1009,7 +1009,7 @@ int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state)
 	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
 	 */
 	if (DISPLAY_VER(display) >= 9)
-		min_cdclk = max(2 * 96000, min_cdclk);
+		min_cdclk = max(min_cdclk, 2 * 96000);
 
 	/*
 	 * "For DP audio configuration, cdclk frequency shall be set to
@@ -1020,7 +1020,7 @@ int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state)
 	 */
 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 	    intel_crtc_has_dp_encoder(crtc_state))
-		min_cdclk = max(crtc_state->port_clock, min_cdclk);
+		min_cdclk = max(min_cdclk, crtc_state->port_clock);
 
 	return min_cdclk;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 47036d4abb33..5f91b009df0d 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -1256,7 +1256,7 @@ int intel_bw_min_cdclk(struct drm_i915_private *i915,
 	min_cdclk = intel_bw_dbuf_min_cdclk(i915, bw_state);
 
 	for_each_pipe(i915, pipe)
-		min_cdclk = max(bw_state->min_cdclk[pipe], min_cdclk);
+		min_cdclk = max(min_cdclk, bw_state->min_cdclk[pipe]);
 
 	return min_cdclk;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9f38dd14b2d8..f16a37ef7316 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2799,7 +2799,7 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
 	int min_cdclk = 0;
 
 	for_each_intel_plane_on_crtc(display->drm, crtc, plane)
-		min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk);
+		min_cdclk = max(min_cdclk, crtc_state->min_cdclk[plane->id]);
 
 	return min_cdclk;
 }
@@ -2812,10 +2812,10 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 		return 0;
 
 	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
-	min_cdclk = max(hsw_ips_min_cdclk(crtc_state), min_cdclk);
-	min_cdclk = max(intel_audio_min_cdclk(crtc_state), min_cdclk);
-	min_cdclk = max(vlv_dsi_min_cdclk(crtc_state), min_cdclk);
-	min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
+	min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state));
+	min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state));
+	min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state));
+	min_cdclk = max(min_cdclk, intel_planes_min_cdclk(crtc_state));
 	min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
 
 	return min_cdclk;
@@ -2868,7 +2868,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
 	min_cdclk = max(cdclk_state->force_min_cdclk,
 			cdclk_state->bw_min_cdclk);
 	for_each_pipe(display, pipe)
-		min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
+		min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]);
 
 	/*
 	 * Avoid glk_force_audio_cdclk() causing excessive screen
@@ -2880,7 +2880,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
 	 */
 	if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes &&
 	    !is_power_of_2(cdclk_state->active_pipes))
-		min_cdclk = max(2 * 96000, min_cdclk);
+		min_cdclk = max(min_cdclk, 2 * 96000);
 
 	if (min_cdclk > display->cdclk.max_cdclk_freq) {
 		drm_dbg_kms(display->drm,
@@ -2936,8 +2936,8 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
 
 	min_voltage_level = 0;
 	for_each_pipe(display, pipe)
-		min_voltage_level = max(cdclk_state->min_voltage_level[pipe],
-					min_voltage_level);
+		min_voltage_level = max(min_voltage_level,
+					cdclk_state->min_voltage_level[pipe]);
 
 	return min_voltage_level;
 }
-- 
2.45.2

✗ Fi.CI.CHECKPATCH: warning for drm/i915/cdclk: Declutter CDCLK code

[Patchwork]

== Series Details ==

Series: drm/i915/cdclk: Declutter CDCLK code
URL   : https://patchwork.freedesktop.org/series/140697/
State : warning

== Summary ==

Error: dim checkpatch failed
692ab31effb0 drm/i915: Introduce HAS_DOUBLE_WIDE()
522cd55cd86a drm/i915/cdclk: Extract intel_cdclk_guardband() and intel_cdclk_ppc()
8949892ee2f3 drm/i915/cdclk: Extract hsw_ips_min_cdclk()
-:16: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#16: 
+ min_cdclk = max(DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95), min_cdclk)

-:75: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#75: FILE: drivers/gpu/drm/i915/display/hsw_ips.h:45:
 }
+static inline int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)

total: 0 errors, 1 warnings, 1 checks, 58 lines checked
e165ed1ea5e7 drm/i915/cdclk: Extract intel_audio_min_cdclk()
fa4557f213c3 drm/i915/cdclk: Factor out has_audio check in intel_audio_min_cdclk()
719bee927307 drm/i915/cdclk: Extract vlv_dsi_min_cdclk()
-:125: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#125: FILE: drivers/gpu/drm/i915/display/vlv_dsi.h:31:
 }
+static inline int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)

total: 0 errors, 0 warnings, 1 checks, 99 lines checked
1495c1655317 drm/i915/cdclk: Factor out INTEL_OUTPUT_DSI check in vlv_dsi_min_cdclk()
9d86712de002 drm/i915/cdclk: Suck the compression_enable check into intel_vdsc_min_cdclk()
d291d73974ad drm/i915/cdclk: Drop pointles max_t() usage in intel_vdsc_min_cdclk()
d8f04e168c73 drm/i915/cdclk: Relocate intel_vdsc_min_cdclk()
ab0b9c40d96f drm/i915/cdclk: Unify cdclk max() parameter order

✗ Fi.CI.SPARSE: warning for drm/i915/cdclk: Declutter CDCLK code

[Patchwork]

== Series Details ==

Series: drm/i915/cdclk: Declutter CDCLK code
URL   : https://patchwork.freedesktop.org/series/140697/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✗ Fi.CI.BAT: failure for drm/i915/cdclk: Declutter CDCLK code

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 7601 bytes --]

== Series Details ==

Series: drm/i915/cdclk: Declutter CDCLK code
URL   : https://patchwork.freedesktop.org/series/140697/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_15608 -> Patchwork_140697v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_140697v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_140697v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v1/index.html

Participating hosts (47 -> 46)
------------------------------

  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_140697v1:

### IGT changes ###

#### Possible regressions ####

  * igt@prime_vgem@basic-fence-flip:
    - bat-apl-1:          [PASS][1] -> [DMESG-WARN][2] +1 other test dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15608/bat-apl-1/igt@prime_vgem@basic-fence-flip.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v1/bat-apl-1/igt@prime_vgem@basic-fence-flip.html

  
Known issues
------------

  Here are the changes found in Patchwork_140697v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_auth@basic-auth:
    - bat-apl-1:          [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 other test dmesg-warn
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15608/bat-apl-1/igt@core_auth@basic-auth.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v1/bat-apl-1/igt@core_auth@basic-auth.html

  * igt@i915_module_load@reload:
    - bat-apl-1:          [PASS][5] -> [DMESG-WARN][6] ([i915#180] / [i915#1982]) +1 other test dmesg-warn
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15608/bat-apl-1/igt@i915_module_load@reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v1/bat-apl-1/igt@i915_module_load@reload.html

  * igt@i915_selftest@live:
    - bat-arls-1:         [PASS][7] -> [DMESG-FAIL][8] ([i915#10262] / [i915#10341] / [i915#12133])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15608/bat-arls-1/igt@i915_selftest@live.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v1/bat-arls-1/igt@i915_selftest@live.html

  * igt@i915_selftest@live@gt_contexts:
    - bat-arls-1:         [PASS][9] -> [DMESG-FAIL][10] ([i915#10262]) +31 other tests dmesg-fail
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15608/bat-arls-1/igt@i915_selftest@live@gt_contexts.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v1/bat-arls-1/igt@i915_selftest@live@gt_contexts.html

  * igt@i915_selftest@live@gt_timelines:
    - bat-arls-1:         [PASS][11] -> [DMESG-WARN][12] ([i915#10341])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15608/bat-arls-1/igt@i915_selftest@live@gt_timelines.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v1/bat-arls-1/igt@i915_selftest@live@gt_timelines.html

  * igt@i915_selftest@live@sanitycheck:
    - bat-apl-1:          [PASS][13] -> [DMESG-WARN][14] ([i915#11621]) +76 other tests dmesg-warn
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15608/bat-apl-1/igt@i915_selftest@live@sanitycheck.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v1/bat-apl-1/igt@i915_selftest@live@sanitycheck.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - bat-apl-1:          [PASS][15] -> [DMESG-WARN][16] ([i915#11621] / [i915#180] / [i915#1982]) +2 other tests dmesg-warn
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15608/bat-apl-1/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v1/bat-apl-1/igt@kms_flip@basic-flip-vs-wf_vblank.html

  * igt@kms_pm_rpm@basic-pci-d3-state:
    - bat-apl-1:          [PASS][17] -> [DMESG-WARN][18] ([i915#11621] / [i915#180]) +43 other tests dmesg-warn
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15608/bat-apl-1/igt@kms_pm_rpm@basic-pci-d3-state.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v1/bat-apl-1/igt@kms_pm_rpm@basic-pci-d3-state.html

  
#### Possible fixes ####

  * igt@i915_selftest@live:
    - bat-twl-1:          [INCOMPLETE][19] ([i915#12133] / [i915#9413]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15608/bat-twl-1/igt@i915_selftest@live.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v1/bat-twl-1/igt@i915_selftest@live.html
    - bat-mtlp-6:         [DMESG-WARN][21] ([i915#10341] / [i915#12133]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15608/bat-mtlp-6/igt@i915_selftest@live.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v1/bat-mtlp-6/igt@i915_selftest@live.html
    - bat-atsm-1:         [ABORT][23] ([i915#12133]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15608/bat-atsm-1/igt@i915_selftest@live.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v1/bat-atsm-1/igt@i915_selftest@live.html

  * igt@i915_selftest@live@client:
    - bat-atsm-1:         [ABORT][25] ([i915#12305]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15608/bat-atsm-1/igt@i915_selftest@live@client.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v1/bat-atsm-1/igt@i915_selftest@live@client.html

  * igt@i915_selftest@live@gt_lrc:
    - bat-twl-1:          [INCOMPLETE][27] ([i915#9413]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15608/bat-twl-1/igt@i915_selftest@live@gt_lrc.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v1/bat-twl-1/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@hangcheck:
    - bat-mtlp-6:         [DMESG-WARN][29] ([i915#11349] / [i915#12133]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15608/bat-mtlp-6/igt@i915_selftest@live@hangcheck.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v1/bat-mtlp-6/igt@i915_selftest@live@hangcheck.html

  
  [i915#10262]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10262
  [i915#10341]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10341
  [i915#11349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11349
  [i915#11621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11621
  [i915#12133]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12133
  [i915#12305]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12305
  [i915#180]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/180
  [i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
  [i915#9413]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9413


Build changes
-------------

  * Linux: CI_DRM_15608 -> Patchwork_140697v1

  CI-20190529: 20190529
  CI_DRM_15608: b97473387ce132222c9b71f7cf39c2cd814cbb6f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8088: 0030d5bc92b8e4ac991db1c88af1f0ad7593812a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_140697v1: b97473387ce132222c9b71f7cf39c2cd814cbb6f @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v1/index.html

[-- Attachment #2: Type: text/html, Size: 9568 bytes --]

Re: [PATCH 02/11] drm/i915/cdclk: Extract intel_cdclk_guardband() and intel_cdclk_ppc()

[Jani Nikula]

On Tue, 29 Oct 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We are duplicating the CDCLK guardband and "pixels per clock"
> figures in two places. Pull those out into small helpers that
> can be used by both places.

Oh, it's not just that, it's great to untangle the conflated two things!

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 50 +++++++++++-----------
>  1 file changed, 26 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 6cef3ca3a069..977fcdaa7372 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2761,23 +2761,34 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
>  			"Post changing CDCLK to");
>  }
>  
> +/* pixels per CDCLK */
> +static int intel_cdclk_ppc(struct intel_display *display, bool double_wide)
> +{
> +	return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1;
> +}
> +
> +/* max pixel rate as % of CDCLK (not accounting for PPC) */
> +static int intel_cdclk_guardband(struct intel_display *display)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> +	if (DISPLAY_VER(display) >= 9 ||
> +	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> +		return 100;
> +	else if (IS_CHERRYVIEW(dev_priv))
> +		return 95;
> +	else
> +		return 90;
> +}
> +
>  static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
> -	struct drm_i915_private *dev_priv = to_i915(display->drm);
> +	int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
> +	int guardband = intel_cdclk_guardband(display);
>  	int pixel_rate = crtc_state->pixel_rate;
>  
> -	if (DISPLAY_VER(display) >= 10)
> -		return DIV_ROUND_UP(pixel_rate, 2);
> -	else if (DISPLAY_VER(display) == 9 ||
> -		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> -		return pixel_rate;
> -	else if (IS_CHERRYVIEW(dev_priv))
> -		return DIV_ROUND_UP(pixel_rate * 100, 95);
> -	else if (crtc_state->double_wide)
> -		return DIV_ROUND_UP(pixel_rate * 100, 90 * 2);
> -	else
> -		return DIV_ROUND_UP(pixel_rate * 100, 90);
> +	return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc);
>  }
>  
>  static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
> @@ -3452,20 +3463,11 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
>  
>  static int intel_compute_max_dotclk(struct intel_display *display)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(display->drm);
> +	int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display));
> +	int guardband = intel_cdclk_guardband(display);
>  	int max_cdclk_freq = display->cdclk.max_cdclk_freq;
>  
> -	if (DISPLAY_VER(display) >= 10)
> -		return 2 * max_cdclk_freq;
> -	else if (DISPLAY_VER(display) == 9 ||
> -		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> -		return max_cdclk_freq;
> -	else if (IS_CHERRYVIEW(dev_priv))
> -		return max_cdclk_freq*95/100;
> -	else if (HAS_DOUBLE_WIDE(display))
> -		return 2*max_cdclk_freq*90/100;
> -	else
> -		return max_cdclk_freq*90/100;
> +	return ppc * max_cdclk_freq * guardband / 100;
>  }
>  
>  /**

-- 
Jani Nikula, Intel

Re: [PATCH 01/11] drm/i915: Introduce HAS_DOUBLE_WIDE()

[Jani Nikula]

On Tue, 29 Oct 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Make the code a bit more self documenting by adding
> HAS_DOUBLE_WIDE().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c          | 2 +-
>  drivers/gpu/drm/i915/display/intel_display.c        | 4 ++--
>  drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
>  3 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 96523526a2c3..6cef3ca3a069 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -3462,7 +3462,7 @@ static int intel_compute_max_dotclk(struct intel_display *display)
>  		return max_cdclk_freq;
>  	else if (IS_CHERRYVIEW(dev_priv))
>  		return max_cdclk_freq*95/100;
> -	else if (DISPLAY_VER(display) < 4)
> +	else if (HAS_DOUBLE_WIDE(display))
>  		return 2*max_cdclk_freq*90/100;
>  	else
>  		return max_cdclk_freq*90/100;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0e6d6c8354ef..9a5102224c59 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2371,7 +2371,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
>  	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	/* GDG double wide on either pipe, otherwise pipe A only */
> -	return DISPLAY_VER(dev_priv) < 4 &&
> +	return HAS_DOUBLE_WIDE(dev_priv) &&
>  		(crtc->pipe == PIPE_A || IS_I915G(dev_priv));
>  }
>  
> @@ -3207,7 +3207,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  
>  	intel_color_get_config(pipe_config);
>  
> -	if (DISPLAY_VER(dev_priv) < 4)
> +	if (HAS_DOUBLE_WIDE(dev_priv))
>  		pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
>  
>  	intel_get_transcoder_timings(crtc, pipe_config);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 410f8b33a8a1..ae7a35cf44ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -129,6 +129,7 @@ enum intel_display_subplatform {
>  #define HAS_DISPLAY(i915)		(DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
>  #define HAS_DMC(i915)			(DISPLAY_RUNTIME_INFO(i915)->has_dmc)
>  #define HAS_DOUBLE_BUFFERED_M_N(i915)	(DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
> +#define HAS_DOUBLE_WIDE(i915)		(DISPLAY_VER(i915) < 4)
>  #define HAS_DP_MST(i915)		(DISPLAY_INFO(i915)->has_dp_mst)
>  #define HAS_DP20(i915)			(IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
>  #define HAS_DPT(i915)			(DISPLAY_VER(i915) >= 13)

-- 
Jani Nikula, Intel

Re: [PATCH 03/11] drm/i915/cdclk: Extract hsw_ips_min_cdclk()

[Jani Nikula]

On Tue, 29 Oct 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pull the whole BDW IPS min CDCLK stuff into the IPS code
> so that all the details around IPS are contained in once
> place.
>
> Note that while
> - min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
> vs.
> + min_cdclk = max(DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95), min_cdclk)
> may look different, they are in fact the same because
> min_cdclk==crtc_state->pixel_rate at this point in
> intel_crtc_compute_min_cdclk() on BDW.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/hsw_ips.c     | 16 +++++++++++++++-
>  drivers/gpu/drm/i915/display/hsw_ips.h     |  6 +++---
>  drivers/gpu/drm/i915/display/intel_cdclk.c |  5 +----
>  3 files changed, 19 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
> index c571c6e76d4a..5a0fc9f2bd6f 100644
> --- a/drivers/gpu/drm/i915/display/hsw_ips.c
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> @@ -186,7 +186,7 @@ bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
>  	return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
>  }
>  
> -bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
> +static bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> @@ -215,6 +215,20 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
>  	return true;
>  }
>  
> +int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +
> +	if (!IS_BROADWELL(i915))
> +		return 0;
> +
> +	if (!hsw_crtc_state_ips_capable(crtc_state))
> +		return 0;
> +
> +	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> +	return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95);
> +}
> +
>  int hsw_ips_compute_config(struct intel_atomic_state *state,
>  			   struct intel_crtc *crtc)
>  {
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.h b/drivers/gpu/drm/i915/display/hsw_ips.h
> index 35364228e1c1..7af12f88a8ce 100644
> --- a/drivers/gpu/drm/i915/display/hsw_ips.h
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.h
> @@ -19,7 +19,7 @@ bool hsw_ips_pre_update(struct intel_atomic_state *state,
>  void hsw_ips_post_update(struct intel_atomic_state *state,
>  			 struct intel_crtc *crtc);
>  bool hsw_crtc_supports_ips(struct intel_crtc *crtc);
> -bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
> +int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state);
>  int hsw_ips_compute_config(struct intel_atomic_state *state,
>  			   struct intel_crtc *crtc);
>  void hsw_ips_get_config(struct intel_crtc_state *crtc_state);
> @@ -42,9 +42,9 @@ static inline bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
>  {
>  	return false;
>  }
> -static inline bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
> +static inline int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)
>  {
> -	return false;
> +	return 0;
>  }
>  static inline int hsw_ips_compute_config(struct intel_atomic_state *state,
>  					 struct intel_crtc *crtc)
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 977fcdaa7372..3103ecab980c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2857,10 +2857,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>  		return 0;
>  
>  	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
> -
> -	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> -	if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
> -		min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
> +	min_cdclk = max(hsw_ips_min_cdclk(crtc_state), min_cdclk);
>  
>  	/* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
>  	 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else

-- 
Jani Nikula, Intel

Re: [PATCH 04/11] drm/i915/cdclk: Extract intel_audio_min_cdclk()

[Jani Nikula]

On Tue, 29 Oct 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pull the audio min cdclk calculation into a helper and hide
> it inside intel_audio.c in order to keep most audio related
> details in one place.
>
> The one audio related thing that remains in intel_cdclk.c
> is commit 451eaa1a614c ("drm/i915: Bump GLK CDCLK frequency when
> driving multiple pipes") but given that's implemented in terms
> of the cdclk_state I think it should stay put.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_audio.c | 45 ++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_audio.h |  1 +
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 37 +-----------------
>  3 files changed, 47 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index 32aa9ec1a204..82c45b24417a 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -978,6 +978,51 @@ static void glk_force_audio_cdclk(struct drm_i915_private *i915,
>  	drm_modeset_acquire_fini(&ctx);
>  }
>  
> +int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct drm_i915_private *dev_priv = to_i915(display->drm);
> +	int min_cdclk = 0;
> +
> +	/* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
> +	 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
> +	 * there may be audio corruption or screen corruption." This cdclk
> +	 * restriction for GLK is 316.8 MHz.
> +	 */
> +	if (intel_crtc_has_dp_encoder(crtc_state) &&
> +	    crtc_state->has_audio &&
> +	    crtc_state->port_clock >= 540000 &&
> +	    crtc_state->lane_count == 4) {
> +		if (DISPLAY_VER(display) == 10) {
> +			/* Display WA #1145: glk */
> +			min_cdclk = max(316800, min_cdclk);
> +		} else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) {
> +			/* Display WA #1144: skl,bxt */
> +			min_cdclk = max(432000, min_cdclk);
> +		}
> +	}
> +
> +	/*
> +	 * According to BSpec, "The CD clock frequency must be at least twice
> +	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> +	 */
> +	if (crtc_state->has_audio && DISPLAY_VER(display) >= 9)
> +		min_cdclk = max(2 * 96000, min_cdclk);
> +
> +	/*
> +	 * "For DP audio configuration, cdclk frequency shall be set to
> +	 *  meet the following requirements:
> +	 *  DP Link Frequency(MHz) | Cdclk frequency(MHz)
> +	 *  270                    | 320 or higher
> +	 *  162                    | 200 or higher"
> +	 */
> +	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> +	    intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
> +		min_cdclk = max(crtc_state->port_clock, min_cdclk);
> +
> +	return min_cdclk;
> +}
> +
>  static unsigned long i915_audio_component_get_power(struct device *kdev)
>  {
>  	struct intel_display *display = to_intel_display(kdev);
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.h b/drivers/gpu/drm/i915/display/intel_audio.h
> index 576c061d72a4..1bafc155434a 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.h
> +++ b/drivers/gpu/drm/i915/display/intel_audio.h
> @@ -27,6 +27,7 @@ void intel_audio_codec_get_config(struct intel_encoder *encoder,
>  				  struct intel_crtc_state *crtc_state);
>  void intel_audio_cdclk_change_pre(struct drm_i915_private *dev_priv);
>  void intel_audio_cdclk_change_post(struct drm_i915_private *dev_priv);
> +int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state);
>  void intel_audio_init(struct drm_i915_private *dev_priv);
>  void intel_audio_register(struct drm_i915_private *i915);
>  void intel_audio_deinit(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 3103ecab980c..89d12c521411 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2858,42 +2858,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>  
>  	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
>  	min_cdclk = max(hsw_ips_min_cdclk(crtc_state), min_cdclk);
> -
> -	/* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
> -	 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
> -	 * there may be audio corruption or screen corruption." This cdclk
> -	 * restriction for GLK is 316.8 MHz.
> -	 */
> -	if (intel_crtc_has_dp_encoder(crtc_state) &&
> -	    crtc_state->has_audio &&
> -	    crtc_state->port_clock >= 540000 &&
> -	    crtc_state->lane_count == 4) {
> -		if (DISPLAY_VER(display) == 10) {
> -			/* Display WA #1145: glk */
> -			min_cdclk = max(316800, min_cdclk);
> -		} else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) {
> -			/* Display WA #1144: skl,bxt */
> -			min_cdclk = max(432000, min_cdclk);
> -		}
> -	}
> -
> -	/*
> -	 * According to BSpec, "The CD clock frequency must be at least twice
> -	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> -	 */
> -	if (crtc_state->has_audio && DISPLAY_VER(display) >= 9)
> -		min_cdclk = max(2 * 96000, min_cdclk);
> -
> -	/*
> -	 * "For DP audio configuration, cdclk frequency shall be set to
> -	 *  meet the following requirements:
> -	 *  DP Link Frequency(MHz) | Cdclk frequency(MHz)
> -	 *  270                    | 320 or higher
> -	 *  162                    | 200 or higher"
> -	 */
> -	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> -	    intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
> -		min_cdclk = max(crtc_state->port_clock, min_cdclk);
> +	min_cdclk = max(intel_audio_min_cdclk(crtc_state), min_cdclk);
>  
>  	/*
>  	 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower

-- 
Jani Nikula, Intel

Re: [PATCH 05/11] drm/i915/cdclk: Factor out has_audio check in intel_audio_min_cdclk()

[Jani Nikula]

On Tue, 29 Oct 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> All the if statements in intel_audio_min_cdclk() check for
> has_audio==true. Check that once ahead of time to make
> things a bit simpler.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_audio.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index 82c45b24417a..af0bfdc44072 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -984,13 +984,15 @@ int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	int min_cdclk = 0;
>  
> +	if (!crtc_state->has_audio)
> +		return 0;
> +
>  	/* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
>  	 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
>  	 * there may be audio corruption or screen corruption." This cdclk
>  	 * restriction for GLK is 316.8 MHz.
>  	 */
>  	if (intel_crtc_has_dp_encoder(crtc_state) &&
> -	    crtc_state->has_audio &&
>  	    crtc_state->port_clock >= 540000 &&
>  	    crtc_state->lane_count == 4) {
>  		if (DISPLAY_VER(display) == 10) {
> @@ -1006,7 +1008,7 @@ int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	 * According to BSpec, "The CD clock frequency must be at least twice
>  	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
>  	 */
> -	if (crtc_state->has_audio && DISPLAY_VER(display) >= 9)
> +	if (DISPLAY_VER(display) >= 9)
>  		min_cdclk = max(2 * 96000, min_cdclk);
>  
>  	/*
> @@ -1017,7 +1019,7 @@ int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	 *  162                    | 200 or higher"
>  	 */
>  	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> -	    intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
> +	    intel_crtc_has_dp_encoder(crtc_state))
>  		min_cdclk = max(crtc_state->port_clock, min_cdclk);
>  
>  	return min_cdclk;

-- 
Jani Nikula, Intel

Re: [PATCH 06/11] drm/i915/cdclk: Extract vlv_dsi_min_cdclk()

[Jani Nikula]

On Tue, 29 Oct 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pull the DSI min cdclk calculation into a helper and hide
> it inside vlv_dsi.c in order to keep most DSI related
> details in one place.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 23 ++------------------
>  drivers/gpu/drm/i915/display/vlv_dsi.c     | 25 ++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/vlv_dsi.h     |  8 +++++++
>  3 files changed, 35 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 89d12c521411..e10378744607 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -46,6 +46,7 @@
>  #include "intel_vdsc.h"
>  #include "skl_watermark.h"
>  #include "skl_watermark_regs.h"
> +#include "vlv_dsi.h"
>  #include "vlv_sideband.h"
>  
>  /**
> @@ -2849,8 +2850,6 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
>  
>  int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_display *display = to_intel_display(crtc_state);
> -	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	int min_cdclk;
>  
>  	if (!crtc_state->hw.enable)
> @@ -2859,25 +2858,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
>  	min_cdclk = max(hsw_ips_min_cdclk(crtc_state), min_cdclk);
>  	min_cdclk = max(intel_audio_min_cdclk(crtc_state), min_cdclk);
> -
> -	/*
> -	 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
> -	 * than 320000KHz.
> -	 */
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> -	    IS_VALLEYVIEW(dev_priv))
> -		min_cdclk = max(320000, min_cdclk);
> -
> -	/*
> -	 * On Geminilake once the CDCLK gets as low as 79200
> -	 * picture gets unstable, despite that values are
> -	 * correct for DSI PLL and DE PLL.
> -	 */
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> -	    IS_GEMINILAKE(dev_priv))
> -		min_cdclk = max(158400, min_cdclk);
> -
> -	/* Account for additional needs from the planes */
> +	min_cdclk = max(vlv_dsi_min_cdclk(crtc_state), min_cdclk);
>  	min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
>  
>  	if (crtc_state->dsc.compression_enable)
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index 9383eedee2d4..49a895589150 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -1760,6 +1760,31 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
>  	intel_dsi_log_params(intel_dsi);
>  }
>  
> +int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> +	int min_cdclk = 0;
> +
> +	/*
> +	 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
> +	 * than 320000KHz.
> +	 */
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> +	    IS_VALLEYVIEW(dev_priv))
> +		min_cdclk = max(320000, min_cdclk);
> +
> +	/*
> +	 * On Geminilake once the CDCLK gets as low as 79200
> +	 * picture gets unstable, despite that values are
> +	 * correct for DSI PLL and DE PLL.
> +	 */
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> +	    IS_GEMINILAKE(dev_priv))
> +		min_cdclk = max(158400, min_cdclk);
> +
> +	return min_cdclk;
> +}
> +
>  typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi);
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.h b/drivers/gpu/drm/i915/display/vlv_dsi.h
> index cf9d7b82f288..5f99059b4c48 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.h
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.h
> @@ -8,13 +8,17 @@
>  
>  #include <linux/types.h>
>  
> +#include <drm/drm_mipi_dsi.h>
> +

Huh, why is this required? At least it's unrelated to the patch.

Other than that,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>  enum port;
>  struct drm_i915_private;
> +struct intel_crtc_state;
>  struct intel_dsi;
>  
>  #ifdef I915
>  void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
>  enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
> +int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state);
>  void vlv_dsi_init(struct drm_i915_private *dev_priv);
>  #else
>  static inline void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
> @@ -24,6 +28,10 @@ static inline enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt
>  {
>  	return 0;
>  }
> +static inline int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)
> +{
> +	return 0;
> +}
>  static inline void vlv_dsi_init(struct drm_i915_private *dev_priv)
>  {
>  }

-- 
Jani Nikula, Intel

Re: [PATCH 07/11] drm/i915/cdclk: Factor out INTEL_OUTPUT_DSI check in vlv_dsi_min_cdclk()

[Jani Nikula]

On Tue, 29 Oct 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> All the if statements in vlv_dsi_min_cdclk() check for
> INTEL_OUTPUT_DSI. Make life simpler by checking that just
> once at the start.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/vlv_dsi.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index 49a895589150..708639178e29 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -1763,26 +1763,26 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
>  int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> -	int min_cdclk = 0;
> +
> +	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> +		return 0;
>  
>  	/*
>  	 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
>  	 * than 320000KHz.
>  	 */
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> -	    IS_VALLEYVIEW(dev_priv))
> -		min_cdclk = max(320000, min_cdclk);
> +	if (IS_VALLEYVIEW(dev_priv))
> +		return 320000;
>  
>  	/*
>  	 * On Geminilake once the CDCLK gets as low as 79200
>  	 * picture gets unstable, despite that values are
>  	 * correct for DSI PLL and DE PLL.
>  	 */
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> -	    IS_GEMINILAKE(dev_priv))
> -		min_cdclk = max(158400, min_cdclk);
> +	if (IS_GEMINILAKE(dev_priv))
> +		return 158400;
>  
> -	return min_cdclk;
> +	return 0;
>  }
>  
>  typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi);

-- 
Jani Nikula, Intel

Re: [PATCH 08/11] drm/i915/cdclk: Suck the compression_enable check into intel_vdsc_min_cdclk()

[Jani Nikula]

On Tue, 29 Oct 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Declutter intel_crtc_compute_min_cdclk() by moving the
> crtc_state->dsc.compression_enable check into
> intel_vdsc_min_cdclk().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index e10378744607..989607c0b35d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2812,6 +2812,9 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
>  	int min_cdclk = 0;
>  
> +	if (!crtc_state->dsc.compression_enable)
> +		return 0;
> +
>  	/*
>  	 * When we decide to use only one VDSC engine, since
>  	 * each VDSC operates with 1 ppc throughput, pixel clock
> @@ -2860,9 +2863,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	min_cdclk = max(intel_audio_min_cdclk(crtc_state), min_cdclk);
>  	min_cdclk = max(vlv_dsi_min_cdclk(crtc_state), min_cdclk);
>  	min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
> -
> -	if (crtc_state->dsc.compression_enable)
> -		min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
> +	min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));

Was going to say that it would be nice to have the params in the same
order... but looks like there's patch later in the series for that. Yay!

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>  
>  	return min_cdclk;
>  }

-- 
Jani Nikula, Intel

Re: [PATCH 09/11] drm/i915/cdclk: Drop pointles max_t() usage in intel_vdsc_min_cdclk()

[Jani Nikula]

On Tue, 29 Oct 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> min_cdclk==0 when intel_vdsc_min_cdclk() calls max_t() on it.
> Drop the redundant max_t().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 989607c0b35d..d376f7bccf21 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2810,7 +2810,7 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct intel_display *display = to_intel_display(crtc);
>  	int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
> -	int min_cdclk = 0;
> +	int min_cdclk;
>  
>  	if (!crtc_state->dsc.compression_enable)
>  		return 0;
> @@ -2822,8 +2822,7 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	 * If there 2 VDSC engines, then pixel clock can't be higher than
>  	 * VDSC clock(cdclk) * 2 and so on.
>  	 */
> -	min_cdclk = max_t(int, min_cdclk,
> -			  DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances));
> +	min_cdclk = DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances);
>  
>  	if (crtc_state->joiner_pipes) {
>  		int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);

-- 
Jani Nikula, Intel

Re: [PATCH 10/11] drm/i915/cdclk: Relocate intel_vdsc_min_cdclk()

[Jani Nikula]

On Tue, 29 Oct 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move intel_vdsc_min_cdclk() into intel_vdsc.c from intel_cdclk.c
> so that details about DSC are better contained.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 46 ----------------------
>  drivers/gpu/drm/i915/display/intel_vdsc.c  | 46 ++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_vdsc.h  |  1 +
>  3 files changed, 47 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index d376f7bccf21..9f38dd14b2d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -37,7 +37,6 @@
>  #include "intel_cdclk.h"
>  #include "intel_crtc.h"
>  #include "intel_de.h"
> -#include "intel_dp.h"
>  #include "intel_display_types.h"
>  #include "intel_mchbar_regs.h"
>  #include "intel_pci_config.h"
> @@ -2805,51 +2804,6 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	return min_cdclk;
>  }
>  
> -static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct intel_display *display = to_intel_display(crtc);
> -	int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
> -	int min_cdclk;
> -
> -	if (!crtc_state->dsc.compression_enable)
> -		return 0;
> -
> -	/*
> -	 * When we decide to use only one VDSC engine, since
> -	 * each VDSC operates with 1 ppc throughput, pixel clock
> -	 * cannot be higher than the VDSC clock (cdclk)
> -	 * If there 2 VDSC engines, then pixel clock can't be higher than
> -	 * VDSC clock(cdclk) * 2 and so on.
> -	 */
> -	min_cdclk = DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances);
> -
> -	if (crtc_state->joiner_pipes) {
> -		int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
> -
> -		/*
> -		 * According to Bigjoiner bw check:
> -		 * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
> -		 *
> -		 * We have already computed compressed_bpp, so now compute the min CDCLK that
> -		 * is required to support this compressed_bpp.
> -		 *
> -		 * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
> -		 *
> -		 * Since PPC = 2 with bigjoiner
> -		 * => CDCLK >= compressed_bpp * Pixel clock  / 2 * Bigjoiner Interface bits
> -		 */
> -		int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24;
> -		int min_cdclk_bj =
> -			(fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
> -			 pixel_clock) / (2 * bigjoiner_interface_bits);
> -
> -		min_cdclk = max(min_cdclk, min_cdclk_bj);
> -	}
> -
> -	return min_cdclk;
> -}
> -
>  int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>  {
>  	int min_cdclk;
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 40525f5c4c42..e6cb712373a9 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -14,6 +14,7 @@
>  #include "intel_crtc.h"
>  #include "intel_de.h"
>  #include "intel_display_types.h"
> +#include "intel_dp.h"
>  #include "intel_dsi.h"
>  #include "intel_qp_tables.h"
>  #include "intel_vdsc.h"
> @@ -1003,3 +1004,48 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent,
>  	intel_vdsc_dump_state(p, indent, crtc_state);
>  	drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);
>  }
> +
> +int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct intel_display *display = to_intel_display(crtc);
> +	int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
> +	int min_cdclk;
> +
> +	if (!crtc_state->dsc.compression_enable)
> +		return 0;
> +
> +	/*
> +	 * When we decide to use only one VDSC engine, since
> +	 * each VDSC operates with 1 ppc throughput, pixel clock
> +	 * cannot be higher than the VDSC clock (cdclk)
> +	 * If there 2 VDSC engines, then pixel clock can't be higher than
> +	 * VDSC clock(cdclk) * 2 and so on.
> +	 */
> +	min_cdclk = DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances);
> +
> +	if (crtc_state->joiner_pipes) {
> +		int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
> +
> +		/*
> +		 * According to Bigjoiner bw check:
> +		 * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
> +		 *
> +		 * We have already computed compressed_bpp, so now compute the min CDCLK that
> +		 * is required to support this compressed_bpp.
> +		 *
> +		 * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
> +		 *
> +		 * Since PPC = 2 with bigjoiner
> +		 * => CDCLK >= compressed_bpp * Pixel clock  / 2 * Bigjoiner Interface bits
> +		 */
> +		int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24;
> +		int min_cdclk_bj =
> +			(fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
> +			 pixel_clock) / (2 * bigjoiner_interface_bits);
> +
> +		min_cdclk = max(min_cdclk, min_cdclk_bj);
> +	}
> +
> +	return min_cdclk;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
> index 290b2e9b3482..9e2812f99dd7 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> @@ -31,5 +31,6 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
>  			    const struct intel_crtc_state *crtc_state);
>  void intel_vdsc_state_dump(struct drm_printer *p, int indent,
>  			   const struct intel_crtc_state *crtc_state);
> +int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state);
>  
>  #endif /* __INTEL_VDSC_H__ */

-- 
Jani Nikula, Intel

Re: [PATCH 11/11] drm/i915/cdclk: Unify cdclk max() parameter order

[Jani Nikula]

On Tue, 29 Oct 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> In some places we do
>  min_cdclk = max(min_cdclk, other_min_cdclk)
> and in other places we have the arguments swapped as
>  min_cdclk = max(other_min_cdclk, min_cdclk)
>
> Unify everyone to use the first order of arguments, because
> it looks cleaner, especially within intel_crtc_compute_min_cdclk()
> which is doing a lot of these back-to-back.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_audio.c |  8 ++++----
>  drivers/gpu/drm/i915/display/intel_bw.c    |  2 +-
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +++++++++---------
>  3 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index af0bfdc44072..047cc5a2ef1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -997,10 +997,10 @@ int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	    crtc_state->lane_count == 4) {
>  		if (DISPLAY_VER(display) == 10) {
>  			/* Display WA #1145: glk */
> -			min_cdclk = max(316800, min_cdclk);
> +			min_cdclk = max(min_cdclk, 316800);
>  		} else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) {
>  			/* Display WA #1144: skl,bxt */
> -			min_cdclk = max(432000, min_cdclk);
> +			min_cdclk = max(min_cdclk, 432000);
>  		}
>  	}
>  
> @@ -1009,7 +1009,7 @@ int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
>  	 */
>  	if (DISPLAY_VER(display) >= 9)
> -		min_cdclk = max(2 * 96000, min_cdclk);
> +		min_cdclk = max(min_cdclk, 2 * 96000);
>  
>  	/*
>  	 * "For DP audio configuration, cdclk frequency shall be set to
> @@ -1020,7 +1020,7 @@ int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	 */
>  	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
>  	    intel_crtc_has_dp_encoder(crtc_state))
> -		min_cdclk = max(crtc_state->port_clock, min_cdclk);
> +		min_cdclk = max(min_cdclk, crtc_state->port_clock);
>  
>  	return min_cdclk;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 47036d4abb33..5f91b009df0d 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -1256,7 +1256,7 @@ int intel_bw_min_cdclk(struct drm_i915_private *i915,
>  	min_cdclk = intel_bw_dbuf_min_cdclk(i915, bw_state);
>  
>  	for_each_pipe(i915, pipe)
> -		min_cdclk = max(bw_state->min_cdclk[pipe], min_cdclk);
> +		min_cdclk = max(min_cdclk, bw_state->min_cdclk[pipe]);
>  
>  	return min_cdclk;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 9f38dd14b2d8..f16a37ef7316 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2799,7 +2799,7 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	int min_cdclk = 0;
>  
>  	for_each_intel_plane_on_crtc(display->drm, crtc, plane)
> -		min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk);
> +		min_cdclk = max(min_cdclk, crtc_state->min_cdclk[plane->id]);
>  
>  	return min_cdclk;
>  }
> @@ -2812,10 +2812,10 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>  		return 0;
>  
>  	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
> -	min_cdclk = max(hsw_ips_min_cdclk(crtc_state), min_cdclk);
> -	min_cdclk = max(intel_audio_min_cdclk(crtc_state), min_cdclk);
> -	min_cdclk = max(vlv_dsi_min_cdclk(crtc_state), min_cdclk);
> -	min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
> +	min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state));
> +	min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state));
> +	min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state));
> +	min_cdclk = max(min_cdclk, intel_planes_min_cdclk(crtc_state));
>  	min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
>  
>  	return min_cdclk;
> @@ -2868,7 +2868,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
>  	min_cdclk = max(cdclk_state->force_min_cdclk,
>  			cdclk_state->bw_min_cdclk);
>  	for_each_pipe(display, pipe)
> -		min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
> +		min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]);
>  
>  	/*
>  	 * Avoid glk_force_audio_cdclk() causing excessive screen
> @@ -2880,7 +2880,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
>  	 */
>  	if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes &&
>  	    !is_power_of_2(cdclk_state->active_pipes))
> -		min_cdclk = max(2 * 96000, min_cdclk);
> +		min_cdclk = max(min_cdclk, 2 * 96000);
>  
>  	if (min_cdclk > display->cdclk.max_cdclk_freq) {
>  		drm_dbg_kms(display->drm,
> @@ -2936,8 +2936,8 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
>  
>  	min_voltage_level = 0;
>  	for_each_pipe(display, pipe)
> -		min_voltage_level = max(cdclk_state->min_voltage_level[pipe],
> -					min_voltage_level);
> +		min_voltage_level = max(min_voltage_level,
> +					cdclk_state->min_voltage_level[pipe]);
>  
>  	return min_voltage_level;
>  }

-- 
Jani Nikula, Intel

Re: [PATCH 06/11] drm/i915/cdclk: Extract vlv_dsi_min_cdclk()

[Ville Syrjälä]

On Wed, Oct 30, 2024 at 01:34:38PM +0200, Jani Nikula wrote:
> On Tue, 29 Oct 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Pull the DSI min cdclk calculation into a helper and hide
> > it inside vlv_dsi.c in order to keep most DSI related
> > details in one place.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 23 ++------------------
> >  drivers/gpu/drm/i915/display/vlv_dsi.c     | 25 ++++++++++++++++++++++
> >  drivers/gpu/drm/i915/display/vlv_dsi.h     |  8 +++++++
> >  3 files changed, 35 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 89d12c521411..e10378744607 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -46,6 +46,7 @@
> >  #include "intel_vdsc.h"
> >  #include "skl_watermark.h"
> >  #include "skl_watermark_regs.h"
> > +#include "vlv_dsi.h"
> >  #include "vlv_sideband.h"
> >  
> >  /**
> > @@ -2849,8 +2850,6 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
> >  
> >  int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> >  {
> > -	struct intel_display *display = to_intel_display(crtc_state);
> > -	struct drm_i915_private *dev_priv = to_i915(display->drm);
> >  	int min_cdclk;
> >  
> >  	if (!crtc_state->hw.enable)
> > @@ -2859,25 +2858,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> >  	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
> >  	min_cdclk = max(hsw_ips_min_cdclk(crtc_state), min_cdclk);
> >  	min_cdclk = max(intel_audio_min_cdclk(crtc_state), min_cdclk);
> > -
> > -	/*
> > -	 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
> > -	 * than 320000KHz.
> > -	 */
> > -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> > -	    IS_VALLEYVIEW(dev_priv))
> > -		min_cdclk = max(320000, min_cdclk);
> > -
> > -	/*
> > -	 * On Geminilake once the CDCLK gets as low as 79200
> > -	 * picture gets unstable, despite that values are
> > -	 * correct for DSI PLL and DE PLL.
> > -	 */
> > -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> > -	    IS_GEMINILAKE(dev_priv))
> > -		min_cdclk = max(158400, min_cdclk);
> > -
> > -	/* Account for additional needs from the planes */
> > +	min_cdclk = max(vlv_dsi_min_cdclk(crtc_state), min_cdclk);
> >  	min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
> >  
> >  	if (crtc_state->dsc.compression_enable)
> > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
> > index 9383eedee2d4..49a895589150 100644
> > --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> > @@ -1760,6 +1760,31 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
> >  	intel_dsi_log_params(intel_dsi);
> >  }
> >  
> > +int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > +	int min_cdclk = 0;
> > +
> > +	/*
> > +	 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
> > +	 * than 320000KHz.
> > +	 */
> > +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> > +	    IS_VALLEYVIEW(dev_priv))
> > +		min_cdclk = max(320000, min_cdclk);
> > +
> > +	/*
> > +	 * On Geminilake once the CDCLK gets as low as 79200
> > +	 * picture gets unstable, despite that values are
> > +	 * correct for DSI PLL and DE PLL.
> > +	 */
> > +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> > +	    IS_GEMINILAKE(dev_priv))
> > +		min_cdclk = max(158400, min_cdclk);
> > +
> > +	return min_cdclk;
> > +}
> > +
> >  typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi);
> >  
> >  /*
> > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.h b/drivers/gpu/drm/i915/display/vlv_dsi.h
> > index cf9d7b82f288..5f99059b4c48 100644
> > --- a/drivers/gpu/drm/i915/display/vlv_dsi.h
> > +++ b/drivers/gpu/drm/i915/display/vlv_dsi.h
> > @@ -8,13 +8,17 @@
> >  
> >  #include <linux/types.h>
> >  
> > +#include <drm/drm_mipi_dsi.h>
> > +
> 
> Huh, why is this required? At least it's unrelated to the patch.

Sorry meant to note that in the commit msg, but forgot.

xe fails to build without this:
../drivers/gpu/drm/i915/display/vlv_dsi.h:28:42: error: return type is an incomplete type

It looks like a forward declaration is not enough for
return types of static inline functions. i915 on the other
hand builds fine.

I suppose one alternative would be to declare is as just
'int' for xe.

> 
> Other than that,
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> 
> >  enum port;
> >  struct drm_i915_private;
> > +struct intel_crtc_state;
> >  struct intel_dsi;
> >  
> >  #ifdef I915
> >  void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
> >  enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
> > +int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state);
> >  void vlv_dsi_init(struct drm_i915_private *dev_priv);
> >  #else
> >  static inline void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
> > @@ -24,6 +28,10 @@ static inline enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt
> >  {
> >  	return 0;
> >  }
> > +static inline int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)
> > +{
> > +	return 0;
> > +}
> >  static inline void vlv_dsi_init(struct drm_i915_private *dev_priv)
> >  {
> >  }
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

Re: [PATCH 06/11] drm/i915/cdclk: Extract vlv_dsi_min_cdclk()

[Jani Nikula]

On Wed, 30 Oct 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Oct 30, 2024 at 01:34:38PM +0200, Jani Nikula wrote:
>> On Tue, 29 Oct 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > Pull the DSI min cdclk calculation into a helper and hide
>> > it inside vlv_dsi.c in order to keep most DSI related
>> > details in one place.
>> >
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 23 ++------------------
>> >  drivers/gpu/drm/i915/display/vlv_dsi.c     | 25 ++++++++++++++++++++++
>> >  drivers/gpu/drm/i915/display/vlv_dsi.h     |  8 +++++++
>> >  3 files changed, 35 insertions(+), 21 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> > index 89d12c521411..e10378744607 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> > @@ -46,6 +46,7 @@
>> >  #include "intel_vdsc.h"
>> >  #include "skl_watermark.h"
>> >  #include "skl_watermark_regs.h"
>> > +#include "vlv_dsi.h"
>> >  #include "vlv_sideband.h"
>> >  
>> >  /**
>> > @@ -2849,8 +2850,6 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
>> >  
>> >  int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>> >  {
>> > -	struct intel_display *display = to_intel_display(crtc_state);
>> > -	struct drm_i915_private *dev_priv = to_i915(display->drm);
>> >  	int min_cdclk;
>> >  
>> >  	if (!crtc_state->hw.enable)
>> > @@ -2859,25 +2858,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>> >  	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
>> >  	min_cdclk = max(hsw_ips_min_cdclk(crtc_state), min_cdclk);
>> >  	min_cdclk = max(intel_audio_min_cdclk(crtc_state), min_cdclk);
>> > -
>> > -	/*
>> > -	 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
>> > -	 * than 320000KHz.
>> > -	 */
>> > -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
>> > -	    IS_VALLEYVIEW(dev_priv))
>> > -		min_cdclk = max(320000, min_cdclk);
>> > -
>> > -	/*
>> > -	 * On Geminilake once the CDCLK gets as low as 79200
>> > -	 * picture gets unstable, despite that values are
>> > -	 * correct for DSI PLL and DE PLL.
>> > -	 */
>> > -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
>> > -	    IS_GEMINILAKE(dev_priv))
>> > -		min_cdclk = max(158400, min_cdclk);
>> > -
>> > -	/* Account for additional needs from the planes */
>> > +	min_cdclk = max(vlv_dsi_min_cdclk(crtc_state), min_cdclk);
>> >  	min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
>> >  
>> >  	if (crtc_state->dsc.compression_enable)
>> > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
>> > index 9383eedee2d4..49a895589150 100644
>> > --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
>> > +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
>> > @@ -1760,6 +1760,31 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
>> >  	intel_dsi_log_params(intel_dsi);
>> >  }
>> >  
>> > +int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)
>> > +{
>> > +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>> > +	int min_cdclk = 0;
>> > +
>> > +	/*
>> > +	 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
>> > +	 * than 320000KHz.
>> > +	 */
>> > +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
>> > +	    IS_VALLEYVIEW(dev_priv))
>> > +		min_cdclk = max(320000, min_cdclk);
>> > +
>> > +	/*
>> > +	 * On Geminilake once the CDCLK gets as low as 79200
>> > +	 * picture gets unstable, despite that values are
>> > +	 * correct for DSI PLL and DE PLL.
>> > +	 */
>> > +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
>> > +	    IS_GEMINILAKE(dev_priv))
>> > +		min_cdclk = max(158400, min_cdclk);
>> > +
>> > +	return min_cdclk;
>> > +}
>> > +
>> >  typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi);
>> >  
>> >  /*
>> > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.h b/drivers/gpu/drm/i915/display/vlv_dsi.h
>> > index cf9d7b82f288..5f99059b4c48 100644
>> > --- a/drivers/gpu/drm/i915/display/vlv_dsi.h
>> > +++ b/drivers/gpu/drm/i915/display/vlv_dsi.h
>> > @@ -8,13 +8,17 @@
>> >  
>> >  #include <linux/types.h>
>> >  
>> > +#include <drm/drm_mipi_dsi.h>
>> > +
>> 
>> Huh, why is this required? At least it's unrelated to the patch.
>
> Sorry meant to note that in the commit msg, but forgot.
>
> xe fails to build without this:
> ../drivers/gpu/drm/i915/display/vlv_dsi.h:28:42: error: return type is an incomplete type
>
> It looks like a forward declaration is not enough for
> return types of static inline functions. i915 on the other
> hand builds fine.
>
> I suppose one alternative would be to declare is as just
> 'int' for xe.

I think I've actually snuck in some of those int usages in the past,
because in the end it doesn't really matter for the inline stubs.

BR,
Jani.

>
>> 
>> Other than that,
>> 
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>> 
>> 
>> >  enum port;
>> >  struct drm_i915_private;
>> > +struct intel_crtc_state;
>> >  struct intel_dsi;
>> >  
>> >  #ifdef I915
>> >  void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
>> >  enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
>> > +int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state);
>> >  void vlv_dsi_init(struct drm_i915_private *dev_priv);
>> >  #else
>> >  static inline void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
>> > @@ -24,6 +28,10 @@ static inline enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt
>> >  {
>> >  	return 0;
>> >  }
>> > +static inline int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)
>> > +{
>> > +	return 0;
>> > +}
>> >  static inline void vlv_dsi_init(struct drm_i915_private *dev_priv)
>> >  {
>> >  }
>> 
>> -- 
>> Jani Nikula, Intel

-- 
Jani Nikula, Intel

✗ Fi.CI.CHECKPATCH: warning for drm/i915/cdclk: Declutter CDCLK code (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/cdclk: Declutter CDCLK code (rev2)
URL   : https://patchwork.freedesktop.org/series/140697/
State : warning

== Summary ==

Error: dim checkpatch failed
d8c52943046e drm/i915: Introduce HAS_DOUBLE_WIDE()
2baaa2d9b614 drm/i915/cdclk: Extract intel_cdclk_guardband() and intel_cdclk_ppc()
1e6f8f727313 drm/i915/cdclk: Extract hsw_ips_min_cdclk()
-:16: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#16: 
+ min_cdclk = max(DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95), min_cdclk)

-:76: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#76: FILE: drivers/gpu/drm/i915/display/hsw_ips.h:45:
 }
+static inline int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)

total: 0 errors, 1 warnings, 1 checks, 58 lines checked
6d2a43667aad drm/i915/cdclk: Extract intel_audio_min_cdclk()
69906fad0988 drm/i915/cdclk: Factor out has_audio check in intel_audio_min_cdclk()
5377ab4abb63 drm/i915/cdclk: Extract vlv_dsi_min_cdclk()
-:126: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#126: FILE: drivers/gpu/drm/i915/display/vlv_dsi.h:31:
 }
+static inline int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)

total: 0 errors, 0 warnings, 1 checks, 99 lines checked
cea5a791510f drm/i915/cdclk: Factor out INTEL_OUTPUT_DSI check in vlv_dsi_min_cdclk()
e89f3af380be drm/i915/cdclk: Suck the compression_enable check into intel_vdsc_min_cdclk()
de864b393cb9 drm/i915/cdclk: Drop pointles max_t() usage in intel_vdsc_min_cdclk()
edb8e292f20a drm/i915/cdclk: Relocate intel_vdsc_min_cdclk()
d440b77a3370 drm/i915/cdclk: Unify cdclk max() parameter order

✗ Fi.CI.SPARSE: warning for drm/i915/cdclk: Declutter CDCLK code (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/cdclk: Declutter CDCLK code (rev2)
URL   : https://patchwork.freedesktop.org/series/140697/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✓ Fi.CI.BAT: success for drm/i915/cdclk: Declutter CDCLK code (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3691 bytes --]

== Series Details ==

Series: drm/i915/cdclk: Declutter CDCLK code (rev2)
URL   : https://patchwork.freedesktop.org/series/140697/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_15619 -> Patchwork_140697v2
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/index.html

Participating hosts (46 -> 45)
------------------------------

  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_140697v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [PASS][1] -> [ABORT][2] ([i915#12133] / [i915#12216])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/bat-mtlp-8/igt@i915_selftest@live.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/bat-mtlp-8/igt@i915_selftest@live.html
    - bat-arlh-3:         [PASS][3] -> [ABORT][4] ([i915#12133])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/bat-arlh-3/igt@i915_selftest@live.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/bat-arlh-3/igt@i915_selftest@live.html

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-3:         [PASS][5] -> [ABORT][6] ([i915#12061])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/bat-arlh-3/igt@i915_selftest@live@workarounds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/bat-arlh-3/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-8:         [PASS][7] -> [ABORT][8] ([i915#12216])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/bat-mtlp-8/igt@i915_selftest@live@workarounds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/bat-mtlp-8/igt@i915_selftest@live@workarounds.html

  * igt@kms_chamelium_edid@hdmi-edid-read:
    - bat-dg2-13:         [PASS][9] -> [DMESG-WARN][10] ([i915#12253])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/bat-dg2-13/igt@kms_chamelium_edid@hdmi-edid-read.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/bat-dg2-13/igt@kms_chamelium_edid@hdmi-edid-read.html

  
#### Possible fixes ####

  * igt@i915_selftest@live:
    - bat-mtlp-6:         [ABORT][11] ([i915#12133] / [i915#12216]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/bat-mtlp-6/igt@i915_selftest@live.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/bat-mtlp-6/igt@i915_selftest@live.html

  * igt@i915_selftest@live@workarounds:
    - bat-mtlp-6:         [ABORT][13] ([i915#12216]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/bat-mtlp-6/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12133]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12133
  [i915#12216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12216
  [i915#12253]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12253


Build changes
-------------

  * Linux: CI_DRM_15619 -> Patchwork_140697v2

  CI-20190529: 20190529
  CI_DRM_15619: fa53c85519aa642bf10aa1692a1b99d1930d2809 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8091: 8091
  Patchwork_140697v2: fa53c85519aa642bf10aa1692a1b99d1930d2809 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/index.html

[-- Attachment #2: Type: text/html, Size: 4783 bytes --]

✗ Fi.CI.IGT: failure for drm/i915/cdclk: Declutter CDCLK code (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 78148 bytes --]

== Series Details ==

Series: drm/i915/cdclk: Declutter CDCLK code (rev2)
URL   : https://patchwork.freedesktop.org/series/140697/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_15619_full -> Patchwork_140697v2_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_140697v2_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_140697v2_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_140697v2_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@blocking-wf_vblank@b-hdmi-a1:
    - shard-snb:          NOTRUN -> [INCOMPLETE][1] +1 other test incomplete
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-snb2/igt@kms_flip@blocking-wf_vblank@b-hdmi-a1.html

  * igt@kms_hdr@brightness-with-hdr@pipe-a-dp-3:
    - shard-dg2:          NOTRUN -> [FAIL][2] +1 other test fail
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-10/igt@kms_hdr@brightness-with-hdr@pipe-a-dp-3.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-mtlp:         [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-mtlp-3/igt@kms_pm_dc@dc5-psr.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-6/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_vblank@wait-forked:
    - shard-glk:          NOTRUN -> [INCOMPLETE][5]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-glk9/igt@kms_vblank@wait-forked.html

  
Known issues
------------

  Here are the changes found in Patchwork_140697v2_full that come from known issues:

### CI changes ###

#### Possible fixes ####

  * boot:
    - {shard-dg2-9}:      ([PASS][6], [PASS][7], [FAIL][8]) -> ([PASS][9], [PASS][10], [PASS][11])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg2-9/boot.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg2-9/boot.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg2-9/boot.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-9/boot.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-9/boot.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-9/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@drm_fdinfo@busy-idle@bcs0:
    - shard-dg2:          NOTRUN -> [SKIP][12] ([i915#8414]) +10 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-11/igt@drm_fdinfo@busy-idle@bcs0.html

  * igt@gem_basic@multigpu-create-close:
    - shard-dg2:          NOTRUN -> [SKIP][13] ([i915#7697])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-11/igt@gem_basic@multigpu-create-close.html

  * igt@gem_busy@close-race:
    - shard-tglu-1:       NOTRUN -> [FAIL][14] ([i915#12297] / [i915#12577])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@gem_busy@close-race.html

  * igt@gem_ccs@block-copy-compressed:
    - shard-tglu-1:       NOTRUN -> [SKIP][15] ([i915#3555] / [i915#9323])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_ccs@suspend-resume:
    - shard-tglu:         NOTRUN -> [SKIP][16] ([i915#9323])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@gem_ccs@suspend-resume.html

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-tglu-1:       NOTRUN -> [SKIP][17] ([i915#6335])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_ctx_sseu@invalid-sseu:
    - shard-dg2:          NOTRUN -> [SKIP][18] ([i915#280])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-3/igt@gem_ctx_sseu@invalid-sseu.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-tglu-1:       NOTRUN -> [SKIP][19] ([i915#280]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_eio@reset-stress:
    - shard-dg1:          [PASS][20] -> [FAIL][21] ([i915#12543] / [i915#5784])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg1-12/igt@gem_eio@reset-stress.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-14/igt@gem_eio@reset-stress.html

  * igt@gem_exec_balancer@bonded-true-hang:
    - shard-dg2:          NOTRUN -> [SKIP][22] ([i915#4812]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-10/igt@gem_exec_balancer@bonded-true-hang.html

  * igt@gem_exec_balancer@noheartbeat:
    - shard-dg2:          NOTRUN -> [SKIP][23] ([i915#8555]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-3/igt@gem_exec_balancer@noheartbeat.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglu:         [PASS][24] -> [FAIL][25] ([i915#2842]) +1 other test fail
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-tglu-8/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-8/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-tglu-1:       NOTRUN -> [FAIL][26] ([i915#2842]) +1 other test fail
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-rkl:          [PASS][27] -> [FAIL][28] ([i915#2842]) +5 other tests fail
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-rkl-6/igt@gem_exec_fair@basic-pace@vecs0.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-rkl-6/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_fence@concurrent:
    - shard-mtlp:         NOTRUN -> [SKIP][29] ([i915#4812])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-2/igt@gem_exec_fence@concurrent.html

  * igt@gem_exec_flush@basic-uc-ro-default:
    - shard-dg2:          NOTRUN -> [SKIP][30] ([i915#3539] / [i915#4852]) +2 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-11/igt@gem_exec_flush@basic-uc-ro-default.html

  * igt@gem_exec_params@secure-non-master:
    - shard-dg2:          NOTRUN -> [SKIP][31] +11 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-10/igt@gem_exec_params@secure-non-master.html

  * igt@gem_exec_reloc@basic-cpu-gtt-active:
    - shard-mtlp:         NOTRUN -> [SKIP][32] ([i915#3281])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-4/igt@gem_exec_reloc@basic-cpu-gtt-active.html

  * igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
    - shard-dg2:          NOTRUN -> [SKIP][33] ([i915#3281]) +9 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-3/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html

  * igt@gem_exec_schedule@preempt-queue:
    - shard-dg2:          NOTRUN -> [SKIP][34] ([i915#4537] / [i915#4812])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@gem_exec_schedule@preempt-queue.html

  * igt@gem_exec_schedule@preempt-queue-contexts:
    - shard-mtlp:         NOTRUN -> [SKIP][35] ([i915#4537] / [i915#4812])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-7/igt@gem_exec_schedule@preempt-queue-contexts.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-tglu:         NOTRUN -> [SKIP][36] ([i915#4613] / [i915#7582])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@massive:
    - shard-glk:          NOTRUN -> [SKIP][37] ([i915#4613])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-glk6/igt@gem_lmem_swapping@massive.html

  * igt@gem_lmem_swapping@parallel-multi:
    - shard-tglu:         NOTRUN -> [SKIP][38] ([i915#4613])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@gem_lmem_swapping@parallel-multi.html

  * igt@gem_media_vme:
    - shard-tglu-1:       NOTRUN -> [SKIP][39] ([i915#284])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@gem_media_vme.html

  * igt@gem_mmap_gtt@zero-extend:
    - shard-dg2:          NOTRUN -> [SKIP][40] ([i915#4077]) +9 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@gem_mmap_gtt@zero-extend.html

  * igt@gem_mmap_offset@clear:
    - shard-mtlp:         [PASS][41] -> [ABORT][42] ([i915#10729])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-mtlp-5/igt@gem_mmap_offset@clear.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-6/igt@gem_mmap_offset@clear.html

  * igt@gem_mmap_offset@clear@smem0:
    - shard-mtlp:         [PASS][43] -> [ABORT][44] ([i915#10029] / [i915#10729])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-mtlp-5/igt@gem_mmap_offset@clear@smem0.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-6/igt@gem_mmap_offset@clear@smem0.html

  * igt@gem_mmap_wc@close:
    - shard-dg2:          NOTRUN -> [SKIP][45] ([i915#4083]) +5 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@gem_mmap_wc@close.html
    - shard-mtlp:         NOTRUN -> [SKIP][46] ([i915#4083]) +2 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-2/igt@gem_mmap_wc@close.html

  * igt@gem_mmap_wc@read-write-distinct:
    - shard-dg1:          NOTRUN -> [SKIP][47] ([i915#4083]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-17/igt@gem_mmap_wc@read-write-distinct.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
    - shard-dg2:          NOTRUN -> [SKIP][48] ([i915#3282]) +3 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-11/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-mtlp:         NOTRUN -> [SKIP][49] ([i915#3282])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-4/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@create-regular-buffer:
    - shard-rkl:          NOTRUN -> [SKIP][50] ([i915#4270])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-rkl-2/igt@gem_pxp@create-regular-buffer.html

  * igt@gem_pxp@protected-raw-src-copy-not-readible:
    - shard-dg2:          NOTRUN -> [SKIP][51] ([i915#4270]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@gem_pxp@protected-raw-src-copy-not-readible.html

  * igt@gem_pxp@reject-modify-context-protection-off-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][52] ([i915#4270]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@gem_pxp@reject-modify-context-protection-off-1.html

  * igt@gem_pxp@reject-modify-context-protection-off-3:
    - shard-tglu:         NOTRUN -> [SKIP][53] ([i915#4270])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@gem_pxp@reject-modify-context-protection-off-3.html

  * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][54] ([i915#8428])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-8/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html

  * igt@gem_render_copy@yf-tiled-to-vebox-linear:
    - shard-dg2:          NOTRUN -> [SKIP][55] ([i915#5190] / [i915#8428]) +4 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-11/igt@gem_render_copy@yf-tiled-to-vebox-linear.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][56] ([i915#4079])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_softpin@evict-snoop-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][57] ([i915#4885])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-10/igt@gem_softpin@evict-snoop-interruptible.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-tglu-1:       NOTRUN -> [SKIP][58] ([i915#3297]) +3 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-rkl:          NOTRUN -> [SKIP][59] ([i915#3297] / [i915#3323])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-rkl-2/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy:
    - shard-dg2:          NOTRUN -> [SKIP][60] ([i915#3297] / [i915#4880]) +1 other test skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-11/igt@gem_userptr_blits@map-fixed-invalidate-busy.html

  * igt@gem_userptr_blits@unsync-unmap:
    - shard-dg2:          NOTRUN -> [SKIP][61] ([i915#3297])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-11/igt@gem_userptr_blits@unsync-unmap.html

  * igt@gen9_exec_parse@bb-large:
    - shard-dg1:          NOTRUN -> [SKIP][62] ([i915#2527]) +1 other test skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-17/igt@gen9_exec_parse@bb-large.html
    - shard-mtlp:         NOTRUN -> [SKIP][63] ([i915#2856])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-8/igt@gen9_exec_parse@bb-large.html

  * igt@gen9_exec_parse@bb-start-cmd:
    - shard-tglu:         NOTRUN -> [SKIP][64] ([i915#2527] / [i915#2856]) +1 other test skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@gen9_exec_parse@bb-start-cmd.html

  * igt@gen9_exec_parse@bb-start-out:
    - shard-dg2:          NOTRUN -> [SKIP][65] ([i915#2856])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@gen9_exec_parse@bb-start-out.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-tglu-1:       NOTRUN -> [SKIP][66] ([i915#2527] / [i915#2856]) +2 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_pm_freq_api@freq-basic-api:
    - shard-tglu-1:       NOTRUN -> [SKIP][67] ([i915#8399]) +1 other test skip
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@i915_pm_freq_api@freq-basic-api.html

  * igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0:
    - shard-dg1:          [PASS][68] -> [FAIL][69] ([i915#12548] / [i915#3591]) +1 other test fail
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html

  * igt@i915_pm_rps@basic-api:
    - shard-dg2:          NOTRUN -> [SKIP][70] ([i915#11681] / [i915#6621])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-10/igt@i915_pm_rps@basic-api.html

  * igt@i915_pm_rps@thresholds-idle:
    - shard-dg2:          NOTRUN -> [SKIP][71] ([i915#11681])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@i915_pm_rps@thresholds-idle.html

  * igt@i915_pm_sseu@full-enable:
    - shard-tglu:         NOTRUN -> [SKIP][72] ([i915#4387])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@i915_pm_sseu@full-enable.html

  * igt@i915_power@sanity:
    - shard-mtlp:         [PASS][73] -> [SKIP][74] ([i915#7984])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-mtlp-4/igt@i915_power@sanity.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-7/igt@i915_power@sanity.html

  * igt@i915_query@test-query-geometry-subslices:
    - shard-tglu-1:       NOTRUN -> [SKIP][75] ([i915#5723])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@i915_query@test-query-geometry-subslices.html

  * igt@kms_addfb_basic@basic-x-tiled-legacy:
    - shard-dg2:          NOTRUN -> [SKIP][76] ([i915#4212]) +3 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-10/igt@kms_addfb_basic@basic-x-tiled-legacy.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-dg2:          NOTRUN -> [SKIP][77] ([i915#9531])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@modeset-transition-fencing:
    - shard-glk:          [PASS][78] -> [FAIL][79] ([i915#12238])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-glk3/igt@kms_atomic_transition@modeset-transition-fencing.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-glk8/igt@kms_atomic_transition@modeset-transition-fencing.html

  * igt@kms_atomic_transition@modeset-transition-fencing@2x-outputs:
    - shard-glk:          [PASS][80] -> [FAIL][81] ([i915#11859]) +1 other test fail
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-glk3/igt@kms_atomic_transition@modeset-transition-fencing@2x-outputs.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-glk8/igt@kms_atomic_transition@modeset-transition-fencing@2x-outputs.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking:
    - shard-glk:          [PASS][82] -> [FAIL][83] ([i915#12177])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-glk3/igt@kms_atomic_transition@modeset-transition-nonblocking.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-0:
    - shard-dg1:          NOTRUN -> [SKIP][84] ([i915#4538] / [i915#5286])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-17/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-180:
    - shard-tglu-1:       NOTRUN -> [SKIP][85] ([i915#5286]) +3 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0:
    - shard-tglu:         NOTRUN -> [SKIP][86] ([i915#5286])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
    - shard-dg2:          NOTRUN -> [SKIP][87] ([i915#4538] / [i915#5190]) +9 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb-size-overflow:
    - shard-dg2:          NOTRUN -> [SKIP][88] ([i915#5190]) +1 other test skip
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-11/igt@kms_big_fb@y-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
    - shard-dg1:          NOTRUN -> [SKIP][89] ([i915#4538])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-17/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
    - shard-mtlp:         NOTRUN -> [SKIP][90] +1 other test skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][91] ([i915#6095]) +135 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-14/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc:
    - shard-mtlp:         NOTRUN -> [SKIP][92] ([i915#6095]) +9 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-4/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][93] ([i915#6095]) +14 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][94] ([i915#6095]) +53 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-rkl-3/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [SKIP][95] +41 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-glk6/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][96] ([i915#10307] / [i915#6095]) +95 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-3/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][97] ([i915#12313])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][98] ([i915#6095]) +39 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][99] ([i915#4423] / [i915#6095]) +1 other test skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-17/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-4.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][100] ([i915#10307] / [i915#10434] / [i915#6095]) +1 other test skip
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][101] ([i915#11616] / [i915#7213]) +4 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-tglu:         NOTRUN -> [SKIP][102] ([i915#7828]) +1 other test skip
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_chamelium_frames@dp-frame-dump:
    - shard-dg2:          NOTRUN -> [SKIP][103] ([i915#7828]) +9 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-10/igt@kms_chamelium_frames@dp-frame-dump.html

  * igt@kms_chamelium_hpd@dp-hpd-for-each-pipe:
    - shard-mtlp:         NOTRUN -> [SKIP][104] ([i915#7828]) +1 other test skip
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-4/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html

  * igt@kms_chamelium_hpd@dp-hpd-storm-disable:
    - shard-tglu-1:       NOTRUN -> [SKIP][105] ([i915#7828]) +5 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html

  * igt@kms_chamelium_hpd@vga-hpd-after-suspend:
    - shard-dg1:          NOTRUN -> [SKIP][106] ([i915#7828])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-17/igt@kms_chamelium_hpd@vga-hpd-after-suspend.html

  * igt@kms_content_protection@atomic:
    - shard-tglu-1:       NOTRUN -> [SKIP][107] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@content-type-change:
    - shard-tglu-1:       NOTRUN -> [SKIP][108] ([i915#6944] / [i915#9424]) +1 other test skip
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@type1:
    - shard-tglu:         NOTRUN -> [SKIP][109] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-onscreen-512x170:
    - shard-dg2:          NOTRUN -> [SKIP][110] ([i915#11453] / [i915#3359])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-10/igt@kms_cursor_crc@cursor-onscreen-512x170.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-tglu-1:       NOTRUN -> [SKIP][111] ([i915#11453] / [i915#3359]) +2 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x512:
    - shard-tglu:         NOTRUN -> [SKIP][112] ([i915#11453] / [i915#3359])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
    - shard-dg1:          NOTRUN -> [SKIP][113] ([i915#4423])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-17/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
    - shard-mtlp:         NOTRUN -> [SKIP][114] ([i915#9809])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-8/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-glk:          [PASS][115] -> [FAIL][116] ([i915#2346])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-dg2:          NOTRUN -> [SKIP][117] ([i915#4103] / [i915#4213])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-tglu-1:       NOTRUN -> [SKIP][118] ([i915#4103])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_display_modes@mst-extended-mode-negative:
    - shard-dg2:          NOTRUN -> [SKIP][119] ([i915#8588])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-11/igt@kms_display_modes@mst-extended-mode-negative.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
    - shard-dg2:          NOTRUN -> [SKIP][120] ([i915#3555]) +2 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-11/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html

  * igt@kms_dp_aux_dev:
    - shard-dg2:          NOTRUN -> [SKIP][121] ([i915#1257])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@kms_dp_aux_dev.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-tglu:         NOTRUN -> [SKIP][122] ([i915#3555] / [i915#3840])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_fbcon_fbt@psr:
    - shard-tglu:         NOTRUN -> [SKIP][123] ([i915#3469])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@psr1:
    - shard-tglu-1:       NOTRUN -> [SKIP][124] ([i915#658])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
    - shard-dg1:          NOTRUN -> [SKIP][125] ([i915#9934])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-17/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-plain-flip:
    - shard-tglu-1:       NOTRUN -> [SKIP][126] ([i915#3637]) +5 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a2:
    - shard-dg2:          [PASS][127] -> [FAIL][128] ([i915#2122]) +1 other test fail
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg2-11/igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a2.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-11/igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a2.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a1:
    - shard-rkl:          NOTRUN -> [FAIL][129] ([i915#2122]) +3 other tests fail
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-rkl-2/igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a1.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@b-vga1:
    - shard-snb:          [PASS][130] -> [FAIL][131] ([i915#2122]) +8 other tests fail
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-snb1/igt@kms_flip@flip-vs-absolute-wf_vblank@b-vga1.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-snb1/igt@kms_flip@flip-vs-absolute-wf_vblank@b-vga1.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-dg1:          [PASS][132] -> [DMESG-WARN][133] ([i915#4423]) +5 other tests dmesg-warn
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg1-18/igt@kms_flip@flip-vs-suspend.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-13/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-mtlp:         [PASS][134] -> [INCOMPLETE][135] ([i915#6113])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-mtlp-3/igt@kms_flip@flip-vs-suspend-interruptible.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1:
    - shard-snb:          [PASS][136] -> [INCOMPLETE][137] ([i915#4839]) +1 other test incomplete
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-snb2/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-snb4/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a2:
    - shard-dg2:          NOTRUN -> [INCOMPLETE][138] ([i915#4839] / [i915#6113]) +1 other test incomplete
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-11/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a2.html

  * igt@kms_flip@flip-vs-suspend-interruptible@d-edp1:
    - shard-mtlp:         [PASS][139] -> [INCOMPLETE][140] ([i915#10056] / [i915#6113])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-mtlp-3/igt@kms_flip@flip-vs-suspend-interruptible@d-edp1.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-1/igt@kms_flip@flip-vs-suspend-interruptible@d-edp1.html

  * igt@kms_flip@flip-vs-suspend@b-hdmi-a3:
    - shard-dg1:          NOTRUN -> [DMESG-WARN][141] ([i915#4423]) +1 other test dmesg-warn
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-13/igt@kms_flip@flip-vs-suspend@b-hdmi-a3.html

  * igt@kms_flip@plain-flip-fb-recreate:
    - shard-rkl:          [PASS][142] -> [FAIL][143] ([i915#2122])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-rkl-3/igt@kms_flip@plain-flip-fb-recreate.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-rkl-4/igt@kms_flip@plain-flip-fb-recreate.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible:
    - shard-glk:          [PASS][144] -> [FAIL][145] ([i915#2122]) +1 other test fail
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-glk3/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-glk6/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
    - shard-dg1:          [PASS][146] -> [FAIL][147] ([i915#2122])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg1-12/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-14/igt@kms_flip@plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-hdmi-a1:
    - shard-dg2:          NOTRUN -> [FAIL][148] ([i915#2122]) +3 other tests fail
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-hdmi-a1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-hdmi-a4:
    - shard-dg1:          NOTRUN -> [FAIL][149] ([i915#2122]) +2 other tests fail
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-14/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-hdmi-a4.html

  * igt@kms_flip@plain-flip-fb-recreate@c-hdmi-a1:
    - shard-tglu:         [PASS][150] -> [FAIL][151] ([i915#2122]) +6 other tests fail
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-tglu-2/igt@kms_flip@plain-flip-fb-recreate@c-hdmi-a1.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-7/igt@kms_flip@plain-flip-fb-recreate@c-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode:
    - shard-tglu-1:       NOTRUN -> [SKIP][152] ([i915#2587] / [i915#2672]) +2 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
    - shard-tglu:         NOTRUN -> [SKIP][153] ([i915#2672] / [i915#3555]) +1 other test skip
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][154] ([i915#2587] / [i915#2672]) +1 other test skip
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
    - shard-snb:          NOTRUN -> [SKIP][155] +25 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-snb5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
    - shard-dg2:          NOTRUN -> [SKIP][156] ([i915#2672] / [i915#3555] / [i915#5190])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][157] ([i915#2672] / [i915#3555]) +2 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
    - shard-dg2:          NOTRUN -> [SKIP][158] ([i915#2672] / [i915#3555]) +1 other test skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-10/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][159] ([i915#2672]) +2 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-10/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][160] ([i915#8708]) +17 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
    - shard-dg2:          [PASS][161] -> [FAIL][162] ([i915#6880])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][163] ([i915#8708])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][164] ([i915#3458]) +11 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][165] ([i915#5354]) +32 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-fullscreen:
    - shard-tglu:         NOTRUN -> [SKIP][166] +15 other tests skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy:
    - shard-dg1:          NOTRUN -> [SKIP][167] ([i915#3458])
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-tglu-1:       NOTRUN -> [SKIP][168] ([i915#5439])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@pipe-fbc-rte:
    - shard-dg2:          NOTRUN -> [SKIP][169] ([i915#9766])
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-2p-pri-indfb-multidraw:
    - shard-dg1:          NOTRUN -> [SKIP][170] +5 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-cpu:
    - shard-mtlp:         NOTRUN -> [SKIP][171] ([i915#1825]) +4 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc:
    - shard-tglu-1:       NOTRUN -> [SKIP][172] +60 other tests skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html

  * igt@kms_getfb@getfb-reject-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][173] ([i915#6118])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-11/igt@kms_getfb@getfb-reject-ccs.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-tglu:         NOTRUN -> [SKIP][174] ([i915#433])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-dg2:          NOTRUN -> [SKIP][175] ([i915#3555] / [i915#8228])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][176] ([i915#12339])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-dg2:          NOTRUN -> [SKIP][177] ([i915#6301]) +1 other test skip
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-tglu-1:       NOTRUN -> [SKIP][178] ([i915#3555]) +3 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
    - shard-dg2:          NOTRUN -> [SKIP][179] ([i915#12247] / [i915#6953] / [i915#9423])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-a:
    - shard-dg2:          NOTRUN -> [SKIP][180] ([i915#12247]) +3 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-a.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
    - shard-tglu-1:       NOTRUN -> [SKIP][181] ([i915#12247] / [i915#6953])
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c:
    - shard-tglu-1:       NOTRUN -> [SKIP][182] ([i915#12247]) +8 other tests skip
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-tglu:         NOTRUN -> [SKIP][183] ([i915#12343])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-tglu-1:       NOTRUN -> [SKIP][184] ([i915#9685])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][185] ([i915#5978])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@kms_pm_dc@dc6-dpms.html
    - shard-mtlp:         NOTRUN -> [SKIP][186] ([i915#10139])
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-2/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_lpsp@screens-disabled:
    - shard-tglu-1:       NOTRUN -> [SKIP][187] ([i915#8430])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_pm_lpsp@screens-disabled.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-rkl:          [PASS][188] -> [SKIP][189] ([i915#9519])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp.html
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-rkl-2/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-tglu:         NOTRUN -> [SKIP][190] ([i915#11520]) +1 other test skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf:
    - shard-dg2:          NOTRUN -> [SKIP][191] ([i915#11520]) +7 other tests skip
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area:
    - shard-mtlp:         NOTRUN -> [SKIP][192] ([i915#12316])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-4/igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-tglu-1:       NOTRUN -> [SKIP][193] ([i915#11520]) +4 other tests skip
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
    - shard-glk:          NOTRUN -> [SKIP][194] ([i915#11520]) +3 other tests skip
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-glk9/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-snb:          NOTRUN -> [SKIP][195] ([i915#11520])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-snb5/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html
    - shard-dg1:          NOTRUN -> [SKIP][196] ([i915#11520])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-17/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area:
    - shard-rkl:          NOTRUN -> [SKIP][197] ([i915#11520])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-rkl-2/igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-tglu-1:       NOTRUN -> [SKIP][198] ([i915#9683])
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-dg2:          NOTRUN -> [SKIP][199] ([i915#9683])
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-10/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-pr-cursor-blt:
    - shard-mtlp:         NOTRUN -> [SKIP][200] ([i915#9688])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-8/igt@kms_psr@fbc-pr-cursor-blt.html

  * igt@kms_psr@fbc-psr2-primary-mmap-gtt:
    - shard-tglu:         NOTRUN -> [SKIP][201] ([i915#9732]) +4 other tests skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@kms_psr@fbc-psr2-primary-mmap-gtt.html

  * igt@kms_psr@psr-sprite-mmap-cpu:
    - shard-tglu-1:       NOTRUN -> [SKIP][202] ([i915#9732]) +15 other tests skip
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_psr@psr-sprite-mmap-cpu.html

  * igt@kms_psr@psr-sprite-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][203] ([i915#1072] / [i915#9732]) +1 other test skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-17/igt@kms_psr@psr-sprite-mmap-gtt.html

  * igt@kms_psr@psr-sprite-mmap-gtt@edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][204] ([i915#4077] / [i915#9688]) +1 other test skip
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-8/igt@kms_psr@psr-sprite-mmap-gtt@edp-1.html

  * igt@kms_psr@psr2-cursor-plane-move:
    - shard-rkl:          NOTRUN -> [SKIP][205] ([i915#1072] / [i915#9732])
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-rkl-2/igt@kms_psr@psr2-cursor-plane-move.html

  * igt@kms_psr@psr2-primary-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][206] ([i915#1072] / [i915#9732]) +16 other tests skip
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-11/igt@kms_psr@psr2-primary-mmap-gtt.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-dg2:          NOTRUN -> [SKIP][207] ([i915#9685])
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-dg2:          NOTRUN -> [SKIP][208] ([i915#11131] / [i915#4235])
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@kms_setmode@basic:
    - shard-tglu-1:       NOTRUN -> [FAIL][209] ([i915#5465]) +1 other test fail
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_setmode@basic.html
    - shard-mtlp:         [PASS][210] -> [FAIL][211] ([i915#5465]) +1 other test fail
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-mtlp-3/igt@kms_setmode@basic.html
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-6/igt@kms_setmode@basic.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-tglu-1:       NOTRUN -> [SKIP][212] ([i915#8623])
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vblank@wait-forked@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][213] ([i915#12276])
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-glk9/igt@kms_vblank@wait-forked@pipe-a-hdmi-a-1.html

  * igt@kms_vrr@max-min:
    - shard-tglu:         NOTRUN -> [SKIP][214] ([i915#9906])
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@kms_vrr@max-min.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-tglu-1:       NOTRUN -> [SKIP][215] ([i915#9906])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-1/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-dg2:          NOTRUN -> [SKIP][216] ([i915#2437] / [i915#9412]) +1 other test skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-3/igt@kms_writeback@writeback-pixel-formats.html

  * igt@perf_pmu@busy-accuracy-98@bcs0:
    - shard-tglu:         [PASS][217] -> [FAIL][218] ([i915#4349])
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-tglu-4/igt@perf_pmu@busy-accuracy-98@bcs0.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-7/igt@perf_pmu@busy-accuracy-98@bcs0.html

  * igt@perf_pmu@busy-accuracy-98@rcs0:
    - shard-tglu:         [PASS][219] -> [FAIL][220] ([i915#12513] / [i915#4349]) +1 other test fail
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-tglu-4/igt@perf_pmu@busy-accuracy-98@rcs0.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-7/igt@perf_pmu@busy-accuracy-98@rcs0.html

  * igt@perf_pmu@rc6@other-idle-gt0:
    - shard-tglu:         NOTRUN -> [SKIP][221] ([i915#8516])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-5/igt@perf_pmu@rc6@other-idle-gt0.html

  * igt@prime_vgem@basic-fence-flip:
    - shard-dg2:          NOTRUN -> [SKIP][222] ([i915#3708])
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-11/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
    - shard-dg2:          NOTRUN -> [SKIP][223] ([i915#3708] / [i915#4077])
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-3/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-fence-read:
    - shard-dg2:          NOTRUN -> [SKIP][224] ([i915#3291] / [i915#3708]) +2 other tests skip
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-4/igt@prime_vgem@basic-fence-read.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0:
    - shard-dg2:          [INCOMPLETE][225] ([i915#11441]) -> [PASS][226] +1 other test pass
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg2-3/igt@gem_exec_suspend@basic-s0.html
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-3/igt@gem_exec_suspend@basic-s0.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-dg1:          [ABORT][227] ([i915#9820]) -> [PASS][228]
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg1-15/igt@i915_module_load@reload-with-fault-injection.html
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-17/igt@i915_module_load@reload-with-fault-injection.html
    - shard-mtlp:         [ABORT][229] ([i915#10131] / [i915#9697]) -> [PASS][230]
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-mtlp-5/igt@i915_module_load@reload-with-fault-injection.html
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-8/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-rkl:          [INCOMPLETE][231] ([i915#4817]) -> [PASS][232]
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-rkl-3/igt@i915_suspend@basic-s3-without-i915.html
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-rkl-2/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1:
    - shard-tglu:         [FAIL][233] ([i915#11808]) -> [PASS][234] +1 other test pass
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-tglu-7/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-8/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-onscreen-128x128:
    - shard-dg1:          [DMESG-WARN][235] ([i915#4423]) -> [PASS][236] +1 other test pass
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg1-12/igt@kms_cursor_crc@cursor-onscreen-128x128.html
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-14/igt@kms_cursor_crc@cursor-onscreen-128x128.html

  * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
    - shard-mtlp:         [FAIL][237] ([i915#2346]) -> [PASS][238]
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-mtlp-8/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-2/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1:
    - shard-mtlp:         [FAIL][239] ([i915#2122]) -> [PASS][240] +5 other tests pass
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-mtlp-2/igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1.html
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-5/igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a1:
    - shard-glk:          [FAIL][241] ([i915#2122]) -> [PASS][242] +3 other tests pass
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-glk6/igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a1.html
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-glk9/igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a1.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@b-edp1:
    - shard-mtlp:         [FAIL][243] ([i915#11989]) -> [PASS][244]
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-mtlp-2/igt@kms_flip@flip-vs-absolute-wf_vblank@b-edp1.html
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-5/igt@kms_flip@flip-vs-absolute-wf_vblank@b-edp1.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@c-hdmi-a4:
    - shard-dg1:          [FAIL][245] ([i915#2122]) -> [PASS][246]
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg1-16/igt@kms_flip@flip-vs-absolute-wf_vblank@c-hdmi-a4.html
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-16/igt@kms_flip@flip-vs-absolute-wf_vblank@c-hdmi-a4.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite:
    - shard-dg2:          [FAIL][247] ([i915#6880]) -> [PASS][248]
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
    - shard-snb:          [SKIP][249] -> [PASS][250] +3 other tests pass
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-snb2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-snb4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite:
    - shard-mtlp:         [INCOMPLETE][251] -> [PASS][252]
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-mtlp-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-mtlp-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-rkl:          [SKIP][253] ([i915#9519]) -> [PASS][254] +2 other tests pass
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-rkl-5/igt@kms_pm_rpm@dpms-lpsp.html
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-rkl-2/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_setmode@basic:
    - shard-dg1:          [FAIL][255] ([i915#12317] / [i915#5465]) -> [PASS][256]
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg1-18/igt@kms_setmode@basic.html
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-12/igt@kms_setmode@basic.html

  * igt@kms_setmode@basic@pipe-a-hdmi-a-1:
    - shard-glk:          [FAIL][257] ([i915#5465]) -> [PASS][258]
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-glk7/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-glk1/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html

  * igt@perf@stress-open-close@0-rcs0:
    - shard-glk:          [ABORT][259] ([i915#8190] / [i915#9853]) -> [PASS][260] +1 other test pass
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-glk5/igt@perf@stress-open-close@0-rcs0.html
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-glk6/igt@perf@stress-open-close@0-rcs0.html

  * igt@perf_pmu@module-unload:
    - shard-snb:          [ABORT][261] ([i915#9853]) -> [PASS][262]
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-snb4/igt@perf_pmu@module-unload.html
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-snb5/igt@perf_pmu@module-unload.html

  
#### Warnings ####

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-tglu:         [FAIL][263] ([i915#2876]) -> [FAIL][264] ([i915#2842])
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-tglu-4/igt@gem_exec_fair@basic-pace@rcs0.html
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-tglu-7/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-rkl:          [ABORT][265] ([i915#9820]) -> [ABORT][266] ([i915#9697] / [i915#9820])
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-rkl-1/igt@i915_module_load@reload-with-fault-injection.html
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-rkl-3/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_selftest@mock:
    - shard-glk:          [DMESG-WARN][267] ([i915#9311]) -> [DMESG-WARN][268] ([i915#1982] / [i915#9311])
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-glk4/igt@i915_selftest@mock.html
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-glk5/igt@i915_selftest@mock.html

  * igt@kms_chamelium_color@ctm-0-75:
    - shard-dg1:          [SKIP][269] -> [SKIP][270] ([i915#4423])
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg1-16/igt@kms_chamelium_color@ctm-0-75.html
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-18/igt@kms_chamelium_color@ctm-0-75.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible:
    - shard-rkl:          [FAIL][271] ([i915#10826] / [i915#2122]) -> [FAIL][272] ([i915#2122])
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-rkl-4/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-rkl-7/igt@kms_flip@plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-hdmi-a1:
    - shard-rkl:          [FAIL][273] ([i915#10826]) -> [FAIL][274] ([i915#2122])
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-rkl-4/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-hdmi-a1.html
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-rkl-7/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move:
    - shard-dg2:          [SKIP][275] ([i915#10433] / [i915#3458]) -> [SKIP][276] ([i915#3458])
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg2-10/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
    - shard-dg1:          [SKIP][277] ([i915#8708]) -> [SKIP][278] ([i915#4423] / [i915#8708])
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg1-18/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-dg1:          [SKIP][279] ([i915#5289]) -> [SKIP][280] ([i915#4423] / [i915#5289])
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-dg1-18/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-dg1-16/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-glk:          [FAIL][281] ([i915#10959]) -> [SKIP][282]
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15619/shard-glk3/igt@kms_tiled_display@basic-test-pattern.html
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/shard-glk8/igt@kms_tiled_display@basic-test-pattern.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10029]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10029
  [i915#10056]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10056
  [i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
  [i915#10139]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10139
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#10729]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10729
  [i915#10826]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10826
  [i915#10959]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10959
  [i915#11131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11131
  [i915#11441]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11441
  [i915#11453]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11453
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11616]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11616
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#11808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11808
  [i915#11859]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11859
  [i915#11989]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11989
  [i915#12177]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12177
  [i915#12238]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12238
  [i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
  [i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
  [i915#12297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12297
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12316]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12316
  [i915#12317]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12317
  [i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
  [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
  [i915#12513]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12513
  [i915#12543]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12543
  [i915#12548]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12548
  [i915#12564]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12564
  [i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
  [i915#12577]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12577
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122
  [i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
  [i915#2436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2436
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#2876]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2876
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
  [i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#3936]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3936
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/433
  [i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
  [i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4879]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4879
  [i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
  [i915#4881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4881
  [i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5465]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5465
  [i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
  [i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
  [i915#5978]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5978
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
  [i915#6118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6118
  [i915#6227]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6227
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
  [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
  [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
  [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
  [i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7213
  [i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8190
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
  [i915#8588]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8588
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8821
  [i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
  [i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
  [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
  [i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9697
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
  [i915#9781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9781
  [i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
  [i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
  [i915#9853]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9853
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_15619 -> Patchwork_140697v2

  CI-20190529: 20190529
  CI_DRM_15619: fa53c85519aa642bf10aa1692a1b99d1930d2809 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8091: 8091
  Patchwork_140697v2: fa53c85519aa642bf10aa1692a1b99d1930d2809 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_140697v2/index.html

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