[RFC v3 0/9] Gen12 E2E compression

[RFC v3 0/9] Gen12 E2E compression

[Dhinakaran Pandiyan]

Patches in this series are at two levels of completion.
The render decompression patches 1, 2, 3 and 4 address feedback provided
for https://patchwork.freedesktop.org/series/66367/

Media decompression patches 5, 6, 7, 8 and 9 are a complete rewrite to
handle planar formats and have not been tested. I would like to get
feedback on the approach before finishing the implementation.

Dhinakaran Pandiyan (9):
  drm/framebuffer: Format modifier for Intel Gen-12 render compression
  drm/i915: Use intel_tile_height() instead of re-implementing
  drm/i915: Move CCS stride alignment W/A inside
    intel_fb_stride_alignment
  drm/i915/tgl: Gen-12 render decompression
  drm/i915: Extract framebufer CCS  offset checks into a function
  drm/framebuffer: Format modifier for Intel Gen-12 media compression
  drm/i915: Skip rotated offset adjustment for unsupported modifiers
  drm/fb: Extend format_info member arrays to handle four planes
  Gen-12 display can decompress surfaces compressed by the media engine.

 drivers/gpu/drm/i915/display/intel_display.c  | 388 +++++++++++++-----
 .../drm/i915/display/intel_display_types.h    |   2 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  61 ++-
 drivers/gpu/drm/i915/i915_reg.h               |   2 +
 include/drm/drm_fourcc.h                      |   8 +-
 include/uapi/drm/drm_fourcc.h                 |  22 +
 6 files changed, 368 insertions(+), 115 deletions(-)

-- 
2.17.1

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[RFC v3 1/9] drm/framebuffer: Format modifier for Intel Gen-12 render compression

[Dhinakaran Pandiyan]

Gen-12 has a new compression format, add a new modifier to indicate that.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 3feeaa3f987a..1f0fbf0398f6 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -410,6 +410,17 @@ extern "C" {
 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
 
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.17.1

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[RFC v3 2/9] drm/i915: Use intel_tile_height() instead of re-implementing

[Dhinakaran Pandiyan]

intel_tile_dims() computes tile height using size and width, when there
is already a function to do just that - intel_tile_height()

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5ecf54270181..a94d145dd048 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1957,7 +1957,7 @@ static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
 	unsigned int cpp = fb->format->cpp[color_plane];
 
 	*tile_width = tile_width_bytes / cpp;
-	*tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
+	*tile_height = intel_tile_height(fb, color_plane);
 }
 
 unsigned int
-- 
2.17.1

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Re: [RFC v3 2/9] drm/i915: Use intel_tile_height() instead of re-implementing

[Matt Roper]

On Mon, Sep 23, 2019 at 03:29:28AM -0700, Dhinakaran Pandiyan wrote:
> intel_tile_dims() computes tile height using size and width, when there
> is already a function to do just that - intel_tile_height()
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 5ecf54270181..a94d145dd048 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1957,7 +1957,7 @@ static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
>  	unsigned int cpp = fb->format->cpp[color_plane];
>  
>  	*tile_width = tile_width_bytes / cpp;
> -	*tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
> +	*tile_height = intel_tile_height(fb, color_plane);
>  }
>  
>  unsigned int
> -- 
> 2.17.1
> 

-- 
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Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[RFC v3 3/9] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment

[Dhinakaran Pandiyan]

Easier to read if all the alignment changes are in one place and contained
within a function.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 31 ++++++++++----------
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a94d145dd048..c437f00c2072 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2551,7 +2551,22 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 		else
 			return 64;
 	} else {
-		return intel_tile_width_bytes(fb, color_plane);
+		u32 tile_width = intel_tile_width_bytes(fb, color_plane);
+
+		/*
+		 * Display WA #0531: skl,bxt,kbl,glk
+		 *
+		 * Render decompression and plane width > 3840
+		 * combined with horizontal panning requires the
+		 * plane stride to be a multiple of 4. We'll just
+		 * require the entire fb to accommodate that to avoid
+		 * potential runtime errors at plane configuration time.
+		 */
+		if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
+		    color_plane == 0 && fb->width > 3840)
+			tile_width *= 4;
+
+		return tile_width;
 	}
 }
 
@@ -15705,20 +15720,6 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 		}
 
 		stride_alignment = intel_fb_stride_alignment(fb, i);
-
-		/*
-		 * Display WA #0531: skl,bxt,kbl,glk
-		 *
-		 * Render decompression and plane width > 3840
-		 * combined with horizontal panning requires the
-		 * plane stride to be a multiple of 4. We'll just
-		 * require the entire fb to accommodate that to avoid
-		 * potential runtime errors at plane configuration time.
-		 */
-		if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
-		    is_ccs_modifier(fb->modifier))
-			stride_alignment *= 4;
-
 		if (fb->pitches[i] & (stride_alignment - 1)) {
 			DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
 				      i, fb->pitches[i], stride_alignment);
-- 
2.17.1

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Re: [RFC v3 3/9] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment

[Matt Roper]

On Mon, Sep 23, 2019 at 03:29:29AM -0700, Dhinakaran Pandiyan wrote:
> Easier to read if all the alignment changes are in one place and contained
> within a function.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 31 ++++++++++----------
>  1 file changed, 16 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a94d145dd048..c437f00c2072 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2551,7 +2551,22 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
>  		else
>  			return 64;
>  	} else {
> -		return intel_tile_width_bytes(fb, color_plane);
> +		u32 tile_width = intel_tile_width_bytes(fb, color_plane);
> +
> +		/*
> +		 * Display WA #0531: skl,bxt,kbl,glk
> +		 *
> +		 * Render decompression and plane width > 3840
> +		 * combined with horizontal panning requires the
> +		 * plane stride to be a multiple of 4. We'll just
> +		 * require the entire fb to accommodate that to avoid
> +		 * potential runtime errors at plane configuration time.
> +		 */
> +		if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
> +		    color_plane == 0 && fb->width > 3840)
> +			tile_width *= 4;

I realize you're only moving this, but I find this workaround
description confusing since the wording is somewhat ambiguous as to
whether it's expecting the plane stride to be a multiple of 4 bytes or 4
tiles.  On casual read, I think most people would assume that we're
talking about bytes here.  Only once you realize that the PLANE_STRIDE
register itself gets programmed in units of tile width does the wording
here become clear.  Maybe we could clarify the comment while moving it?

Also it might be slightly more clear to do a "return tile_width * 4"
here instead of modifying tile_width since that's a bit more intuitive
description of what we're trying to do.

Either way,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


Matt


> +
> +		return tile_width;
>  	}
>  }
>  
> @@ -15705,20 +15720,6 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  		}
>  
>  		stride_alignment = intel_fb_stride_alignment(fb, i);
> -
> -		/*
> -		 * Display WA #0531: skl,bxt,kbl,glk
> -		 *
> -		 * Render decompression and plane width > 3840
> -		 * combined with horizontal panning requires the
> -		 * plane stride to be a multiple of 4. We'll just
> -		 * require the entire fb to accommodate that to avoid
> -		 * potential runtime errors at plane configuration time.
> -		 */
> -		if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
> -		    is_ccs_modifier(fb->modifier))
> -			stride_alignment *= 4;
> -
>  		if (fb->pitches[i] & (stride_alignment - 1)) {
>  			DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
>  				      i, fb->pitches[i], stride_alignment);
> -- 
> 2.17.1
> 

-- 
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VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [RFC v3 3/9] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment

[Pandiyan, Dhinakaran]

On Wed, 2019-10-02 at 15:29 -0700, Matt Roper wrote:
> On Mon, Sep 23, 2019 at 03:29:29AM -0700, Dhinakaran Pandiyan wrote:
> > Easier to read if all the alignment changes are in one place and contained
> > within a function.
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 31 ++++++++++----------
> >  1 file changed, 16 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index a94d145dd048..c437f00c2072 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -2551,7 +2551,22 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int
> > color_plane)
> >  		else
> >  			return 64;
> >  	} else {
> > -		return intel_tile_width_bytes(fb, color_plane);
> > +		u32 tile_width = intel_tile_width_bytes(fb, color_plane);
> > +
> > +		/*
> > +		 * Display WA #0531: skl,bxt,kbl,glk
> > +		 *
> > +		 * Render decompression and plane width > 3840
> > +		 * combined with horizontal panning requires the
> > +		 * plane stride to be a multiple of 4. We'll just
> > +		 * require the entire fb to accommodate that to avoid
> > +		 * potential runtime errors at plane configuration time.
> > +		 */
> > +		if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
> > +		    color_plane == 0 && fb->width > 3840)
> > +			tile_width *= 4;
> 
> I realize you're only moving this, but I find this workaround
> description confusing since the wording is somewhat ambiguous as to
> whether it's expecting the plane stride to be a multiple of 4 bytes or 4
> tiles.  On casual read, I think most people would assume that we're
> talking about bytes here.  Only once you realize that the PLANE_STRIDE
> register itself gets programmed in units of tile width does the wording
> here become clear.  Maybe we could clarify the comment while moving it?
I remember wanting to rewrite that comment for the exact reason, but forgot to do so. Thanks for the
review, I'll fix it.

> 
> Also it might be slightly more clear to do a "return tile_width * 4"
> here instead of modifying tile_width since that's a bit more intuitive
> description of what we're trying to do.
> 
> Either way,
> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> 
> 
> Matt
> 
> 
> > +
> > +		return tile_width;
> >  	}
> >  }
> >  
> > @@ -15705,20 +15720,6 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> >  		}
> >  
> >  		stride_alignment = intel_fb_stride_alignment(fb, i);
> > -
> > -		/*
> > -		 * Display WA #0531: skl,bxt,kbl,glk
> > -		 *
> > -		 * Render decompression and plane width > 3840
> > -		 * combined with horizontal panning requires the
> > -		 * plane stride to be a multiple of 4. We'll just
> > -		 * require the entire fb to accommodate that to avoid
> > -		 * potential runtime errors at plane configuration time.
> > -		 */
> > -		if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
> > -		    is_ccs_modifier(fb->modifier))
> > -			stride_alignment *= 4;
> > -
> >  		if (fb->pitches[i] & (stride_alignment - 1)) {
> >  			DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
> >  				      i, fb->pitches[i], stride_alignment);
> > -- 
> > 2.17.1
> > 
> 
> 
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[RFC v3 4/9] drm/i915/tgl: Gen-12 render decompression

[Dhinakaran Pandiyan]

Gen-12 display decompression operates on Y-tiled compressed main surface.
The CCS is linear and has 4 bits of metadata for each main surface cache
line pair, a size ratio of 1:256. Gen-12 display decompression is
incompatible with buffers compressed by earlier GPUs, so make use of a new
modifier to identify gen-12 compression. Another notable change is that
render decompression is supported on all planes except cursor and on all
pipes. Start by adding render decompression support for [A,X]BGR888 pixel
formats.

v2: Fix checkpatch warnings (Lucas)
v3:
Rebase, disable color clear, styling changes and modify
intel_tile_width_bytes and intel_tile_height to handle linear CCS

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 85 ++++++++++++++++----
 drivers/gpu/drm/i915/display/intel_sprite.c  | 23 ++++--
 drivers/gpu/drm/i915/i915_reg.h              |  1 +
 3 files changed, 84 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c437f00c2072..6fec43cdddf4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1911,6 +1911,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 		if (color_plane == 1)
 			return 128;
 		/* fall through */
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		if (color_plane == 1)
+			return 64;
+		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED:
 		if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
 			return 128;
@@ -1944,8 +1948,15 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 static unsigned int
 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
 {
-	return intel_tile_size(to_i915(fb->dev)) /
-		intel_tile_width_bytes(fb, color_plane);
+	switch (fb->modifier) {
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		if (color_plane == 1)
+			return 1;
+		/* fall through */
+	default:
+		return intel_tile_size(to_i915(fb->dev)) /
+			intel_tile_width_bytes(fb, color_plane);
+	}
 }
 
 /* Return the tile dimensions in pixel units */
@@ -2044,6 +2055,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 		if (INTEL_GEN(dev_priv) >= 9)
 			return 256 * 1024;
 		return 0;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return 16 * 1024;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED:
@@ -2243,7 +2256,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
 
 static bool is_surface_linear(u64 modifier, int color_plane)
 {
-	return modifier == DRM_FORMAT_MOD_LINEAR;
+	return modifier == DRM_FORMAT_MOD_LINEAR ||
+	       (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
 }
 
 static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2430,6 +2444,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 		return I915_TILING_X;
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		return I915_TILING_Y;
 	default:
 		return I915_TILING_NONE;
@@ -2450,7 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
  * us a ratio of one byte in the CCS for each 8x16 pixels in the
  * main surface.
  */
-static const struct drm_format_info ccs_formats[] = {
+static const struct drm_format_info skl_ccs_formats[] = {
 	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
 	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
@@ -2461,6 +2476,24 @@ static const struct drm_format_info ccs_formats[] = {
 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
 };
 
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
+ * the main surface.
+ */
+static const struct drm_format_info gen12_ccs_formats[] = {
+	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
+	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
+	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
+	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
+	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
 static const struct drm_format_info *
 lookup_format_info(const struct drm_format_info formats[],
 		   int num_formats, u32 format)
@@ -2481,8 +2514,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 	switch (cmd->modifier[0]) {
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
-		return lookup_format_info(ccs_formats,
-					  ARRAY_SIZE(ccs_formats),
+		return lookup_format_info(skl_ccs_formats,
+					  ARRAY_SIZE(skl_ccs_formats),
+					  cmd->pixel_format);
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return lookup_format_info(gen12_ccs_formats,
+					  ARRAY_SIZE(gen12_ccs_formats),
 					  cmd->pixel_format);
 	default:
 		return NULL;
@@ -2491,7 +2528,8 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 
 bool is_ccs_modifier(u64 modifier)
 {
-	return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 }
 
@@ -2536,8 +2574,9 @@ static u32
 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 {
 	struct drm_i915_private *dev_priv = to_i915(fb->dev);
+	u32 tile_width;
 
-	if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+	if (is_surface_linear(fb->modifier, color_plane)) {
 		u32 max_stride = intel_plane_fb_max_stride(dev_priv,
 							   fb->format->format,
 							   fb->modifier);
@@ -2546,13 +2585,14 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 		 * To make remapping with linear generally feasible
 		 * we need the stride to be page aligned.
 		 */
-		if (fb->pitches[color_plane] > max_stride)
+		if (fb->pitches[color_plane] > max_stride && !is_ccs_modifier(fb->modifier))
 			return intel_tile_size(dev_priv);
 		else
 			return 64;
-	} else {
-		u32 tile_width = intel_tile_width_bytes(fb, color_plane);
+	}
 
+	tile_width = intel_tile_width_bytes(fb, color_plane);
+	if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
 		/*
 		 * Display WA #0531: skl,bxt,kbl,glk
 		 *
@@ -2562,12 +2602,16 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 		 * require the entire fb to accommodate that to avoid
 		 * potential runtime errors at plane configuration time.
 		 */
-		if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
-		    color_plane == 0 && fb->width > 3840)
+		if (IS_GEN(dev_priv, 9) && fb->width > 3840)
+			tile_width *= 4;
+		/*
+		 * The main surface pitch must be padded to a multiple of four
+		 * tile widths.
+		 */
+		else if (INTEL_GEN(dev_priv) >= 12)
 			tile_width *= 4;
-
-		return tile_width;
 	}
+	return tile_width;
 }
 
 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
@@ -2676,6 +2720,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 			int ccs_x, ccs_y;
 
 			intel_tile_dims(fb, i, &tile_width, &tile_height);
+
 			tile_width *= hsub;
 			tile_height *= vsub;
 
@@ -3972,7 +4017,7 @@ static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
 	 * The stride is either expressed as a multiple of 64 bytes chunks for
 	 * linear buffers or in number of tiles for tiled buffers.
 	 */
-	if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
+	if (is_surface_linear(fb->modifier, color_plane))
 		return 64;
 	else if (drm_rotation_90_or_270(rotation))
 		return intel_tile_height(fb, color_plane);
@@ -4098,6 +4143,10 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 		return PLANE_CTL_TILED_Y;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return PLANE_CTL_TILED_Y |
+		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
+		       PLANE_CTL_CLEAR_COLOR_DISABLE;
 	case I915_FORMAT_MOD_Yf_TILED:
 		return PLANE_CTL_TILED_YF;
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -9899,7 +9948,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 	case PLANE_CTL_TILED_Y:
 		plane_config->tiling = I915_TILING_Y;
 		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
-			fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
+			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
+				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
+				I915_FORMAT_MOD_Y_TILED_CCS;
 		else
 			fb->modifier = I915_FORMAT_MOD_Y_TILED;
 		break;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 7a7078d0ba23..866d25d38d04 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -535,6 +535,7 @@ skl_program_plane(struct intel_plane *plane,
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 	u32 surf_addr = plane_state->color_plane[color_plane].offset;
 	u32 stride = skl_plane_stride(plane_state, color_plane);
+	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
 	u32 aux_stride = skl_plane_stride(plane_state, 1);
 	int crtc_x = plane_state->base.dst.x1;
 	int crtc_y = plane_state->base.dst.y1;
@@ -576,8 +577,10 @@ skl_program_plane(struct intel_plane *plane,
 	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 	I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
-	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
-		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
+
+	if (INTEL_GEN(dev_priv) < 12)
+		aux_dist |= aux_stride;
+	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist);
 
 	if (icl_is_hdr_plane(dev_priv, plane_id)) {
 		u32 cus_ctl = 0;
@@ -1733,7 +1736,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	    (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
-	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
+	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
 		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
 		return -EINVAL;
 	}
@@ -2145,7 +2149,8 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
 	DRM_FORMAT_MOD_INVALID
 };
 
-static const u64 gen12_plane_format_modifiers_noccs[] = {
+static const u64 gen12_plane_format_modifiers_ccs[] = {
+	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
 	DRM_FORMAT_MOD_LINEAR,
@@ -2307,6 +2312,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_MOD_LINEAR:
 	case I915_FORMAT_MOD_X_TILED:
 	case I915_FORMAT_MOD_Y_TILED:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		break;
 	default:
 		return false;
@@ -2317,6 +2323,9 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_XBGR8888:
 	case DRM_FORMAT_ARGB8888:
 	case DRM_FORMAT_ABGR8888:
+		if (is_ccs_modifier(modifier))
+			return true;
+		/* fall through */
 	case DRM_FORMAT_RGB565:
 	case DRM_FORMAT_XRGB2101010:
 	case DRM_FORMAT_XBGR2101010:
@@ -2525,13 +2534,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 		formats = skl_get_plane_formats(dev_priv, pipe,
 						plane_id, &num_formats);
 
+	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
 	if (INTEL_GEN(dev_priv) >= 12) {
-		/* TODO: Implement support for gen-12 CCS modifiers */
-		plane->has_ccs = false;
-		modifiers = gen12_plane_format_modifiers_noccs;
+		modifiers = gen12_plane_format_modifiers_ccs;
 		plane_funcs = &gen12_plane_funcs;
 	} else {
-		plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
 		if (plane->has_ccs)
 			modifiers = skl_plane_format_modifiers_ccs;
 		else
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6ecb64c042ef..b465eae11763 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6688,6 +6688,7 @@ enum {
 #define   PLANE_CTL_YUV422_VYUY			(3 << 16)
 #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE	(1 << 15)
 #define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
+#define   PLANE_CTL_CLEAR_COLOR_DISABLE		(1 << 13) /* TGL+ */
 #define   PLANE_CTL_PLANE_GAMMA_DISABLE		(1 << 13) /* Pre-GLK */
 #define   PLANE_CTL_TILED_MASK			(0x7 << 10)
 #define   PLANE_CTL_TILED_LINEAR		(0 << 10)
-- 
2.17.1

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Intel-gfx@lists.freedesktop.org
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Re: [RFC v3 4/9] drm/i915/tgl: Gen-12 render decompression

[Matt Roper]

On Mon, Sep 23, 2019 at 03:29:30AM -0700, Dhinakaran Pandiyan wrote:
> Gen-12 display decompression operates on Y-tiled compressed main surface.
> The CCS is linear

I'd mention in the commit message that we opt to to treat the
CCS as if it were a bunch of 64x1 tiles.

There are a handful of cosmetic changes suggested below, but otherwise,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> and has 4 bits of metadata for each main surface cache
> line pair, a size ratio of 1:256. Gen-12 display decompression is
> incompatible with buffers compressed by earlier GPUs, so make use of a new
> modifier to identify gen-12 compression. Another notable change is that
> render decompression is supported on all planes except cursor and on all
> pipes. Start by adding render decompression support for [A,X]BGR888 pixel
> formats.
> 
> v2: Fix checkpatch warnings (Lucas)
> v3:
> Rebase, disable color clear, styling changes and modify
> intel_tile_width_bytes and intel_tile_height to handle linear CCS
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Nanley G Chery <nanley.g.chery@intel.com>
> Cc: Jason Ekstrand <jason@jlekstrand.net>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 85 ++++++++++++++++----
>  drivers/gpu/drm/i915/display/intel_sprite.c  | 23 ++++--
>  drivers/gpu/drm/i915/i915_reg.h              |  1 +
>  3 files changed, 84 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index c437f00c2072..6fec43cdddf4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1911,6 +1911,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>  		if (color_plane == 1)
>  			return 128;
>  		/* fall through */
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		if (color_plane == 1)
> +			return 64;
> +		/* fall through */
>  	case I915_FORMAT_MOD_Y_TILED:
>  		if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
>  			return 128;
> @@ -1944,8 +1948,15 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>  static unsigned int
>  intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
>  {
> -	return intel_tile_size(to_i915(fb->dev)) /
> -		intel_tile_width_bytes(fb, color_plane);
> +	switch (fb->modifier) {
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		if (color_plane == 1)
> +			return 1;
> +		/* fall through */
> +	default:
> +		return intel_tile_size(to_i915(fb->dev)) /
> +			intel_tile_width_bytes(fb, color_plane);
> +	}

I'd just use an 'if' instead of a 'switch' here since I can't see us
ending up with a bunch of different cases in the future.  Either we have
real tiles that follow normal rules or else we have pretend tiles for
stuff like CCS that have a height of 1.

>  }
>  
>  /* Return the tile dimensions in pixel units */
> @@ -2044,6 +2055,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
>  		if (INTEL_GEN(dev_priv) >= 9)
>  			return 256 * 1024;
>  		return 0;
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		return 16 * 1024;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
>  	case I915_FORMAT_MOD_Y_TILED:
> @@ -2243,7 +2256,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
>  
>  static bool is_surface_linear(u64 modifier, int color_plane)
>  {
> -	return modifier == DRM_FORMAT_MOD_LINEAR;
> +	return modifier == DRM_FORMAT_MOD_LINEAR ||
> +	       (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);

Long line; needs a split to stay under 80 chars.

>  }
>  
>  static u32 intel_adjust_aligned_offset(int *x, int *y,
> @@ -2430,6 +2444,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
>  		return I915_TILING_X;
>  	case I915_FORMAT_MOD_Y_TILED:
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		return I915_TILING_Y;
>  	default:
>  		return I915_TILING_NONE;
> @@ -2450,7 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
>   * us a ratio of one byte in the CCS for each 8x16 pixels in the
>   * main surface.
>   */
> -static const struct drm_format_info ccs_formats[] = {
> +static const struct drm_format_info skl_ccs_formats[] = {
>  	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
>  	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
>  	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> @@ -2461,6 +2476,24 @@ static const struct drm_format_info ccs_formats[] = {
>  	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
>  };
>  
> +/*
> + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
> + * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
> + * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
> + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
> + * the main surface.
> + */
> +static const struct drm_format_info gen12_ccs_formats[] = {
> +	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> +	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
> +	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> +	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
> +	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
> +	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> +	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> +	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> +};
> +
>  static const struct drm_format_info *
>  lookup_format_info(const struct drm_format_info formats[],
>  		   int num_formats, u32 format)
> @@ -2481,8 +2514,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
>  	switch (cmd->modifier[0]) {
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> -		return lookup_format_info(ccs_formats,
> -					  ARRAY_SIZE(ccs_formats),
> +		return lookup_format_info(skl_ccs_formats,
> +					  ARRAY_SIZE(skl_ccs_formats),
> +					  cmd->pixel_format);
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		return lookup_format_info(gen12_ccs_formats,
> +					  ARRAY_SIZE(gen12_ccs_formats),
>  					  cmd->pixel_format);
>  	default:
>  		return NULL;
> @@ -2491,7 +2528,8 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
>  
>  bool is_ccs_modifier(u64 modifier)
>  {
> -	return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>  	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
>  }
>  
> @@ -2536,8 +2574,9 @@ static u32
>  intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(fb->dev);
> +	u32 tile_width;
>  
> -	if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
> +	if (is_surface_linear(fb->modifier, color_plane)) {
>  		u32 max_stride = intel_plane_fb_max_stride(dev_priv,
>  							   fb->format->format,
>  							   fb->modifier);
> @@ -2546,13 +2585,14 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
>  		 * To make remapping with linear generally feasible
>  		 * we need the stride to be page aligned.
>  		 */
> -		if (fb->pitches[color_plane] > max_stride)
> +		if (fb->pitches[color_plane] > max_stride && !is_ccs_modifier(fb->modifier))

Need to split this line to keep it under 80 chars.

>  			return intel_tile_size(dev_priv);
>  		else
>  			return 64;
> -	} else {
> -		u32 tile_width = intel_tile_width_bytes(fb, color_plane);
> +	}
>  
> +	tile_width = intel_tile_width_bytes(fb, color_plane);
> +	if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
>  		/*
>  		 * Display WA #0531: skl,bxt,kbl,glk
>  		 *
> @@ -2562,12 +2602,16 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
>  		 * require the entire fb to accommodate that to avoid
>  		 * potential runtime errors at plane configuration time.
>  		 */
> -		if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
> -		    color_plane == 0 && fb->width > 3840)
> +		if (IS_GEN(dev_priv, 9) && fb->width > 3840)
> +			tile_width *= 4;
> +		/*
> +		 * The main surface pitch must be padded to a multiple of four
> +		 * tile widths.
> +		 */
> +		else if (INTEL_GEN(dev_priv) >= 12)
>  			tile_width *= 4;
> -
> -		return tile_width;
>  	}
> +	return tile_width;
>  }
>  
>  bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
> @@ -2676,6 +2720,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
>  			int ccs_x, ccs_y;
>  
>  			intel_tile_dims(fb, i, &tile_width, &tile_height);
> +

Unwanted change?

>  			tile_width *= hsub;
>  			tile_height *= vsub;
>  
> @@ -3972,7 +4017,7 @@ static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
>  	 * The stride is either expressed as a multiple of 64 bytes chunks for
>  	 * linear buffers or in number of tiles for tiled buffers.
>  	 */
> -	if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
> +	if (is_surface_linear(fb->modifier, color_plane))
>  		return 64;
>  	else if (drm_rotation_90_or_270(rotation))
>  		return intel_tile_height(fb, color_plane);
> @@ -4098,6 +4143,10 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
>  		return PLANE_CTL_TILED_Y;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +		return PLANE_CTL_TILED_Y |
> +		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> +		       PLANE_CTL_CLEAR_COLOR_DISABLE;
>  	case I915_FORMAT_MOD_Yf_TILED:
>  		return PLANE_CTL_TILED_YF;
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -9899,7 +9948,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
>  	case PLANE_CTL_TILED_Y:
>  		plane_config->tiling = I915_TILING_Y;
>  		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> -			fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
> +			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
> +				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> +				I915_FORMAT_MOD_Y_TILED_CCS;
>  		else
>  			fb->modifier = I915_FORMAT_MOD_Y_TILED;
>  		break;
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 7a7078d0ba23..866d25d38d04 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -535,6 +535,7 @@ skl_program_plane(struct intel_plane *plane,
>  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
>  	u32 surf_addr = plane_state->color_plane[color_plane].offset;
>  	u32 stride = skl_plane_stride(plane_state, color_plane);
> +	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
>  	u32 aux_stride = skl_plane_stride(plane_state, 1);
>  	int crtc_x = plane_state->base.dst.x1;
>  	int crtc_y = plane_state->base.dst.y1;
> @@ -576,8 +577,10 @@ skl_program_plane(struct intel_plane *plane,
>  	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
>  	I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
>  	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
> -	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
> -		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
> +
> +	if (INTEL_GEN(dev_priv) < 12)
> +		aux_dist |= aux_stride;
> +	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist);
>  
>  	if (icl_is_hdr_plane(dev_priv, plane_id)) {
>  		u32 cus_ctl = 0;
> @@ -1733,7 +1736,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>  	    (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
>  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
>  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> -	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
> +	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
>  		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
>  		return -EINVAL;
>  	}
> @@ -2145,7 +2149,8 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
>  	DRM_FORMAT_MOD_INVALID
>  };
>  
> -static const u64 gen12_plane_format_modifiers_noccs[] = {
> +static const u64 gen12_plane_format_modifiers_ccs[] = {
> +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
>  	I915_FORMAT_MOD_Y_TILED,
>  	I915_FORMAT_MOD_X_TILED,
>  	DRM_FORMAT_MOD_LINEAR,
> @@ -2307,6 +2312,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_MOD_LINEAR:
>  	case I915_FORMAT_MOD_X_TILED:
>  	case I915_FORMAT_MOD_Y_TILED:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		break;
>  	default:
>  		return false;
> @@ -2317,6 +2323,9 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_XBGR8888:
>  	case DRM_FORMAT_ARGB8888:
>  	case DRM_FORMAT_ABGR8888:
> +		if (is_ccs_modifier(modifier))
> +			return true;
> +		/* fall through */
>  	case DRM_FORMAT_RGB565:
>  	case DRM_FORMAT_XRGB2101010:
>  	case DRM_FORMAT_XBGR2101010:
> @@ -2525,13 +2534,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>  		formats = skl_get_plane_formats(dev_priv, pipe,
>  						plane_id, &num_formats);
>  
> +	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
>  	if (INTEL_GEN(dev_priv) >= 12) {
> -		/* TODO: Implement support for gen-12 CCS modifiers */
> -		plane->has_ccs = false;
> -		modifiers = gen12_plane_format_modifiers_noccs;
> +		modifiers = gen12_plane_format_modifiers_ccs;
>  		plane_funcs = &gen12_plane_funcs;
>  	} else {
> -		plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
>  		if (plane->has_ccs)
>  			modifiers = skl_plane_format_modifiers_ccs;
>  		else
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6ecb64c042ef..b465eae11763 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6688,6 +6688,7 @@ enum {
>  #define   PLANE_CTL_YUV422_VYUY			(3 << 16)
>  #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE	(1 << 15)
>  #define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
> +#define   PLANE_CTL_CLEAR_COLOR_DISABLE		(1 << 13) /* TGL+ */
>  #define   PLANE_CTL_PLANE_GAMMA_DISABLE		(1 << 13) /* Pre-GLK */
>  #define   PLANE_CTL_TILED_MASK			(0x7 << 10)
>  #define   PLANE_CTL_TILED_LINEAR		(0 << 10)
> -- 
> 2.17.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [RFC v3 4/9] drm/i915/tgl: Gen-12 render decompression

[Ville Syrjälä]

On Wed, Oct 02, 2019 at 03:32:41PM -0700, Matt Roper wrote:
> On Mon, Sep 23, 2019 at 03:29:30AM -0700, Dhinakaran Pandiyan wrote:
> > Gen-12 display decompression operates on Y-tiled compressed main surface.
> > The CCS is linear
> 
> I'd mention in the commit message that we opt to to treat the
> CCS as if it were a bunch of 64x1 tiles.
> 
> There are a handful of cosmetic changes suggested below, but otherwise,
> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> 
> > and has 4 bits of metadata for each main surface cache
> > line pair, a size ratio of 1:256. Gen-12 display decompression is
> > incompatible with buffers compressed by earlier GPUs, so make use of a new
> > modifier to identify gen-12 compression. Another notable change is that
> > render decompression is supported on all planes except cursor and on all
> > pipes. Start by adding render decompression support for [A,X]BGR888 pixel
> > formats.
> > 
> > v2: Fix checkpatch warnings (Lucas)
> > v3:
> > Rebase, disable color clear, styling changes and modify
> > intel_tile_width_bytes and intel_tile_height to handle linear CCS
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Nanley G Chery <nanley.g.chery@intel.com>
> > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 85 ++++++++++++++++----
> >  drivers/gpu/drm/i915/display/intel_sprite.c  | 23 ++++--
> >  drivers/gpu/drm/i915/i915_reg.h              |  1 +
> >  3 files changed, 84 insertions(+), 25 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index c437f00c2072..6fec43cdddf4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1911,6 +1911,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> >  		if (color_plane == 1)
> >  			return 128;
> >  		/* fall through */
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > +		if (color_plane == 1)
> > +			return 64;
> > +		/* fall through */

I don't remember off hand if we even need this thing here. Maybe we can
just let it go the same path as normal linear stuff?

-- 
Ville Syrjälä
Intel
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[RFC v3 5/9] drm/i915: Extract framebufer CCS offset checks into a function

[Dhinakaran Pandiyan]

intel_fill_fb_info() has grown quite large and wrapping the offset checks
into a separate function makes the loop a bit easier to follow.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 69 ++++++++++++--------
 1 file changed, 40 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6fec43cdddf4..7447001c1f85 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2682,6 +2682,43 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
 	return stride > max_stride;
 }
 
+static int
+intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
+{
+	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+	int hsub = fb->format->hsub;
+	int vsub = fb->format->vsub;
+	int tile_width, tile_height;
+	int ccs_x, ccs_y;
+	int main_x, main_y;
+
+	intel_tile_dims(fb, 1, &tile_width, &tile_height);
+
+	tile_width *= hsub;
+	tile_height *= vsub;
+
+	ccs_x = (x * hsub) % tile_width;
+	ccs_y = (y * vsub) % tile_height;
+	main_x = intel_fb->normal[0].x % tile_width;
+	main_y = intel_fb->normal[0].y % tile_height;
+
+	/*
+	* CCS doesn't have its own x/y offset register, so the intra CCS tile
+	* x/y offsets must match between CCS and the main surface.
+	*/
+	if (main_x != ccs_x || main_y != ccs_y) {
+		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
+			      main_x, main_y,
+			      ccs_x, ccs_y,
+			      intel_fb->normal[0].x,
+			      intel_fb->normal[0].y,
+			      x, y);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static int
 intel_fill_fb_info(struct drm_i915_private *dev_priv,
 		   struct drm_framebuffer *fb)
@@ -2713,35 +2750,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 		}
 
 		if (is_ccs_modifier(fb->modifier) && i == 1) {
-			int hsub = fb->format->hsub;
-			int vsub = fb->format->vsub;
-			int tile_width, tile_height;
-			int main_x, main_y;
-			int ccs_x, ccs_y;
-
-			intel_tile_dims(fb, i, &tile_width, &tile_height);
-
-			tile_width *= hsub;
-			tile_height *= vsub;
-
-			ccs_x = (x * hsub) % tile_width;
-			ccs_y = (y * vsub) % tile_height;
-			main_x = intel_fb->normal[0].x % tile_width;
-			main_y = intel_fb->normal[0].y % tile_height;
-
-			/*
-			 * CCS doesn't have its own x/y offset register, so the intra CCS tile
-			 * x/y offsets must match between CCS and the main surface.
-			 */
-			if (main_x != ccs_x || main_y != ccs_y) {
-				DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
-					      main_x, main_y,
-					      ccs_x, ccs_y,
-					      intel_fb->normal[0].x,
-					      intel_fb->normal[0].y,
-					      x, y);
-				return -EINVAL;
-			}
+			ret = intel_fb_check_ccs_xy(fb, x, y);
+			if (ret)
+				return ret;
 		}
 
 		/*
-- 
2.17.1

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Re: [RFC v3 5/9] drm/i915: Extract framebufer CCS offset checks into a function

[Ville Syrjälä]

On Mon, Sep 23, 2019 at 03:29:31AM -0700, Dhinakaran Pandiyan wrote:
> intel_fill_fb_info() has grown quite large and wrapping the offset checks
> into a separate function makes the loop a bit easier to follow.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 69 ++++++++++++--------
>  1 file changed, 40 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6fec43cdddf4..7447001c1f85 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2682,6 +2682,43 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
>  	return stride > max_stride;
>  }
>  
> +static int
> +intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)

fb can be const

> +{
> +	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> +	int hsub = fb->format->hsub;
> +	int vsub = fb->format->vsub;
> +	int tile_width, tile_height;
> +	int ccs_x, ccs_y;
> +	int main_x, main_y;
> +
> +	intel_tile_dims(fb, 1, &tile_width, &tile_height);
> +
> +	tile_width *= hsub;
> +	tile_height *= vsub;
> +
> +	ccs_x = (x * hsub) % tile_width;
> +	ccs_y = (y * vsub) % tile_height;
> +	main_x = intel_fb->normal[0].x % tile_width;
> +	main_y = intel_fb->normal[0].y % tile_height;
> +
> +	/*
> +	* CCS doesn't have its own x/y offset register, so the intra CCS tile
> +	* x/y offsets must match between CCS and the main surface.
> +	*/

Formatting fail with the comment?

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +	if (main_x != ccs_x || main_y != ccs_y) {
> +		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
> +			      main_x, main_y,
> +			      ccs_x, ccs_y,
> +			      intel_fb->normal[0].x,
> +			      intel_fb->normal[0].y,
> +			      x, y);
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
>  static int
>  intel_fill_fb_info(struct drm_i915_private *dev_priv,
>  		   struct drm_framebuffer *fb)
> @@ -2713,35 +2750,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
>  		}
>  
>  		if (is_ccs_modifier(fb->modifier) && i == 1) {
> -			int hsub = fb->format->hsub;
> -			int vsub = fb->format->vsub;
> -			int tile_width, tile_height;
> -			int main_x, main_y;
> -			int ccs_x, ccs_y;
> -
> -			intel_tile_dims(fb, i, &tile_width, &tile_height);
> -
> -			tile_width *= hsub;
> -			tile_height *= vsub;
> -
> -			ccs_x = (x * hsub) % tile_width;
> -			ccs_y = (y * vsub) % tile_height;
> -			main_x = intel_fb->normal[0].x % tile_width;
> -			main_y = intel_fb->normal[0].y % tile_height;
> -
> -			/*
> -			 * CCS doesn't have its own x/y offset register, so the intra CCS tile
> -			 * x/y offsets must match between CCS and the main surface.
> -			 */
> -			if (main_x != ccs_x || main_y != ccs_y) {
> -				DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
> -					      main_x, main_y,
> -					      ccs_x, ccs_y,
> -					      intel_fb->normal[0].x,
> -					      intel_fb->normal[0].y,
> -					      x, y);
> -				return -EINVAL;
> -			}
> +			ret = intel_fb_check_ccs_xy(fb, x, y);
> +			if (ret)
> +				return ret;
>  		}
>  
>  		/*
> -- 
> 2.17.1

-- 
Ville Syrjälä
Intel
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Re: [RFC v3 5/9] drm/i915: Extract framebufer CCS offset checks into a function

[Matt Roper]

On Mon, Sep 23, 2019 at 03:29:31AM -0700, Dhinakaran Pandiyan wrote:
> intel_fill_fb_info() has grown quite large and wrapping the offset checks
> into a separate function makes the loop a bit easier to follow.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

I agree with Ville's comments, but otherwise,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 69 ++++++++++++--------
>  1 file changed, 40 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6fec43cdddf4..7447001c1f85 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2682,6 +2682,43 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
>  	return stride > max_stride;
>  }
>  
> +static int
> +intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
> +{
> +	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> +	int hsub = fb->format->hsub;
> +	int vsub = fb->format->vsub;
> +	int tile_width, tile_height;
> +	int ccs_x, ccs_y;
> +	int main_x, main_y;
> +
> +	intel_tile_dims(fb, 1, &tile_width, &tile_height);
> +
> +	tile_width *= hsub;
> +	tile_height *= vsub;
> +
> +	ccs_x = (x * hsub) % tile_width;
> +	ccs_y = (y * vsub) % tile_height;
> +	main_x = intel_fb->normal[0].x % tile_width;
> +	main_y = intel_fb->normal[0].y % tile_height;
> +
> +	/*
> +	* CCS doesn't have its own x/y offset register, so the intra CCS tile
> +	* x/y offsets must match between CCS and the main surface.
> +	*/
> +	if (main_x != ccs_x || main_y != ccs_y) {
> +		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
> +			      main_x, main_y,
> +			      ccs_x, ccs_y,
> +			      intel_fb->normal[0].x,
> +			      intel_fb->normal[0].y,
> +			      x, y);
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
>  static int
>  intel_fill_fb_info(struct drm_i915_private *dev_priv,
>  		   struct drm_framebuffer *fb)
> @@ -2713,35 +2750,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
>  		}
>  
>  		if (is_ccs_modifier(fb->modifier) && i == 1) {
> -			int hsub = fb->format->hsub;
> -			int vsub = fb->format->vsub;
> -			int tile_width, tile_height;
> -			int main_x, main_y;
> -			int ccs_x, ccs_y;
> -
> -			intel_tile_dims(fb, i, &tile_width, &tile_height);
> -
> -			tile_width *= hsub;
> -			tile_height *= vsub;
> -
> -			ccs_x = (x * hsub) % tile_width;
> -			ccs_y = (y * vsub) % tile_height;
> -			main_x = intel_fb->normal[0].x % tile_width;
> -			main_y = intel_fb->normal[0].y % tile_height;
> -
> -			/*
> -			 * CCS doesn't have its own x/y offset register, so the intra CCS tile
> -			 * x/y offsets must match between CCS and the main surface.
> -			 */
> -			if (main_x != ccs_x || main_y != ccs_y) {
> -				DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
> -					      main_x, main_y,
> -					      ccs_x, ccs_y,
> -					      intel_fb->normal[0].x,
> -					      intel_fb->normal[0].y,
> -					      x, y);
> -				return -EINVAL;
> -			}
> +			ret = intel_fb_check_ccs_xy(fb, x, y);
> +			if (ret)
> +				return ret;
>  		}
>  
>  		/*
> -- 
> 2.17.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
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[RFC v3 6/9] drm/framebuffer: Format modifier for Intel Gen-12 media compression

[Dhinakaran Pandiyan]

Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.

Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 1f0fbf0398f6..c4a4e0fdbee5 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -421,6 +421,19 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
 
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths. For semi-planar formats like NV12, CCS plane follows the
+ * Y and UV planes i.e., planes 0 and 2 are used for Y and UV surfaces,
+ * planes 1 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.17.1

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Re: [RFC v3 6/9] drm/framebuffer: Format modifier for Intel Gen-12 media compression

[Pandiyan, Dhinakaran]

On Mon, 2019-09-23 at 03:29 -0700, Dhinakaran Pandiyan wrote:
> Gen-12 display can decompress surfaces compressed by the media engine, add
> a new modifier as the driver needs to know the surface was compressed by
> the media or render engine.
> 
> Cc: Nanley G Chery <nanley.g.chery@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

Cc: Guangyao

> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  include/uapi/drm/drm_fourcc.h | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 1f0fbf0398f6..c4a4e0fdbee5 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -421,6 +421,19 @@ extern "C" {
>   */
>  #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
>  
> +/*
> + * Intel color control surfaces (CCS) for Gen-12 media compression
> + *
> + * The main surface is Y-tiled and at plane index 0, the CCS is linear and
> + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
> + * main surface. In other words, 4 bits in CCS map to a main surface cache
> + * line pair. The main surface pitch is required to be a multiple of four
> + * Y-tile widths. For semi-planar formats like NV12, CCS plane follows the
> + * Y and UV planes i.e., planes 0 and 2 are used for Y and UV surfaces,
> + * planes 1 and 3 for the respective CCS.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>   *
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[RFC v3 7/9] drm/i915: Skip rotated offset adjustment for unsupported modifiers

[Dhinakaran Pandiyan]

During framebuffer creation, we pre-compute offsets for 90/270 plane
rotation. However, only Y and Yf modifiers support 90/270 rotation. So,
skip the calculations for other modifiers.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7447001c1f85..6f0f38157697 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2784,7 +2784,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 						      tile_size);
 		offset /= tile_size;
 
-		if (!is_surface_linear(fb->modifier, i)) {
+		/* Y or Yf modifiers required for 90/270 rotation */
+		if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
+		    fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
 			unsigned int tile_width, tile_height;
 			unsigned int pitch_tiles;
 			struct drm_rect r;
-- 
2.17.1

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Re: [RFC v3 7/9] drm/i915: Skip rotated offset adjustment for unsupported modifiers

[Dhinakaran Pandiyan]

On Mon, 2019-09-23 at 03:29 -0700, Dhinakaran Pandiyan wrote:
> During framebuffer creation, we pre-compute offsets for 90/270 plane
> rotation. However, only Y and Yf modifiers support 90/270 rotation. So,
> skip the calculations for other modifiers.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 7447001c1f85..6f0f38157697 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2784,7 +2784,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
>  						      tile_size);
>  		offset /= tile_size;
>  
> -		if (!is_surface_linear(fb->modifier, i)) {
> +		/* Y or Yf modifiers required for 90/270 rotation */
> +		if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
> +		    fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
This is wrong, as CI results clearly show igt@kms_addfb_basic@bo-too-small-due-to-tiling fails.
Please ignore this patch.

-DK

>  			unsigned int tile_width, tile_height;
>  			unsigned int pitch_tiles;
>  			struct drm_rect r;

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[RFC v3 8/9] drm/fb: Extend format_info member arrays to handle four planes

[Dhinakaran Pandiyan]

addfb() uAPI has supported four planes for a while now, make format_info
compatible with that.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 include/drm/drm_fourcc.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 306d1efeb5e0..156b122c0ad5 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -78,7 +78,7 @@ struct drm_format_info {
 		 * triplet @char_per_block, @block_w, @block_h for better
 		 * describing the pixel format.
 		 */
-		u8 cpp[3];
+		u8 cpp[4];
 
 		/**
 		 * @char_per_block:
@@ -104,7 +104,7 @@ struct drm_format_info {
 		 * information from their drm_mode_config.get_format_info hook
 		 * if they want the core to be validating the pitch.
 		 */
-		u8 char_per_block[3];
+		u8 char_per_block[4];
 	};
 
 	/**
@@ -113,7 +113,7 @@ struct drm_format_info {
 	 * Block width in pixels, this is intended to be accessed through
 	 * drm_format_info_block_width()
 	 */
-	u8 block_w[3];
+	u8 block_w[4];
 
 	/**
 	 * @block_h:
@@ -121,7 +121,7 @@ struct drm_format_info {
 	 * Block height in pixels, this is intended to be accessed through
 	 * drm_format_info_block_height()
 	 */
-	u8 block_h[3];
+	u8 block_h[4];
 
 	/** @hsub: Horizontal chroma subsampling factor */
 	u8 hsub;
-- 
2.17.1

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[RFC v3 9/9] Gen-12 display can decompress surfaces compressed by the media engine.

[Dhinakaran Pandiyan]

Detect the modifier corresponding to media compression to enable
display decompression for YUV and xRGB packed formats. A new modifier is
added so that the driver can distinguish between media and render
compressed buffers. Unlike render decompression, plane 6 and  plane 7 do not
support media decompression.

v2: Fix checkpatch warnings on code style (Lucas)

From DK:
Separate modifier array for planes that cannot decompress media (Ville)

v3: Support planar formats

Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 239 +++++++++++++-----
 .../drm/i915/display/intel_display_types.h    |   2 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  44 +++-
 drivers/gpu/drm/i915/i915_reg.h               |   1 +
 4 files changed, 222 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6f0f38157697..e55ef715b53d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1911,6 +1911,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 		if (color_plane == 1)
 			return 128;
 		/* fall through */
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		if (color_plane == 3)
+			return 64;
+		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		if (color_plane == 1)
 			return 64;
@@ -2256,8 +2260,16 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
 
 static bool is_surface_linear(u64 modifier, int color_plane)
 {
-	return modifier == DRM_FORMAT_MOD_LINEAR ||
-	       (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
+	switch (modifier) {
+	case DRM_FORMAT_MOD_LINEAR:
+		return true;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+		return color_plane == 1;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		return color_plane == 1 || color_plane == 3;
+	default:
+		return false;
+	}
 }
 
 static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2445,6 +2457,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return I915_TILING_Y;
 	default:
 		return I915_TILING_NONE;
@@ -2492,6 +2505,10 @@ static const struct drm_format_info gen12_ccs_formats[] = {
 	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
 	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
 	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+	{ .format = DRM_FORMAT_YUYV, .num_planes = 2,
+	  .cpp = { 2, 1, }, .hsub = 4, .vsub = 32, .is_yuv = true },
+	{ .format = DRM_FORMAT_NV12, .num_planes = 4,
+	  .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
 };
 
 static const struct drm_format_info *
@@ -2529,6 +2546,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 bool is_ccs_modifier(u64 modifier)
 {
 	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
 	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 }
@@ -2592,7 +2610,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 	}
 
 	tile_width = intel_tile_width_bytes(fb, color_plane);
-	if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
+	if (is_ccs_modifier(fb->modifier)) {
 		/*
 		 * Display WA #0531: skl,bxt,kbl,glk
 		 *
@@ -2602,7 +2620,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 		 * require the entire fb to accommodate that to avoid
 		 * potential runtime errors at plane configuration time.
 		 */
-		if (IS_GEN(dev_priv, 9) && fb->width > 3840)
+		if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
 			tile_width *= 4;
 		/*
 		 * The main surface pitch must be padded to a multiple of four
@@ -2682,25 +2700,71 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
 	return stride > max_stride;
 }
 
+static void
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)
+{
+	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) {
+		static const struct {
+			int cpp[4];
+			int vsub[4];
+			int hsub[4];
+		} mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2, 16}, .vsub = {1, 32, 2, 32}};
+
+		*hsub = mc_ccs_subsampling.hsub[color_plane];
+		*vsub = mc_ccs_subsampling.vsub[color_plane];
+	} else {
+		*hsub = fb->format->hsub;
+		*vsub = fb->format->vsub;
+	}
+}
+
+static void
+intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
+{
+	int hsub, vsub;
+
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
+	*w = fb->width/hsub;
+	*h = fb->height/vsub;
+}
+
+static bool is_ccs_plane(u64 modifier, int color_plane)
+{
+	if (!is_ccs_modifier(modifier))
+		return false;
+	else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+		return color_plane == 3 || color_plane == 1;
+	else
+		return color_plane == 1;
+}
+
 static int
-intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
+intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int color_plane, int x, int y)
 {
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-	int hsub = fb->format->hsub;
-	int vsub = fb->format->vsub;
+	int hsub, vsub;
+	int hsub_main, vsub_main;
 	int tile_width, tile_height;
 	int ccs_x, ccs_y;
 	int main_x, main_y;
 
-	intel_tile_dims(fb, 1, &tile_width, &tile_height);
+	if (!is_ccs_plane(fb->modifier, color_plane))
+		return 0;
+
+	intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
+	intel_fb_plane_get_subsampling(&hsub_main, &vsub_main, fb, color_plane - 1);
+
+	hsub /= hsub_main;
+	vsub /= vsub_main;
 
 	tile_width *= hsub;
 	tile_height *= vsub;
 
 	ccs_x = (x * hsub) % tile_width;
 	ccs_y = (y * vsub) % tile_height;
-	main_x = intel_fb->normal[0].x % tile_width;
-	main_y = intel_fb->normal[0].y % tile_height;
+	main_x = intel_fb->normal[color_plane - 1].x % tile_width;
+	main_y = intel_fb->normal[color_plane - 1].y % tile_height;
 
 	/*
 	* CCS doesn't have its own x/y offset register, so the intra CCS tile
@@ -2710,8 +2774,8 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
 		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
 			      main_x, main_y,
 			      ccs_x, ccs_y,
-			      intel_fb->normal[0].x,
-			      intel_fb->normal[0].y,
+			      intel_fb->normal[color_plane - 1].x,
+			      intel_fb->normal[color_plane - 1].y,
 			      x, y);
 		return -EINVAL;
 	}
@@ -2739,8 +2803,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 		int ret;
 
 		cpp = fb->format->cpp[i];
-		width = drm_framebuffer_plane_width(fb->width, fb, i);
-		height = drm_framebuffer_plane_height(fb->height, fb, i);
+		intel_fb_plane_dims(&width, &height, fb, i);
 
 		ret = intel_fb_offset_to_xy(&x, &y, fb, i);
 		if (ret) {
@@ -2749,11 +2812,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 			return ret;
 		}
 
-		if (is_ccs_modifier(fb->modifier) && i == 1) {
-			ret = intel_fb_check_ccs_xy(fb, x, y);
-			if (ret)
-				return ret;
-		}
+		ret = intel_fb_check_ccs_xy(fb, i, x, y);
+		if (ret)
+			return ret;
 
 		/*
 		 * The fence (if used) is aligned to the start of the object
@@ -3371,6 +3432,7 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb,
 			return 5120;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		/* FIXME AUX plane? */
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Yf_TILED:
@@ -3430,16 +3492,18 @@ static int icl_max_plane_height(void)
 }
 
 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
-					   int main_x, int main_y, u32 main_offset)
+					   int main_x, int main_y, u32 main_offset,
+					   int aux_plane)
 {
 	const struct drm_framebuffer *fb = plane_state->base.fb;
-	int hsub = fb->format->hsub;
-	int vsub = fb->format->vsub;
-	int aux_x = plane_state->color_plane[1].x;
-	int aux_y = plane_state->color_plane[1].y;
-	u32 aux_offset = plane_state->color_plane[1].offset;
-	u32 alignment = intel_surf_alignment(fb, 1);
-
+	int hsub;
+	int vsub;
+	int aux_x = plane_state->color_plane[aux_plane].x;
+	int aux_y = plane_state->color_plane[aux_plane].y;
+	u32 aux_offset = plane_state->color_plane[aux_plane].offset;
+	u32 alignment = intel_surf_alignment(fb, aux_plane);
+
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, aux_plane);
 	while (aux_offset >= main_offset && aux_y <= main_y) {
 		int x, y;
 
@@ -3451,7 +3515,7 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
 
 		x = aux_x / hsub;
 		y = aux_y / vsub;
-		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
+		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, aux_plane,
 							       aux_offset, aux_offset - alignment);
 		aux_x = x * hsub + aux_x % hsub;
 		aux_y = y * vsub + aux_y % vsub;
@@ -3460,9 +3524,9 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
 	if (aux_x != main_x || aux_y != main_y)
 		return false;
 
-	plane_state->color_plane[1].offset = aux_offset;
-	plane_state->color_plane[1].x = aux_x;
-	plane_state->color_plane[1].y = aux_y;
+	plane_state->color_plane[aux_plane].offset = aux_offset;
+	plane_state->color_plane[aux_plane].x = aux_x;
+	plane_state->color_plane[aux_plane].y = aux_y;
 
 	return true;
 }
@@ -3536,7 +3600,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
 	 * they match with the main surface x/y offsets.
 	 */
 	if (is_ccs_modifier(fb->modifier)) {
-		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
+		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset, 1)) {
 			if (offset == 0)
 				break;
 
@@ -3569,7 +3633,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 {
 	const struct drm_framebuffer *fb = plane_state->base.fb;
 	unsigned int rotation = plane_state->base.rotation;
-	int max_width = skl_max_plane_width(fb, 1, rotation);
+	int uv = is_ccs_modifier(fb->modifier) ? 2 : 1;
+	int max_width = skl_max_plane_width(fb, uv, rotation);
 	int max_height = 4096;
 	int x = plane_state->base.src.x1 >> 17;
 	int y = plane_state->base.src.y1 >> 17;
@@ -3577,8 +3642,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 	int h = drm_rect_height(&plane_state->base.src) >> 17;
 	u32 offset;
 
-	intel_add_fb_offsets(&x, &y, plane_state, 1);
-	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
+	intel_add_fb_offsets(&x, &y, plane_state, uv);
+	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, uv);
 
 	/* FIXME not quite sure how/if these apply to the chroma plane */
 	if (w > max_width || h > max_height) {
@@ -3587,9 +3652,43 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 		return -EINVAL;
 	}
 
-	plane_state->color_plane[1].offset = offset;
-	plane_state->color_plane[1].x = x;
-	plane_state->color_plane[1].y = y;
+	if (is_ccs_modifier(fb->modifier)) {
+		int aux_offset = plane_state->color_plane[3].offset;
+		int alignment = intel_surf_alignment(fb, uv);
+
+		if (offset > aux_offset) {
+			int hsub, vsub;
+			int main_x = x, main_y = y;
+
+
+			intel_fb_plane_get_subsampling(&hsub, &vsub, fb, uv);
+			x = main_x / hsub;
+			y = main_y / vsub;
+			offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, uv,
+								   offset,
+								   aux_offset & ~(alignment - 1));
+			x = x * hsub + main_x % hsub;
+			y = y * vsub + main_y % vsub;
+
+		}
+
+		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset, 3)) {
+			if (offset == 0)
+				break;
+
+			offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, uv,
+								   offset, offset - alignment);
+		}
+
+		if (x != plane_state->color_plane[3].x || y != plane_state->color_plane[3].y) {
+			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
+			return -EINVAL;
+		}
+	}
+
+	plane_state->color_plane[uv].offset = offset;
+	plane_state->color_plane[uv].x = x;
+	plane_state->color_plane[uv].y = y;
 
 	return 0;
 }
@@ -3599,19 +3698,30 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
 	const struct drm_framebuffer *fb = plane_state->base.fb;
 	int src_x = plane_state->base.src.x1 >> 16;
 	int src_y = plane_state->base.src.y1 >> 16;
-	int hsub = fb->format->hsub;
-	int vsub = fb->format->vsub;
-	int x = src_x / hsub;
-	int y = src_y / vsub;
 	u32 offset;
+	int ccs;
+
 
-	intel_add_fb_offsets(&x, &y, plane_state, 1);
-	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
+	for (ccs = 1; ccs < fb->format->num_planes; ccs += 2) {
+		int hsub, vsub;
+		int main_hsub, main_vsub;
+		int x, y;
 
-	plane_state->color_plane[1].offset = offset;
-	plane_state->color_plane[1].x = x * hsub + src_x % hsub;
-	plane_state->color_plane[1].y = y * vsub + src_y % vsub;
+		intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs);
+		intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, ccs - 1);
 
+		hsub /= main_hsub;
+		vsub /= main_vsub;
+		x = src_x / hsub;
+		y = src_y / vsub;
+
+		intel_add_fb_offsets(&x, &y, plane_state, ccs);
+		offset = intel_plane_compute_aligned_offset(&x, &y,
+							    plane_state, ccs);
+		plane_state->color_plane[ccs].offset = offset;
+		plane_state->color_plane[ccs].x = x * hsub + src_x % hsub;
+		plane_state->color_plane[ccs].y = y * vsub + src_y % vsub;
+	}
 	return 0;
 }
 
@@ -3619,6 +3729,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
 {
 	const struct drm_framebuffer *fb = plane_state->base.fb;
 	int ret;
+	bool needs_aux = false;
 
 	ret = intel_plane_compute_gtt(plane_state);
 	if (ret)
@@ -3628,21 +3739,31 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
 		return 0;
 
 	/*
-	 * Handle the AUX surface first since
-	 * the main surface setup depends on it.
+	 * Handle the AUX surface first since the main surface setup depends on
+	 * it.
 	 */
-	if (drm_format_info_is_yuv_semiplanar(fb->format)) {
-		ret = skl_check_nv12_aux_surface(plane_state);
+	if (is_ccs_modifier(fb->modifier)) {
+		needs_aux = true;
+		ret = skl_check_ccs_aux_surface(plane_state);
 		if (ret)
 			return ret;
-	} else if (is_ccs_modifier(fb->modifier)) {
-		ret = skl_check_ccs_aux_surface(plane_state);
+	}
+
+	if (drm_format_info_is_yuv_semiplanar(fb->format)) {
+		needs_aux = true;
+		ret = skl_check_nv12_aux_surface(plane_state);
 		if (ret)
 			return ret;
-	} else {
-		plane_state->color_plane[1].offset = ~0xfff;
-		plane_state->color_plane[1].x = 0;
-		plane_state->color_plane[1].y = 0;
+	}
+
+	if (!needs_aux) {
+		int i;
+
+		for (i = 1; i < fb->format->num_planes; i++) {
+			plane_state->color_plane[i].offset = ~0xfff;
+			plane_state->color_plane[i].x = 0;
+			plane_state->color_plane[i].y = 0;
+		}
 	}
 
 	ret = skl_check_main_surface(plane_state);
@@ -4160,6 +4281,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 		return PLANE_CTL_TILED_Y |
 		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
 		       PLANE_CTL_CLEAR_COLOR_DISABLE;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
 	case I915_FORMAT_MOD_Yf_TILED:
 		return PLANE_CTL_TILED_YF;
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -9964,6 +10087,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
 				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
 				I915_FORMAT_MOD_Y_TILED_CCS;
+		else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
+			fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
 		else
 			fb->modifier = I915_FORMAT_MOD_Y_TILED;
 		break;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 49c902b00484..a4d2ebae407a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -530,7 +530,7 @@ struct intel_plane_state {
 		 */
 		u32 stride;
 		int x, y;
-	} color_plane[2];
+	} color_plane[4];
 
 	/* plane control register */
 	u32 ctl;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 866d25d38d04..ad28ee94c968 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1737,7 +1737,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
-	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
 		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
 		return -EINVAL;
 	}
@@ -2149,7 +2150,16 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
 	DRM_FORMAT_MOD_INVALID
 };
 
-static const u64 gen12_plane_format_modifiers_ccs[] = {
+static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
+	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
+	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+	I915_FORMAT_MOD_Y_TILED,
+	I915_FORMAT_MOD_X_TILED,
+	DRM_FORMAT_MOD_LINEAR,
+	DRM_FORMAT_MOD_INVALID
+};
+
+static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
 	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
@@ -2305,10 +2315,21 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 	}
 }
 
+static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id)
+{
+	return plane_id < PLANE_SPRITE4;
+}
+
 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 					     u32 format, u64 modifier)
 {
+	struct intel_plane *plane = to_intel_plane(_plane);
+
 	switch (modifier) {
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		if (!gen12_plane_supports_mc_ccs(plane->id))
+			return false;
+		/* fall through */
 	case DRM_FORMAT_MOD_LINEAR:
 	case I915_FORMAT_MOD_X_TILED:
 	case I915_FORMAT_MOD_Y_TILED:
@@ -2326,14 +2347,17 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 		if (is_ccs_modifier(modifier))
 			return true;
 		/* fall through */
-	case DRM_FORMAT_RGB565:
-	case DRM_FORMAT_XRGB2101010:
-	case DRM_FORMAT_XBGR2101010:
 	case DRM_FORMAT_YUYV:
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
+		if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+			return true;
+		/* fall through */
 	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_RGB565:
+	case DRM_FORMAT_XRGB2101010:
+	case DRM_FORMAT_XBGR2101010:
 	case DRM_FORMAT_P010:
 	case DRM_FORMAT_P012:
 	case DRM_FORMAT_P016:
@@ -2470,6 +2494,14 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
 	}
 }
 
+static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id)
+{
+	if (gen12_plane_supports_mc_ccs(plane_id))
+		return gen12_plane_format_modifiers_mc_ccs;
+	else
+		return gen12_plane_format_modifiers_rc_ccs;
+}
+
 static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
 			      enum pipe pipe, enum plane_id plane_id)
 {
@@ -2536,7 +2568,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 
 	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
 	if (INTEL_GEN(dev_priv) >= 12) {
-		modifiers = gen12_plane_format_modifiers_ccs;
+		modifiers = gen12_get_plane_modifiers(plane_id);
 		plane_funcs = &gen12_plane_funcs;
 	} else {
 		if (plane->has_ccs)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b465eae11763..c8ba8dc6e45b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6696,6 +6696,7 @@ enum {
 #define   PLANE_CTL_TILED_Y			(4 << 10)
 #define   PLANE_CTL_TILED_YF			(5 << 10)
 #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
+#define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
 #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
 #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(2 << 4)
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v4 9/9] Gen-12 display can decompress surfaces compressed by the media engine.

[Dhinakaran Pandiyan]

Detect the modifier corresponding to media compression to enable
display decompression for YUV and xRGB packed formats. A new modifier is
added so that the driver can distinguish between media and render
compressed buffers. Unlike render decompression, plane 6 and  plane 7 do not
support media decompression.

v2: Fix checkpatch warnings on code style (Lucas)

From DK:
Separate modifier array for planes that cannot decompress media (Ville)

v3: Support planar formats
v4: Switch plane order

Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 290 +++++++++++++-----
 .../drm/i915/display/intel_display_types.h    |   2 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  55 +++-
 drivers/gpu/drm/i915/i915_reg.h               |   1 +
 4 files changed, 267 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8ea55d67442c..df3ebaa167ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1888,6 +1888,22 @@ static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
 		intel_wait_for_pipe_off(old_crtc_state);
 }
 
+bool is_ccs_modifier(u64 modifier)
+{
+	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+}
+
+static bool is_ccs_plane(const struct drm_framebuffer *fb, int color_plane)
+{
+	if (!is_ccs_modifier(fb->modifier))
+		return false;
+
+	return color_plane >= fb->format->num_planes / 2;
+}
+
 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
 {
 	return IS_GEN(dev_priv, 2) ? 2048 : 4096;
@@ -1908,11 +1924,13 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 		else
 			return 512;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
-		if (color_plane == 1)
+		if (is_ccs_plane(fb, color_plane))
 			return 128;
 		/* fall through */
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
-		if (color_plane == 1)
+		if (is_ccs_plane(fb, color_plane))
 			return 64;
 		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED:
@@ -1921,7 +1939,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 		else
 			return 512;
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
-		if (color_plane == 1)
+		if (is_ccs_plane(fb, color_plane))
 			return 128;
 		/* fall through */
 	case I915_FORMAT_MOD_Yf_TILED:
@@ -1949,8 +1967,9 @@ static unsigned int
 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
 {
 	switch (fb->modifier) {
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
-		if (color_plane == 1)
+		if (is_ccs_plane(fb, color_plane))
 			return 1;
 		/* fall through */
 	default:
@@ -2055,6 +2074,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 		if (INTEL_GEN(dev_priv) >= 9)
 			return 256 * 1024;
 		return 0;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		return 16 * 1024;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
@@ -2254,10 +2274,17 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
 	return new_offset;
 }
 
-static bool is_surface_linear(u64 modifier, int color_plane)
+static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
 {
-	return modifier == DRM_FORMAT_MOD_LINEAR ||
-	       (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
+	switch (fb->modifier) {
+	case DRM_FORMAT_MOD_LINEAR:
+		return true;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		return is_ccs_plane(fb, color_plane);
+	default:
+		return false;
+	}
 }
 
 static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2272,7 +2299,7 @@ static u32 intel_adjust_aligned_offset(int *x, int *y,
 
 	WARN_ON(new_offset > old_offset);
 
-	if (!is_surface_linear(fb->modifier, color_plane)) {
+	if (!is_surface_linear(fb, color_plane)) {
 		unsigned int tile_size, tile_width, tile_height;
 		unsigned int pitch_tiles;
 
@@ -2342,7 +2369,7 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
 	if (alignment)
 		alignment--;
 
-	if (!is_surface_linear(fb->modifier, color_plane)) {
+	if (!is_surface_linear(fb, color_plane)) {
 		unsigned int tile_size, tile_width, tile_height;
 		unsigned int tile_rows, tiles, pitch_tiles;
 
@@ -2445,6 +2472,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		return I915_TILING_Y;
 	default:
 		return I915_TILING_NONE;
@@ -2494,6 +2522,13 @@ static const struct drm_format_info gen12_ccs_formats[] = {
 	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
 };
 
+static const struct drm_format_info gen12_mc_ccs_formats[] = {
+	{ .format = DRM_FORMAT_YUYV, .num_planes = 2,
+	  .cpp = { 2, 1, }, .hsub = 4, .vsub = 32, .is_yuv = true },
+	{ .format = DRM_FORMAT_NV12, .num_planes = 4,
+	  .cpp = { 1, 2, 1, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
+};
+
 static const struct drm_format_info *
 lookup_format_info(const struct drm_format_info formats[],
 		   int num_formats, u32 format)
@@ -2511,12 +2546,21 @@ lookup_format_info(const struct drm_format_info formats[],
 static const struct drm_format_info *
 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 {
+	const struct drm_format_info *info;
+
 	switch (cmd->modifier[0]) {
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
 		return lookup_format_info(skl_ccs_formats,
 					  ARRAY_SIZE(skl_ccs_formats),
 					  cmd->pixel_format);
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		info = lookup_format_info(gen12_mc_ccs_formats,
+					  ARRAY_SIZE(gen12_mc_ccs_formats),
+					  cmd->pixel_format);
+		if (info)
+			return info;
+		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 		return lookup_format_info(gen12_ccs_formats,
 					  ARRAY_SIZE(gen12_ccs_formats),
@@ -2526,13 +2570,6 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 	}
 }
 
-bool is_ccs_modifier(u64 modifier)
-{
-	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
-	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
-	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
-}
-
 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 			      u32 pixel_format, u64 modifier)
 {
@@ -2576,7 +2613,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 	struct drm_i915_private *dev_priv = to_i915(fb->dev);
 	u32 tile_width;
 
-	if (is_surface_linear(fb->modifier, color_plane)) {
+	if (is_surface_linear(fb, color_plane)) {
 		u32 max_stride = intel_plane_fb_max_stride(dev_priv,
 							   fb->format->format,
 							   fb->modifier);
@@ -2592,7 +2629,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 	}
 
 	tile_width = intel_tile_width_bytes(fb, color_plane);
-	if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
+	if (is_ccs_modifier(fb->modifier)) {
 		/*
 		 * Display WA #0531: skl,bxt,kbl,glk
 		 *
@@ -2602,7 +2639,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 		 * require the entire fb to accommodate that to avoid
 		 * potential runtime errors at plane configuration time.
 		 */
-		if (IS_GEN(dev_priv, 9) && fb->width > 3840)
+		if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
 			tile_width *= 4;
 		/*
 		 * The main surface pitch must be padded to a multiple of four
@@ -2682,25 +2719,75 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
 	return stride > max_stride;
 }
 
+static void
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)
+{
+	int i;
+	static const struct {
+		u32 format;
+		int vsub[4];
+		int hsub[4];
+	} mc_ccs_subsampling[] = { { .hsub = { 1, 2, 8, 16 },
+				     .vsub = { 1, 2, 32, 32 },
+				     .format = DRM_FORMAT_NV12, },
+				 };
+
+	*hsub = fb->format->hsub;
+	*vsub = fb->format->vsub;
+
+	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS &&
+	    fb->format->num_planes == 4) {
+		for (i = 0; i < ARRAY_SIZE(mc_ccs_subsampling); i++) {
+			if  (mc_ccs_subsampling[i].format == fb->format->format) {
+				*hsub = mc_ccs_subsampling[i].hsub[color_plane];
+				*vsub = mc_ccs_subsampling[i].vsub[color_plane];
+				break;
+			}
+		}
+		WARN_ON(i == ARRAY_SIZE(mc_ccs_subsampling));
+	}
+}
+
+static void
+intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
+{
+	int hsub, vsub;
+
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
+	*w = fb->width/hsub;
+	*h = fb->height/vsub;
+}
+
 static int
-intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
+intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int aux_plane, int x, int y)
 {
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-	int hsub = fb->format->hsub;
-	int vsub = fb->format->vsub;
+	int hsub, vsub;
+	int hsub_main, vsub_main;
 	int tile_width, tile_height;
 	int ccs_x, ccs_y;
 	int main_x, main_y;
+	int main_plane;
+
+	if (!is_ccs_plane(fb, aux_plane))
+		return 0;
+
+	main_plane = (aux_plane - 1) / 2;
+	intel_tile_dims(fb, aux_plane, &tile_width, &tile_height);
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, aux_plane);
+	intel_fb_plane_get_subsampling(&hsub_main, &vsub_main, fb,
+				       main_plane);
 
-	intel_tile_dims(fb, 1, &tile_width, &tile_height);
+	hsub /= hsub_main;
+	vsub /= vsub_main;
 
 	tile_width *= hsub;
 	tile_height *= vsub;
 
 	ccs_x = (x * hsub) % tile_width;
 	ccs_y = (y * vsub) % tile_height;
-	main_x = intel_fb->normal[0].x % tile_width;
-	main_y = intel_fb->normal[0].y % tile_height;
+	main_x = intel_fb->normal[main_plane].x % tile_width;
+	main_y = intel_fb->normal[main_plane].y % tile_height;
 
 	/*
 	* CCS doesn't have its own x/y offset register, so the intra CCS tile
@@ -2710,8 +2797,8 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
 		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
 			      main_x, main_y,
 			      ccs_x, ccs_y,
-			      intel_fb->normal[0].x,
-			      intel_fb->normal[0].y,
+			      intel_fb->normal[main_plane].x,
+			      intel_fb->normal[main_plane].y,
 			      x, y);
 		return -EINVAL;
 	}
@@ -2739,8 +2826,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 		int ret;
 
 		cpp = fb->format->cpp[i];
-		width = drm_framebuffer_plane_width(fb->width, fb, i);
-		height = drm_framebuffer_plane_height(fb->height, fb, i);
+		intel_fb_plane_dims(&width, &height, fb, i);
 
 		ret = intel_fb_offset_to_xy(&x, &y, fb, i);
 		if (ret) {
@@ -2749,11 +2835,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 			return ret;
 		}
 
-		if (is_ccs_modifier(fb->modifier) && i == 1) {
-			ret = intel_fb_check_ccs_xy(fb, x, y);
-			if (ret)
-				return ret;
-		}
+		ret = intel_fb_check_ccs_xy(fb, i, x, y);
+		if (ret)
+			return ret;
 
 		/*
 		 * The fence (if used) is aligned to the start of the object
@@ -3371,6 +3455,7 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb,
 			return 5120;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 		/* FIXME AUX plane? */
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Yf_TILED:
@@ -3430,16 +3515,18 @@ static int icl_max_plane_height(void)
 }
 
 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
-					   int main_x, int main_y, u32 main_offset)
+					   int main_x, int main_y,
+					   u32 main_offset, int aux_plane)
 {
 	const struct drm_framebuffer *fb = plane_state->base.fb;
-	int hsub = fb->format->hsub;
-	int vsub = fb->format->vsub;
-	int aux_x = plane_state->color_plane[1].x;
-	int aux_y = plane_state->color_plane[1].y;
-	u32 aux_offset = plane_state->color_plane[1].offset;
-	u32 alignment = intel_surf_alignment(fb, 1);
-
+	int hsub;
+	int vsub;
+	int aux_x = plane_state->color_plane[aux_plane].x;
+	int aux_y = plane_state->color_plane[aux_plane].y;
+	u32 aux_offset = plane_state->color_plane[aux_plane].offset;
+	u32 alignment = intel_surf_alignment(fb, aux_plane);
+
+	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, aux_plane);
 	while (aux_offset >= main_offset && aux_y <= main_y) {
 		int x, y;
 
@@ -3451,7 +3538,7 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
 
 		x = aux_x / hsub;
 		y = aux_y / vsub;
-		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
+		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, aux_plane,
 							       aux_offset, aux_offset - alignment);
 		aux_x = x * hsub + aux_x % hsub;
 		aux_y = y * vsub + aux_y % vsub;
@@ -3460,9 +3547,9 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
 	if (aux_x != main_x || aux_y != main_y)
 		return false;
 
-	plane_state->color_plane[1].offset = aux_offset;
-	plane_state->color_plane[1].x = aux_x;
-	plane_state->color_plane[1].y = aux_y;
+	plane_state->color_plane[aux_plane].offset = aux_offset;
+	plane_state->color_plane[aux_plane].x = aux_x;
+	plane_state->color_plane[aux_plane].y = aux_y;
 
 	return true;
 }
@@ -3478,7 +3565,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
 	int h = drm_rect_height(&plane_state->base.src) >> 16;
 	int max_width;
 	int max_height;
-	u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
+	int aux_plane = fb->format->num_planes / 2;
+	u32 alignment, offset, aux_offset = plane_state->color_plane[aux_plane].offset;
 
 	if (INTEL_GEN(dev_priv) >= 11)
 		max_width = icl_max_plane_width(fb, 0, rotation);
@@ -3536,7 +3624,9 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
 	 * they match with the main surface x/y offsets.
 	 */
 	if (is_ccs_modifier(fb->modifier)) {
-		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
+
+		while (!skl_check_main_ccs_coordinates(plane_state, x, y,
+						       offset, aux_plane)) {
 			if (offset == 0)
 				break;
 
@@ -3544,7 +3634,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
 								   offset, offset - alignment);
 		}
 
-		if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
+		if (x != plane_state->color_plane[aux_plane].x ||
+		    y != plane_state->color_plane[aux_plane].y) {
 			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
 			return -EINVAL;
 		}
@@ -3587,6 +3678,41 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 		return -EINVAL;
 	}
 
+	if (is_ccs_modifier(fb->modifier)) {
+		int aux_offset = plane_state->color_plane[3].offset;
+		int alignment = intel_surf_alignment(fb, 1);
+
+		if (offset > aux_offset) {
+			int hsub, vsub;
+			int main_x = x, main_y = y;
+
+
+			intel_fb_plane_get_subsampling(&hsub, &vsub, fb, 1);
+			x = main_x / hsub;
+			y = main_y / vsub;
+			offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
+								   offset,
+								   aux_offset & ~(alignment - 1));
+			x = x * hsub + main_x % hsub;
+			y = y * vsub + main_y % vsub;
+
+		}
+
+		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset, 3)) {
+			if (offset == 0)
+				break;
+
+			offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
+								   offset, offset - alignment);
+		}
+
+		if (x != plane_state->color_plane[3].x ||
+		    y != plane_state->color_plane[3].y) {
+			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
+			return -EINVAL;
+		}
+	}
+
 	plane_state->color_plane[1].offset = offset;
 	plane_state->color_plane[1].x = x;
 	plane_state->color_plane[1].y = y;
@@ -3599,19 +3725,30 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
 	const struct drm_framebuffer *fb = plane_state->base.fb;
 	int src_x = plane_state->base.src.x1 >> 16;
 	int src_y = plane_state->base.src.y1 >> 16;
-	int hsub = fb->format->hsub;
-	int vsub = fb->format->vsub;
-	int x = src_x / hsub;
-	int y = src_y / vsub;
 	u32 offset;
+	int ccs;
 
-	intel_add_fb_offsets(&x, &y, plane_state, 1);
-	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
 
-	plane_state->color_plane[1].offset = offset;
-	plane_state->color_plane[1].x = x * hsub + src_x % hsub;
-	plane_state->color_plane[1].y = y * vsub + src_y % vsub;
+	for (ccs = fb->format->num_planes / 2; ccs < fb->format->num_planes; ccs++) {
+		int hsub, vsub;
+		int main_hsub, main_vsub;
+		int x, y;
+
+		intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs);
+		intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, (ccs - 1)/ 2);
+
+		hsub /= main_hsub;
+		vsub /= main_vsub;
+		x = src_x / hsub;
+		y = src_y / vsub;
 
+		intel_add_fb_offsets(&x, &y, plane_state, ccs);
+		offset = intel_plane_compute_aligned_offset(&x, &y,
+							    plane_state, ccs);
+		plane_state->color_plane[ccs].offset = offset;
+		plane_state->color_plane[ccs].x = x * hsub + src_x % hsub;
+		plane_state->color_plane[ccs].y = y * vsub + src_y % vsub;
+	}
 	return 0;
 }
 
@@ -3619,6 +3756,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
 {
 	const struct drm_framebuffer *fb = plane_state->base.fb;
 	int ret;
+	bool needs_aux = false;
 
 	ret = intel_plane_compute_gtt(plane_state);
 	if (ret)
@@ -3628,21 +3766,31 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
 		return 0;
 
 	/*
-	 * Handle the AUX surface first since
-	 * the main surface setup depends on it.
+	 * Handle the AUX surface first since the main surface setup depends on
+	 * it.
 	 */
-	if (drm_format_info_is_yuv_semiplanar(fb->format)) {
-		ret = skl_check_nv12_aux_surface(plane_state);
+	if (is_ccs_modifier(fb->modifier)) {
+		needs_aux = true;
+		ret = skl_check_ccs_aux_surface(plane_state);
 		if (ret)
 			return ret;
-	} else if (is_ccs_modifier(fb->modifier)) {
-		ret = skl_check_ccs_aux_surface(plane_state);
+	}
+
+	if (drm_format_info_is_yuv_semiplanar(fb->format)) {
+		needs_aux = true;
+		ret = skl_check_nv12_aux_surface(plane_state);
 		if (ret)
 			return ret;
-	} else {
-		plane_state->color_plane[1].offset = ~0xfff;
-		plane_state->color_plane[1].x = 0;
-		plane_state->color_plane[1].y = 0;
+	}
+
+	if (!needs_aux) {
+		int i;
+
+		for (i = 1; i < fb->format->num_planes; i++) {
+			plane_state->color_plane[i].offset = ~0xfff;
+			plane_state->color_plane[i].x = 0;
+			plane_state->color_plane[i].y = 0;
+		}
 	}
 
 	ret = skl_check_main_surface(plane_state);
@@ -4030,7 +4178,7 @@ static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
 	 * The stride is either expressed as a multiple of 64 bytes chunks for
 	 * linear buffers or in number of tiles for tiled buffers.
 	 */
-	if (is_surface_linear(fb->modifier, color_plane))
+	if (is_surface_linear(fb, color_plane))
 		return 64;
 	else if (drm_rotation_90_or_270(rotation))
 		return intel_tile_height(fb, color_plane);
@@ -4160,6 +4308,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 		return PLANE_CTL_TILED_Y |
 		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
 		       PLANE_CTL_CLEAR_COLOR_DISABLE;
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
 	case I915_FORMAT_MOD_Yf_TILED:
 		return PLANE_CTL_TILED_YF;
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -9968,6 +10118,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
 				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
 				I915_FORMAT_MOD_Y_TILED_CCS;
+		else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
+			fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
 		else
 			fb->modifier = I915_FORMAT_MOD_Y_TILED;
 		break;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 976669f01a8c..5998b959225c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -530,7 +530,7 @@ struct intel_plane_state {
 		 */
 		u32 stride;
 		int x, y;
-	} color_plane[2];
+	} color_plane[4];
 
 	/* plane control register */
 	u32 ctl;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 9b9b41b0fc91..788d0fc8d8ef 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -532,11 +532,13 @@ skl_program_plane(struct intel_plane *plane,
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum plane_id plane_id = plane->id;
 	enum pipe pipe = plane->pipe;
+	const struct drm_framebuffer *fb = plane_state->base.fb;
+	int aux_plane = fb->format->num_planes / 2 + color_plane;
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 	u32 surf_addr = plane_state->color_plane[color_plane].offset;
 	u32 stride = skl_plane_stride(plane_state, color_plane);
-	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
-	u32 aux_stride = skl_plane_stride(plane_state, 1);
+	u32 aux_dist = plane_state->color_plane[aux_plane].offset - surf_addr;
+	u32 aux_stride = skl_plane_stride(plane_state, aux_plane);
 	int crtc_x = plane_state->base.dst.x1;
 	int crtc_y = plane_state->base.dst.y1;
 	u32 x = plane_state->color_plane[color_plane].x;
@@ -544,7 +546,6 @@ skl_program_plane(struct intel_plane *plane,
 	u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
 	u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
 	struct intel_plane *linked = plane_state->planar_linked_plane;
-	const struct drm_framebuffer *fb = plane_state->base.fb;
 	u8 alpha = plane_state->base.alpha >> 8;
 	u32 plane_color_ctl = 0;
 	unsigned long irqflags;
@@ -619,8 +620,8 @@ skl_program_plane(struct intel_plane *plane,
 
 	if (INTEL_GEN(dev_priv) < 11)
 		I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
-			      (plane_state->color_plane[1].y << 16) |
-			      plane_state->color_plane[1].x);
+			      (plane_state->color_plane[aux_plane].y << 16) |
+			      plane_state->color_plane[aux_plane].x);
 
 	/*
 	 * The control register self-arms if the plane was previously
@@ -1737,7 +1738,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
-	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
 		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
 		return -EINVAL;
 	}
@@ -2149,7 +2151,16 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
 	DRM_FORMAT_MOD_INVALID
 };
 
-static const u64 gen12_plane_format_modifiers_ccs[] = {
+static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
+	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
+	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+	I915_FORMAT_MOD_Y_TILED,
+	I915_FORMAT_MOD_X_TILED,
+	DRM_FORMAT_MOD_LINEAR,
+	DRM_FORMAT_MOD_INVALID
+};
+
+static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
 	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
 	I915_FORMAT_MOD_Y_TILED,
 	I915_FORMAT_MOD_X_TILED,
@@ -2305,10 +2316,21 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 	}
 }
 
+static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id)
+{
+	return plane_id < PLANE_SPRITE4;
+}
+
 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 					     u32 format, u64 modifier)
 {
+	struct intel_plane *plane = to_intel_plane(_plane);
+
 	switch (modifier) {
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+		if (!gen12_plane_supports_mc_ccs(plane->id))
+			return false;
+		/* fall through */
 	case DRM_FORMAT_MOD_LINEAR:
 	case I915_FORMAT_MOD_X_TILED:
 	case I915_FORMAT_MOD_Y_TILED:
@@ -2326,14 +2348,17 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 		if (is_ccs_modifier(modifier))
 			return true;
 		/* fall through */
-	case DRM_FORMAT_RGB565:
-	case DRM_FORMAT_XRGB2101010:
-	case DRM_FORMAT_XBGR2101010:
 	case DRM_FORMAT_YUYV:
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
+		if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+			return true;
+		/* fall through */
 	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_RGB565:
+	case DRM_FORMAT_XRGB2101010:
+	case DRM_FORMAT_XBGR2101010:
 	case DRM_FORMAT_P010:
 	case DRM_FORMAT_P012:
 	case DRM_FORMAT_P016:
@@ -2470,6 +2495,14 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
 	}
 }
 
+static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id)
+{
+	if (gen12_plane_supports_mc_ccs(plane_id))
+		return gen12_plane_format_modifiers_mc_ccs;
+	else
+		return gen12_plane_format_modifiers_rc_ccs;
+}
+
 static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
 			      enum pipe pipe, enum plane_id plane_id)
 {
@@ -2536,7 +2569,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 
 	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
 	if (INTEL_GEN(dev_priv) >= 12) {
-		modifiers = gen12_plane_format_modifiers_ccs;
+		modifiers = gen12_get_plane_modifiers(plane_id);
 		plane_funcs = &gen12_plane_funcs;
 	} else {
 		if (plane->has_ccs)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 519cfb0a5c42..02eaef8adac0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6697,6 +6697,7 @@ enum {
 #define   PLANE_CTL_TILED_Y			(4 << 10)
 #define   PLANE_CTL_TILED_YF			(5 << 10)
 #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
+#define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
 #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
 #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(2 << 4)
-- 
2.17.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
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Re: [PATCH v4 9/9] Gen-12 display can decompress surfaces compressed by the media engine.

[Ville Syrjälä]

On Thu, Sep 26, 2019 at 03:55:12AM -0700, Dhinakaran Pandiyan wrote:
> Detect the modifier corresponding to media compression to enable
> display decompression for YUV and xRGB packed formats. A new modifier is
> added so that the driver can distinguish between media and render
> compressed buffers. Unlike render decompression, plane 6 and  plane 7 do not
> support media decompression.
> 
> v2: Fix checkpatch warnings on code style (Lucas)
> 
> From DK:
> Separate modifier array for planes that cannot decompress media (Ville)
> 
> v3: Support planar formats
> v4: Switch plane order
> 
> Cc: Nanley G Chery <nanley.g.chery@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 290 +++++++++++++-----
>  .../drm/i915/display/intel_display_types.h    |   2 +-
>  drivers/gpu/drm/i915/display/intel_sprite.c   |  55 +++-
>  drivers/gpu/drm/i915/i915_reg.h               |   1 +
>  4 files changed, 267 insertions(+), 81 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 8ea55d67442c..df3ebaa167ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1888,6 +1888,22 @@ static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
>  		intel_wait_for_pipe_off(old_crtc_state);
>  }
>  
> +bool is_ccs_modifier(u64 modifier)
> +{
> +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> +	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> +	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> +}
> +
> +static bool is_ccs_plane(const struct drm_framebuffer *fb, int color_plane)
> +{
> +	if (!is_ccs_modifier(fb->modifier))
> +		return false;

A comment here could help clarify things for the reader. Eg.:
/*
 * [0] RGB
 * [1] RGB CCS
 * or
 * [0] Y
 * [1] CbCr
 * [2] Y CCS
 * [3] CbCr CCS
 */

> +
> +	return color_plane >= fb->format->num_planes / 2;
> +}
> +
>  static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
>  {
>  	return IS_GEN(dev_priv, 2) ? 2048 : 4096;
> @@ -1908,11 +1924,13 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>  		else
>  			return 512;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
> -		if (color_plane == 1)
> +		if (is_ccs_plane(fb, color_plane))
>  			return 128;
>  		/* fall through */
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> +		/* fall through */
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> -		if (color_plane == 1)
> +		if (is_ccs_plane(fb, color_plane))
>  			return 64;
>  		/* fall through */
>  	case I915_FORMAT_MOD_Y_TILED:
> @@ -1921,7 +1939,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>  		else
>  			return 512;
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> -		if (color_plane == 1)
> +		if (is_ccs_plane(fb, color_plane))
>  			return 128;
>  		/* fall through */
>  	case I915_FORMAT_MOD_Yf_TILED:
> @@ -1949,8 +1967,9 @@ static unsigned int
>  intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
>  {
>  	switch (fb->modifier) {
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> -		if (color_plane == 1)
> +		if (is_ccs_plane(fb, color_plane))
>  			return 1;
>  		/* fall through */
>  	default:
> @@ -2055,6 +2074,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
>  		if (INTEL_GEN(dev_priv) >= 9)
>  			return 256 * 1024;
>  		return 0;
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		return 16 * 1024;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
> @@ -2254,10 +2274,17 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
>  	return new_offset;
>  }
>  
> -static bool is_surface_linear(u64 modifier, int color_plane)
> +static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
>  {
> -	return modifier == DRM_FORMAT_MOD_LINEAR ||
> -	       (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
> +	switch (fb->modifier) {
> +	case DRM_FORMAT_MOD_LINEAR:
> +		return true;
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> +		return is_ccs_plane(fb, color_plane);
> +	default:
> +		return false;
> +	}
>  }
>  
>  static u32 intel_adjust_aligned_offset(int *x, int *y,
> @@ -2272,7 +2299,7 @@ static u32 intel_adjust_aligned_offset(int *x, int *y,
>  
>  	WARN_ON(new_offset > old_offset);
>  
> -	if (!is_surface_linear(fb->modifier, color_plane)) {
> +	if (!is_surface_linear(fb, color_plane)) {
>  		unsigned int tile_size, tile_width, tile_height;
>  		unsigned int pitch_tiles;
>  
> @@ -2342,7 +2369,7 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
>  	if (alignment)
>  		alignment--;
>  
> -	if (!is_surface_linear(fb->modifier, color_plane)) {
> +	if (!is_surface_linear(fb, color_plane)) {
>  		unsigned int tile_size, tile_width, tile_height;
>  		unsigned int tile_rows, tiles, pitch_tiles;
>  
> @@ -2445,6 +2472,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
>  	case I915_FORMAT_MOD_Y_TILED:
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  		return I915_TILING_Y;
>  	default:
>  		return I915_TILING_NONE;
> @@ -2494,6 +2522,13 @@ static const struct drm_format_info gen12_ccs_formats[] = {
>  	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
>  };
>  
> +static const struct drm_format_info gen12_mc_ccs_formats[] = {
> +	{ .format = DRM_FORMAT_YUYV, .num_planes = 2,
> +	  .cpp = { 2, 1, }, .hsub = 4, .vsub = 32, .is_yuv = true },
> +	{ .format = DRM_FORMAT_NV12, .num_planes = 4,
> +	  .cpp = { 1, 2, 1, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
> +};
> +
>  static const struct drm_format_info *
>  lookup_format_info(const struct drm_format_info formats[],
>  		   int num_formats, u32 format)
> @@ -2511,12 +2546,21 @@ lookup_format_info(const struct drm_format_info formats[],
>  static const struct drm_format_info *
>  intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
>  {
> +	const struct drm_format_info *info;
> +
>  	switch (cmd->modifier[0]) {
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
>  		return lookup_format_info(skl_ccs_formats,
>  					  ARRAY_SIZE(skl_ccs_formats),
>  					  cmd->pixel_format);
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> +		info = lookup_format_info(gen12_mc_ccs_formats,
> +					  ARRAY_SIZE(gen12_mc_ccs_formats),
> +					  cmd->pixel_format);
> +		if (info)
> +			return info;
> +		/* fall through */
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		return lookup_format_info(gen12_ccs_formats,
>  					  ARRAY_SIZE(gen12_ccs_formats),
> @@ -2526,13 +2570,6 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
>  	}
>  }
>  
> -bool is_ccs_modifier(u64 modifier)
> -{
> -	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> -	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> -	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> -}
> -
>  u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
>  			      u32 pixel_format, u64 modifier)
>  {
> @@ -2576,7 +2613,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
>  	struct drm_i915_private *dev_priv = to_i915(fb->dev);
>  	u32 tile_width;
>  
> -	if (is_surface_linear(fb->modifier, color_plane)) {
> +	if (is_surface_linear(fb, color_plane)) {
>  		u32 max_stride = intel_plane_fb_max_stride(dev_priv,
>  							   fb->format->format,
>  							   fb->modifier);
> @@ -2592,7 +2629,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
>  	}
>  
>  	tile_width = intel_tile_width_bytes(fb, color_plane);
> -	if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
> +	if (is_ccs_modifier(fb->modifier)) {
>  		/*
>  		 * Display WA #0531: skl,bxt,kbl,glk
>  		 *
> @@ -2602,7 +2639,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
>  		 * require the entire fb to accommodate that to avoid
>  		 * potential runtime errors at plane configuration time.
>  		 */
> -		if (IS_GEN(dev_priv, 9) && fb->width > 3840)
> +		if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
>  			tile_width *= 4;
>  		/*
>  		 * The main surface pitch must be padded to a multiple of four
> @@ -2682,25 +2719,75 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
>  	return stride > max_stride;
>  }
>  
> +static void
> +intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)
> +{
> +	int i;
> +	static const struct {
> +		u32 format;
> +		int vsub[4];
> +		int hsub[4];
> +	} mc_ccs_subsampling[] = { { .hsub = { 1, 2, 8, 16 },
> +				     .vsub = { 1, 2, 32, 32 },
> +				     .format = DRM_FORMAT_NV12, },
> +				 };
> +
> +	*hsub = fb->format->hsub;
> +	*vsub = fb->format->vsub;
> +
> +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS &&
> +	    fb->format->num_planes == 4) {
> +		for (i = 0; i < ARRAY_SIZE(mc_ccs_subsampling); i++) {
> +			if  (mc_ccs_subsampling[i].format == fb->format->format) {
> +				*hsub = mc_ccs_subsampling[i].hsub[color_plane];
> +				*vsub = mc_ccs_subsampling[i].vsub[color_plane];
> +				break;
> +			}
> +		}
> +		WARN_ON(i == ARRAY_SIZE(mc_ccs_subsampling));
> +	}

Hmm. I wonder if we could switch over to that block size stuff
in the format info? As is I don't think framebuffer_check() will
do the right thing for this stuff.

> +}
> +
> +static void
> +intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
> +{
> +	int hsub, vsub;
> +
> +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
> +	*w = fb->width/hsub;
> +	*h = fb->height/vsub;
> +}
> +
>  static int
> -intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
> +intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int aux_plane, int x, int y)
>  {
>  	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> -	int hsub = fb->format->hsub;
> -	int vsub = fb->format->vsub;
> +	int hsub, vsub;
> +	int hsub_main, vsub_main;
>  	int tile_width, tile_height;
>  	int ccs_x, ccs_y;
>  	int main_x, main_y;
> +	int main_plane;
> +
> +	if (!is_ccs_plane(fb, aux_plane))
> +		return 0;
> +
> +	main_plane = (aux_plane - 1) / 2;

'aux_plane - num_planes/2' might be a clearer way to write that.
The num_planes/2 already made an appearance in the is_ccs_plane() thing.

Could also extract this to a small helper to help readability.

> +	intel_tile_dims(fb, aux_plane, &tile_width, &tile_height);
> +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, aux_plane);
> +	intel_fb_plane_get_subsampling(&hsub_main, &vsub_main, fb,
> +				       main_plane);
>  
> -	intel_tile_dims(fb, 1, &tile_width, &tile_height);
> +	hsub /= hsub_main;
> +	vsub /= vsub_main;
>  
>  	tile_width *= hsub;
>  	tile_height *= vsub;
>  
>  	ccs_x = (x * hsub) % tile_width;
>  	ccs_y = (y * vsub) % tile_height;
> -	main_x = intel_fb->normal[0].x % tile_width;
> -	main_y = intel_fb->normal[0].y % tile_height;
> +	main_x = intel_fb->normal[main_plane].x % tile_width;
> +	main_y = intel_fb->normal[main_plane].y % tile_height;
>  
>  	/*
>  	* CCS doesn't have its own x/y offset register, so the intra CCS tile
> @@ -2710,8 +2797,8 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
>  		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
>  			      main_x, main_y,
>  			      ccs_x, ccs_y,
> -			      intel_fb->normal[0].x,
> -			      intel_fb->normal[0].y,
> +			      intel_fb->normal[main_plane].x,
> +			      intel_fb->normal[main_plane].y,
>  			      x, y);
>  		return -EINVAL;
>  	}
> @@ -2739,8 +2826,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
>  		int ret;
>  
>  		cpp = fb->format->cpp[i];
> -		width = drm_framebuffer_plane_width(fb->width, fb, i);
> -		height = drm_framebuffer_plane_height(fb->height, fb, i);
> +		intel_fb_plane_dims(&width, &height, fb, i);
>  
>  		ret = intel_fb_offset_to_xy(&x, &y, fb, i);
>  		if (ret) {
> @@ -2749,11 +2835,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
>  			return ret;
>  		}
>  
> -		if (is_ccs_modifier(fb->modifier) && i == 1) {
> -			ret = intel_fb_check_ccs_xy(fb, x, y);
> -			if (ret)
> -				return ret;
> -		}
> +		ret = intel_fb_check_ccs_xy(fb, i, x, y);
> +		if (ret)
> +			return ret;
>  
>  		/*
>  		 * The fence (if used) is aligned to the start of the object
> @@ -3371,6 +3455,7 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb,
>  			return 5120;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  		/* FIXME AUX plane? */
>  	case I915_FORMAT_MOD_Y_TILED:
>  	case I915_FORMAT_MOD_Yf_TILED:
> @@ -3430,16 +3515,18 @@ static int icl_max_plane_height(void)
>  }
>  
>  static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
> -					   int main_x, int main_y, u32 main_offset)
> +					   int main_x, int main_y,
> +					   u32 main_offset, int aux_plane)
>  {
>  	const struct drm_framebuffer *fb = plane_state->base.fb;
> -	int hsub = fb->format->hsub;
> -	int vsub = fb->format->vsub;
> -	int aux_x = plane_state->color_plane[1].x;
> -	int aux_y = plane_state->color_plane[1].y;
> -	u32 aux_offset = plane_state->color_plane[1].offset;
> -	u32 alignment = intel_surf_alignment(fb, 1);
> -
> +	int hsub;
> +	int vsub;
> +	int aux_x = plane_state->color_plane[aux_plane].x;
> +	int aux_y = plane_state->color_plane[aux_plane].y;
> +	u32 aux_offset = plane_state->color_plane[aux_plane].offset;
> +	u32 alignment = intel_surf_alignment(fb, aux_plane);
> +
> +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, aux_plane);
>  	while (aux_offset >= main_offset && aux_y <= main_y) {
>  		int x, y;
>  
> @@ -3451,7 +3538,7 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
>  
>  		x = aux_x / hsub;
>  		y = aux_y / vsub;
> -		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
> +		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, aux_plane,
>  							       aux_offset, aux_offset - alignment);
>  		aux_x = x * hsub + aux_x % hsub;
>  		aux_y = y * vsub + aux_y % vsub;
> @@ -3460,9 +3547,9 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
>  	if (aux_x != main_x || aux_y != main_y)
>  		return false;
>  
> -	plane_state->color_plane[1].offset = aux_offset;
> -	plane_state->color_plane[1].x = aux_x;
> -	plane_state->color_plane[1].y = aux_y;
> +	plane_state->color_plane[aux_plane].offset = aux_offset;
> +	plane_state->color_plane[aux_plane].x = aux_x;
> +	plane_state->color_plane[aux_plane].y = aux_y;
>  
>  	return true;
>  }
> @@ -3478,7 +3565,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
>  	int h = drm_rect_height(&plane_state->base.src) >> 16;
>  	int max_width;
>  	int max_height;
> -	u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
> +	int aux_plane = fb->format->num_planes / 2;
> +	u32 alignment, offset, aux_offset = plane_state->color_plane[aux_plane].offset;
>  
>  	if (INTEL_GEN(dev_priv) >= 11)
>  		max_width = icl_max_plane_width(fb, 0, rotation);
> @@ -3536,7 +3624,9 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
>  	 * they match with the main surface x/y offsets.
>  	 */
>  	if (is_ccs_modifier(fb->modifier)) {
> -		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
> +
> +		while (!skl_check_main_ccs_coordinates(plane_state, x, y,
> +						       offset, aux_plane)) {
>  			if (offset == 0)
>  				break;
>  
> @@ -3544,7 +3634,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
>  								   offset, offset - alignment);
>  		}
>  
> -		if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
> +		if (x != plane_state->color_plane[aux_plane].x ||
> +		    y != plane_state->color_plane[aux_plane].y) {
>  			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
>  			return -EINVAL;
>  		}
> @@ -3587,6 +3678,41 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
>  		return -EINVAL;
>  	}
>  
> +	if (is_ccs_modifier(fb->modifier)) {
> +		int aux_offset = plane_state->color_plane[3].offset;
> +		int alignment = intel_surf_alignment(fb, 1);
> +
> +		if (offset > aux_offset) {
> +			int hsub, vsub;
> +			int main_x = x, main_y = y;
> +
> +
> +			intel_fb_plane_get_subsampling(&hsub, &vsub, fb, 1);
> +			x = main_x / hsub;
> +			y = main_y / vsub;
> +			offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
> +								   offset,
> +								   aux_offset & ~(alignment - 1));
> +			x = x * hsub + main_x % hsub;
> +			y = y * vsub + main_y % vsub;
> +
> +		}
> +
> +		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset, 3)) {
> +			if (offset == 0)
> +				break;
> +
> +			offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
> +								   offset, offset - alignment);
> +		}
> +
> +		if (x != plane_state->color_plane[3].x ||
> +		    y != plane_state->color_plane[3].y) {
> +			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
> +			return -EINVAL;
> +		}

Probably time to refactor some of the stuff so we don't have to copy
paste so much.

> +	}
> +
>  	plane_state->color_plane[1].offset = offset;
>  	plane_state->color_plane[1].x = x;
>  	plane_state->color_plane[1].y = y;
> @@ -3599,19 +3725,30 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
>  	const struct drm_framebuffer *fb = plane_state->base.fb;
>  	int src_x = plane_state->base.src.x1 >> 16;
>  	int src_y = plane_state->base.src.y1 >> 16;
> -	int hsub = fb->format->hsub;
> -	int vsub = fb->format->vsub;
> -	int x = src_x / hsub;
> -	int y = src_y / vsub;
>  	u32 offset;
> +	int ccs;
>  
> -	intel_add_fb_offsets(&x, &y, plane_state, 1);
> -	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
>  
> -	plane_state->color_plane[1].offset = offset;
> -	plane_state->color_plane[1].x = x * hsub + src_x % hsub;
> -	plane_state->color_plane[1].y = y * vsub + src_y % vsub;
> +	for (ccs = fb->format->num_planes / 2;

I guess another helper to do the main->aux index calculation would make
this less magicy.

ccs < fb->format->num_planes; ccs++) {
> +		int hsub, vsub;
> +		int main_hsub, main_vsub;
> +		int x, y;
> +
> +		intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs);
> +		intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, (ccs - 1)/ 2);
> +
> +		hsub /= main_hsub;
> +		vsub /= main_vsub;
> +		x = src_x / hsub;
> +		y = src_y / vsub;
>  
> +		intel_add_fb_offsets(&x, &y, plane_state, ccs);
> +		offset = intel_plane_compute_aligned_offset(&x, &y,
> +							    plane_state, ccs);
> +		plane_state->color_plane[ccs].offset = offset;
> +		plane_state->color_plane[ccs].x = x * hsub + src_x % hsub;
> +		plane_state->color_plane[ccs].y = y * vsub + src_y % vsub;
> +	}
>  	return 0;
>  }
>  
> @@ -3619,6 +3756,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
>  {
>  	const struct drm_framebuffer *fb = plane_state->base.fb;
>  	int ret;
> +	bool needs_aux = false;
>  
>  	ret = intel_plane_compute_gtt(plane_state);
>  	if (ret)
> @@ -3628,21 +3766,31 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
>  		return 0;
>  
>  	/*
> -	 * Handle the AUX surface first since
> -	 * the main surface setup depends on it.
> +	 * Handle the AUX surface first since the main surface setup depends on
> +	 * it.
>  	 */
> -	if (drm_format_info_is_yuv_semiplanar(fb->format)) {
> -		ret = skl_check_nv12_aux_surface(plane_state);
> +	if (is_ccs_modifier(fb->modifier)) {
> +		needs_aux = true;
> +		ret = skl_check_ccs_aux_surface(plane_state);
>  		if (ret)
>  			return ret;
> -	} else if (is_ccs_modifier(fb->modifier)) {
> -		ret = skl_check_ccs_aux_surface(plane_state);
> +	}
> +
> +	if (drm_format_info_is_yuv_semiplanar(fb->format)) {
> +		needs_aux = true;
> +		ret = skl_check_nv12_aux_surface(plane_state);
>  		if (ret)
>  			return ret;
> -	} else {
> -		plane_state->color_plane[1].offset = ~0xfff;
> -		plane_state->color_plane[1].x = 0;
> -		plane_state->color_plane[1].y = 0;
> +	}
> +
> +	if (!needs_aux) {
> +		int i;
> +
> +		for (i = 1; i < fb->format->num_planes; i++) {
> +			plane_state->color_plane[i].offset = ~0xfff;
> +			plane_state->color_plane[i].x = 0;
> +			plane_state->color_plane[i].y = 0;
> +		}
>  	}
>  
>  	ret = skl_check_main_surface(plane_state);
> @@ -4030,7 +4178,7 @@ static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
>  	 * The stride is either expressed as a multiple of 64 bytes chunks for
>  	 * linear buffers or in number of tiles for tiled buffers.
>  	 */
> -	if (is_surface_linear(fb->modifier, color_plane))
> +	if (is_surface_linear(fb, color_plane))
>  		return 64;
>  	else if (drm_rotation_90_or_270(rotation))
>  		return intel_tile_height(fb, color_plane);
> @@ -4160,6 +4308,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
>  		return PLANE_CTL_TILED_Y |
>  		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
>  		       PLANE_CTL_CLEAR_COLOR_DISABLE;
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> +		return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
>  	case I915_FORMAT_MOD_Yf_TILED:
>  		return PLANE_CTL_TILED_YF;
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -9968,6 +10118,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
>  			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
>  				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
>  				I915_FORMAT_MOD_Y_TILED_CCS;
> +		else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
> +			fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
>  		else
>  			fb->modifier = I915_FORMAT_MOD_Y_TILED;
>  		break;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 976669f01a8c..5998b959225c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -530,7 +530,7 @@ struct intel_plane_state {
>  		 */
>  		u32 stride;
>  		int x, y;
> -	} color_plane[2];
> +	} color_plane[4];
>  
>  	/* plane control register */
>  	u32 ctl;
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 9b9b41b0fc91..788d0fc8d8ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -532,11 +532,13 @@ skl_program_plane(struct intel_plane *plane,
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	enum plane_id plane_id = plane->id;
>  	enum pipe pipe = plane->pipe;
> +	const struct drm_framebuffer *fb = plane_state->base.fb;
> +	int aux_plane = fb->format->num_planes / 2 + color_plane;
>  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
>  	u32 surf_addr = plane_state->color_plane[color_plane].offset;
>  	u32 stride = skl_plane_stride(plane_state, color_plane);
> -	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
> -	u32 aux_stride = skl_plane_stride(plane_state, 1);
> +	u32 aux_dist = plane_state->color_plane[aux_plane].offset - surf_addr;
> +	u32 aux_stride = skl_plane_stride(plane_state, aux_plane);
>  	int crtc_x = plane_state->base.dst.x1;
>  	int crtc_y = plane_state->base.dst.y1;
>  	u32 x = plane_state->color_plane[color_plane].x;
> @@ -544,7 +546,6 @@ skl_program_plane(struct intel_plane *plane,
>  	u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
>  	u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
>  	struct intel_plane *linked = plane_state->planar_linked_plane;
> -	const struct drm_framebuffer *fb = plane_state->base.fb;
>  	u8 alpha = plane_state->base.alpha >> 8;
>  	u32 plane_color_ctl = 0;
>  	unsigned long irqflags;
> @@ -619,8 +620,8 @@ skl_program_plane(struct intel_plane *plane,
>  
>  	if (INTEL_GEN(dev_priv) < 11)
>  		I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
> -			      (plane_state->color_plane[1].y << 16) |
> -			      plane_state->color_plane[1].x);
> +			      (plane_state->color_plane[aux_plane].y << 16) |
> +			      plane_state->color_plane[aux_plane].x);
>  
>  	/*
>  	 * The control register self-arms if the plane was previously
> @@ -1737,7 +1738,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
>  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> -	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
> +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
>  		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
>  		return -EINVAL;
>  	}
> @@ -2149,7 +2151,16 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
>  	DRM_FORMAT_MOD_INVALID
>  };
>  
> -static const u64 gen12_plane_format_modifiers_ccs[] = {
> +static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
> +	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> +	I915_FORMAT_MOD_Y_TILED,
> +	I915_FORMAT_MOD_X_TILED,
> +	DRM_FORMAT_MOD_LINEAR,
> +	DRM_FORMAT_MOD_INVALID
> +};
> +
> +static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
>  	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
>  	I915_FORMAT_MOD_Y_TILED,
>  	I915_FORMAT_MOD_X_TILED,
> @@ -2305,10 +2316,21 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>  	}
>  }
>  
> +static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id)

plane_has_foo() is the common idiom.

> +{
> +	return plane_id < PLANE_SPRITE4;
> +}
> +
>  static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  					     u32 format, u64 modifier)
>  {
> +	struct intel_plane *plane = to_intel_plane(_plane);
> +
>  	switch (modifier) {
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> +		if (!gen12_plane_supports_mc_ccs(plane->id))
> +			return false;
> +		/* fall through */
>  	case DRM_FORMAT_MOD_LINEAR:
>  	case I915_FORMAT_MOD_X_TILED:
>  	case I915_FORMAT_MOD_Y_TILED:
> @@ -2326,14 +2348,17 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  		if (is_ccs_modifier(modifier))
>  			return true;
>  		/* fall through */
> -	case DRM_FORMAT_RGB565:
> -	case DRM_FORMAT_XRGB2101010:
> -	case DRM_FORMAT_XBGR2101010:
>  	case DRM_FORMAT_YUYV:
>  	case DRM_FORMAT_YVYU:
>  	case DRM_FORMAT_UYVY:
>  	case DRM_FORMAT_VYUY:
> +		if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
> +			return true;
> +		/* fall through */
>  	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_RGB565:
> +	case DRM_FORMAT_XRGB2101010:
> +	case DRM_FORMAT_XBGR2101010:
>  	case DRM_FORMAT_P010:
>  	case DRM_FORMAT_P012:
>  	case DRM_FORMAT_P016:
> @@ -2470,6 +2495,14 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
>  	}
>  }
>  
> +static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id)
> +{
> +	if (gen12_plane_supports_mc_ccs(plane_id))
> +		return gen12_plane_format_modifiers_mc_ccs;
> +	else
> +		return gen12_plane_format_modifiers_rc_ccs;
> +}
> +
>  static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
>  			      enum pipe pipe, enum plane_id plane_id)
>  {
> @@ -2536,7 +2569,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>  
>  	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
>  	if (INTEL_GEN(dev_priv) >= 12) {
> -		modifiers = gen12_plane_format_modifiers_ccs;
> +		modifiers = gen12_get_plane_modifiers(plane_id);
>  		plane_funcs = &gen12_plane_funcs;
>  	} else {
>  		if (plane->has_ccs)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 519cfb0a5c42..02eaef8adac0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6697,6 +6697,7 @@ enum {
>  #define   PLANE_CTL_TILED_Y			(4 << 10)
>  #define   PLANE_CTL_TILED_YF			(5 << 10)
>  #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
> +#define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
>  #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
>  #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
>  #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(2 << 4)
> -- 
> 2.17.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v4 9/9] Gen-12 display can decompress surfaces compressed by the media engine.

[Dhinakaran Pandiyan]

On Fri, 2019-10-04 at 18:36 +0300, Ville Syrjälä wrote:
> On Thu, Sep 26, 2019 at 03:55:12AM -0700, Dhinakaran Pandiyan wrote:
> > Detect the modifier corresponding to media compression to enable
> > display decompression for YUV and xRGB packed formats. A new modifier is
> > added so that the driver can distinguish between media and render
> > compressed buffers. Unlike render decompression, plane 6 and  plane 7 do not
> > support media decompression.
> > 
> > v2: Fix checkpatch warnings on code style (Lucas)
> > 
> > From DK:
> > Separate modifier array for planes that cannot decompress media (Ville)
> > 
> > v3: Support planar formats
> > v4: Switch plane order
> > 
> > Cc: Nanley G Chery <nanley.g.chery@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c  | 290 +++++++++++++-----
> >  .../drm/i915/display/intel_display_types.h    |   2 +-
> >  drivers/gpu/drm/i915/display/intel_sprite.c   |  55 +++-
> >  drivers/gpu/drm/i915/i915_reg.h               |   1 +
> >  4 files changed, 267 insertions(+), 81 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 8ea55d67442c..df3ebaa167ab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1888,6 +1888,22 @@ static void intel_disable_pipe(const struct intel_crtc_state
> > *old_crtc_state)
> >  		intel_wait_for_pipe_off(old_crtc_state);
> >  }
> >  
> > +bool is_ccs_modifier(u64 modifier)
> > +{
> > +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > +	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> > +	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > +	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > +}
> > +
> > +static bool is_ccs_plane(const struct drm_framebuffer *fb, int color_plane)
> > +{
> > +	if (!is_ccs_modifier(fb->modifier))
> > +		return false;
> 
> A comment here could help clarify things for the reader. Eg.:
> /*
>  * [0] RGB
>  * [1] RGB CCS
>  * or
>  * [0] Y
>  * [1] CbCr
>  * [2] Y CCS
>  * [3] CbCr CCS
>  */
> 
Will do.

> > +
> > +	return color_plane >= fb->format->num_planes / 2;
> > +}
> > +
> >  static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
> >  {
> >  	return IS_GEN(dev_priv, 2) ? 2048 : 4096;
> > @@ -1908,11 +1924,13 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int
> > color_plane)
> >  		else
> >  			return 512;
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> > -		if (color_plane == 1)
> > +		if (is_ccs_plane(fb, color_plane))
> >  			return 128;
> >  		/* fall through */
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > +		/* fall through */
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > -		if (color_plane == 1)
> > +		if (is_ccs_plane(fb, color_plane))
> >  			return 64;
> >  		/* fall through */
> >  	case I915_FORMAT_MOD_Y_TILED:
> > @@ -1921,7 +1939,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> >  		else
> >  			return 512;
> >  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> > -		if (color_plane == 1)
> > +		if (is_ccs_plane(fb, color_plane))
> >  			return 128;
> >  		/* fall through */
> >  	case I915_FORMAT_MOD_Yf_TILED:
> > @@ -1949,8 +1967,9 @@ static unsigned int
> >  intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
> >  {
> >  	switch (fb->modifier) {
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > -		if (color_plane == 1)
> > +		if (is_ccs_plane(fb, color_plane))
> >  			return 1;
> >  		/* fall through */
> >  	default:
> > @@ -2055,6 +2074,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> >  		if (INTEL_GEN(dev_priv) >= 9)
> >  			return 256 * 1024;
> >  		return 0;
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> >  		return 16 * 1024;
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> > @@ -2254,10 +2274,17 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
> >  	return new_offset;
> >  }
> >  
> > -static bool is_surface_linear(u64 modifier, int color_plane)
> > +static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
> >  {
> > -	return modifier == DRM_FORMAT_MOD_LINEAR ||
> > -	       (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
> > +	switch (fb->modifier) {
> > +	case DRM_FORMAT_MOD_LINEAR:
> > +		return true;
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > +		return is_ccs_plane(fb, color_plane);
> > +	default:
> > +		return false;
> > +	}
> >  }
> >  
> >  static u32 intel_adjust_aligned_offset(int *x, int *y,
> > @@ -2272,7 +2299,7 @@ static u32 intel_adjust_aligned_offset(int *x, int *y,
> >  
> >  	WARN_ON(new_offset > old_offset);
> >  
> > -	if (!is_surface_linear(fb->modifier, color_plane)) {
> > +	if (!is_surface_linear(fb, color_plane)) {
> >  		unsigned int tile_size, tile_width, tile_height;
> >  		unsigned int pitch_tiles;
> >  
> > @@ -2342,7 +2369,7 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
> >  	if (alignment)
> >  		alignment--;
> >  
> > -	if (!is_surface_linear(fb->modifier, color_plane)) {
> > +	if (!is_surface_linear(fb, color_plane)) {
> >  		unsigned int tile_size, tile_width, tile_height;
> >  		unsigned int tile_rows, tiles, pitch_tiles;
> >  
> > @@ -2445,6 +2472,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> >  	case I915_FORMAT_MOD_Y_TILED:
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> >  		return I915_TILING_Y;
> >  	default:
> >  		return I915_TILING_NONE;
> > @@ -2494,6 +2522,13 @@ static const struct drm_format_info gen12_ccs_formats[] = {
> >  	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> >  };
> >  
> > +static const struct drm_format_info gen12_mc_ccs_formats[] = {
> > +	{ .format = DRM_FORMAT_YUYV, .num_planes = 2,
> > +	  .cpp = { 2, 1, }, .hsub = 4, .vsub = 32, .is_yuv = true },
> > +	{ .format = DRM_FORMAT_NV12, .num_planes = 4,
> > +	  .cpp = { 1, 2, 1, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
> > +};
> > +
> >  static const struct drm_format_info *
> >  lookup_format_info(const struct drm_format_info formats[],
> >  		   int num_formats, u32 format)
> > @@ -2511,12 +2546,21 @@ lookup_format_info(const struct drm_format_info formats[],
> >  static const struct drm_format_info *
> >  intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> >  {
> > +	const struct drm_format_info *info;
> > +
> >  	switch (cmd->modifier[0]) {
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> >  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> >  		return lookup_format_info(skl_ccs_formats,
> >  					  ARRAY_SIZE(skl_ccs_formats),
> >  					  cmd->pixel_format);
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > +		info = lookup_format_info(gen12_mc_ccs_formats,
> > +					  ARRAY_SIZE(gen12_mc_ccs_formats),
> > +					  cmd->pixel_format);
> > +		if (info)
> > +			return info;
> > +		/* fall through */
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> >  		return lookup_format_info(gen12_ccs_formats,
> >  					  ARRAY_SIZE(gen12_ccs_formats),
> > @@ -2526,13 +2570,6 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> >  	}
> >  }
> >  
> > -bool is_ccs_modifier(u64 modifier)
> > -{
> > -	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > -	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > -	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > -}
> > -
> >  u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> >  			      u32 pixel_format, u64 modifier)
> >  {
> > @@ -2576,7 +2613,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int
> > color_plane)
> >  	struct drm_i915_private *dev_priv = to_i915(fb->dev);
> >  	u32 tile_width;
> >  
> > -	if (is_surface_linear(fb->modifier, color_plane)) {
> > +	if (is_surface_linear(fb, color_plane)) {
> >  		u32 max_stride = intel_plane_fb_max_stride(dev_priv,
> >  							   fb->format->format,
> >  							   fb->modifier);
> > @@ -2592,7 +2629,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int
> > color_plane)
> >  	}
> >  
> >  	tile_width = intel_tile_width_bytes(fb, color_plane);
> > -	if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
> > +	if (is_ccs_modifier(fb->modifier)) {
> >  		/*
> >  		 * Display WA #0531: skl,bxt,kbl,glk
> >  		 *
> > @@ -2602,7 +2639,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int
> > color_plane)
> >  		 * require the entire fb to accommodate that to avoid
> >  		 * potential runtime errors at plane configuration time.
> >  		 */
> > -		if (IS_GEN(dev_priv, 9) && fb->width > 3840)
> > +		if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
> >  			tile_width *= 4;
> >  		/*
> >  		 * The main surface pitch must be padded to a multiple of four
> > @@ -2682,25 +2719,75 @@ static bool intel_plane_needs_remap(const struct intel_plane_state
> > *plane_state)
> >  	return stride > max_stride;
> >  }
> >  
> > +static void
> > +intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int
> > color_plane)
> > +{
> > +	int i;
> > +	static const struct {
> > +		u32 format;
> > +		int vsub[4];
> > +		int hsub[4];
> > +	} mc_ccs_subsampling[] = { { .hsub = { 1, 2, 8, 16 },
> > +				     .vsub = { 1, 2, 32, 32 },
> > +				     .format = DRM_FORMAT_NV12, },
> > +				 };
> > +
> > +	*hsub = fb->format->hsub;
> > +	*vsub = fb->format->vsub;
> > +
> > +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS &&
> > +	    fb->format->num_planes == 4) {
> > +		for (i = 0; i < ARRAY_SIZE(mc_ccs_subsampling); i++) {
> > +			if  (mc_ccs_subsampling[i].format == fb->format->format) {
> > +				*hsub = mc_ccs_subsampling[i].hsub[color_plane];
> > +				*vsub = mc_ccs_subsampling[i].vsub[color_plane];
> > +				break;
> > +			}
> > +		}
> > +		WARN_ON(i == ARRAY_SIZE(mc_ccs_subsampling));
> > +	}
> 
> Hmm. I wonder if we could switch over to that block size stuff
> in the format info? As is I don't think framebuffer_check() will
> do the right thing for this stuff.

Thought about it quite a bit (even coded some parts). I wasn't 100% sure if it matches what we need
and had too many questions about it's intended usage. Are block dimensions for each plane
independent of each other? Should relative plane dimensions be taken into account or we just define
the dimensions based on each plane's unit block? Do the block dimensions complement vsub and hsub or
is that an alternative?

In any case, felt it would be better to convert all formats/modifiers to switch to using blocks
together. Thoughts?

-DK
> 
> > +}
> > +
> > +static void
> > +intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
> > +{
> > +	int hsub, vsub;
> > +
> > +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
> > +	*w = fb->width/hsub;
> > +	*h = fb->height/vsub;
> > +}
> > +
> >  static int
> > -intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
> > +intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int aux_plane, int x, int y)
> >  {
> >  	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> > -	int hsub = fb->format->hsub;
> > -	int vsub = fb->format->vsub;
> > +	int hsub, vsub;
> > +	int hsub_main, vsub_main;
> >  	int tile_width, tile_height;
> >  	int ccs_x, ccs_y;
> >  	int main_x, main_y;
> > +	int main_plane;
> > +
> > +	if (!is_ccs_plane(fb, aux_plane))
> > +		return 0;
> > +
> > +	main_plane = (aux_plane - 1) / 2;
> 
> 'aux_plane - num_planes/2' might be a clearer way to write that.
> The num_planes/2 already made an appearance in the is_ccs_plane() thing.
> 
> Could also extract this to a small helper to help readability.
Okay.

> 
> > +	intel_tile_dims(fb, aux_plane, &tile_width, &tile_height);
> > +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, aux_plane);
> > +	intel_fb_plane_get_subsampling(&hsub_main, &vsub_main, fb,
> > +				       main_plane);
> >  
> > -	intel_tile_dims(fb, 1, &tile_width, &tile_height);
> > +	hsub /= hsub_main;
> > +	vsub /= vsub_main;
> >  
> >  	tile_width *= hsub;
> >  	tile_height *= vsub;
> >  
> >  	ccs_x = (x * hsub) % tile_width;
> >  	ccs_y = (y * vsub) % tile_height;
> > -	main_x = intel_fb->normal[0].x % tile_width;
> > -	main_y = intel_fb->normal[0].y % tile_height;
> > +	main_x = intel_fb->normal[main_plane].x % tile_width;
> > +	main_y = intel_fb->normal[main_plane].y % tile_height;
> >  
> >  	/*
> >  	* CCS doesn't have its own x/y offset register, so the intra CCS tile
> > @@ -2710,8 +2797,8 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
> >  		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
> >  			      main_x, main_y,
> >  			      ccs_x, ccs_y,
> > -			      intel_fb->normal[0].x,
> > -			      intel_fb->normal[0].y,
> > +			      intel_fb->normal[main_plane].x,
> > +			      intel_fb->normal[main_plane].y,
> >  			      x, y);
> >  		return -EINVAL;
> >  	}
> > @@ -2739,8 +2826,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
> >  		int ret;
> >  
> >  		cpp = fb->format->cpp[i];
> > -		width = drm_framebuffer_plane_width(fb->width, fb, i);
> > -		height = drm_framebuffer_plane_height(fb->height, fb, i);
> > +		intel_fb_plane_dims(&width, &height, fb, i);
> >  
> >  		ret = intel_fb_offset_to_xy(&x, &y, fb, i);
> >  		if (ret) {
> > @@ -2749,11 +2835,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
> >  			return ret;
> >  		}
> >  
> > -		if (is_ccs_modifier(fb->modifier) && i == 1) {
> > -			ret = intel_fb_check_ccs_xy(fb, x, y);
> > -			if (ret)
> > -				return ret;
> > -		}
> > +		ret = intel_fb_check_ccs_xy(fb, i, x, y);
> > +		if (ret)
> > +			return ret;
> >  
> >  		/*
> >  		 * The fence (if used) is aligned to the start of the object
> > @@ -3371,6 +3455,7 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb,
> >  			return 5120;
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> >  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> >  		/* FIXME AUX plane? */
> >  	case I915_FORMAT_MOD_Y_TILED:
> >  	case I915_FORMAT_MOD_Yf_TILED:
> > @@ -3430,16 +3515,18 @@ static int icl_max_plane_height(void)
> >  }
> >  
> >  static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
> > -					   int main_x, int main_y, u32 main_offset)
> > +					   int main_x, int main_y,
> > +					   u32 main_offset, int aux_plane)
> >  {
> >  	const struct drm_framebuffer *fb = plane_state->base.fb;
> > -	int hsub = fb->format->hsub;
> > -	int vsub = fb->format->vsub;
> > -	int aux_x = plane_state->color_plane[1].x;
> > -	int aux_y = plane_state->color_plane[1].y;
> > -	u32 aux_offset = plane_state->color_plane[1].offset;
> > -	u32 alignment = intel_surf_alignment(fb, 1);
> > -
> > +	int hsub;
> > +	int vsub;
> > +	int aux_x = plane_state->color_plane[aux_plane].x;
> > +	int aux_y = plane_state->color_plane[aux_plane].y;
> > +	u32 aux_offset = plane_state->color_plane[aux_plane].offset;
> > +	u32 alignment = intel_surf_alignment(fb, aux_plane);
> > +
> > +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, aux_plane);
> >  	while (aux_offset >= main_offset && aux_y <= main_y) {
> >  		int x, y;
> >  
> > @@ -3451,7 +3538,7 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state
> > *plane_state
> >  
> >  		x = aux_x / hsub;
> >  		y = aux_y / vsub;
> > -		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
> > +		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, aux_plane,
> >  							       aux_offset, aux_offset - alignment);
> >  		aux_x = x * hsub + aux_x % hsub;
> >  		aux_y = y * vsub + aux_y % vsub;
> > @@ -3460,9 +3547,9 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state
> > *plane_state
> >  	if (aux_x != main_x || aux_y != main_y)
> >  		return false;
> >  
> > -	plane_state->color_plane[1].offset = aux_offset;
> > -	plane_state->color_plane[1].x = aux_x;
> > -	plane_state->color_plane[1].y = aux_y;
> > +	plane_state->color_plane[aux_plane].offset = aux_offset;
> > +	plane_state->color_plane[aux_plane].x = aux_x;
> > +	plane_state->color_plane[aux_plane].y = aux_y;
> >  
> >  	return true;
> >  }
> > @@ -3478,7 +3565,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> >  	int h = drm_rect_height(&plane_state->base.src) >> 16;
> >  	int max_width;
> >  	int max_height;
> > -	u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
> > +	int aux_plane = fb->format->num_planes / 2;
> > +	u32 alignment, offset, aux_offset = plane_state->color_plane[aux_plane].offset;
> >  
> >  	if (INTEL_GEN(dev_priv) >= 11)
> >  		max_width = icl_max_plane_width(fb, 0, rotation);
> > @@ -3536,7 +3624,9 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> >  	 * they match with the main surface x/y offsets.
> >  	 */
> >  	if (is_ccs_modifier(fb->modifier)) {
> > -		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
> > +
> > +		while (!skl_check_main_ccs_coordinates(plane_state, x, y,
> > +						       offset, aux_plane)) {
> >  			if (offset == 0)
> >  				break;
> >  
> > @@ -3544,7 +3634,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> >  								   offset, offset - alignment);
> >  		}
> >  
> > -		if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
> > +		if (x != plane_state->color_plane[aux_plane].x ||
> > +		    y != plane_state->color_plane[aux_plane].y) {
> >  			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to
> > CCS\n");
> >  			return -EINVAL;
> >  		}
> > @@ -3587,6 +3678,41 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state
> > *plane_state)
> >  		return -EINVAL;
> >  	}
> >  
> > +	if (is_ccs_modifier(fb->modifier)) {
> > +		int aux_offset = plane_state->color_plane[3].offset;
> > +		int alignment = intel_surf_alignment(fb, 1);
> > +
> > +		if (offset > aux_offset) {
> > +			int hsub, vsub;
> > +			int main_x = x, main_y = y;
> > +
> > +
> > +			intel_fb_plane_get_subsampling(&hsub, &vsub, fb, 1);
> > +			x = main_x / hsub;
> > +			y = main_y / vsub;
> > +			offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
> > +								   offset,
> > +								   aux_offset & ~(alignment - 1));
> > +			x = x * hsub + main_x % hsub;
> > +			y = y * vsub + main_y % vsub;
> > +
> > +		}
> > +
> > +		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset, 3)) {
> > +			if (offset == 0)
> > +				break;
> > +
> > +			offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
> > +								   offset, offset - alignment);
> > +		}
> > +
> > +		if (x != plane_state->color_plane[3].x ||
> > +		    y != plane_state->color_plane[3].y) {
> > +			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to
> > CCS\n");
> > +			return -EINVAL;
> > +		}
> 
> Probably time to refactor some of the stuff so we don't have to copy
> paste so much.
> 
> > +	}
> > +
> >  	plane_state->color_plane[1].offset = offset;
> >  	plane_state->color_plane[1].x = x;
> >  	plane_state->color_plane[1].y = y;
> > @@ -3599,19 +3725,30 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state
> > *plane_state)
> >  	const struct drm_framebuffer *fb = plane_state->base.fb;
> >  	int src_x = plane_state->base.src.x1 >> 16;
> >  	int src_y = plane_state->base.src.y1 >> 16;
> > -	int hsub = fb->format->hsub;
> > -	int vsub = fb->format->vsub;
> > -	int x = src_x / hsub;
> > -	int y = src_y / vsub;
> >  	u32 offset;
> > +	int ccs;
> >  
> > -	intel_add_fb_offsets(&x, &y, plane_state, 1);
> > -	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
> >  
> > -	plane_state->color_plane[1].offset = offset;
> > -	plane_state->color_plane[1].x = x * hsub + src_x % hsub;
> > -	plane_state->color_plane[1].y = y * vsub + src_y % vsub;
> > +	for (ccs = fb->format->num_planes / 2;
> 
> I guess another helper to do the main->aux index calculation would make
> this less magicy.
> 
> ccs < fb->format->num_planes; ccs++) {
> > +		int hsub, vsub;
> > +		int main_hsub, main_vsub;
> > +		int x, y;
> > +
> > +		intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs);
> > +		intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, (ccs - 1)/ 2);
> > +
> > +		hsub /= main_hsub;
> > +		vsub /= main_vsub;
> > +		x = src_x / hsub;
> > +		y = src_y / vsub;
> >  
> > +		intel_add_fb_offsets(&x, &y, plane_state, ccs);
> > +		offset = intel_plane_compute_aligned_offset(&x, &y,
> > +							    plane_state, ccs);
> > +		plane_state->color_plane[ccs].offset = offset;
> > +		plane_state->color_plane[ccs].x = x * hsub + src_x % hsub;
> > +		plane_state->color_plane[ccs].y = y * vsub + src_y % vsub;
> > +	}
> >  	return 0;
> >  }
> >  
> > @@ -3619,6 +3756,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
> >  {
> >  	const struct drm_framebuffer *fb = plane_state->base.fb;
> >  	int ret;
> > +	bool needs_aux = false;
> >  
> >  	ret = intel_plane_compute_gtt(plane_state);
> >  	if (ret)
> > @@ -3628,21 +3766,31 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
> >  		return 0;
> >  
> >  	/*
> > -	 * Handle the AUX surface first since
> > -	 * the main surface setup depends on it.
> > +	 * Handle the AUX surface first since the main surface setup depends on
> > +	 * it.
> >  	 */
> > -	if (drm_format_info_is_yuv_semiplanar(fb->format)) {
> > -		ret = skl_check_nv12_aux_surface(plane_state);
> > +	if (is_ccs_modifier(fb->modifier)) {
> > +		needs_aux = true;
> > +		ret = skl_check_ccs_aux_surface(plane_state);
> >  		if (ret)
> >  			return ret;
> > -	} else if (is_ccs_modifier(fb->modifier)) {
> > -		ret = skl_check_ccs_aux_surface(plane_state);
> > +	}
> > +
> > +	if (drm_format_info_is_yuv_semiplanar(fb->format)) {
> > +		needs_aux = true;
> > +		ret = skl_check_nv12_aux_surface(plane_state);
> >  		if (ret)
> >  			return ret;
> > -	} else {
> > -		plane_state->color_plane[1].offset = ~0xfff;
> > -		plane_state->color_plane[1].x = 0;
> > -		plane_state->color_plane[1].y = 0;
> > +	}
> > +
> > +	if (!needs_aux) {
> > +		int i;
> > +
> > +		for (i = 1; i < fb->format->num_planes; i++) {
> > +			plane_state->color_plane[i].offset = ~0xfff;
> > +			plane_state->color_plane[i].x = 0;
> > +			plane_state->color_plane[i].y = 0;
> > +		}
> >  	}
> >  
> >  	ret = skl_check_main_surface(plane_state);
> > @@ -4030,7 +4178,7 @@ static unsigned int skl_plane_stride_mult(const struct drm_framebuffer
> > *fb,
> >  	 * The stride is either expressed as a multiple of 64 bytes chunks for
> >  	 * linear buffers or in number of tiles for tiled buffers.
> >  	 */
> > -	if (is_surface_linear(fb->modifier, color_plane))
> > +	if (is_surface_linear(fb, color_plane))
> >  		return 64;
> >  	else if (drm_rotation_90_or_270(rotation))
> >  		return intel_tile_height(fb, color_plane);
> > @@ -4160,6 +4308,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> >  		return PLANE_CTL_TILED_Y |
> >  		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> >  		       PLANE_CTL_CLEAR_COLOR_DISABLE;
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > +		return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
> >  	case I915_FORMAT_MOD_Yf_TILED:
> >  		return PLANE_CTL_TILED_YF;
> >  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> > @@ -9968,6 +10118,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
> >  			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
> >  				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> >  				I915_FORMAT_MOD_Y_TILED_CCS;
> > +		else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
> > +			fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> >  		else
> >  			fb->modifier = I915_FORMAT_MOD_Y_TILED;
> >  		break;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 976669f01a8c..5998b959225c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -530,7 +530,7 @@ struct intel_plane_state {
> >  		 */
> >  		u32 stride;
> >  		int x, y;
> > -	} color_plane[2];
> > +	} color_plane[4];
> >  
> >  	/* plane control register */
> >  	u32 ctl;
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index 9b9b41b0fc91..788d0fc8d8ef 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -532,11 +532,13 @@ skl_program_plane(struct intel_plane *plane,
> >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> >  	enum plane_id plane_id = plane->id;
> >  	enum pipe pipe = plane->pipe;
> > +	const struct drm_framebuffer *fb = plane_state->base.fb;
> > +	int aux_plane = fb->format->num_planes / 2 + color_plane;
> >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> >  	u32 surf_addr = plane_state->color_plane[color_plane].offset;
> >  	u32 stride = skl_plane_stride(plane_state, color_plane);
> > -	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
> > -	u32 aux_stride = skl_plane_stride(plane_state, 1);
> > +	u32 aux_dist = plane_state->color_plane[aux_plane].offset - surf_addr;
> > +	u32 aux_stride = skl_plane_stride(plane_state, aux_plane);
> >  	int crtc_x = plane_state->base.dst.x1;
> >  	int crtc_y = plane_state->base.dst.y1;
> >  	u32 x = plane_state->color_plane[color_plane].x;
> > @@ -544,7 +546,6 @@ skl_program_plane(struct intel_plane *plane,
> >  	u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
> >  	u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
> >  	struct intel_plane *linked = plane_state->planar_linked_plane;
> > -	const struct drm_framebuffer *fb = plane_state->base.fb;
> >  	u8 alpha = plane_state->base.alpha >> 8;
> >  	u32 plane_color_ctl = 0;
> >  	unsigned long irqflags;
> > @@ -619,8 +620,8 @@ skl_program_plane(struct intel_plane *plane,
> >  
> >  	if (INTEL_GEN(dev_priv) < 11)
> >  		I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
> > -			      (plane_state->color_plane[1].y << 16) |
> > -			      plane_state->color_plane[1].x);
> > +			      (plane_state->color_plane[aux_plane].y << 16) |
> > +			      plane_state->color_plane[aux_plane].x);
> >  
> >  	/*
> >  	 * The control register self-arms if the plane was previously
> > @@ -1737,7 +1738,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> >  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
> >  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> >  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> > -	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
> > +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
> >  		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
> >  		return -EINVAL;
> >  	}
> > @@ -2149,7 +2151,16 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
> >  	DRM_FORMAT_MOD_INVALID
> >  };
> >  
> > -static const u64 gen12_plane_format_modifiers_ccs[] = {
> > +static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
> > +	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > +	I915_FORMAT_MOD_Y_TILED,
> > +	I915_FORMAT_MOD_X_TILED,
> > +	DRM_FORMAT_MOD_LINEAR,
> > +	DRM_FORMAT_MOD_INVALID
> > +};
> > +
> > +static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
> >  	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> >  	I915_FORMAT_MOD_Y_TILED,
> >  	I915_FORMAT_MOD_X_TILED,
> > @@ -2305,10 +2316,21 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> >  	}
> >  }
> >  
> > +static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id)
> 
> plane_has_foo() is the common idiom.
> 
> > +{
> > +	return plane_id < PLANE_SPRITE4;
> > +}
> > +
> >  static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> >  					     u32 format, u64 modifier)
> >  {
> > +	struct intel_plane *plane = to_intel_plane(_plane);
> > +
> >  	switch (modifier) {
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > +		if (!gen12_plane_supports_mc_ccs(plane->id))
> > +			return false;
> > +		/* fall through */
> >  	case DRM_FORMAT_MOD_LINEAR:
> >  	case I915_FORMAT_MOD_X_TILED:
> >  	case I915_FORMAT_MOD_Y_TILED:
> > @@ -2326,14 +2348,17 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> >  		if (is_ccs_modifier(modifier))
> >  			return true;
> >  		/* fall through */
> > -	case DRM_FORMAT_RGB565:
> > -	case DRM_FORMAT_XRGB2101010:
> > -	case DRM_FORMAT_XBGR2101010:
> >  	case DRM_FORMAT_YUYV:
> >  	case DRM_FORMAT_YVYU:
> >  	case DRM_FORMAT_UYVY:
> >  	case DRM_FORMAT_VYUY:
> > +		if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
> > +			return true;
> > +		/* fall through */
> >  	case DRM_FORMAT_NV12:
> > +	case DRM_FORMAT_RGB565:
> > +	case DRM_FORMAT_XRGB2101010:
> > +	case DRM_FORMAT_XBGR2101010:
> >  	case DRM_FORMAT_P010:
> >  	case DRM_FORMAT_P012:
> >  	case DRM_FORMAT_P016:
> > @@ -2470,6 +2495,14 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private
> > *dev_priv,
> >  	}
> >  }
> >  
> > +static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id)
> > +{
> > +	if (gen12_plane_supports_mc_ccs(plane_id))
> > +		return gen12_plane_format_modifiers_mc_ccs;
> > +	else
> > +		return gen12_plane_format_modifiers_rc_ccs;
> > +}
> > +
> >  static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
> >  			      enum pipe pipe, enum plane_id plane_id)
> >  {
> > @@ -2536,7 +2569,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> >  
> >  	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
> >  	if (INTEL_GEN(dev_priv) >= 12) {
> > -		modifiers = gen12_plane_format_modifiers_ccs;
> > +		modifiers = gen12_get_plane_modifiers(plane_id);
> >  		plane_funcs = &gen12_plane_funcs;
> >  	} else {
> >  		if (plane->has_ccs)
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 519cfb0a5c42..02eaef8adac0 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6697,6 +6697,7 @@ enum {
> >  #define   PLANE_CTL_TILED_Y			(4 << 10)
> >  #define   PLANE_CTL_TILED_YF			(5 << 10)
> >  #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
> > +#define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
> >  #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
> >  #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
> >  #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(2 << 4)
> > -- 
> > 2.17.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 

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Intel-gfx@lists.freedesktop.org
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Re: [PATCH v4 9/9] Gen-12 display can decompress surfaces compressed by the media engine.

[Matt Roper]

On Thu, Sep 26, 2019 at 03:55:12AM -0700, Dhinakaran Pandiyan wrote:
> Detect the modifier corresponding to media compression to enable
> display decompression for YUV and xRGB packed formats. A new modifier is
> added so that the driver can distinguish between media and render
> compressed buffers. Unlike render decompression, plane 6 and  plane 7 do not
> support media decompression.
> 
> v2: Fix checkpatch warnings on code style (Lucas)
> 
> From DK:
> Separate modifier array for planes that cannot decompress media (Ville)
> 
> v3: Support planar formats
> v4: Switch plane order
> 
> Cc: Nanley G Chery <nanley.g.chery@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 290 +++++++++++++-----
>  .../drm/i915/display/intel_display_types.h    |   2 +-
>  drivers/gpu/drm/i915/display/intel_sprite.c   |  55 +++-
>  drivers/gpu/drm/i915/i915_reg.h               |   1 +
>  4 files changed, 267 insertions(+), 81 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 8ea55d67442c..df3ebaa167ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1888,6 +1888,22 @@ static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
>  		intel_wait_for_pipe_off(old_crtc_state);
>  }
>  
> +bool is_ccs_modifier(u64 modifier)
> +{
> +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> +	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> +	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> +}
> +
> +static bool is_ccs_plane(const struct drm_framebuffer *fb, int color_plane)
> +{
> +	if (!is_ccs_modifier(fb->modifier))
> +		return false;
> +
> +	return color_plane >= fb->format->num_planes / 2;
> +}

This appears to contradict what you indicated on the modifier patch:

  + * Y-tile widths. For semi-planar formats like NV12, CCS plane follows the
  + * Y and UV planes i.e., planes 0 and 2 are used for Y and UV surfaces,
  + * planes 1 and 3 for the respective CCS.

Based on that comment I'd expect something more like (color_plane % 2).


> +
>  static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
>  {
>  	return IS_GEN(dev_priv, 2) ? 2048 : 4096;
> @@ -1908,11 +1924,13 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>  		else
>  			return 512;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
> -		if (color_plane == 1)
> +		if (is_ccs_plane(fb, color_plane))
>  			return 128;
>  		/* fall through */
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> +		/* fall through */
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> -		if (color_plane == 1)
> +		if (is_ccs_plane(fb, color_plane))
>  			return 64;
>  		/* fall through */
>  	case I915_FORMAT_MOD_Y_TILED:
> @@ -1921,7 +1939,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>  		else
>  			return 512;
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> -		if (color_plane == 1)
> +		if (is_ccs_plane(fb, color_plane))
>  			return 128;
>  		/* fall through */
>  	case I915_FORMAT_MOD_Yf_TILED:
> @@ -1949,8 +1967,9 @@ static unsigned int
>  intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
>  {
>  	switch (fb->modifier) {
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> -		if (color_plane == 1)
> +		if (is_ccs_plane(fb, color_plane))
>  			return 1;
>  		/* fall through */
>  	default:
> @@ -2055,6 +2074,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
>  		if (INTEL_GEN(dev_priv) >= 9)
>  			return 256 * 1024;
>  		return 0;
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		return 16 * 1024;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
> @@ -2254,10 +2274,17 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
>  	return new_offset;
>  }
>  
> -static bool is_surface_linear(u64 modifier, int color_plane)
> +static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
>  {
> -	return modifier == DRM_FORMAT_MOD_LINEAR ||
> -	       (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
> +	switch (fb->modifier) {
> +	case DRM_FORMAT_MOD_LINEAR:
> +		return true;
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> +		return is_ccs_plane(fb, color_plane);
> +	default:
> +		return false;
> +	}
>  }
>  
>  static u32 intel_adjust_aligned_offset(int *x, int *y,
> @@ -2272,7 +2299,7 @@ static u32 intel_adjust_aligned_offset(int *x, int *y,
>  
>  	WARN_ON(new_offset > old_offset);
>  
> -	if (!is_surface_linear(fb->modifier, color_plane)) {
> +	if (!is_surface_linear(fb, color_plane)) {
>  		unsigned int tile_size, tile_width, tile_height;
>  		unsigned int pitch_tiles;
>  
> @@ -2342,7 +2369,7 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
>  	if (alignment)
>  		alignment--;
>  
> -	if (!is_surface_linear(fb->modifier, color_plane)) {
> +	if (!is_surface_linear(fb, color_plane)) {
>  		unsigned int tile_size, tile_width, tile_height;
>  		unsigned int tile_rows, tiles, pitch_tiles;
>  
> @@ -2445,6 +2472,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
>  	case I915_FORMAT_MOD_Y_TILED:
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  		return I915_TILING_Y;
>  	default:
>  		return I915_TILING_NONE;
> @@ -2494,6 +2522,13 @@ static const struct drm_format_info gen12_ccs_formats[] = {
>  	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
>  };
>  
> +static const struct drm_format_info gen12_mc_ccs_formats[] = {
> +	{ .format = DRM_FORMAT_YUYV, .num_planes = 2,
> +	  .cpp = { 2, 1, }, .hsub = 4, .vsub = 32, .is_yuv = true },
> +	{ .format = DRM_FORMAT_NV12, .num_planes = 4,
> +	  .cpp = { 1, 2, 1, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
> +};

Don't we also support media compression on RGB and more packed YUV
formats?  I.e., see the matrix on bspec page 49250.

> +
>  static const struct drm_format_info *
>  lookup_format_info(const struct drm_format_info formats[],
>  		   int num_formats, u32 format)
> @@ -2511,12 +2546,21 @@ lookup_format_info(const struct drm_format_info formats[],
>  static const struct drm_format_info *
>  intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
>  {
> +	const struct drm_format_info *info;
> +
>  	switch (cmd->modifier[0]) {
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
>  		return lookup_format_info(skl_ccs_formats,
>  					  ARRAY_SIZE(skl_ccs_formats),
>  					  cmd->pixel_format);
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> +		info = lookup_format_info(gen12_mc_ccs_formats,
> +					  ARRAY_SIZE(gen12_mc_ccs_formats),
> +					  cmd->pixel_format);
> +		if (info)
> +			return info;
> +		/* fall through */

Oh, I see.  You're effectively unioning gen12_ccs_formats in with this
fall through.  I still thing that winds up being a bit confusing so I'd
at least put a comment up above the mc_ccs_formats table.  Although I
also worry that a future platform might allow render compression on some
format that it doesn't support media compression on, which would force
us to decouple the tables at that point.

Even given the union of the two tables, are we still missing some of the
arrangements of YUV422 (i.e., YVYU, UYVY, and VYUY)?

>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
>  		return lookup_format_info(gen12_ccs_formats,
>  					  ARRAY_SIZE(gen12_ccs_formats),
> @@ -2526,13 +2570,6 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
>  	}
>  }
>  
> -bool is_ccs_modifier(u64 modifier)
> -{
> -	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> -	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> -	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> -}
> -
>  u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
>  			      u32 pixel_format, u64 modifier)
>  {
> @@ -2576,7 +2613,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
>  	struct drm_i915_private *dev_priv = to_i915(fb->dev);
>  	u32 tile_width;
>  
> -	if (is_surface_linear(fb->modifier, color_plane)) {
> +	if (is_surface_linear(fb, color_plane)) {
>  		u32 max_stride = intel_plane_fb_max_stride(dev_priv,
>  							   fb->format->format,
>  							   fb->modifier);
> @@ -2592,7 +2629,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
>  	}
>  
>  	tile_width = intel_tile_width_bytes(fb, color_plane);
> -	if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
> +	if (is_ccs_modifier(fb->modifier)) {
>  		/*
>  		 * Display WA #0531: skl,bxt,kbl,glk
>  		 *
> @@ -2602,7 +2639,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
>  		 * require the entire fb to accommodate that to avoid
>  		 * potential runtime errors at plane configuration time.
>  		 */
> -		if (IS_GEN(dev_priv, 9) && fb->width > 3840)
> +		if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
>  			tile_width *= 4;
>  		/*
>  		 * The main surface pitch must be padded to a multiple of four
> @@ -2682,25 +2719,75 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
>  	return stride > max_stride;
>  }
>  
> +static void
> +intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)
> +{
> +	int i;
> +	static const struct {
> +		u32 format;
> +		int vsub[4];
> +		int hsub[4];
> +	} mc_ccs_subsampling[] = { { .hsub = { 1, 2, 8, 16 },
> +				     .vsub = { 1, 2, 32, 32 },
> +				     .format = DRM_FORMAT_NV12, },
> +				 };
> +
> +	*hsub = fb->format->hsub;
> +	*vsub = fb->format->vsub;
> +
> +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS &&
> +	    fb->format->num_planes == 4) {
> +		for (i = 0; i < ARRAY_SIZE(mc_ccs_subsampling); i++) {
> +			if  (mc_ccs_subsampling[i].format == fb->format->format) {
> +				*hsub = mc_ccs_subsampling[i].hsub[color_plane];
> +				*vsub = mc_ccs_subsampling[i].vsub[color_plane];
> +				break;
> +			}
> +		}
> +		WARN_ON(i == ARRAY_SIZE(mc_ccs_subsampling));
> +	}
> +}
> +
> +static void
> +intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
> +{
> +	int hsub, vsub;
> +
> +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
> +	*w = fb->width/hsub;
> +	*h = fb->height/vsub;
> +}
> +
>  static int
> -intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
> +intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int aux_plane, int x, int y)
>  {
>  	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> -	int hsub = fb->format->hsub;
> -	int vsub = fb->format->vsub;
> +	int hsub, vsub;
> +	int hsub_main, vsub_main;
>  	int tile_width, tile_height;
>  	int ccs_x, ccs_y;
>  	int main_x, main_y;
> +	int main_plane;
> +
> +	if (!is_ccs_plane(fb, aux_plane))
> +		return 0;
> +
> +	main_plane = (aux_plane - 1) / 2;

This also doesn't mention the modifier description comment.  So I guess
that comment just needs to be updated, and maybe with a description that
the drm_framebuffer color plane ordering doesn't match the order that
they show up in memory.

> +	intel_tile_dims(fb, aux_plane, &tile_width, &tile_height);
> +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, aux_plane);
> +	intel_fb_plane_get_subsampling(&hsub_main, &vsub_main, fb,
> +				       main_plane);
>  
> -	intel_tile_dims(fb, 1, &tile_width, &tile_height);
> +	hsub /= hsub_main;
> +	vsub /= vsub_main;
>  
>  	tile_width *= hsub;
>  	tile_height *= vsub;
>  
>  	ccs_x = (x * hsub) % tile_width;
>  	ccs_y = (y * vsub) % tile_height;
> -	main_x = intel_fb->normal[0].x % tile_width;
> -	main_y = intel_fb->normal[0].y % tile_height;
> +	main_x = intel_fb->normal[main_plane].x % tile_width;
> +	main_y = intel_fb->normal[main_plane].y % tile_height;
>  
>  	/*
>  	* CCS doesn't have its own x/y offset register, so the intra CCS tile
> @@ -2710,8 +2797,8 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
>  		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
>  			      main_x, main_y,
>  			      ccs_x, ccs_y,
> -			      intel_fb->normal[0].x,
> -			      intel_fb->normal[0].y,
> +			      intel_fb->normal[main_plane].x,
> +			      intel_fb->normal[main_plane].y,
>  			      x, y);
>  		return -EINVAL;
>  	}
> @@ -2739,8 +2826,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
>  		int ret;
>  
>  		cpp = fb->format->cpp[i];
> -		width = drm_framebuffer_plane_width(fb->width, fb, i);
> -		height = drm_framebuffer_plane_height(fb->height, fb, i);
> +		intel_fb_plane_dims(&width, &height, fb, i);
>  
>  		ret = intel_fb_offset_to_xy(&x, &y, fb, i);
>  		if (ret) {
> @@ -2749,11 +2835,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
>  			return ret;
>  		}
>  
> -		if (is_ccs_modifier(fb->modifier) && i == 1) {
> -			ret = intel_fb_check_ccs_xy(fb, x, y);
> -			if (ret)
> -				return ret;
> -		}
> +		ret = intel_fb_check_ccs_xy(fb, i, x, y);
> +		if (ret)
> +			return ret;
>  
>  		/*
>  		 * The fence (if used) is aligned to the start of the object
> @@ -3371,6 +3455,7 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb,
>  			return 5120;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
>  		/* FIXME AUX plane? */
>  	case I915_FORMAT_MOD_Y_TILED:
>  	case I915_FORMAT_MOD_Yf_TILED:
> @@ -3430,16 +3515,18 @@ static int icl_max_plane_height(void)
>  }
>  
>  static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
> -					   int main_x, int main_y, u32 main_offset)
> +					   int main_x, int main_y,
> +					   u32 main_offset, int aux_plane)
>  {
>  	const struct drm_framebuffer *fb = plane_state->base.fb;
> -	int hsub = fb->format->hsub;
> -	int vsub = fb->format->vsub;
> -	int aux_x = plane_state->color_plane[1].x;
> -	int aux_y = plane_state->color_plane[1].y;
> -	u32 aux_offset = plane_state->color_plane[1].offset;
> -	u32 alignment = intel_surf_alignment(fb, 1);
> -
> +	int hsub;
> +	int vsub;
> +	int aux_x = plane_state->color_plane[aux_plane].x;
> +	int aux_y = plane_state->color_plane[aux_plane].y;
> +	u32 aux_offset = plane_state->color_plane[aux_plane].offset;
> +	u32 alignment = intel_surf_alignment(fb, aux_plane);
> +
> +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, aux_plane);
>  	while (aux_offset >= main_offset && aux_y <= main_y) {
>  		int x, y;
>  
> @@ -3451,7 +3538,7 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
>  
>  		x = aux_x / hsub;
>  		y = aux_y / vsub;
> -		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
> +		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, aux_plane,
>  							       aux_offset, aux_offset - alignment);
>  		aux_x = x * hsub + aux_x % hsub;
>  		aux_y = y * vsub + aux_y % vsub;
> @@ -3460,9 +3547,9 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
>  	if (aux_x != main_x || aux_y != main_y)
>  		return false;
>  
> -	plane_state->color_plane[1].offset = aux_offset;
> -	plane_state->color_plane[1].x = aux_x;
> -	plane_state->color_plane[1].y = aux_y;
> +	plane_state->color_plane[aux_plane].offset = aux_offset;
> +	plane_state->color_plane[aux_plane].x = aux_x;
> +	plane_state->color_plane[aux_plane].y = aux_y;
>  
>  	return true;
>  }
> @@ -3478,7 +3565,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
>  	int h = drm_rect_height(&plane_state->base.src) >> 16;
>  	int max_width;
>  	int max_height;
> -	u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
> +	int aux_plane = fb->format->num_planes / 2;
> +	u32 alignment, offset, aux_offset = plane_state->color_plane[aux_plane].offset;
>  
>  	if (INTEL_GEN(dev_priv) >= 11)
>  		max_width = icl_max_plane_width(fb, 0, rotation);
> @@ -3536,7 +3624,9 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
>  	 * they match with the main surface x/y offsets.
>  	 */
>  	if (is_ccs_modifier(fb->modifier)) {
> -		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
> +
> +		while (!skl_check_main_ccs_coordinates(plane_state, x, y,
> +						       offset, aux_plane)) {
>  			if (offset == 0)
>  				break;
>  
> @@ -3544,7 +3634,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
>  								   offset, offset - alignment);
>  		}
>  
> -		if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
> +		if (x != plane_state->color_plane[aux_plane].x ||
> +		    y != plane_state->color_plane[aux_plane].y) {
>  			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
>  			return -EINVAL;
>  		}
> @@ -3587,6 +3678,41 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
>  		return -EINVAL;
>  	}
>  
> +	if (is_ccs_modifier(fb->modifier)) {
> +		int aux_offset = plane_state->color_plane[3].offset;
> +		int alignment = intel_surf_alignment(fb, 1);
> +
> +		if (offset > aux_offset) {
> +			int hsub, vsub;
> +			int main_x = x, main_y = y;
> +
> +
> +			intel_fb_plane_get_subsampling(&hsub, &vsub, fb, 1);
> +			x = main_x / hsub;
> +			y = main_y / vsub;
> +			offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
> +								   offset,
> +								   aux_offset & ~(alignment - 1));
> +			x = x * hsub + main_x % hsub;
> +			y = y * vsub + main_y % vsub;
> +
> +		}
> +
> +		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset, 3)) {
> +			if (offset == 0)
> +				break;
> +
> +			offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
> +								   offset, offset - alignment);
> +		}
> +
> +		if (x != plane_state->color_plane[3].x ||
> +		    y != plane_state->color_plane[3].y) {
> +			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
> +			return -EINVAL;
> +		}
> +	}
> +
>  	plane_state->color_plane[1].offset = offset;
>  	plane_state->color_plane[1].x = x;
>  	plane_state->color_plane[1].y = y;
> @@ -3599,19 +3725,30 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
>  	const struct drm_framebuffer *fb = plane_state->base.fb;
>  	int src_x = plane_state->base.src.x1 >> 16;
>  	int src_y = plane_state->base.src.y1 >> 16;
> -	int hsub = fb->format->hsub;
> -	int vsub = fb->format->vsub;
> -	int x = src_x / hsub;
> -	int y = src_y / vsub;
>  	u32 offset;
> +	int ccs;
>  
> -	intel_add_fb_offsets(&x, &y, plane_state, 1);
> -	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
>  
> -	plane_state->color_plane[1].offset = offset;
> -	plane_state->color_plane[1].x = x * hsub + src_x % hsub;
> -	plane_state->color_plane[1].y = y * vsub + src_y % vsub;
> +	for (ccs = fb->format->num_planes / 2; ccs < fb->format->num_planes; ccs++) {
> +		int hsub, vsub;
> +		int main_hsub, main_vsub;
> +		int x, y;
> +
> +		intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs);
> +		intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, (ccs - 1)/ 2);
> +
> +		hsub /= main_hsub;
> +		vsub /= main_vsub;
> +		x = src_x / hsub;
> +		y = src_y / vsub;
>  
> +		intel_add_fb_offsets(&x, &y, plane_state, ccs);
> +		offset = intel_plane_compute_aligned_offset(&x, &y,
> +							    plane_state, ccs);
> +		plane_state->color_plane[ccs].offset = offset;
> +		plane_state->color_plane[ccs].x = x * hsub + src_x % hsub;
> +		plane_state->color_plane[ccs].y = y * vsub + src_y % vsub;
> +	}
>  	return 0;
>  }
>  
> @@ -3619,6 +3756,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
>  {
>  	const struct drm_framebuffer *fb = plane_state->base.fb;
>  	int ret;
> +	bool needs_aux = false;
>  
>  	ret = intel_plane_compute_gtt(plane_state);
>  	if (ret)
> @@ -3628,21 +3766,31 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
>  		return 0;
>  
>  	/*
> -	 * Handle the AUX surface first since
> -	 * the main surface setup depends on it.
> +	 * Handle the AUX surface first since the main surface setup depends on
> +	 * it.
>  	 */
> -	if (drm_format_info_is_yuv_semiplanar(fb->format)) {
> -		ret = skl_check_nv12_aux_surface(plane_state);
> +	if (is_ccs_modifier(fb->modifier)) {
> +		needs_aux = true;
> +		ret = skl_check_ccs_aux_surface(plane_state);
>  		if (ret)
>  			return ret;
> -	} else if (is_ccs_modifier(fb->modifier)) {
> -		ret = skl_check_ccs_aux_surface(plane_state);
> +	}
> +
> +	if (drm_format_info_is_yuv_semiplanar(fb->format)) {
> +		needs_aux = true;
> +		ret = skl_check_nv12_aux_surface(plane_state);
>  		if (ret)
>  			return ret;
> -	} else {
> -		plane_state->color_plane[1].offset = ~0xfff;
> -		plane_state->color_plane[1].x = 0;
> -		plane_state->color_plane[1].y = 0;
> +	}
> +
> +	if (!needs_aux) {
> +		int i;
> +
> +		for (i = 1; i < fb->format->num_planes; i++) {
> +			plane_state->color_plane[i].offset = ~0xfff;
> +			plane_state->color_plane[i].x = 0;
> +			plane_state->color_plane[i].y = 0;
> +		}
>  	}
>  
>  	ret = skl_check_main_surface(plane_state);
> @@ -4030,7 +4178,7 @@ static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
>  	 * The stride is either expressed as a multiple of 64 bytes chunks for
>  	 * linear buffers or in number of tiles for tiled buffers.
>  	 */
> -	if (is_surface_linear(fb->modifier, color_plane))
> +	if (is_surface_linear(fb, color_plane))
>  		return 64;
>  	else if (drm_rotation_90_or_270(rotation))
>  		return intel_tile_height(fb, color_plane);
> @@ -4160,6 +4308,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
>  		return PLANE_CTL_TILED_Y |
>  		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
>  		       PLANE_CTL_CLEAR_COLOR_DISABLE;
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> +		return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
>  	case I915_FORMAT_MOD_Yf_TILED:
>  		return PLANE_CTL_TILED_YF;
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -9968,6 +10118,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
>  			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
>  				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
>  				I915_FORMAT_MOD_Y_TILED_CCS;
> +		else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
> +			fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
>  		else
>  			fb->modifier = I915_FORMAT_MOD_Y_TILED;
>  		break;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 976669f01a8c..5998b959225c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -530,7 +530,7 @@ struct intel_plane_state {
>  		 */
>  		u32 stride;
>  		int x, y;
> -	} color_plane[2];
> +	} color_plane[4];
>  
>  	/* plane control register */
>  	u32 ctl;
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 9b9b41b0fc91..788d0fc8d8ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -532,11 +532,13 @@ skl_program_plane(struct intel_plane *plane,
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	enum plane_id plane_id = plane->id;
>  	enum pipe pipe = plane->pipe;
> +	const struct drm_framebuffer *fb = plane_state->base.fb;
> +	int aux_plane = fb->format->num_planes / 2 + color_plane;
>  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
>  	u32 surf_addr = plane_state->color_plane[color_plane].offset;
>  	u32 stride = skl_plane_stride(plane_state, color_plane);
> -	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
> -	u32 aux_stride = skl_plane_stride(plane_state, 1);
> +	u32 aux_dist = plane_state->color_plane[aux_plane].offset - surf_addr;
> +	u32 aux_stride = skl_plane_stride(plane_state, aux_plane);
>  	int crtc_x = plane_state->base.dst.x1;
>  	int crtc_y = plane_state->base.dst.y1;
>  	u32 x = plane_state->color_plane[color_plane].x;
> @@ -544,7 +546,6 @@ skl_program_plane(struct intel_plane *plane,
>  	u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
>  	u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
>  	struct intel_plane *linked = plane_state->planar_linked_plane;
> -	const struct drm_framebuffer *fb = plane_state->base.fb;
>  	u8 alpha = plane_state->base.alpha >> 8;
>  	u32 plane_color_ctl = 0;
>  	unsigned long irqflags;
> @@ -619,8 +620,8 @@ skl_program_plane(struct intel_plane *plane,
>  
>  	if (INTEL_GEN(dev_priv) < 11)
>  		I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
> -			      (plane_state->color_plane[1].y << 16) |
> -			      plane_state->color_plane[1].x);
> +			      (plane_state->color_plane[aux_plane].y << 16) |
> +			      plane_state->color_plane[aux_plane].x);
>  
>  	/*
>  	 * The control register self-arms if the plane was previously
> @@ -1737,7 +1738,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
>  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> -	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
> +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
>  		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
>  		return -EINVAL;
>  	}
> @@ -2149,7 +2151,16 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
>  	DRM_FORMAT_MOD_INVALID
>  };
>  
> -static const u64 gen12_plane_format_modifiers_ccs[] = {
> +static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
> +	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> +	I915_FORMAT_MOD_Y_TILED,
> +	I915_FORMAT_MOD_X_TILED,
> +	DRM_FORMAT_MOD_LINEAR,
> +	DRM_FORMAT_MOD_INVALID
> +};
> +
> +static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
>  	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
>  	I915_FORMAT_MOD_Y_TILED,
>  	I915_FORMAT_MOD_X_TILED,
> @@ -2305,10 +2316,21 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>  	}
>  }
>  
> +static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id)
> +{
> +	return plane_id < PLANE_SPRITE4;
> +}
> +
>  static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  					     u32 format, u64 modifier)
>  {
> +	struct intel_plane *plane = to_intel_plane(_plane);
> +
>  	switch (modifier) {
> +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> +		if (!gen12_plane_supports_mc_ccs(plane->id))
> +			return false;
> +		/* fall through */
>  	case DRM_FORMAT_MOD_LINEAR:
>  	case I915_FORMAT_MOD_X_TILED:
>  	case I915_FORMAT_MOD_Y_TILED:
> @@ -2326,14 +2348,17 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  		if (is_ccs_modifier(modifier))
>  			return true;
>  		/* fall through */
> -	case DRM_FORMAT_RGB565:
> -	case DRM_FORMAT_XRGB2101010:
> -	case DRM_FORMAT_XBGR2101010:
>  	case DRM_FORMAT_YUYV:
>  	case DRM_FORMAT_YVYU:
>  	case DRM_FORMAT_UYVY:
>  	case DRM_FORMAT_VYUY:
> +		if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
> +			return true;
> +		/* fall through */
>  	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_RGB565:
> +	case DRM_FORMAT_XRGB2101010:
> +	case DRM_FORMAT_XBGR2101010:
>  	case DRM_FORMAT_P010:
>  	case DRM_FORMAT_P012:
>  	case DRM_FORMAT_P016:
> @@ -2470,6 +2495,14 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
>  	}
>  }
>  
> +static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id)
> +{
> +	if (gen12_plane_supports_mc_ccs(plane_id))
> +		return gen12_plane_format_modifiers_mc_ccs;
> +	else
> +		return gen12_plane_format_modifiers_rc_ccs;
> +}
> +
>  static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
>  			      enum pipe pipe, enum plane_id plane_id)
>  {
> @@ -2536,7 +2569,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>  
>  	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
>  	if (INTEL_GEN(dev_priv) >= 12) {
> -		modifiers = gen12_plane_format_modifiers_ccs;
> +		modifiers = gen12_get_plane_modifiers(plane_id);
>  		plane_funcs = &gen12_plane_funcs;
>  	} else {
>  		if (plane->has_ccs)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 519cfb0a5c42..02eaef8adac0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6697,6 +6697,7 @@ enum {
>  #define   PLANE_CTL_TILED_Y			(4 << 10)
>  #define   PLANE_CTL_TILED_YF			(5 << 10)
>  #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
> +#define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
>  #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
>  #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
>  #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(2 << 4)
> -- 
> 2.17.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v4 9/9] Gen-12 display can decompress surfaces compressed by the media engine.

[Dhinakaran Pandiyan]

On Fri, 2019-10-04 at 13:27 -0700, Matt Roper wrote:
> On Thu, Sep 26, 2019 at 03:55:12AM -0700, Dhinakaran Pandiyan wrote:
> > Detect the modifier corresponding to media compression to enable
> > display decompression for YUV and xRGB packed formats. A new modifier is
> > added so that the driver can distinguish between media and render
> > compressed buffers. Unlike render decompression, plane 6 and  plane 7 do not
> > support media decompression.
> > 
> > v2: Fix checkpatch warnings on code style (Lucas)
> > 
> > From DK:
> > Separate modifier array for planes that cannot decompress media (Ville)
> > 
> > v3: Support planar formats
> > v4: Switch plane order
> > 
> > Cc: Nanley G Chery <nanley.g.chery@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c  | 290 +++++++++++++-----
> >  .../drm/i915/display/intel_display_types.h    |   2 +-
> >  drivers/gpu/drm/i915/display/intel_sprite.c   |  55 +++-
> >  drivers/gpu/drm/i915/i915_reg.h               |   1 +
> >  4 files changed, 267 insertions(+), 81 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 8ea55d67442c..df3ebaa167ab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1888,6 +1888,22 @@ static void intel_disable_pipe(const struct intel_crtc_state
> > *old_crtc_state)
> >  		intel_wait_for_pipe_off(old_crtc_state);
> >  }
> >  
> > +bool is_ccs_modifier(u64 modifier)
> > +{
> > +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > +	       modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> > +	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > +	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > +}
> > +
> > +static bool is_ccs_plane(const struct drm_framebuffer *fb, int color_plane)
> > +{
> > +	if (!is_ccs_modifier(fb->modifier))
> > +		return false;
> > +
> > +	return color_plane >= fb->format->num_planes / 2;
> > +}
> 
> This appears to contradict what you indicated on the modifier patch:
> 
>   + * Y-tile widths. For semi-planar formats like NV12, CCS plane follows the
>   + * Y and UV planes i.e., planes 0 and 2 are used for Y and UV surfaces,
>   + * planes 1 and 3 for the respective CCS.
> 
> Based on that comment I'd expect something more like (color_plane % 2).

I need to update the comment in the modifier patch, thanks for catching this. The major change in
this version is 

for planar formats: planes 2 and 3 will be used for CCS instead of 1 and 3. 
for packed formats: plane 1 will be used for CCS

> 
> 
> > +
> >  static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
> >  {
> >  	return IS_GEN(dev_priv, 2) ? 2048 : 4096;
> > @@ -1908,11 +1924,13 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int
> > color_plane)
> >  		else
> >  			return 512;
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> > -		if (color_plane == 1)
> > +		if (is_ccs_plane(fb, color_plane))
> >  			return 128;
> >  		/* fall through */
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > +		/* fall through */
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > -		if (color_plane == 1)
> > +		if (is_ccs_plane(fb, color_plane))
> >  			return 64;
> >  		/* fall through */
> >  	case I915_FORMAT_MOD_Y_TILED:
> > @@ -1921,7 +1939,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> >  		else
> >  			return 512;
> >  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> > -		if (color_plane == 1)
> > +		if (is_ccs_plane(fb, color_plane))
> >  			return 128;
> >  		/* fall through */
> >  	case I915_FORMAT_MOD_Yf_TILED:
> > @@ -1949,8 +1967,9 @@ static unsigned int
> >  intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
> >  {
> >  	switch (fb->modifier) {
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > -		if (color_plane == 1)
> > +		if (is_ccs_plane(fb, color_plane))
> >  			return 1;
> >  		/* fall through */
> >  	default:
> > @@ -2055,6 +2074,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> >  		if (INTEL_GEN(dev_priv) >= 9)
> >  			return 256 * 1024;
> >  		return 0;
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> >  		return 16 * 1024;
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> > @@ -2254,10 +2274,17 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
> >  	return new_offset;
> >  }
> >  
> > -static bool is_surface_linear(u64 modifier, int color_plane)
> > +static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
> >  {
> > -	return modifier == DRM_FORMAT_MOD_LINEAR ||
> > -	       (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
> > +	switch (fb->modifier) {
> > +	case DRM_FORMAT_MOD_LINEAR:
> > +		return true;
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > +		return is_ccs_plane(fb, color_plane);
> > +	default:
> > +		return false;
> > +	}
> >  }
> >  
> >  static u32 intel_adjust_aligned_offset(int *x, int *y,
> > @@ -2272,7 +2299,7 @@ static u32 intel_adjust_aligned_offset(int *x, int *y,
> >  
> >  	WARN_ON(new_offset > old_offset);
> >  
> > -	if (!is_surface_linear(fb->modifier, color_plane)) {
> > +	if (!is_surface_linear(fb, color_plane)) {
> >  		unsigned int tile_size, tile_width, tile_height;
> >  		unsigned int pitch_tiles;
> >  
> > @@ -2342,7 +2369,7 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
> >  	if (alignment)
> >  		alignment--;
> >  
> > -	if (!is_surface_linear(fb->modifier, color_plane)) {
> > +	if (!is_surface_linear(fb, color_plane)) {
> >  		unsigned int tile_size, tile_width, tile_height;
> >  		unsigned int tile_rows, tiles, pitch_tiles;
> >  
> > @@ -2445,6 +2472,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> >  	case I915_FORMAT_MOD_Y_TILED:
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> >  		return I915_TILING_Y;
> >  	default:
> >  		return I915_TILING_NONE;
> > @@ -2494,6 +2522,13 @@ static const struct drm_format_info gen12_ccs_formats[] = {
> >  	  .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> >  };
> >  
> > +static const struct drm_format_info gen12_mc_ccs_formats[] = {
> > +	{ .format = DRM_FORMAT_YUYV, .num_planes = 2,
> > +	  .cpp = { 2, 1, }, .hsub = 4, .vsub = 32, .is_yuv = true },
> > +	{ .format = DRM_FORMAT_NV12, .num_planes = 4,
> > +	  .cpp = { 1, 2, 1, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
> > +};
> 
> Don't we also support media compression on RGB and more packed YUV
> formats?  I.e., see the matrix on bspec page 49250.
> 
> > +
> >  static const struct drm_format_info *
> >  lookup_format_info(const struct drm_format_info formats[],
> >  		   int num_formats, u32 format)
> > @@ -2511,12 +2546,21 @@ lookup_format_info(const struct drm_format_info formats[],
> >  static const struct drm_format_info *
> >  intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> >  {
> > +	const struct drm_format_info *info;
> > +
> >  	switch (cmd->modifier[0]) {
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> >  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> >  		return lookup_format_info(skl_ccs_formats,
> >  					  ARRAY_SIZE(skl_ccs_formats),
> >  					  cmd->pixel_format);
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > +		info = lookup_format_info(gen12_mc_ccs_formats,
> > +					  ARRAY_SIZE(gen12_mc_ccs_formats),
> > +					  cmd->pixel_format);
> > +		if (info)
> > +			return info;
> > +		/* fall through */
> 
> Oh, I see.  You're effectively unioning gen12_ccs_formats in with this
> fall through.  I still thing that winds up being a bit confusing so I'd
> at least put a comment up above the mc_ccs_formats table.  Although I
> also worry that a future platform might allow render compression on some
> format that it doesn't support media compression on, which would force
> us to decouple the tables at that point.
> 
> Even given the union of the two tables, are we still missing some of the
> arrangements of YUV422 (i.e., YVYU, UYVY, and VYUY)?

I did not include all the supported formats I wanted to get feedback on the interface for planar
formats. I'll add them in the next version.
 
> 
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> >  		return lookup_format_info(gen12_ccs_formats,
> >  					  ARRAY_SIZE(gen12_ccs_formats),
> > @@ -2526,13 +2570,6 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> >  	}
> >  }
> >  
> > -bool is_ccs_modifier(u64 modifier)
> > -{
> > -	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > -	       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > -	       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > -}
> > -
> >  u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> >  			      u32 pixel_format, u64 modifier)
> >  {
> > @@ -2576,7 +2613,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int
> > color_plane)
> >  	struct drm_i915_private *dev_priv = to_i915(fb->dev);
> >  	u32 tile_width;
> >  
> > -	if (is_surface_linear(fb->modifier, color_plane)) {
> > +	if (is_surface_linear(fb, color_plane)) {
> >  		u32 max_stride = intel_plane_fb_max_stride(dev_priv,
> >  							   fb->format->format,
> >  							   fb->modifier);
> > @@ -2592,7 +2629,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int
> > color_plane)
> >  	}
> >  
> >  	tile_width = intel_tile_width_bytes(fb, color_plane);
> > -	if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
> > +	if (is_ccs_modifier(fb->modifier)) {
> >  		/*
> >  		 * Display WA #0531: skl,bxt,kbl,glk
> >  		 *
> > @@ -2602,7 +2639,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int
> > color_plane)
> >  		 * require the entire fb to accommodate that to avoid
> >  		 * potential runtime errors at plane configuration time.
> >  		 */
> > -		if (IS_GEN(dev_priv, 9) && fb->width > 3840)
> > +		if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
> >  			tile_width *= 4;
> >  		/*
> >  		 * The main surface pitch must be padded to a multiple of four
> > @@ -2682,25 +2719,75 @@ static bool intel_plane_needs_remap(const struct intel_plane_state
> > *plane_state)
> >  	return stride > max_stride;
> >  }
> >  
> > +static void
> > +intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int
> > color_plane)
> > +{
> > +	int i;
> > +	static const struct {
> > +		u32 format;
> > +		int vsub[4];
> > +		int hsub[4];
> > +	} mc_ccs_subsampling[] = { { .hsub = { 1, 2, 8, 16 },
> > +				     .vsub = { 1, 2, 32, 32 },
> > +				     .format = DRM_FORMAT_NV12, },
> > +				 };
> > +
> > +	*hsub = fb->format->hsub;
> > +	*vsub = fb->format->vsub;
> > +
> > +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS &&
> > +	    fb->format->num_planes == 4) {
> > +		for (i = 0; i < ARRAY_SIZE(mc_ccs_subsampling); i++) {
> > +			if  (mc_ccs_subsampling[i].format == fb->format->format) {
> > +				*hsub = mc_ccs_subsampling[i].hsub[color_plane];
> > +				*vsub = mc_ccs_subsampling[i].vsub[color_plane];
> > +				break;
> > +			}
> > +		}
> > +		WARN_ON(i == ARRAY_SIZE(mc_ccs_subsampling));
> > +	}
> > +}
> > +
> > +static void
> > +intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
> > +{
> > +	int hsub, vsub;
> > +
> > +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
> > +	*w = fb->width/hsub;
> > +	*h = fb->height/vsub;
> > +}
> > +
> >  static int
> > -intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
> > +intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int aux_plane, int x, int y)
> >  {
> >  	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> > -	int hsub = fb->format->hsub;
> > -	int vsub = fb->format->vsub;
> > +	int hsub, vsub;
> > +	int hsub_main, vsub_main;
> >  	int tile_width, tile_height;
> >  	int ccs_x, ccs_y;
> >  	int main_x, main_y;
> > +	int main_plane;
> > +
> > +	if (!is_ccs_plane(fb, aux_plane))
> > +		return 0;
> > +
> > +	main_plane = (aux_plane - 1) / 2;
> 
> This also doesn't mention the modifier description comment.  So I guess
> that comment just needs to be updated, 
Yeah.

> and maybe with a description that
> the drm_framebuffer color plane ordering doesn't match the order that
> they show up in memory.

The color plane ordering is expected to match the surfaces positions in memory. My understanding is
that UMD's have the flexibility in their ordering, with the only constraints being 
1) CCS must be placed after the corresponding main surface
2) UV must be placed after Y.

Thanks for the feedback.

-DK

> 
> > +	intel_tile_dims(fb, aux_plane, &tile_width, &tile_height);
> > +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, aux_plane);
> > +	intel_fb_plane_get_subsampling(&hsub_main, &vsub_main, fb,
> > +				       main_plane);
> >  
> > -	intel_tile_dims(fb, 1, &tile_width, &tile_height);
> > +	hsub /= hsub_main;
> > +	vsub /= vsub_main;
> >  
> >  	tile_width *= hsub;
> >  	tile_height *= vsub;
> >  
> >  	ccs_x = (x * hsub) % tile_width;
> >  	ccs_y = (y * vsub) % tile_height;
> > -	main_x = intel_fb->normal[0].x % tile_width;
> > -	main_y = intel_fb->normal[0].y % tile_height;
> > +	main_x = intel_fb->normal[main_plane].x % tile_width;
> > +	main_y = intel_fb->normal[main_plane].y % tile_height;
> >  
> >  	/*
> >  	* CCS doesn't have its own x/y offset register, so the intra CCS tile
> > @@ -2710,8 +2797,8 @@ intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
> >  		DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
> >  			      main_x, main_y,
> >  			      ccs_x, ccs_y,
> > -			      intel_fb->normal[0].x,
> > -			      intel_fb->normal[0].y,
> > +			      intel_fb->normal[main_plane].x,
> > +			      intel_fb->normal[main_plane].y,
> >  			      x, y);
> >  		return -EINVAL;
> >  	}
> > @@ -2739,8 +2826,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
> >  		int ret;
> >  
> >  		cpp = fb->format->cpp[i];
> > -		width = drm_framebuffer_plane_width(fb->width, fb, i);
> > -		height = drm_framebuffer_plane_height(fb->height, fb, i);
> > +		intel_fb_plane_dims(&width, &height, fb, i);
> >  
> >  		ret = intel_fb_offset_to_xy(&x, &y, fb, i);
> >  		if (ret) {
> > @@ -2749,11 +2835,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
> >  			return ret;
> >  		}
> >  
> > -		if (is_ccs_modifier(fb->modifier) && i == 1) {
> > -			ret = intel_fb_check_ccs_xy(fb, x, y);
> > -			if (ret)
> > -				return ret;
> > -		}
> > +		ret = intel_fb_check_ccs_xy(fb, i, x, y);
> > +		if (ret)
> > +			return ret;
> >  
> >  		/*
> >  		 * The fence (if used) is aligned to the start of the object
> > @@ -3371,6 +3455,7 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb,
> >  			return 5120;
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> >  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> >  		/* FIXME AUX plane? */
> >  	case I915_FORMAT_MOD_Y_TILED:
> >  	case I915_FORMAT_MOD_Yf_TILED:
> > @@ -3430,16 +3515,18 @@ static int icl_max_plane_height(void)
> >  }
> >  
> >  static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
> > -					   int main_x, int main_y, u32 main_offset)
> > +					   int main_x, int main_y,
> > +					   u32 main_offset, int aux_plane)
> >  {
> >  	const struct drm_framebuffer *fb = plane_state->base.fb;
> > -	int hsub = fb->format->hsub;
> > -	int vsub = fb->format->vsub;
> > -	int aux_x = plane_state->color_plane[1].x;
> > -	int aux_y = plane_state->color_plane[1].y;
> > -	u32 aux_offset = plane_state->color_plane[1].offset;
> > -	u32 alignment = intel_surf_alignment(fb, 1);
> > -
> > +	int hsub;
> > +	int vsub;
> > +	int aux_x = plane_state->color_plane[aux_plane].x;
> > +	int aux_y = plane_state->color_plane[aux_plane].y;
> > +	u32 aux_offset = plane_state->color_plane[aux_plane].offset;
> > +	u32 alignment = intel_surf_alignment(fb, aux_plane);
> > +
> > +	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, aux_plane);
> >  	while (aux_offset >= main_offset && aux_y <= main_y) {
> >  		int x, y;
> >  
> > @@ -3451,7 +3538,7 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state
> > *plane_state
> >  
> >  		x = aux_x / hsub;
> >  		y = aux_y / vsub;
> > -		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
> > +		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, aux_plane,
> >  							       aux_offset, aux_offset - alignment);
> >  		aux_x = x * hsub + aux_x % hsub;
> >  		aux_y = y * vsub + aux_y % vsub;
> > @@ -3460,9 +3547,9 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state
> > *plane_state
> >  	if (aux_x != main_x || aux_y != main_y)
> >  		return false;
> >  
> > -	plane_state->color_plane[1].offset = aux_offset;
> > -	plane_state->color_plane[1].x = aux_x;
> > -	plane_state->color_plane[1].y = aux_y;
> > +	plane_state->color_plane[aux_plane].offset = aux_offset;
> > +	plane_state->color_plane[aux_plane].x = aux_x;
> > +	plane_state->color_plane[aux_plane].y = aux_y;
> >  
> >  	return true;
> >  }
> > @@ -3478,7 +3565,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> >  	int h = drm_rect_height(&plane_state->base.src) >> 16;
> >  	int max_width;
> >  	int max_height;
> > -	u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
> > +	int aux_plane = fb->format->num_planes / 2;
> > +	u32 alignment, offset, aux_offset = plane_state->color_plane[aux_plane].offset;
> >  
> >  	if (INTEL_GEN(dev_priv) >= 11)
> >  		max_width = icl_max_plane_width(fb, 0, rotation);
> > @@ -3536,7 +3624,9 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> >  	 * they match with the main surface x/y offsets.
> >  	 */
> >  	if (is_ccs_modifier(fb->modifier)) {
> > -		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
> > +
> > +		while (!skl_check_main_ccs_coordinates(plane_state, x, y,
> > +						       offset, aux_plane)) {
> >  			if (offset == 0)
> >  				break;
> >  
> > @@ -3544,7 +3634,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> >  								   offset, offset - alignment);
> >  		}
> >  
> > -		if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
> > +		if (x != plane_state->color_plane[aux_plane].x ||
> > +		    y != plane_state->color_plane[aux_plane].y) {
> >  			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to
> > CCS\n");
> >  			return -EINVAL;
> >  		}
> > @@ -3587,6 +3678,41 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state
> > *plane_state)
> >  		return -EINVAL;
> >  	}
> >  
> > +	if (is_ccs_modifier(fb->modifier)) {
> > +		int aux_offset = plane_state->color_plane[3].offset;
> > +		int alignment = intel_surf_alignment(fb, 1);
> > +
> > +		if (offset > aux_offset) {
> > +			int hsub, vsub;
> > +			int main_x = x, main_y = y;
> > +
> > +
> > +			intel_fb_plane_get_subsampling(&hsub, &vsub, fb, 1);
> > +			x = main_x / hsub;
> > +			y = main_y / vsub;
> > +			offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
> > +								   offset,
> > +								   aux_offset & ~(alignment - 1));
> > +			x = x * hsub + main_x % hsub;
> > +			y = y * vsub + main_y % vsub;
> > +
> > +		}
> > +
> > +		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset, 3)) {
> > +			if (offset == 0)
> > +				break;
> > +
> > +			offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
> > +								   offset, offset - alignment);
> > +		}
> > +
> > +		if (x != plane_state->color_plane[3].x ||
> > +		    y != plane_state->color_plane[3].y) {
> > +			DRM_DEBUG_KMS("Unable to find suitable display surface offset due to
> > CCS\n");
> > +			return -EINVAL;
> > +		}
> > +	}
> > +
> >  	plane_state->color_plane[1].offset = offset;
> >  	plane_state->color_plane[1].x = x;
> >  	plane_state->color_plane[1].y = y;
> > @@ -3599,19 +3725,30 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state
> > *plane_state)
> >  	const struct drm_framebuffer *fb = plane_state->base.fb;
> >  	int src_x = plane_state->base.src.x1 >> 16;
> >  	int src_y = plane_state->base.src.y1 >> 16;
> > -	int hsub = fb->format->hsub;
> > -	int vsub = fb->format->vsub;
> > -	int x = src_x / hsub;
> > -	int y = src_y / vsub;
> >  	u32 offset;
> > +	int ccs;
> >  
> > -	intel_add_fb_offsets(&x, &y, plane_state, 1);
> > -	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
> >  
> > -	plane_state->color_plane[1].offset = offset;
> > -	plane_state->color_plane[1].x = x * hsub + src_x % hsub;
> > -	plane_state->color_plane[1].y = y * vsub + src_y % vsub;
> > +	for (ccs = fb->format->num_planes / 2; ccs < fb->format->num_planes; ccs++) {
> > +		int hsub, vsub;
> > +		int main_hsub, main_vsub;
> > +		int x, y;
> > +
> > +		intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs);
> > +		intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, (ccs - 1)/ 2);
> > +
> > +		hsub /= main_hsub;
> > +		vsub /= main_vsub;
> > +		x = src_x / hsub;
> > +		y = src_y / vsub;
> >  
> > +		intel_add_fb_offsets(&x, &y, plane_state, ccs);
> > +		offset = intel_plane_compute_aligned_offset(&x, &y,
> > +							    plane_state, ccs);
> > +		plane_state->color_plane[ccs].offset = offset;
> > +		plane_state->color_plane[ccs].x = x * hsub + src_x % hsub;
> > +		plane_state->color_plane[ccs].y = y * vsub + src_y % vsub;
> > +	}
> >  	return 0;
> >  }
> >  
> > @@ -3619,6 +3756,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
> >  {
> >  	const struct drm_framebuffer *fb = plane_state->base.fb;
> >  	int ret;
> > +	bool needs_aux = false;
> >  
> >  	ret = intel_plane_compute_gtt(plane_state);
> >  	if (ret)
> > @@ -3628,21 +3766,31 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
> >  		return 0;
> >  
> >  	/*
> > -	 * Handle the AUX surface first since
> > -	 * the main surface setup depends on it.
> > +	 * Handle the AUX surface first since the main surface setup depends on
> > +	 * it.
> >  	 */
> > -	if (drm_format_info_is_yuv_semiplanar(fb->format)) {
> > -		ret = skl_check_nv12_aux_surface(plane_state);
> > +	if (is_ccs_modifier(fb->modifier)) {
> > +		needs_aux = true;
> > +		ret = skl_check_ccs_aux_surface(plane_state);
> >  		if (ret)
> >  			return ret;
> > -	} else if (is_ccs_modifier(fb->modifier)) {
> > -		ret = skl_check_ccs_aux_surface(plane_state);
> > +	}
> > +
> > +	if (drm_format_info_is_yuv_semiplanar(fb->format)) {
> > +		needs_aux = true;
> > +		ret = skl_check_nv12_aux_surface(plane_state);
> >  		if (ret)
> >  			return ret;
> > -	} else {
> > -		plane_state->color_plane[1].offset = ~0xfff;
> > -		plane_state->color_plane[1].x = 0;
> > -		plane_state->color_plane[1].y = 0;
> > +	}
> > +
> > +	if (!needs_aux) {
> > +		int i;
> > +
> > +		for (i = 1; i < fb->format->num_planes; i++) {
> > +			plane_state->color_plane[i].offset = ~0xfff;
> > +			plane_state->color_plane[i].x = 0;
> > +			plane_state->color_plane[i].y = 0;
> > +		}
> >  	}
> >  
> >  	ret = skl_check_main_surface(plane_state);
> > @@ -4030,7 +4178,7 @@ static unsigned int skl_plane_stride_mult(const struct drm_framebuffer
> > *fb,
> >  	 * The stride is either expressed as a multiple of 64 bytes chunks for
> >  	 * linear buffers or in number of tiles for tiled buffers.
> >  	 */
> > -	if (is_surface_linear(fb->modifier, color_plane))
> > +	if (is_surface_linear(fb, color_plane))
> >  		return 64;
> >  	else if (drm_rotation_90_or_270(rotation))
> >  		return intel_tile_height(fb, color_plane);
> > @@ -4160,6 +4308,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> >  		return PLANE_CTL_TILED_Y |
> >  		       PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> >  		       PLANE_CTL_CLEAR_COLOR_DISABLE;
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > +		return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
> >  	case I915_FORMAT_MOD_Yf_TILED:
> >  		return PLANE_CTL_TILED_YF;
> >  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> > @@ -9968,6 +10118,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
> >  			fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
> >  				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> >  				I915_FORMAT_MOD_Y_TILED_CCS;
> > +		else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
> > +			fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> >  		else
> >  			fb->modifier = I915_FORMAT_MOD_Y_TILED;
> >  		break;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 976669f01a8c..5998b959225c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -530,7 +530,7 @@ struct intel_plane_state {
> >  		 */
> >  		u32 stride;
> >  		int x, y;
> > -	} color_plane[2];
> > +	} color_plane[4];
> >  
> >  	/* plane control register */
> >  	u32 ctl;
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index 9b9b41b0fc91..788d0fc8d8ef 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -532,11 +532,13 @@ skl_program_plane(struct intel_plane *plane,
> >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> >  	enum plane_id plane_id = plane->id;
> >  	enum pipe pipe = plane->pipe;
> > +	const struct drm_framebuffer *fb = plane_state->base.fb;
> > +	int aux_plane = fb->format->num_planes / 2 + color_plane;
> >  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> >  	u32 surf_addr = plane_state->color_plane[color_plane].offset;
> >  	u32 stride = skl_plane_stride(plane_state, color_plane);
> > -	u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
> > -	u32 aux_stride = skl_plane_stride(plane_state, 1);
> > +	u32 aux_dist = plane_state->color_plane[aux_plane].offset - surf_addr;
> > +	u32 aux_stride = skl_plane_stride(plane_state, aux_plane);
> >  	int crtc_x = plane_state->base.dst.x1;
> >  	int crtc_y = plane_state->base.dst.y1;
> >  	u32 x = plane_state->color_plane[color_plane].x;
> > @@ -544,7 +546,6 @@ skl_program_plane(struct intel_plane *plane,
> >  	u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
> >  	u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
> >  	struct intel_plane *linked = plane_state->planar_linked_plane;
> > -	const struct drm_framebuffer *fb = plane_state->base.fb;
> >  	u8 alpha = plane_state->base.alpha >> 8;
> >  	u32 plane_color_ctl = 0;
> >  	unsigned long irqflags;
> > @@ -619,8 +620,8 @@ skl_program_plane(struct intel_plane *plane,
> >  
> >  	if (INTEL_GEN(dev_priv) < 11)
> >  		I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
> > -			      (plane_state->color_plane[1].y << 16) |
> > -			      plane_state->color_plane[1].x);
> > +			      (plane_state->color_plane[aux_plane].y << 16) |
> > +			      plane_state->color_plane[aux_plane].x);
> >  
> >  	/*
> >  	 * The control register self-arms if the plane was previously
> > @@ -1737,7 +1738,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> >  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
> >  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> >  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> > -	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
> > +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > +	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
> >  		DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
> >  		return -EINVAL;
> >  	}
> > @@ -2149,7 +2151,16 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
> >  	DRM_FORMAT_MOD_INVALID
> >  };
> >  
> > -static const u64 gen12_plane_format_modifiers_ccs[] = {
> > +static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
> > +	I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > +	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > +	I915_FORMAT_MOD_Y_TILED,
> > +	I915_FORMAT_MOD_X_TILED,
> > +	DRM_FORMAT_MOD_LINEAR,
> > +	DRM_FORMAT_MOD_INVALID
> > +};
> > +
> > +static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
> >  	I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> >  	I915_FORMAT_MOD_Y_TILED,
> >  	I915_FORMAT_MOD_X_TILED,
> > @@ -2305,10 +2316,21 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> >  	}
> >  }
> >  
> > +static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id)
> > +{
> > +	return plane_id < PLANE_SPRITE4;
> > +}
> > +
> >  static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> >  					     u32 format, u64 modifier)
> >  {
> > +	struct intel_plane *plane = to_intel_plane(_plane);
> > +
> >  	switch (modifier) {
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > +		if (!gen12_plane_supports_mc_ccs(plane->id))
> > +			return false;
> > +		/* fall through */
> >  	case DRM_FORMAT_MOD_LINEAR:
> >  	case I915_FORMAT_MOD_X_TILED:
> >  	case I915_FORMAT_MOD_Y_TILED:
> > @@ -2326,14 +2348,17 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> >  		if (is_ccs_modifier(modifier))
> >  			return true;
> >  		/* fall through */
> > -	case DRM_FORMAT_RGB565:
> > -	case DRM_FORMAT_XRGB2101010:
> > -	case DRM_FORMAT_XBGR2101010:
> >  	case DRM_FORMAT_YUYV:
> >  	case DRM_FORMAT_YVYU:
> >  	case DRM_FORMAT_UYVY:
> >  	case DRM_FORMAT_VYUY:
> > +		if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
> > +			return true;
> > +		/* fall through */
> >  	case DRM_FORMAT_NV12:
> > +	case DRM_FORMAT_RGB565:
> > +	case DRM_FORMAT_XRGB2101010:
> > +	case DRM_FORMAT_XBGR2101010:
> >  	case DRM_FORMAT_P010:
> >  	case DRM_FORMAT_P012:
> >  	case DRM_FORMAT_P016:
> > @@ -2470,6 +2495,14 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private
> > *dev_priv,
> >  	}
> >  }
> >  
> > +static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id)
> > +{
> > +	if (gen12_plane_supports_mc_ccs(plane_id))
> > +		return gen12_plane_format_modifiers_mc_ccs;
> > +	else
> > +		return gen12_plane_format_modifiers_rc_ccs;
> > +}
> > +
> >  static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
> >  			      enum pipe pipe, enum plane_id plane_id)
> >  {
> > @@ -2536,7 +2569,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> >  
> >  	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
> >  	if (INTEL_GEN(dev_priv) >= 12) {
> > -		modifiers = gen12_plane_format_modifiers_ccs;
> > +		modifiers = gen12_get_plane_modifiers(plane_id);
> >  		plane_funcs = &gen12_plane_funcs;
> >  	} else {
> >  		if (plane->has_ccs)
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 519cfb0a5c42..02eaef8adac0 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6697,6 +6697,7 @@ enum {
> >  #define   PLANE_CTL_TILED_Y			(4 << 10)
> >  #define   PLANE_CTL_TILED_YF			(5 << 10)
> >  #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
> > +#define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
> >  #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
> >  #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
> >  #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(2 << 4)
> > -- 
> > 2.17.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 

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✗ Fi.CI.CHECKPATCH: warning for Gen12 E2E compression

[Patchwork]

== Series Details ==

Series: Gen12 E2E compression
URL   : https://patchwork.freedesktop.org/series/67078/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b66ba0b6ed71 drm/framebuffer: Format modifier for Intel Gen-12 render compression
3d964432ccb8 drm/i915: Use intel_tile_height() instead of re-implementing
162c293caa32 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
684bed694380 drm/i915/tgl: Gen-12 render decompression
8c40f9ea2959 drm/i915: Extract framebufer CCS offset checks into a function
-:46: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line
#46: FILE: drivers/gpu/drm/i915/display/intel_display.c:2706:
+	/*
+	* CCS doesn't have its own x/y offset register, so the intra CCS tile

total: 0 errors, 1 warnings, 0 checks, 81 lines checked
be91a93ca86b drm/framebuffer: Format modifier for Intel Gen-12 media compression
7c44c2214c99 drm/i915: Skip rotated offset adjustment for unsupported modifiers
b518c6edfa29 drm/fb: Extend format_info member arrays to handle four planes
1a2bdfbf6347 Gen-12 display can decompress surfaces compressed by the media engine.
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#13: 
compressed buffers. Unlike render decompression, plane 6 and  plane 7 do not

-:113: WARNING:LONG_LINE: line over 100 characters
#113: FILE: drivers/gpu/drm/i915/display/intel_display.c:2704:
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)

-:120: WARNING:LONG_LINE: line over 100 characters
#120: FILE: drivers/gpu/drm/i915/display/intel_display.c:2711:
+		} mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2, 16}, .vsub = {1, 32, 2, 32}};

-:120: ERROR:SPACING: space required after that close brace '}'
#120: FILE: drivers/gpu/drm/i915/display/intel_display.c:2711:
+		} mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2, 16}, .vsub = {1, 32, 2, 32}};

-:136: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#136: FILE: drivers/gpu/drm/i915/display/intel_display.c:2727:
+	*w = fb->width/hsub;
 	              ^

-:137: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#137: FILE: drivers/gpu/drm/i915/display/intel_display.c:2728:
+	*h = fb->height/vsub;
 	               ^

-:324: CHECK:LINE_SPACING: Please don't use multiple blank lines
#324: FILE: drivers/gpu/drm/i915/display/intel_display.c:3663:
+
+

-:334: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#334: FILE: drivers/gpu/drm/i915/display/intel_display.c:3673:
+
+		}

total: 1 errors, 3 warnings, 4 checks, 511 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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✗ Fi.CI.BAT: failure for Gen12 E2E compression

[Patchwork]

== Series Details ==

Series: Gen12 E2E compression
URL   : https://patchwork.freedesktop.org/series/67078/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6939 -> Patchwork_14496
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_14496 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14496, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14496:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_addfb_basic@bo-too-small-due-to-tiling:
    - fi-kbl-x1275:       [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-kbl-x1275/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-kbl-x1275/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-apl-guc:         [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-apl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-apl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bsw-kefka:       [PASS][5] -> [FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-bsw-kefka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-bsw-kefka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bdw-5557u:       [PASS][7] -> [FAIL][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-bdw-5557u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-bdw-5557u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bwr-2160:        [PASS][9] -> [FAIL][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-bwr-2160/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-bwr-2160/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6770hq:      [PASS][11] -> [FAIL][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-skl-6770hq/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-skl-6770hq/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6600u:       [PASS][13] -> [FAIL][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-skl-6600u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-skl-6600u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-guc:         [PASS][15] -> [FAIL][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-kbl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-kbl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-8809g:       [PASS][17] -> [FAIL][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-kbl-8809g/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-kbl-8809g/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-lmem:        [PASS][19] -> [FAIL][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-skl-lmem/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-skl-lmem/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-r:           [PASS][21] -> [FAIL][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-kbl-r/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-kbl-r/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6260u:       [PASS][23] -> [FAIL][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-skl-6260u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-skl-6260u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-byt-n2820:       [PASS][25] -> [FAIL][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-byt-n2820/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-byt-n2820/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-snb-2600:        [PASS][27] -> [FAIL][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-snb-2600/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-snb-2600/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-ilk-650:         [PASS][29] -> [FAIL][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-ilk-650/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-ilk-650/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-elk-e7500:       [PASS][31] -> [FAIL][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-elk-e7500/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-elk-e7500/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bdw-gvtdvm:      [PASS][33] -> [FAIL][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-bdw-gvtdvm/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-bdw-gvtdvm/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-hsw-peppy:       [PASS][35] -> [FAIL][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-hsw-peppy/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-hsw-peppy/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-icl-u2:          [PASS][37] -> [FAIL][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-icl-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-icl-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-glk-dsi:         [PASS][39] -> [FAIL][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-glk-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-glk-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-snb-2520m:       [PASS][41] -> [FAIL][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-snb-2520m/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-snb-2520m/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-pnv-d510:        [PASS][43] -> [FAIL][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-pnv-d510/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-pnv-d510/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cfl-8109u:       [PASS][45] -> [FAIL][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-cfl-8109u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-cfl-8109u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-7500u:       [PASS][47] -> [FAIL][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-kbl-7500u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-kbl-7500u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-gdg-551:         [PASS][49] -> [FAIL][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-gdg-551/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-gdg-551/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cml-u2:          [PASS][51] -> [FAIL][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-cml-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-cml-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bxt-dsi:         [PASS][53] -> [FAIL][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-bxt-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-bxt-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-byt-j1900:       [PASS][55] -> [FAIL][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-byt-j1900/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-byt-j1900/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-hsw-4770:        [PASS][57] -> [FAIL][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-hsw-4770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-hsw-4770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cfl-guc:         [PASS][59] -> [FAIL][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-cfl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-cfl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-whl-u:           [PASS][61] -> [FAIL][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-whl-u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-whl-u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-icl-u3:          [PASS][63] -> [FAIL][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-icl-u3/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-icl-u3/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-guc:         [PASS][65] -> [FAIL][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-skl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-skl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bsw-n3050:       [PASS][67] -> [FAIL][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-bsw-n3050/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-bsw-n3050/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-ivb-3770:        [PASS][69] -> [FAIL][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-ivb-3770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-ivb-3770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-iommu:       [PASS][71] -> [FAIL][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-skl-iommu/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-skl-iommu/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cfl-8700k:       [PASS][73] -> [FAIL][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-cfl-8700k/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-cfl-8700k/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6700k2:      [PASS][75] -> [FAIL][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-skl-6700k2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-skl-6700k2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_addfb_basic@bo-too-small-due-to-tiling:
    - {fi-icl-u4}:        [PASS][77] -> [FAIL][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-icl-u4/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-icl-u4/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-icl-dsi}:       [PASS][79] -> [FAIL][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-icl-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-icl-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-tgl-u}:         [PASS][81] -> [FAIL][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-tgl-u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-tgl-u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-tgl-u2}:        [PASS][83] -> [FAIL][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-tgl-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-tgl-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-cml-h}:         [PASS][85] -> [FAIL][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-cml-h/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-cml-h/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-kbl-soraka}:    [PASS][87] -> [FAIL][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-kbl-soraka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-kbl-soraka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-icl-guc}:       NOTRUN -> [FAIL][89]
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-icl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-cml-s}:         [PASS][90] -> [FAIL][91]
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-cml-s/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-cml-s/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html

  
Known issues
------------

  Here are the changes found in Patchwork_14496 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       [PASS][92] -> [INCOMPLETE][93] ([fdo#107718])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
    - fi-icl-u3:          [PASS][94] -> [DMESG-WARN][95] ([fdo#107724]) +2 similar issues
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html

  
#### Possible fixes ####

  * igt@gem_exec_reloc@basic-write-read:
    - fi-icl-u3:          [DMESG-WARN][96] ([fdo#107724]) -> [PASS][97] +2 similar issues
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-icl-u3/igt@gem_exec_reloc@basic-write-read.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-icl-u3/igt@gem_exec_reloc@basic-write-read.html

  * igt@kms_busy@basic-flip-a:
    - fi-cml-u2:          [DMESG-WARN][98] ([fdo#105763]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-cml-u2/igt@kms_busy@basic-flip-a.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-cml-u2/igt@kms_busy@basic-flip-a.html

  * igt@kms_chamelium@dp-edid-read:
    - {fi-icl-u4}:        [FAIL][100] ([fdo#111045]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-icl-u4/igt@kms_chamelium@dp-edid-read.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-icl-u4/igt@kms_chamelium@dp-edid-read.html

  
#### Warnings ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][102] ([fdo#111045] / [fdo#111096]) -> [FAIL][103] ([fdo#111407])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6939/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407


Participating hosts (54 -> 47)
------------------------------

  Additional (1): fi-icl-guc 
  Missing    (8): fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6939 -> Patchwork_14496

  CI-20190529: 20190529
  CI_DRM_6939: f839fe27dcaf8e4e0716c0b83a9481df3a1de27e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5196: 98783313b8b3097680df69007a9551c6248ab209 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14496: 1a2bdfbf6347122ca765f351932a4de0ef66458f @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

1a2bdfbf6347 Gen-12 display can decompress surfaces compressed by the media engine.
b518c6edfa29 drm/fb: Extend format_info member arrays to handle four planes
7c44c2214c99 drm/i915: Skip rotated offset adjustment for unsupported modifiers
be91a93ca86b drm/framebuffer: Format modifier for Intel Gen-12 media compression
8c40f9ea2959 drm/i915: Extract framebufer CCS offset checks into a function
684bed694380 drm/i915/tgl: Gen-12 render decompression
162c293caa32 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
3d964432ccb8 drm/i915: Use intel_tile_height() instead of re-implementing
b66ba0b6ed71 drm/framebuffer: Format modifier for Intel Gen-12 render compression

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14496/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for Gen12 E2E compression (rev2)

[Patchwork]

== Series Details ==

Series: Gen12 E2E compression (rev2)
URL   : https://patchwork.freedesktop.org/series/67078/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b4a0858736dc drm/framebuffer: Format modifier for Intel Gen-12 render compression
97529f698ecd drm/i915: Use intel_tile_height() instead of re-implementing
e0aac1d19bd8 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
32db1b3e4687 drm/i915/tgl: Gen-12 render decompression
f9b5443feb41 drm/i915: Extract framebufer CCS offset checks into a function
-:46: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line
#46: FILE: drivers/gpu/drm/i915/display/intel_display.c:2706:
+	/*
+	* CCS doesn't have its own x/y offset register, so the intra CCS tile

total: 0 errors, 1 warnings, 0 checks, 81 lines checked
3815b3cf3f91 drm/framebuffer: Format modifier for Intel Gen-12 media compression
70f5e38938bb drm/i915: Skip rotated offset adjustment for unsupported modifiers
1a74294adf44 drm/fb: Extend format_info member arrays to handle four planes
cd165d81961a Gen-12 display can decompress surfaces compressed by the media engine.
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#13: 
compressed buffers. Unlike render decompression, plane 6 and  plane 7 do not

-:230: WARNING:LONG_LINE: line over 100 characters
#230: FILE: drivers/gpu/drm/i915/display/intel_display.c:2723:
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)

-:264: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_display.c:2757:
+	*w = fb->width/hsub;
 	              ^

-:265: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#265: FILE: drivers/gpu/drm/i915/display/intel_display.c:2758:
+	*h = fb->height/vsub;
 	               ^

-:415: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#415: FILE: drivers/gpu/drm/i915/display/intel_display.c:3627:
 	if (is_ccs_modifier(fb->modifier)) {
+

-:443: CHECK:LINE_SPACING: Please don't use multiple blank lines
#443: FILE: drivers/gpu/drm/i915/display/intel_display.c:3689:
+
+

-:453: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#453: FILE: drivers/gpu/drm/i915/display/intel_display.c:3699:
+
+		}

-:496: CHECK:SPACING: spaces preferred around that '/' (ctx:VxW)
#496: FILE: drivers/gpu/drm/i915/display/intel_display.c:3738:
+		intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, (ccs - 1)/ 2);
 		                                                                    ^

total: 0 errors, 2 warnings, 6 checks, 659 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.BAT: failure for Gen12 E2E compression (rev2)

[Patchwork]

== Series Details ==

Series: Gen12 E2E compression (rev2)
URL   : https://patchwork.freedesktop.org/series/67078/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14551
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_14551 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14551, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14551:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_addfb_basic@bo-too-small-due-to-tiling:
    - fi-blb-e6850:       [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-blb-e6850/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-blb-e6850/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-x1275:       [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-kbl-x1275/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-kbl-x1275/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-apl-guc:         [PASS][5] -> [FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-apl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-apl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bsw-kefka:       [PASS][7] -> [FAIL][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-bsw-kefka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-bsw-kefka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bdw-5557u:       [PASS][9] -> [FAIL][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-bdw-5557u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-bdw-5557u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bwr-2160:        [PASS][11] -> [FAIL][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-bwr-2160/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-bwr-2160/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6770hq:      [PASS][13] -> [FAIL][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-skl-6770hq/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-skl-6770hq/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6600u:       [PASS][15] -> [FAIL][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-skl-6600u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-skl-6600u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-guc:         [PASS][17] -> [FAIL][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-kbl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-kbl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-8809g:       [PASS][19] -> [FAIL][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-kbl-8809g/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-kbl-8809g/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-lmem:        [PASS][21] -> [FAIL][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-skl-lmem/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-skl-lmem/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-r:           [PASS][23] -> [FAIL][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-kbl-r/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-kbl-r/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6260u:       [PASS][25] -> [FAIL][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-skl-6260u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-skl-6260u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-byt-n2820:       [PASS][27] -> [FAIL][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-byt-n2820/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-byt-n2820/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-snb-2600:        [PASS][29] -> [FAIL][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-snb-2600/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-snb-2600/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-ilk-650:         [PASS][31] -> [FAIL][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-ilk-650/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-ilk-650/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-elk-e7500:       [PASS][33] -> [FAIL][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-elk-e7500/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-elk-e7500/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bdw-gvtdvm:      [PASS][35] -> [FAIL][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-bdw-gvtdvm/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-bdw-gvtdvm/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-hsw-peppy:       [PASS][37] -> [FAIL][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-hsw-peppy/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-hsw-peppy/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-icl-u2:          [PASS][39] -> [FAIL][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-icl-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-icl-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-glk-dsi:         [PASS][41] -> [FAIL][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-glk-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-glk-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-snb-2520m:       [PASS][43] -> [FAIL][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-snb-2520m/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-snb-2520m/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-pnv-d510:        [PASS][45] -> [FAIL][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-pnv-d510/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-pnv-d510/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cfl-8109u:       [PASS][47] -> [FAIL][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-cfl-8109u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-cfl-8109u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-7500u:       [PASS][49] -> [FAIL][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-kbl-7500u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-kbl-7500u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-gdg-551:         [PASS][51] -> [FAIL][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-gdg-551/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-gdg-551/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bxt-dsi:         [PASS][53] -> [FAIL][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-bxt-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-bxt-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-byt-j1900:       [PASS][55] -> [FAIL][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-byt-j1900/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-byt-j1900/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-hsw-4770:        [PASS][57] -> [FAIL][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-hsw-4770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-hsw-4770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cfl-guc:         [PASS][59] -> [FAIL][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-cfl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-cfl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-whl-u:           [PASS][61] -> [FAIL][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-whl-u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-whl-u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-guc:         [PASS][63] -> [FAIL][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-skl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-skl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bsw-n3050:       [PASS][65] -> [FAIL][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-bsw-n3050/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-bsw-n3050/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-ivb-3770:        [PASS][67] -> [FAIL][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-ivb-3770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-ivb-3770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-iommu:       [PASS][69] -> [FAIL][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-skl-iommu/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-skl-iommu/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cfl-8700k:       [PASS][71] -> [FAIL][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-cfl-8700k/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-cfl-8700k/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6700k2:      [PASS][73] -> [FAIL][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-skl-6700k2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-skl-6700k2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live_hugepages:
    - {fi-tgl-u2}:        NOTRUN -> [INCOMPLETE][75]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-tgl-u2/igt@i915_selftest@live_hugepages.html

  * igt@kms_addfb_basic@bo-too-small-due-to-tiling:
    - {fi-icl-dsi}:       [PASS][76] -> [FAIL][77]
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-icl-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-icl-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-tgl-u2}:        [PASS][78] -> [FAIL][79]
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-tgl-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-tgl-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-kbl-soraka}:    NOTRUN -> [FAIL][80]
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-kbl-soraka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-icl-guc}:       [PASS][81] -> [FAIL][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-icl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-icl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html

  
Known issues
------------

  Here are the changes found in Patchwork_14551 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_reloc@basic-gtt-read-active:
    - fi-skl-6260u:       [PASS][83] -> [DMESG-WARN][84] ([fdo#105541])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-skl-6260u/igt@gem_exec_reloc@basic-gtt-read-active.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-skl-6260u/igt@gem_exec_reloc@basic-gtt-read-active.html

  * igt@i915_selftest@live_hangcheck:
    - fi-icl-u2:          [PASS][85] -> [DMESG-FAIL][86] ([fdo#111678])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-icl-u2/igt@i915_selftest@live_hangcheck.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       [PASS][87] -> [DMESG-WARN][88] ([fdo#102614])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
    - fi-icl-u2:          [PASS][89] -> [FAIL][90] ([fdo#103167])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html

  
#### Possible fixes ####

  * igt@i915_selftest@live_gtt:
    - {fi-tgl-u2}:        [INCOMPLETE][91] -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-tgl-u2/igt@i915_selftest@live_gtt.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-tgl-u2/igt@i915_selftest@live_gtt.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-icl-u2:          [FAIL][93] ([fdo#109483]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
    - fi-kbl-7500u:       [FAIL][95] ([fdo#111045] / [fdo#111096]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678
  [fdo#111699]: https://bugs.freedesktop.org/show_bug.cgi?id=111699


Participating hosts (50 -> 41)
------------------------------

  Additional (1): fi-kbl-soraka 
  Missing    (10): fi-cml-u2 fi-icl-u4 fi-ilk-m540 fi-cml-s fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6963 -> Patchwork_14551

  CI-20190529: 20190529
  CI_DRM_6963: 364bf33c246115063174fa2a07e9f5a6bddc9f72 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5203: 82326332f7af336d390e00ae87187bc207fd33dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14551: cd165d81961a1ae2adc157f58100754743337d0f @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

cd165d81961a Gen-12 display can decompress surfaces compressed by the media engine.
1a74294adf44 drm/fb: Extend format_info member arrays to handle four planes
70f5e38938bb drm/i915: Skip rotated offset adjustment for unsupported modifiers
3815b3cf3f91 drm/framebuffer: Format modifier for Intel Gen-12 media compression
f9b5443feb41 drm/i915: Extract framebufer CCS offset checks into a function
32db1b3e4687 drm/i915/tgl: Gen-12 render decompression
e0aac1d19bd8 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
97529f698ecd drm/i915: Use intel_tile_height() instead of re-implementing
b4a0858736dc drm/framebuffer: Format modifier for Intel Gen-12 render compression

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14551/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for Gen12 E2E compression (rev3)

[Patchwork]

== Series Details ==

Series: Gen12 E2E compression (rev3)
URL   : https://patchwork.freedesktop.org/series/67078/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
a2306a44f000 drm/framebuffer: Format modifier for Intel Gen-12 render compression
7fceadb0dd8f drm/i915: Use intel_tile_height() instead of re-implementing
c5ab08ba0ad9 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
50577506a5d2 drm/i915/tgl: Gen-12 render decompression
5e136b5b4a25 drm/i915: Extract framebufer CCS offset checks into a function
-:48: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line
#48: FILE: drivers/gpu/drm/i915/display/intel_display.c:2703:
+	/*
+	* CCS doesn't have its own x/y offset register, so the intra CCS tile

total: 0 errors, 1 warnings, 0 checks, 81 lines checked
eeb4a92dd984 drm/framebuffer: Format modifier for Intel Gen-12 media compression
6049b78b30bd drm/i915: Skip rotated offset adjustment for unsupported modifiers
7ccb87c9160b drm/fb: Extend format_info member arrays to handle four planes
cf0459685876 Gen-12 display can decompress surfaces compressed by the media engine.
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#13: 
compressed buffers. Unlike render decompression, plane 6 and  plane 7 do not

-:230: WARNING:LONG_LINE: line over 100 characters
#230: FILE: drivers/gpu/drm/i915/display/intel_display.c:2720:
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)

-:264: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_display.c:2754:
+	*w = fb->width/hsub;
 	              ^

-:265: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#265: FILE: drivers/gpu/drm/i915/display/intel_display.c:2755:
+	*h = fb->height/vsub;
 	               ^

-:415: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#415: FILE: drivers/gpu/drm/i915/display/intel_display.c:3620:
 	if (is_ccs_modifier(fb->modifier)) {
+

-:443: CHECK:LINE_SPACING: Please don't use multiple blank lines
#443: FILE: drivers/gpu/drm/i915/display/intel_display.c:3682:
+
+

-:453: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#453: FILE: drivers/gpu/drm/i915/display/intel_display.c:3692:
+
+		}

-:496: CHECK:SPACING: spaces preferred around that '/' (ctx:VxW)
#496: FILE: drivers/gpu/drm/i915/display/intel_display.c:3731:
+		intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, (ccs - 1)/ 2);
 		                                                                    ^

total: 0 errors, 2 warnings, 6 checks, 659 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.BAT: failure for Gen12 E2E compression (rev3)

[Patchwork]

== Series Details ==

Series: Gen12 E2E compression (rev3)
URL   : https://patchwork.freedesktop.org/series/67078/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7049 -> Patchwork_14744
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_14744 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14744, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14744:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_addfb_basic@bo-too-small-due-to-tiling:
    - fi-kbl-x1275:       [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-kbl-x1275/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-kbl-x1275/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-apl-guc:         [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-apl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-apl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bsw-kefka:       [PASS][5] -> [FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-bsw-kefka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-bsw-kefka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bdw-5557u:       [PASS][7] -> [FAIL][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-bdw-5557u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-bdw-5557u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bwr-2160:        [PASS][9] -> [FAIL][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-bwr-2160/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-bwr-2160/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6770hq:      [PASS][11] -> [FAIL][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-skl-6770hq/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-skl-6770hq/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6600u:       [PASS][13] -> [FAIL][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-skl-6600u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-skl-6600u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-guc:         [PASS][15] -> [FAIL][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-kbl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-kbl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-8809g:       [PASS][17] -> [FAIL][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-kbl-8809g/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-kbl-8809g/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-lmem:        [PASS][19] -> [FAIL][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-skl-lmem/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-skl-lmem/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-r:           [PASS][21] -> [FAIL][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-kbl-r/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-kbl-r/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-6260u:       [PASS][23] -> [FAIL][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-skl-6260u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-skl-6260u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-byt-n2820:       [PASS][25] -> [FAIL][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-byt-n2820/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-byt-n2820/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-snb-2600:        [PASS][27] -> [FAIL][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-snb-2600/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-snb-2600/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-ilk-650:         [PASS][29] -> [FAIL][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-ilk-650/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-ilk-650/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-elk-e7500:       [PASS][31] -> [FAIL][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-elk-e7500/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-elk-e7500/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-hsw-peppy:       [PASS][33] -> [FAIL][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-hsw-peppy/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-hsw-peppy/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-icl-u2:          [PASS][35] -> [FAIL][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-icl-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-icl-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-glk-dsi:         [PASS][37] -> [FAIL][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-glk-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-glk-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-snb-2520m:       [PASS][39] -> [FAIL][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-snb-2520m/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-snb-2520m/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-pnv-d510:        [PASS][41] -> [FAIL][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-pnv-d510/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-pnv-d510/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cfl-8109u:       [PASS][43] -> [FAIL][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-cfl-8109u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-cfl-8109u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-kbl-7500u:       [PASS][45] -> [FAIL][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-kbl-7500u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-kbl-7500u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-gdg-551:         [PASS][47] -> [FAIL][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-gdg-551/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-gdg-551/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cml-u2:          [PASS][49] -> [FAIL][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-cml-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-cml-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bxt-dsi:         [PASS][51] -> [FAIL][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-bxt-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-bxt-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-byt-j1900:       [PASS][53] -> [FAIL][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-byt-j1900/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-byt-j1900/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-hsw-4770:        [PASS][55] -> [FAIL][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-hsw-4770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-hsw-4770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cfl-guc:         [PASS][57] -> [FAIL][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-cfl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-cfl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-whl-u:           [PASS][59] -> [FAIL][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-whl-u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-whl-u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-icl-u3:          [PASS][61] -> [FAIL][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-icl-u3/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-icl-u3/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-guc:         [PASS][63] -> [FAIL][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-skl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-skl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-bsw-n3050:       [PASS][65] -> [FAIL][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-bsw-n3050/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-bsw-n3050/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-ivb-3770:        [PASS][67] -> [FAIL][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-ivb-3770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-ivb-3770/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-skl-iommu:       [PASS][69] -> [FAIL][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-skl-iommu/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-skl-iommu/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-cfl-8700k:       [PASS][71] -> [FAIL][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-cfl-8700k/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-cfl-8700k/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - fi-hsw-4770r:       [PASS][73] -> [FAIL][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-hsw-4770r/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-hsw-4770r/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_addfb_basic@bo-too-small-due-to-tiling:
    - {fi-icl-u4}:        [PASS][75] -> [FAIL][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-icl-u4/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-icl-u4/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-icl-dsi}:       [PASS][77] -> [FAIL][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-icl-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-icl-dsi/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-tgl-u}:         [PASS][79] -> [FAIL][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-tgl-u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-tgl-u/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-tgl-u2}:        [PASS][81] -> [FAIL][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-tgl-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-tgl-u2/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-kbl-soraka}:    [PASS][83] -> [FAIL][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-kbl-soraka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-kbl-soraka/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-icl-guc}:       [PASS][85] -> [FAIL][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-icl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-icl-guc/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
    - {fi-cml-s}:         [PASS][87] -> [FAIL][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-cml-s/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-cml-s/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html

  
Known issues
------------

  Here are the changes found in Patchwork_14744 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       [PASS][89] -> [INCOMPLETE][90] ([fdo#107718])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_mmap_gtt@basic-read-write-distinct:
    - fi-icl-u3:          [PASS][91] -> [DMESG-WARN][92] ([fdo#107724]) +1 similar issue
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@basic-copy:
    - fi-icl-u3:          [DMESG-WARN][93] ([fdo#107724]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-icl-u3/igt@gem_mmap_gtt@basic-copy.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-icl-u3/igt@gem_mmap_gtt@basic-copy.html

  * igt@i915_selftest@live_execlists:
    - fi-icl-u3:          [INCOMPLETE][95] ([fdo#107713]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-icl-u3/igt@i915_selftest@live_execlists.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-icl-u3/igt@i915_selftest@live_execlists.html

  * igt@i915_selftest@live_hangcheck:
    - {fi-tgl-u}:         [INCOMPLETE][97] ([fdo#111747]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-tgl-u/igt@i915_selftest@live_hangcheck.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-tgl-u/igt@i915_selftest@live_hangcheck.html

  * igt@kms_chamelium@dp-crc-fast:
    - {fi-icl-u4}:        [FAIL][99] ([fdo#111045]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-icl-u4/igt@kms_chamelium@dp-crc-fast.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-icl-u4/igt@kms_chamelium@dp-crc-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#111831]: https://bugs.freedesktop.org/show_bug.cgi?id=111831


Participating hosts (53 -> 47)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7049 -> Patchwork_14744

  CI-20190529: 20190529
  CI_DRM_7049: e3f56bf12848ea0ee9fee0114a3682bbe2278e34 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14744: cf04596858765a1d21ebcb6520ef8989b1292e70 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

cf0459685876 Gen-12 display can decompress surfaces compressed by the media engine.
7ccb87c9160b drm/fb: Extend format_info member arrays to handle four planes
6049b78b30bd drm/i915: Skip rotated offset adjustment for unsupported modifiers
eeb4a92dd984 drm/framebuffer: Format modifier for Intel Gen-12 media compression
5e136b5b4a25 drm/i915: Extract framebufer CCS offset checks into a function
50577506a5d2 drm/i915/tgl: Gen-12 render decompression
c5ab08ba0ad9 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
7fceadb0dd8f drm/i915: Use intel_tile_height() instead of re-implementing
a2306a44f000 drm/framebuffer: Format modifier for Intel Gen-12 render compression

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/index.html
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