Re: [PATCH v2 11/22] drm/xe/nvl: Define NVL-S platform

[Gustavo Sousa <gustavo.sousa@intel.com>]

Quoting Lucas De Marchi (2025-10-15 19:06:26-03:00)
>From: Matt Roper <matthew.d.roper@intel.com>
>
>Provide the basic platform definitions and PCI IDs for NVL-S.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>---
> drivers/gpu/drm/xe/xe_pci.c            | 9 +++++++++
> drivers/gpu/drm/xe/xe_platform_types.h | 1 +
> include/drm/intel/pciids.h             | 9 +++++++++
> 3 files changed, 19 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index b72f71b0f52c9..d836fd8e187a6 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -377,6 +377,14 @@ static const struct xe_device_desc ptl_desc = {
>         .vm_max_level = 4,
> };
> 
>+static const struct xe_device_desc nvls_desc = {
>+        PLATFORM(NOVALAKE_S),
>+        .dma_mask_size = 46,
>+        .has_display = true,
>+        .max_gt_per_tile = 2,
>+        .require_force_probe = true,

With the recent merge of [1], we now need to define some extra
attributes here.  I believe we need to define: va_bits, vm_max_level,
has_flat_ccs.

[1] https://lore.kernel.org/all/20251013200944.2499947-25-matthew.d.roper@intel.com/T/

--
Gustavo Sousa

>+};
>+
> #undef PLATFORM
> __diag_pop();
> 
>@@ -405,6 +413,7 @@ static const struct pci_device_id pciidlist[] = {
>         INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
>         INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
>         INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
>+        INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
>         { }
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
>diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
>index 3e332214c7bb4..78286285c2495 100644
>--- a/drivers/gpu/drm/xe/xe_platform_types.h
>+++ b/drivers/gpu/drm/xe/xe_platform_types.h
>@@ -24,6 +24,7 @@ enum xe_platform {
>         XE_LUNARLAKE,
>         XE_BATTLEMAGE,
>         XE_PANTHERLAKE,
>+        XE_NOVALAKE_S,
> };
> 
> enum xe_subplatform {
>diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
>index 452c1de606ff2..13c592e1a28c7 100644
>--- a/include/drm/intel/pciids.h
>+++ b/include/drm/intel/pciids.h
>@@ -887,4 +887,13 @@
>         MACRO__(0xFD80, ## __VA_ARGS__), \
>         MACRO__(0xFD81, ## __VA_ARGS__)
> 
>+/* NVL-S */
>+#define INTEL_NVLS_IDS(MACRO__, ...) \
>+        MACRO__(0xD740, ## __VA_ARGS__), \
>+        MACRO__(0xD741, ## __VA_ARGS__), \
>+        MACRO__(0xD742, ## __VA_ARGS__), \
>+        MACRO__(0xD743, ## __VA_ARGS__), \
>+        MACRO__(0xD744, ## __VA_ARGS__), \
>+        MACRO__(0xD745, ## __VA_ARGS__)
>+
> #endif /* __PCIIDS_H__ */
>
>-- 
>2.51.0
>