From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>,
Shekhar Chauhan <shekhar.chauhan@intel.com>,
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>,
Matt Roper <matthew.d.roper@intel.com>,
Tejas Upadhyay <tejas.upadhyay@intel.com>,
Wang Xin <x.wang@intel.com>,
Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Subject: [PATCH v2 10/22] drm/xe/xe3p: Dump CSMQDEBUG register
Date: Wed, 15 Oct 2025 15:06:25 -0700 [thread overview]
Message-ID: <20251015-xe3p-v2-10-b9189b3056a2@intel.com> (raw)
In-Reply-To: <20251015-xe3p-v2-0-b9189b3056a2@intel.com>
From: Wang Xin <x.wang@intel.com>
The CSMQDEBUG is useful for the development of MQ feature. Start dumping
the debug register.
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Wang Xin <x.wang@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2:
- Extract CSMQDEBUG from other patch dumping multiple register (Matt
Roper)
- Simplify version check (Matt Roper)
- Do not dump CSMQDEBUG for engines that do not support MQ (Matt Roper)
---
drivers/gpu/drm/xe/regs/xe_engine_regs.h | 2 ++
drivers/gpu/drm/xe/xe_guc_capture.c | 48 +++++++++++++++++++++++++++++++-
2 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index 3c05d85902c69..7b6ec0cf78c85 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -156,6 +156,8 @@
#define GFX_DISABLE_LEGACY_MODE REG_BIT(3)
#define GFX_MSIX_INTERRUPT_ENABLE REG_BIT(13)
+#define RING_CSMQDEBUG(base) XE_REG((base) + 0x2b0)
+
#define RING_TIMESTAMP(base) XE_REG((base) + 0x358)
#define RING_TIMESTAMP_UDW(base) XE_REG((base) + 0x358 + 4)
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 8d1bfa2cdb151..035b9b6c0df58 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -150,6 +150,9 @@ struct __guc_capture_parsed_output {
{ SFC_DONE(2), 0, 0, 0, 0, "SFC_DONE[2]"}, \
{ SFC_DONE(3), 0, 0, 0, 0, "SFC_DONE[3]"}
+#define XE3P_BASE_ENGINE_INSTANCE \
+ { RING_CSMQDEBUG(0), REG_32BIT, 0, 0, 0, "CSMQDEBUG"}
+
/* XE_LP Global */
static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = {
COMMON_XELP_BASE_GLOBAL,
@@ -196,6 +199,32 @@ static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = {
COMMON_BASE_ENGINE_INSTANCE,
};
+/* Render / Compute Per-Engine-Instance */
+static const struct __guc_mmio_reg_descr xe3p_rc_inst_regs[] = {
+ COMMON_BASE_ENGINE_INSTANCE,
+ XE3P_BASE_ENGINE_INSTANCE,
+};
+
+/* Media Decode/Encode Per-Engine-Instance */
+static const struct __guc_mmio_reg_descr xe3p_vd_inst_regs[] = {
+ COMMON_BASE_ENGINE_INSTANCE,
+};
+
+/* Video Enhancement Per-Engine-Instance */
+static const struct __guc_mmio_reg_descr xe3p_vec_inst_regs[] = {
+ COMMON_BASE_ENGINE_INSTANCE,
+};
+
+/* Blitter Per-Engine-Instance */
+static const struct __guc_mmio_reg_descr xe3p_blt_inst_regs[] = {
+ COMMON_BASE_ENGINE_INSTANCE,
+};
+
+/* XE3P - GSC Per-Engine-Instance */
+static const struct __guc_mmio_reg_descr xe3p_gsc_inst_regs[] = {
+ COMMON_BASE_ENGINE_INSTANCE,
+};
+
/*
* Empty list to prevent warnings about unknown class/instance types
* as not all class/instance types have entries on all platforms.
@@ -246,6 +275,21 @@ static const struct __guc_mmio_reg_descr_group xe_hpg_lists[] = {
{}
};
+ /* List of lists for Xe3p and beyond */
+static const struct __guc_mmio_reg_descr_group xe3p_lists[] = {
+ MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0),
+ MAKE_REGLIST(xe_hpg_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
+ MAKE_REGLIST(xe3p_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
+ MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO),
+ MAKE_REGLIST(xe3p_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO),
+ MAKE_REGLIST(xe_vec_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
+ MAKE_REGLIST(xe3p_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
+ MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
+ MAKE_REGLIST(xe3p_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
+ MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
+ MAKE_REGLIST(xe3p_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
+ {}
+};
static const char * const capture_list_type_names[] = {
"Global",
"Class",
@@ -293,7 +337,9 @@ guc_capture_remove_stale_matches_from_list(struct xe_guc_state_capture *gc,
static const struct __guc_mmio_reg_descr_group *
guc_capture_get_device_reglist(struct xe_device *xe)
{
- if (GRAPHICS_VERx100(xe) >= 1255)
+ if (GRAPHICS_VER(xe) >= 35)
+ return xe3p_lists;
+ else if (GRAPHICS_VERx100(xe) >= 1255)
return xe_hpg_lists;
else
return xe_lp_lists;
--
2.51.0
next prev parent reply other threads:[~2025-10-15 22:07 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-15 22:06 [PATCH v2 00/22] drm/xe: Add Xe3p support Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 01/22] drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05 Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 02/22] drm/xe/xe3p_lpm: Add support for media IP versions 35.00 & 35.03 Lucas De Marchi
2025-10-16 16:12 ` Gustavo Sousa
2025-10-16 16:46 ` Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 03/22] drm/xe: Drop CTC_MODE register read Lucas De Marchi
2025-10-15 23:26 ` Matt Roper
2025-10-15 22:06 ` [PATCH v2 04/22] drm/xe: Add GT_VER() to check version specific to gt type Lucas De Marchi
2025-10-15 23:34 ` Matt Roper
2025-10-15 22:06 ` [PATCH v2 05/22] drm/xe/xe3p_lpm: Skip disabling NOA on unsupported IPs Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 06/22] drm/xe/xe3p_lpm: Handle MCR steering Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 07/22] drm/xe/xe3p: Stop programming RCU_MODE's fixed slice mode setting Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 08/22] drm/xe/xe3p: Determine service copy availability from fuse Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 09/22] drm/xe: Dump CURRENT_LRCA register Lucas De Marchi
2025-10-15 23:28 ` Matt Roper
2025-10-15 22:06 ` Lucas De Marchi [this message]
2025-10-15 23:33 ` [PATCH v2 10/22] drm/xe/xe3p: Dump CSMQDEBUG register Matt Roper
2025-10-15 22:06 ` [PATCH v2 11/22] drm/xe/nvl: Define NVL-S platform Lucas De Marchi
2025-10-16 16:41 ` Gustavo Sousa
2025-10-15 22:06 ` [PATCH v2 12/22] drm/xe/nvls: Define GuC firmware for NVL-S Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 13/22] drm/xe/nvls: Attach MOCS table " Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 14/22] drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 15/22] drm/xe/xe3p_xpc: Add L3 bank mask Lucas De Marchi
2025-10-15 23:29 ` Matt Roper
2025-10-15 22:06 ` [PATCH v2 16/22] drm/xe/xe3p_xpc: Add MCR steering Lucas De Marchi
2025-10-16 11:44 ` Gustavo Sousa
2025-10-16 19:48 ` Lucas De Marchi
2025-10-16 20:16 ` Gustavo Sousa
2025-10-15 22:06 ` [PATCH v2 17/22] drm/xe/irq: Rename fuse mask variables Lucas De Marchi
2025-10-15 23:39 ` Matt Roper
2025-10-15 22:06 ` [PATCH v2 18/22] drm/xe/irq: Split irq mask per engine class Lucas De Marchi
2025-10-15 23:52 ` Matt Roper
2025-10-16 4:38 ` Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 19/22] drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx Lucas De Marchi
2025-10-16 0:07 ` Matt Roper
2025-10-16 5:33 ` Lucas De Marchi
2025-10-16 6:52 ` Muqthyar Ahmed, Syed Abdul
2025-10-16 13:59 ` Lucas De Marchi
2025-10-17 6:52 ` Joonas Lahtinen
2025-10-15 22:06 ` [PATCH v2 20/22] drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs Lucas De Marchi
2025-10-16 12:30 ` Gustavo Sousa
2025-10-16 16:54 ` Matt Roper
2025-10-15 22:06 ` [PATCH v2 21/22] drm/xe/xe3p_xpc: Setup PAT table Lucas De Marchi
2025-10-16 14:30 ` Vivekanandan, Balasubramani
2025-10-16 20:22 ` Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 22/22] drm/xe/xe3p: Add xe3p EU stall data format Lucas De Marchi
2025-10-15 23:58 ` Dixit, Ashutosh
2025-10-16 3:25 ` Lucas De Marchi
2025-10-16 5:11 ` ✗ CI.checkpatch: warning for drm/xe: Add Xe3p support (rev2) Patchwork
2025-10-16 5:13 ` ✓ CI.KUnit: success " Patchwork
2025-10-16 5:55 ` ✗ Xe.CI.BAT: failure " Patchwork
2025-10-16 23:29 ` ✗ Xe.CI.Full: " Patchwork
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