From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>,
Shekhar Chauhan <shekhar.chauhan@intel.com>,
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>,
Matt Roper <matthew.d.roper@intel.com>,
Tejas Upadhyay <tejas.upadhyay@intel.com>,
Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>,
S A Muqthyar Ahmed <syed.abdul.muqthyar.ahmed@intel.com>
Subject: [PATCH v2 19/22] drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx
Date: Wed, 15 Oct 2025 15:06:34 -0700 [thread overview]
Message-ID: <20251015-xe3p-v2-19-b9189b3056a2@intel.com> (raw)
In-Reply-To: <20251015-xe3p-v2-0-b9189b3056a2@intel.com>
Current implementation of compute walker has dependency on GPU/SW Stack
which requires SW/UMD to wait for event from KMD to indicate
PIPE_CONTROL interrupt was done. This created latency on SW stack.
This feature adds support to generate completion interrupt from GPGPU
walker which does not support MSIx and avoid software using Pipe control
drain/idle latency.
Suggested-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: S A Muqthyar Ahmed <syed.abdul.muqthyar.ahmed@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2: Rebase on split mask per engine class
---
drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
drivers/gpu/drm/xe/xe_irq.c | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
index 7c2a3a1401424..9c46b5fb81412 100644
--- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
@@ -82,6 +82,7 @@
#define GSC_ER_COMPLETE REG_BIT(5)
#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT REG_BIT(4)
#define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
+#define GT_COMPUTE_WALKER_INTERRUPT REG_BIT(2)
#define GT_RENDER_USER_INTERRUPT REG_BIT(0)
/* irqs for OTHER_KCR_INSTANCE */
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 103804546b280..ac5524cbe4b9a 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -149,6 +149,12 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
if (xe_device_uc_enabled(xe)) {
common_mask = GT_RENDER_USER_INTERRUPT |
GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
+
+ /* Enable Compute Walker Interrupt for non-MSIX platforms */
+ if (GRAPHICS_VERx100(xe) >= 3511 && !xe_device_has_msix(xe)) {
+ rcs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
+ ccs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
+ }
} else {
common_mask = GT_RENDER_USER_INTERRUPT |
GT_CS_MASTER_ERROR_INTERRUPT |
--
2.51.0
next prev parent reply other threads:[~2025-10-15 22:07 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-15 22:06 [PATCH v2 00/22] drm/xe: Add Xe3p support Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 01/22] drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05 Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 02/22] drm/xe/xe3p_lpm: Add support for media IP versions 35.00 & 35.03 Lucas De Marchi
2025-10-16 16:12 ` Gustavo Sousa
2025-10-16 16:46 ` Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 03/22] drm/xe: Drop CTC_MODE register read Lucas De Marchi
2025-10-15 23:26 ` Matt Roper
2025-10-15 22:06 ` [PATCH v2 04/22] drm/xe: Add GT_VER() to check version specific to gt type Lucas De Marchi
2025-10-15 23:34 ` Matt Roper
2025-10-15 22:06 ` [PATCH v2 05/22] drm/xe/xe3p_lpm: Skip disabling NOA on unsupported IPs Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 06/22] drm/xe/xe3p_lpm: Handle MCR steering Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 07/22] drm/xe/xe3p: Stop programming RCU_MODE's fixed slice mode setting Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 08/22] drm/xe/xe3p: Determine service copy availability from fuse Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 09/22] drm/xe: Dump CURRENT_LRCA register Lucas De Marchi
2025-10-15 23:28 ` Matt Roper
2025-10-15 22:06 ` [PATCH v2 10/22] drm/xe/xe3p: Dump CSMQDEBUG register Lucas De Marchi
2025-10-15 23:33 ` Matt Roper
2025-10-15 22:06 ` [PATCH v2 11/22] drm/xe/nvl: Define NVL-S platform Lucas De Marchi
2025-10-16 16:41 ` Gustavo Sousa
2025-10-15 22:06 ` [PATCH v2 12/22] drm/xe/nvls: Define GuC firmware for NVL-S Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 13/22] drm/xe/nvls: Attach MOCS table " Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 14/22] drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 15/22] drm/xe/xe3p_xpc: Add L3 bank mask Lucas De Marchi
2025-10-15 23:29 ` Matt Roper
2025-10-15 22:06 ` [PATCH v2 16/22] drm/xe/xe3p_xpc: Add MCR steering Lucas De Marchi
2025-10-16 11:44 ` Gustavo Sousa
2025-10-16 19:48 ` Lucas De Marchi
2025-10-16 20:16 ` Gustavo Sousa
2025-10-15 22:06 ` [PATCH v2 17/22] drm/xe/irq: Rename fuse mask variables Lucas De Marchi
2025-10-15 23:39 ` Matt Roper
2025-10-15 22:06 ` [PATCH v2 18/22] drm/xe/irq: Split irq mask per engine class Lucas De Marchi
2025-10-15 23:52 ` Matt Roper
2025-10-16 4:38 ` Lucas De Marchi
2025-10-15 22:06 ` Lucas De Marchi [this message]
2025-10-16 0:07 ` [PATCH v2 19/22] drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx Matt Roper
2025-10-16 5:33 ` Lucas De Marchi
2025-10-16 6:52 ` Muqthyar Ahmed, Syed Abdul
2025-10-16 13:59 ` Lucas De Marchi
2025-10-17 6:52 ` Joonas Lahtinen
2025-10-15 22:06 ` [PATCH v2 20/22] drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs Lucas De Marchi
2025-10-16 12:30 ` Gustavo Sousa
2025-10-16 16:54 ` Matt Roper
2025-10-15 22:06 ` [PATCH v2 21/22] drm/xe/xe3p_xpc: Setup PAT table Lucas De Marchi
2025-10-16 14:30 ` Vivekanandan, Balasubramani
2025-10-16 20:22 ` Lucas De Marchi
2025-10-15 22:06 ` [PATCH v2 22/22] drm/xe/xe3p: Add xe3p EU stall data format Lucas De Marchi
2025-10-15 23:58 ` Dixit, Ashutosh
2025-10-16 3:25 ` Lucas De Marchi
2025-10-16 5:11 ` ✗ CI.checkpatch: warning for drm/xe: Add Xe3p support (rev2) Patchwork
2025-10-16 5:13 ` ✓ CI.KUnit: success " Patchwork
2025-10-16 5:55 ` ✗ Xe.CI.BAT: failure " Patchwork
2025-10-16 23:29 ` ✗ Xe.CI.Full: " Patchwork
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