Re: [PATCH v2 10/22] drm/xe/xe3p: Dump CSMQDEBUG register

[Matt Roper <matthew.d.roper@intel.com>]

On Wed, Oct 15, 2025 at 03:06:25PM -0700, Lucas De Marchi wrote:
> From: Wang Xin <x.wang@intel.com>
> 
> The CSMQDEBUG is useful for the development of MQ feature. Start dumping
> the debug register.
> 
> Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Wang Xin <x.wang@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> v2:
>  - Extract CSMQDEBUG from other patch dumping multiple register (Matt
>    Roper)
>  - Simplify version check (Matt Roper)
>  - Do not dump CSMQDEBUG for engines that do not support MQ (Matt Roper)
> ---
>  drivers/gpu/drm/xe/regs/xe_engine_regs.h |  2 ++
>  drivers/gpu/drm/xe/xe_guc_capture.c      | 48 +++++++++++++++++++++++++++++++-
>  2 files changed, 49 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index 3c05d85902c69..7b6ec0cf78c85 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -156,6 +156,8 @@
>  #define   GFX_DISABLE_LEGACY_MODE		REG_BIT(3)
>  #define   GFX_MSIX_INTERRUPT_ENABLE		REG_BIT(13)
>  
> +#define RING_CSMQDEBUG(base)			XE_REG((base) + 0x2b0)
> +
>  #define RING_TIMESTAMP(base)			XE_REG((base) + 0x358)
>  
>  #define RING_TIMESTAMP_UDW(base)		XE_REG((base) + 0x358 + 4)
> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
> index 8d1bfa2cdb151..035b9b6c0df58 100644
> --- a/drivers/gpu/drm/xe/xe_guc_capture.c
> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c
> @@ -150,6 +150,9 @@ struct __guc_capture_parsed_output {
>  	{ SFC_DONE(2),			0,	0,	0,	0,	"SFC_DONE[2]"}, \
>  	{ SFC_DONE(3),			0,	0,	0,	0,	"SFC_DONE[3]"}
>  
> +#define XE3P_BASE_ENGINE_INSTANCE \
> +	{ RING_CSMQDEBUG(0),		REG_32BIT,	0,	0,	0,	"CSMQDEBUG"}
> +
>  /* XE_LP Global */
>  static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = {
>  	COMMON_XELP_BASE_GLOBAL,
> @@ -196,6 +199,32 @@ static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = {
>  	COMMON_BASE_ENGINE_INSTANCE,
>  };
>  
> +/* Render / Compute Per-Engine-Instance */
> +static const struct __guc_mmio_reg_descr xe3p_rc_inst_regs[] = {
> +	COMMON_BASE_ENGINE_INSTANCE,
> +	XE3P_BASE_ENGINE_INSTANCE,
> +};
> +
> +/* Media Decode/Encode Per-Engine-Instance */
> +static const struct __guc_mmio_reg_descr xe3p_vd_inst_regs[] = {
> +	COMMON_BASE_ENGINE_INSTANCE,
> +};

We can skip xe3p definitions for vd / ve / blt / gsc and just re-use the
existing definitions like xe_vd_inst_regs[] as we have on past
platforms.  We only need new platform-specific tables when we're adding
something new that's different from the previous platforms.


Matt

> +
> +/* Video Enhancement Per-Engine-Instance */
> +static const struct __guc_mmio_reg_descr xe3p_vec_inst_regs[] = {
> +	COMMON_BASE_ENGINE_INSTANCE,
> +};
> +
> +/* Blitter Per-Engine-Instance */
> +static const struct __guc_mmio_reg_descr xe3p_blt_inst_regs[] = {
> +	COMMON_BASE_ENGINE_INSTANCE,
> +};
> +
> +/* XE3P - GSC Per-Engine-Instance */
> +static const struct __guc_mmio_reg_descr xe3p_gsc_inst_regs[] = {
> +	COMMON_BASE_ENGINE_INSTANCE,
> +};
> +
>  /*
>   * Empty list to prevent warnings about unknown class/instance types
>   * as not all class/instance types have entries on all platforms.
> @@ -246,6 +275,21 @@ static const struct __guc_mmio_reg_descr_group xe_hpg_lists[] = {
>  	{}
>  };
>  
> + /* List of lists for Xe3p and beyond */
> +static const struct __guc_mmio_reg_descr_group xe3p_lists[] = {
> +	MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0),
> +	MAKE_REGLIST(xe_hpg_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
> +	MAKE_REGLIST(xe3p_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
> +	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO),
> +	MAKE_REGLIST(xe3p_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO),
> +	MAKE_REGLIST(xe_vec_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
> +	MAKE_REGLIST(xe3p_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
> +	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
> +	MAKE_REGLIST(xe3p_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
> +	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
> +	MAKE_REGLIST(xe3p_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
> +	{}
> +};
>  static const char * const capture_list_type_names[] = {
>  	"Global",
>  	"Class",
> @@ -293,7 +337,9 @@ guc_capture_remove_stale_matches_from_list(struct xe_guc_state_capture *gc,
>  static const struct __guc_mmio_reg_descr_group *
>  guc_capture_get_device_reglist(struct xe_device *xe)
>  {
> -	if (GRAPHICS_VERx100(xe) >= 1255)
> +	if (GRAPHICS_VER(xe) >= 35)
> +		return xe3p_lists;
> +	else if (GRAPHICS_VERx100(xe) >= 1255)
>  		return xe_hpg_lists;
>  	else
>  		return xe_lp_lists;
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation