[PATCH v2 00/22] drm/xe: Add Xe3p support

[Lucas De Marchi <lucas.demarchi@intel.com>]

This begins the support for the Xe3p arch - it contains generic support
for graphics version 35 and the Xe3p_xpc IP, the Xe3p_LPM IP for media
and support for Nova Lake S (NVL-S), that uses a mix of IPs - the
display side for NVL-S will be submitted separately.

Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
Changes in v2:
- Rebase on latest drm-tip as some interfaces changed like the device
  flags location and RTP helper signature
- Drop patches to handle app transient and additional flushes as they
  are not currently used
- Drop patches to handle main gam control - they are actually correct,
  but having a spec reference to embed in the commit message is
  preferred
- Add 2 patches to refactor irq enabling on hw engines so we don blindly
  set bits intended for one engine class in another.
- Some other changes, mentioned in the individual commits
- Link to v1: https://lore.kernel.org/r/20251013-xe3p-v1-0-bfb74f038215@intel.com
---
Balasubramani Vivekanandan (3):
      drm/xe: Drop CTC_MODE register read
      drm/xe/xe3p_lpm: Skip disabling NOA on unsupported IPs
      drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition

Dnyaneshwar Bhadane (1):
      drm/xe/nvls: Attach MOCS table for NVL-S

Fei Yang (1):
      drm/xe/xe3p_xpc: Add L3 bank mask

Harish Chegondi (1):
      drm/xe/xe3p: Add xe3p EU stall data format

Lucas De Marchi (4):
      drm/xe: Add GT_VER() to check version specific to gt type
      drm/xe/irq: Rename fuse mask variables
      drm/xe/irq: Split irq mask per engine class
      drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx

Matt Roper (8):
      drm/xe/xe3p_lpm: Handle MCR steering
      drm/xe/xe3p: Stop programming RCU_MODE's fixed slice mode setting
      drm/xe/xe3p: Determine service copy availability from fuse
      drm/xe/nvl: Define NVL-S platform
      drm/xe/nvls: Define GuC firmware for NVL-S
      drm/xe/xe3p_xpc: Add MCR steering
      drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs
      drm/xe/xe3p_xpc: Setup PAT table

Shekhar Chauhan (2):
      drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05
      drm/xe/xe3p_lpm: Add support for media IP versions 35.00 & 35.03

Wang Xin (2):
      drm/xe: Dump CURRENT_LRCA register
      drm/xe/xe3p: Dump CSMQDEBUG register

 drivers/gpu/drm/xe/regs/xe_engine_regs.h |   5 ++
 drivers/gpu/drm/xe/regs/xe_gt_regs.h     |   7 +-
 drivers/gpu/drm/xe/regs/xe_irq_regs.h    |   1 +
 drivers/gpu/drm/xe/xe_eu_stall.c         |  28 +++++++-
 drivers/gpu/drm/xe/xe_gt.h               |   6 ++
 drivers/gpu/drm/xe/xe_gt_clock.c         |  19 ------
 drivers/gpu/drm/xe/xe_gt_mcr.c           |  61 +++++++++++++++--
 drivers/gpu/drm/xe/xe_gt_topology.c      |   6 +-
 drivers/gpu/drm/xe/xe_gt_types.h         |  15 +++++
 drivers/gpu/drm/xe/xe_guc_capture.c      |  49 +++++++++++++-
 drivers/gpu/drm/xe/xe_hw_engine.c        |  50 +++++++++++---
 drivers/gpu/drm/xe/xe_irq.c              | 109 ++++++++++++++++++++-----------
 drivers/gpu/drm/xe/xe_mocs.c             |   1 +
 drivers/gpu/drm/xe/xe_oa.c               |   3 +-
 drivers/gpu/drm/xe/xe_pat.c              |  96 ++++++++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_pci.c              |  21 ++++++
 drivers/gpu/drm/xe/xe_platform_types.h   |   1 +
 drivers/gpu/drm/xe/xe_rtp.c              |   7 ++
 drivers/gpu/drm/xe/xe_rtp.h              |  12 ++++
 drivers/gpu/drm/xe/xe_tuning.c           |   9 ++-
 drivers/gpu/drm/xe/xe_uc_fw.c            |   1 +
 drivers/gpu/drm/xe/xe_wa.c               |   6 +-
 drivers/gpu/drm/xe/xe_wa_oob.rules       |   9 +--
 include/drm/intel/pciids.h               |   9 +++
 24 files changed, 441 insertions(+), 90 deletions(-)

base-commit: f019aaad58112f89234f7b68557c831846437008
change-id: 20251013-xe3p-81bb749e9de0

Lucas De Marchi