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From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
To: intel-xe@lists.freedesktop.org
Cc: kernel-dev@igalia.com, Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Subject: [PATCH 03/12] drm/xe: Pass flags directly to emit_flush_imm_ggtt
Date: Fri, 21 Feb 2025 10:17:22 +0000	[thread overview]
Message-ID: <20250221101736.78986-4-tvrtko.ursulin@igalia.com> (raw)
In-Reply-To: <20250221101736.78986-1-tvrtko.ursulin@igalia.com>

This is more readable than the nameless booleans and will also come handy
later.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
---
 drivers/gpu/drm/xe/xe_ring_ops.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index a2d1fb8f0adf..21520ff97599 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -90,11 +90,10 @@ static int emit_flush_dw(u32 *dw, int i)
 	return i;
 }
 
-static int emit_flush_imm_ggtt(u32 addr, u32 value, bool invalidate_tlb,
-			       u32 *dw, int i)
+static int emit_flush_imm_ggtt(u32 addr, u32 value, u32 flags, u32 *dw, int i)
 {
 	dw[i++] = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW |
-		(invalidate_tlb ? MI_INVALIDATE_TLB : 0);
+		  flags;
 	dw[i++] = addr | MI_FLUSH_DW_USE_GTT;
 	dw[i++] = 0;
 	dw[i++] = value;
@@ -250,7 +249,7 @@ static void __emit_job_gen12_simple(struct xe_sched_job *job, struct xe_lrc *lrc
 	if (job->ring_ops_flush_tlb) {
 		dw[i++] = preparser_disable(true);
 		i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
-					seqno, true, dw, i);
+					seqno, MI_INVALIDATE_TLB, dw, i);
 		dw[i++] = preparser_disable(false);
 	} else {
 		i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
@@ -266,7 +265,7 @@ static void __emit_job_gen12_simple(struct xe_sched_job *job, struct xe_lrc *lrc
 						dw, i);
 	}
 
-	i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, false, dw, i);
+	i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, 0, dw, i);
 
 	i = emit_user_interrupt(dw, i);
 
@@ -312,7 +311,7 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
 
 	if (job->ring_ops_flush_tlb)
 		i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
-					seqno, true, dw, i);
+					seqno, MI_INVALIDATE_TLB, dw, i);
 
 	dw[i++] = preparser_disable(false);
 
@@ -329,7 +328,7 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
 						dw, i);
 	}
 
-	i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, false, dw, i);
+	i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, 0, dw, i);
 
 	i = emit_user_interrupt(dw, i);
 
-- 
2.48.0


  parent reply	other threads:[~2025-02-21 10:17 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-21 10:17 [PATCH 00/12] AuxCCS handling and render compression modifiers Tvrtko Ursulin
2025-02-21 10:17 ` [PATCH 01/12] drm/xe: Fix MOCS debugfs LNCF readout Tvrtko Ursulin
2025-02-27 20:21   ` Rodrigo Vivi
2025-02-27 23:24   ` Matt Roper
2025-02-28  8:10     ` Tvrtko Ursulin
2025-02-21 10:17 ` [PATCH 02/12] drm/xe: Fix ring flush invalidation Tvrtko Ursulin
2025-02-27 23:46   ` Matt Roper
2025-02-28  9:08     ` Tvrtko Ursulin
2025-02-21 10:17 ` Tvrtko Ursulin [this message]
2025-02-27 23:47   ` [PATCH 03/12] drm/xe: Pass flags directly to emit_flush_imm_ggtt Matt Roper
2025-02-21 10:17 ` [PATCH 04/12] drm/xe: Add ring buffer handling for AuxCCS Tvrtko Ursulin
2025-02-21 10:17 ` [PATCH 05/12] drm/xe: Use correct type width for alignment in fb pinning code Tvrtko Ursulin
2025-02-28 14:57   ` Rodrigo Vivi
2025-02-21 10:17 ` [PATCH 06/12] drm/xe: Use fb cached min alignment Tvrtko Ursulin
2025-02-28 19:21   ` Rodrigo Vivi
2025-02-21 10:17 ` [PATCH 07/12] drm/xe: Reduce DPT table alignment as in i915 Tvrtko Ursulin
2025-02-28 19:25   ` Rodrigo Vivi
2025-02-21 10:17 ` [PATCH 08/12] drm/xe: Flush GGTT writes after populating DPT Tvrtko Ursulin
2025-02-28 19:27   ` Rodrigo Vivi
2025-03-04 14:23     ` Tvrtko Ursulin
2025-02-21 10:17 ` [PATCH 09/12] drm/xe: Handle DPT in system memory Tvrtko Ursulin
2025-02-21 10:17 ` [PATCH 10/12] drm/xe: Force flush system memory AuxCCS framebuffers before scan out Tvrtko Ursulin
2025-02-28 19:34   ` Rodrigo Vivi
2025-03-04 14:21     ` Tvrtko Ursulin
2025-02-21 10:17 ` [PATCH 11/12] drm/xe/display: Add support for AuxCCS Tvrtko Ursulin
2025-02-21 10:17 ` [PATCH 12/12] drm/xe/display: Expose AuxCCS frame buffer modifiers Tvrtko Ursulin
2025-02-28 19:32   ` Rodrigo Vivi
2025-02-21 10:25 ` ✓ CI.Patch_applied: success for AuxCCS handling and render compression modifiers (rev2) Patchwork
2025-02-21 10:25 ` ✗ CI.checkpatch: warning " Patchwork
2025-02-21 10:27 ` ✓ CI.KUnit: success " Patchwork
2025-02-21 10:53 ` ✓ CI.Build: " Patchwork
2025-02-21 10:56 ` ✓ CI.Hooks: " Patchwork
2025-02-21 10:57 ` ✓ CI.checksparse: " Patchwork
2025-02-21 11:16 ` ✓ Xe.CI.BAT: " Patchwork
2025-02-22  0:13 ` ✗ Xe.CI.Full: failure " Patchwork

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