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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: <intel-xe@lists.freedesktop.org>, <kernel-dev@igalia.com>
Subject: Re: [PATCH 07/12] drm/xe: Reduce DPT table alignment as in i915
Date: Fri, 28 Feb 2025 14:25:48 -0500	[thread overview]
Message-ID: <Z8INvLjsBh-0zWnk@intel.com> (raw)
In-Reply-To: <20250221101736.78986-8-tvrtko.ursulin@igalia.com>

On Fri, Feb 21, 2025 at 10:17:26AM +0000, Tvrtko Ursulin wrote:
> There is some magic going on with DPT alignment values which are
> multiplied by 512, and then for specifically pinning the DPT table
> scaled back down.

This does follow same pattern as i915's intel_plane_pin_fb()
and it looks like it would deserve some refactor to make this
512 magic less magical and more clear.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

But I believe Ville has a better view on this, so it is better
to double check.

> 
> Make xe do it in the same way as i915.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> ---
>  drivers/gpu/drm/xe/display/xe_fb_pin.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> index 496257a60009..6c85e03dfd79 100644
> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> @@ -326,7 +326,7 @@ static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb,
>  
>  	vma->bo = bo;
>  	if (intel_fb_uses_dpt(&fb->base))
> -		ret = __xe_pin_fb_vma_dpt(fb, view, vma, alignment);
> +		ret = __xe_pin_fb_vma_dpt(fb, view, vma, alignment / 512);
>  	else
>  		ret = __xe_pin_fb_vma_ggtt(fb, view, vma,  alignment);
>  	if (ret)
> -- 
> 2.48.0
> 

  reply	other threads:[~2025-02-28 19:26 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-21 10:17 [PATCH 00/12] AuxCCS handling and render compression modifiers Tvrtko Ursulin
2025-02-21 10:17 ` [PATCH 01/12] drm/xe: Fix MOCS debugfs LNCF readout Tvrtko Ursulin
2025-02-27 20:21   ` Rodrigo Vivi
2025-02-27 23:24   ` Matt Roper
2025-02-28  8:10     ` Tvrtko Ursulin
2025-02-21 10:17 ` [PATCH 02/12] drm/xe: Fix ring flush invalidation Tvrtko Ursulin
2025-02-27 23:46   ` Matt Roper
2025-02-28  9:08     ` Tvrtko Ursulin
2025-02-21 10:17 ` [PATCH 03/12] drm/xe: Pass flags directly to emit_flush_imm_ggtt Tvrtko Ursulin
2025-02-27 23:47   ` Matt Roper
2025-02-21 10:17 ` [PATCH 04/12] drm/xe: Add ring buffer handling for AuxCCS Tvrtko Ursulin
2025-02-21 10:17 ` [PATCH 05/12] drm/xe: Use correct type width for alignment in fb pinning code Tvrtko Ursulin
2025-02-28 14:57   ` Rodrigo Vivi
2025-02-21 10:17 ` [PATCH 06/12] drm/xe: Use fb cached min alignment Tvrtko Ursulin
2025-02-28 19:21   ` Rodrigo Vivi
2025-02-21 10:17 ` [PATCH 07/12] drm/xe: Reduce DPT table alignment as in i915 Tvrtko Ursulin
2025-02-28 19:25   ` Rodrigo Vivi [this message]
2025-02-21 10:17 ` [PATCH 08/12] drm/xe: Flush GGTT writes after populating DPT Tvrtko Ursulin
2025-02-28 19:27   ` Rodrigo Vivi
2025-03-04 14:23     ` Tvrtko Ursulin
2025-02-21 10:17 ` [PATCH 09/12] drm/xe: Handle DPT in system memory Tvrtko Ursulin
2025-02-21 10:17 ` [PATCH 10/12] drm/xe: Force flush system memory AuxCCS framebuffers before scan out Tvrtko Ursulin
2025-02-28 19:34   ` Rodrigo Vivi
2025-03-04 14:21     ` Tvrtko Ursulin
2025-02-21 10:17 ` [PATCH 11/12] drm/xe/display: Add support for AuxCCS Tvrtko Ursulin
2025-02-21 10:17 ` [PATCH 12/12] drm/xe/display: Expose AuxCCS frame buffer modifiers Tvrtko Ursulin
2025-02-28 19:32   ` Rodrigo Vivi
2025-02-21 10:25 ` ✓ CI.Patch_applied: success for AuxCCS handling and render compression modifiers (rev2) Patchwork
2025-02-21 10:25 ` ✗ CI.checkpatch: warning " Patchwork
2025-02-21 10:27 ` ✓ CI.KUnit: success " Patchwork
2025-02-21 10:53 ` ✓ CI.Build: " Patchwork
2025-02-21 10:56 ` ✓ CI.Hooks: " Patchwork
2025-02-21 10:57 ` ✓ CI.checksparse: " Patchwork
2025-02-21 11:16 ` ✓ Xe.CI.BAT: " Patchwork
2025-02-22  0:13 ` ✗ Xe.CI.Full: failure " Patchwork

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