[PATCH v4 00/23] Allow configfs to disable specific GT type(s)

[PATCH v4 00/23] Allow configfs to disable specific GT type(s)

[Matt Roper]

During various debug or hardware bring-up activities, it is often useful
to completely disable one of the GTs to reduce the scope of the debug.
Add a configfs attribute to make this easy to do in a standard manner,
similar to the existing attribute we have to limit engines.

One of the changes in this series is that we reverse direction on the
placement of a few feature flags.  Previously we had moved things like
number of page table levels, size of the virtual address space, or
presence/absence of FlatCCS into the graphics descriptor to tie it to
the general architecture (Xe2, Xe3, etc.).  But upon further reflection,
these kind of flags and values are truly platform-specific
characteristics rather than being tied just to the graphics IP.  The
value of these winds up being platform-wide (as already evidenced by the
fact that we copied their values into xe->info rather than gt->info) and
all IP blocks in a hardware platform (graphics, media, and display) are
going to have a consistent understanding of these characteristics;
they're not just "graphics" values, and we need to be able to detect and
handle them properly even when "graphics" (in the form of the primary
GT) is absent.  So this series moves some of those flags back into the
platform-level descriptors and tries to keep the graphics descriptor's
fields focused on values that are truly tied to the primary GT.

Note that at the moment it's only possible to disable the media GT.
Although this series includes a number of patches aimed at reducing the
driver's reliance on the primary GT and assumptions that the primary GT
will always be present and non-NULL, we're not quite at the point where
the driver can actually run with primary GT disabled.  The main
remaining blocker for that is the reliance on the BCS engines (which
reside in the primary GT) for various VRAM and migration operations.
Additional work after this series will be required to eliminate those
dependencies.

v4:
 - Initialize gt->tile for SR-IOV's dummy GT to prevent null derefence.
 - Switch internal function interface from one function that returns a
   mask to two functions (one primary, one media) that return true/false
   if the engine type is enabled.
 - Use scope-based cleanup in a couple places to fix memory leaks on
   error paths and to make code simpler in general.
 - Block SR-IOV without primary GT simply by adjusting .has_sriov during
   early init.
 - Drop some outdated comments and commit message paragraphs that should
   have been removed with the code changes in v3.
 - Tweak wording of a couple commit messages to reduce ambiguity of
   meaning.

v3:
 - Drop default values and set va_bits / vm_max_level on all descriptors
   (Michal, Lucas)
 - Use a specifically allocated GT to do SRIOV pre-init GT operations
   rather than filling tile0's primary GT with data for each tile & GT.
   This allows the primary GT's allocation to be moved to a more
   appropriate place (and skipped completely if the primary GT is
   disabled).
 - If primary GT is disabled, do PF->native demotion and VF probe failure
   in xe_info_init rather than SRIOV pre-init.  (Michal)

v2:
 - About 20 extra patches added to reduce dependencies on an
   always-present primary GT.
 - Kerneldoc and string parsing fixes to the configfs attribute handling
   (Gustavo)

Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>

Matt Roper (23):
  drm/xe/huc: Adjust HuC check on primary GT
  drm/xe: Drop GT parameter to xe_display_irq_postinstall()
  drm/xe: Move 'va_bits' flag back to platform descriptor
  drm/xe: Move 'vm_max_level' flag back to platform descriptor
  drm/xe: Move 'vram_flags' flag back to platform descriptor
  drm/xe: Move 'has_flatccs' flag back to platform descriptor
  drm/xe: Read VF GMD_ID with a specifically-allocated dummy GT
  drm/xe: Move primary GT allocation from xe_tile_init_early to
    xe_tile_init
  drm/xe: Skip L2 / TDF cache flushes if primary GT is disabled
  drm/xe/query: Report hwconfig size as 0 if primary GT is disabled
  drm/xe/pmu: Initialize PMU event types based on first available GT
  drm/xe: Check for primary GT before looking up Wa_22019338487
  drm/xe: Make display part of Wa_22019338487 a device workaround
  drm/xe/irq: Don't try to lookup engine masks for non-existent primary
    GT
  drm/xe: Handle Wa_22010954014 and Wa_14022085890 as device workarounds
  drm/xe/rtp: Pass xe_device parameter to FUNC matches
  drm/xe: Bypass Wa_14018094691 when primary GT is disabled
  drm/xe: Correct lineage for Wa_22014953428 and only check with valid
    GT
  drm/xe: Check that GT is not NULL before testing Wa_16023588340
  drm/xe: Don't check BIOS-disabled FlatCCS if primary GT is disabled
  drm/xe: Break GT setup out of xe_info_init()
  drm/xe/configfs: Add attribute to disable GT types
  drm/xe/sriov: Disable SR-IOV if primary GT is disabled via configfs

 drivers/gpu/drm/xe/display/intel_fbdev_fb.c   |   4 +-
 drivers/gpu/drm/xe/display/xe_display.c       |   5 +-
 drivers/gpu/drm/xe/display/xe_display.h       |   4 +-
 drivers/gpu/drm/xe/display/xe_display_wa.c    |   3 +-
 drivers/gpu/drm/xe/display/xe_plane_initial.c |   4 +-
 drivers/gpu/drm/xe/tests/xe_pci.c             |   6 +-
 drivers/gpu/drm/xe/tests/xe_rtp_test.c        |   6 +-
 drivers/gpu/drm/xe/xe_configfs.c              | 145 +++++++++++
 drivers/gpu/drm/xe/xe_configfs.h              |   4 +
 drivers/gpu/drm/xe/xe_device.c                |   7 +
 drivers/gpu/drm/xe/xe_device_wa_oob.rules     |   3 +
 drivers/gpu/drm/xe/xe_ggtt.c                  |  31 ++-
 drivers/gpu/drm/xe/xe_gsc.c                   |   4 +-
 drivers/gpu/drm/xe/xe_guc_pc.c                |   3 +-
 drivers/gpu/drm/xe/xe_huc.c                   |  10 +-
 drivers/gpu/drm/xe/xe_hw_engine.c             |  10 +-
 drivers/gpu/drm/xe/xe_irq.c                   |  14 +-
 drivers/gpu/drm/xe/xe_pci.c                   | 236 ++++++++++++------
 drivers/gpu/drm/xe/xe_pci_types.h             |   9 +-
 drivers/gpu/drm/xe/xe_platform_types.h        |   1 +
 drivers/gpu/drm/xe/xe_pmu.c                   |  11 +-
 drivers/gpu/drm/xe/xe_query.c                 |   2 +-
 drivers/gpu/drm/xe/xe_reg_whitelist.c         |   3 +-
 drivers/gpu/drm/xe/xe_rtp.c                   |  24 +-
 drivers/gpu/drm/xe/xe_rtp.h                   |  18 +-
 drivers/gpu/drm/xe/xe_rtp_types.h             |   4 +-
 drivers/gpu/drm/xe/xe_tile.c                  |   4 -
 drivers/gpu/drm/xe/xe_vm.c                    |   3 +-
 drivers/gpu/drm/xe/xe_wa.c                    |   2 +-
 drivers/gpu/drm/xe/xe_wa_oob.rules            |   8 +-
 include/drm/intel/pciids.h                    |   7 +-
 31 files changed, 439 insertions(+), 156 deletions(-)

-- 
2.51.0

[PATCH v4 01/23] drm/xe/huc: Adjust HuC check on primary GT

[Matt Roper]

The HuC initialization code determines whether a platform can have a HuC
on the primary GT by checking whether tile->media_gt is NULL; old Xe1
platforms that combined render+media into a single GT will always have a
NULL media_gt pointer.  However once we allow media to be disabled via
configfs, there will also be cases where tile->media_gt is NULL on more
modern platforms, causing this condition to behave incorrectly.

To handle cases where media gets disabled via configfs (or theoretical
cases where media is truly fused off in hardware), change the condition
to consider the graphics version of the primary GT; only the old Xe1
platforms with graphics versions 12.55 or earlier should try to
initialize a HuC on the primary GT.

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_huc.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_huc.c b/drivers/gpu/drm/xe/xe_huc.c
index 7e43b2dd6a32..0a70c8924582 100644
--- a/drivers/gpu/drm/xe/xe_huc.c
+++ b/drivers/gpu/drm/xe/xe_huc.c
@@ -66,14 +66,18 @@ static int huc_alloc_gsc_pkt(struct xe_huc *huc)
 int xe_huc_init(struct xe_huc *huc)
 {
 	struct xe_gt *gt = huc_to_gt(huc);
-	struct xe_tile *tile = gt_to_tile(gt);
 	struct xe_device *xe = gt_to_xe(gt);
 	int ret;
 
 	huc->fw.type = XE_UC_FW_TYPE_HUC;
 
-	/* On platforms with a media GT the HuC is only available there */
-	if (tile->media_gt && (gt != tile->media_gt)) {
+	/*
+	 * The HuC is only available on the media GT on most platforms.  The
+	 * exception to that rule are the old Xe1 platforms where there was
+	 * no separate GT for media IP, so the HuC was part of the primary
+	 * GT.  Such platforms have graphics versions 12.55 and earlier.
+	 */
+	if (!xe_gt_is_media_type(gt) && GRAPHICS_VERx100(xe) > 1255) {
 		xe_uc_fw_change_status(&huc->fw, XE_UC_FIRMWARE_NOT_SUPPORTED);
 		return 0;
 	}
-- 
2.51.0

[PATCH v4 02/23] drm/xe: Drop GT parameter to xe_display_irq_postinstall()

[Matt Roper]

Display interrupt handling has no relation to GT(s) on the platforms
supported by the Xe driver.  We only call xe_display_irq_postinstall
with the first tile's primary GT, so the single condition that uses the
GT pointer within the function always evaluates to true.  Drop the
unnecessary parameter and the condition.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/display/xe_display.c | 5 ++---
 drivers/gpu/drm/xe/display/xe_display.h | 4 ++--
 drivers/gpu/drm/xe/xe_irq.c             | 2 +-
 3 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index 5f4044e63185..47619bb8dc10 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -227,15 +227,14 @@ void xe_display_irq_reset(struct xe_device *xe)
 	gen11_display_irq_reset(display);
 }
 
-void xe_display_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
+void xe_display_irq_postinstall(struct xe_device *xe)
 {
 	struct intel_display *display = xe->display;
 
 	if (!xe->info.probe_display)
 		return;
 
-	if (gt->info.id == XE_GT0)
-		gen11_de_irq_postinstall(display);
+	gen11_de_irq_postinstall(display);
 }
 
 static bool suspend_to_idle(void)
diff --git a/drivers/gpu/drm/xe/display/xe_display.h b/drivers/gpu/drm/xe/display/xe_display.h
index e533aa4750bc..76db95c25f7e 100644
--- a/drivers/gpu/drm/xe/display/xe_display.h
+++ b/drivers/gpu/drm/xe/display/xe_display.h
@@ -26,7 +26,7 @@ void xe_display_unregister(struct xe_device *xe);
 void xe_display_irq_handler(struct xe_device *xe, u32 master_ctl);
 void xe_display_irq_enable(struct xe_device *xe, u32 gu_misc_iir);
 void xe_display_irq_reset(struct xe_device *xe);
-void xe_display_irq_postinstall(struct xe_device *xe, struct xe_gt *gt);
+void xe_display_irq_postinstall(struct xe_device *xe);
 
 void xe_display_pm_suspend(struct xe_device *xe);
 void xe_display_pm_shutdown(struct xe_device *xe);
@@ -55,7 +55,7 @@ static inline void xe_display_unregister(struct xe_device *xe) {}
 static inline void xe_display_irq_handler(struct xe_device *xe, u32 master_ctl) {}
 static inline void xe_display_irq_enable(struct xe_device *xe, u32 gu_misc_iir) {}
 static inline void xe_display_irq_reset(struct xe_device *xe) {}
-static inline void xe_display_irq_postinstall(struct xe_device *xe, struct xe_gt *gt) {}
+static inline void xe_display_irq_postinstall(struct xe_device *xe) {}
 
 static inline void xe_display_pm_suspend(struct xe_device *xe) {}
 static inline void xe_display_pm_shutdown(struct xe_device *xe) {}
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 870edaf69388..5018a116852f 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -656,7 +656,7 @@ static void xe_irq_postinstall(struct xe_device *xe)
 			xe_memirq_postinstall(&tile->memirq);
 	}
 
-	xe_display_irq_postinstall(xe, xe_root_mmio_gt(xe));
+	xe_display_irq_postinstall(xe);
 
 	/*
 	 * ASLE backlight operations are reported via GUnit GSE interrupts
-- 
2.51.0

[PATCH v4 03/23] drm/xe: Move 'va_bits' flag back to platform descriptor

[Matt Roper]

The number of virtual address bits is something that should be tracked
at the platform level rather than the IP level.  Even when mixing and
matching various graphics, media, and display IP blocks, the platform as
a whole has to have consistent page table handling.  This is also a
trait that should be tied to the platform even if the graphics IP itself
is not present (e.g., if we disable the primary GT via configfs).

v2:
 - Drop the default value of 48 and explicitly set it in each relevant
   descriptor.  (Lucas, Michal)
v3:
 - Drop an outdated comment about default value.  (Michal)

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c       | 21 +++++++++++++++------
 drivers/gpu/drm/xe/xe_pci_types.h |  2 +-
 2 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 3f42b91efa28..69ed987fef67 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -52,13 +52,11 @@ __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
 static const struct xe_graphics_desc graphics_xelp = {
 	.hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0),
 
-	.va_bits = 48,
 	.vm_max_level = 3,
 };
 
 #define XE_HP_FEATURES \
 	.has_range_tlb_inval = true, \
-	.va_bits = 48, \
 	.vm_max_level = 3
 
 static const struct xe_graphics_desc graphics_xehpg = {
@@ -84,7 +82,6 @@ static const struct xe_graphics_desc graphics_xehpc = {
 		BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
 
 	XE_HP_FEATURES,
-	.va_bits = 57,
 	.vm_max_level = 4,
 	.vram_flags = XE_VRAM_FLAGS_NEED64K,
 
@@ -108,7 +105,6 @@ static const struct xe_graphics_desc graphics_xelpg = {
 	.has_range_tlb_inval = 1, \
 	.has_usm = 1, \
 	.has_64bit_timestamp = 1, \
-	.va_bits = 48, \
 	.vm_max_level = 4, \
 	.hw_engine_mask = \
 		BIT(XE_HW_ENGINE_RCS0) | \
@@ -174,6 +170,7 @@ static const struct xe_device_desc tgl_desc = {
 	.has_sriov = true,
 	.max_gt_per_tile = 1,
 	.require_force_probe = true,
+	.va_bits = 48,
 };
 
 static const struct xe_device_desc rkl_desc = {
@@ -185,6 +182,7 @@ static const struct xe_device_desc rkl_desc = {
 	.has_llc = true,
 	.max_gt_per_tile = 1,
 	.require_force_probe = true,
+	.va_bits = 48,
 };
 
 static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 };
@@ -203,6 +201,7 @@ static const struct xe_device_desc adl_s_desc = {
 		{ XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
 		{},
 	},
+	.va_bits = 48,
 };
 
 static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 };
@@ -221,6 +220,7 @@ static const struct xe_device_desc adl_p_desc = {
 		{ XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
 		{},
 	},
+	.va_bits = 48,
 };
 
 static const struct xe_device_desc adl_n_desc = {
@@ -233,6 +233,7 @@ static const struct xe_device_desc adl_n_desc = {
 	.has_sriov = true,
 	.max_gt_per_tile = 1,
 	.require_force_probe = true,
+	.va_bits = 48,
 };
 
 #define DGFX_FEATURES \
@@ -249,6 +250,7 @@ static const struct xe_device_desc dg1_desc = {
 	.has_heci_gscfi = 1,
 	.max_gt_per_tile = 1,
 	.require_force_probe = true,
+	.va_bits = 48,
 };
 
 static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 };
@@ -265,7 +267,8 @@ static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 };
 		{ XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \
 		{ XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \
 		{ } \
-	}
+	}, \
+	.va_bits = 48
 
 static const struct xe_device_desc ats_m_desc = {
 	.pre_gmdid_graphics_ip = &graphics_ip_xehpg,
@@ -303,6 +306,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
 	.max_gt_per_tile = 1,
 	.max_remote_tiles = 1,
 	.require_force_probe = true,
+	.va_bits = 57,
 	.has_mbx_power_limits = false,
 };
 
@@ -314,6 +318,7 @@ static const struct xe_device_desc mtl_desc = {
 	.has_display = true,
 	.has_pxp = true,
 	.max_gt_per_tile = 2,
+	.va_bits = 48,
 };
 
 static const struct xe_device_desc lnl_desc = {
@@ -323,6 +328,7 @@ static const struct xe_device_desc lnl_desc = {
 	.has_pxp = true,
 	.max_gt_per_tile = 2,
 	.needs_scratch = true,
+	.va_bits = 48,
 };
 
 static const struct xe_device_desc bmg_desc = {
@@ -338,6 +344,7 @@ static const struct xe_device_desc bmg_desc = {
 	.has_sriov = true,
 	.max_gt_per_tile = 2,
 	.needs_scratch = true,
+	.va_bits = 48,
 };
 
 static const struct xe_device_desc ptl_desc = {
@@ -347,6 +354,7 @@ static const struct xe_device_desc ptl_desc = {
 	.has_sriov = true,
 	.max_gt_per_tile = 2,
 	.needs_scratch = true,
+	.va_bits = 48,
 };
 
 #undef PLATFORM
@@ -584,6 +592,8 @@ static int xe_info_init_early(struct xe_device *xe,
 		subplatform_desc->subplatform : XE_SUBPLATFORM_NONE;
 
 	xe->info.dma_mask_size = desc->dma_mask_size;
+	xe->info.va_bits = desc->va_bits;
+
 	xe->info.is_dgfx = desc->is_dgfx;
 	xe->info.has_fan_control = desc->has_fan_control;
 	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
@@ -713,7 +723,6 @@ static int xe_info_init(struct xe_device *xe,
 	}
 
 	xe->info.vram_flags = graphics_desc->vram_flags;
-	xe->info.va_bits = graphics_desc->va_bits;
 	xe->info.vm_max_level = graphics_desc->vm_max_level;
 	xe->info.has_asid = graphics_desc->has_asid;
 	xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 9b9766a3baa3..796439571abe 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -30,6 +30,7 @@ struct xe_device_desc {
 	u8 dma_mask_size;
 	u8 max_remote_tiles:2;
 	u8 max_gt_per_tile:2;
+	u8 va_bits;
 
 	u8 require_force_probe:1;
 	u8 is_dgfx:1;
@@ -51,7 +52,6 @@ struct xe_device_desc {
 };
 
 struct xe_graphics_desc {
-	u8 va_bits;
 	u8 vm_max_level;
 	u8 vram_flags;
 
-- 
2.51.0

[PATCH v4 04/23] drm/xe: Move 'vm_max_level' flag back to platform descriptor

[Matt Roper]

The number of page table levels for PPGTT virtual addresses is something
that should be tracked at the platform level rather than the IP level.
Even when mixing and matching various graphics, media, and display IP
blocks, the platform as a whole has to have consistent page table
handling.  This is also a trait that should be tied to the platform even
if the graphics IP itself is not present (e.g., if we disable the
primary GT via configfs).

v2:
 - Drop default value of 4 and explicitly set the value in each platform
   descriptor.  (Lucas)
v3:
 - Drop outdated code comment and commit message paragraph about default
   value.  (Gustavo)

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c       | 22 ++++++++++++++--------
 drivers/gpu/drm/xe/xe_pci_types.h |  2 +-
 2 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 69ed987fef67..8688f40f55d8 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -51,13 +51,10 @@ __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
 
 static const struct xe_graphics_desc graphics_xelp = {
 	.hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0),
-
-	.vm_max_level = 3,
 };
 
 #define XE_HP_FEATURES \
-	.has_range_tlb_inval = true, \
-	.vm_max_level = 3
+	.has_range_tlb_inval = true
 
 static const struct xe_graphics_desc graphics_xehpg = {
 	.hw_engine_mask =
@@ -82,7 +79,6 @@ static const struct xe_graphics_desc graphics_xehpc = {
 		BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
 
 	XE_HP_FEATURES,
-	.vm_max_level = 4,
 	.vram_flags = XE_VRAM_FLAGS_NEED64K,
 
 	.has_asid = 1,
@@ -105,7 +101,6 @@ static const struct xe_graphics_desc graphics_xelpg = {
 	.has_range_tlb_inval = 1, \
 	.has_usm = 1, \
 	.has_64bit_timestamp = 1, \
-	.vm_max_level = 4, \
 	.hw_engine_mask = \
 		BIT(XE_HW_ENGINE_RCS0) | \
 		BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \
@@ -183,6 +178,7 @@ static const struct xe_device_desc rkl_desc = {
 	.max_gt_per_tile = 1,
 	.require_force_probe = true,
 	.va_bits = 48,
+	.vm_max_level = 3,
 };
 
 static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 };
@@ -202,6 +198,7 @@ static const struct xe_device_desc adl_s_desc = {
 		{},
 	},
 	.va_bits = 48,
+	.vm_max_level = 3,
 };
 
 static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 };
@@ -221,6 +218,7 @@ static const struct xe_device_desc adl_p_desc = {
 		{},
 	},
 	.va_bits = 48,
+	.vm_max_level = 3,
 };
 
 static const struct xe_device_desc adl_n_desc = {
@@ -234,6 +232,7 @@ static const struct xe_device_desc adl_n_desc = {
 	.max_gt_per_tile = 1,
 	.require_force_probe = true,
 	.va_bits = 48,
+	.vm_max_level = 3,
 };
 
 #define DGFX_FEATURES \
@@ -251,6 +250,7 @@ static const struct xe_device_desc dg1_desc = {
 	.max_gt_per_tile = 1,
 	.require_force_probe = true,
 	.va_bits = 48,
+	.vm_max_level = 3,
 };
 
 static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 };
@@ -268,7 +268,8 @@ static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 };
 		{ XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \
 		{ } \
 	}, \
-	.va_bits = 48
+	.va_bits = 48, \
+	.vm_max_level = 3
 
 static const struct xe_device_desc ats_m_desc = {
 	.pre_gmdid_graphics_ip = &graphics_ip_xehpg,
@@ -307,6 +308,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
 	.max_remote_tiles = 1,
 	.require_force_probe = true,
 	.va_bits = 57,
+	.vm_max_level = 4,
 	.has_mbx_power_limits = false,
 };
 
@@ -319,6 +321,7 @@ static const struct xe_device_desc mtl_desc = {
 	.has_pxp = true,
 	.max_gt_per_tile = 2,
 	.va_bits = 48,
+	.vm_max_level = 4,
 };
 
 static const struct xe_device_desc lnl_desc = {
@@ -329,6 +332,7 @@ static const struct xe_device_desc lnl_desc = {
 	.max_gt_per_tile = 2,
 	.needs_scratch = true,
 	.va_bits = 48,
+	.vm_max_level = 4,
 };
 
 static const struct xe_device_desc bmg_desc = {
@@ -345,6 +349,7 @@ static const struct xe_device_desc bmg_desc = {
 	.max_gt_per_tile = 2,
 	.needs_scratch = true,
 	.va_bits = 48,
+	.vm_max_level = 4,
 };
 
 static const struct xe_device_desc ptl_desc = {
@@ -355,6 +360,7 @@ static const struct xe_device_desc ptl_desc = {
 	.max_gt_per_tile = 2,
 	.needs_scratch = true,
 	.va_bits = 48,
+	.vm_max_level = 4,
 };
 
 #undef PLATFORM
@@ -593,6 +599,7 @@ static int xe_info_init_early(struct xe_device *xe,
 
 	xe->info.dma_mask_size = desc->dma_mask_size;
 	xe->info.va_bits = desc->va_bits;
+	xe->info.vm_max_level = desc->vm_max_level;
 
 	xe->info.is_dgfx = desc->is_dgfx;
 	xe->info.has_fan_control = desc->has_fan_control;
@@ -723,7 +730,6 @@ static int xe_info_init(struct xe_device *xe,
 	}
 
 	xe->info.vram_flags = graphics_desc->vram_flags;
-	xe->info.vm_max_level = graphics_desc->vm_max_level;
 	xe->info.has_asid = graphics_desc->has_asid;
 	xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit;
 	if (xe->info.platform != XE_PVC)
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 796439571abe..6354280584d9 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -31,6 +31,7 @@ struct xe_device_desc {
 	u8 max_remote_tiles:2;
 	u8 max_gt_per_tile:2;
 	u8 va_bits;
+	u8 vm_max_level;
 
 	u8 require_force_probe:1;
 	u8 is_dgfx:1;
@@ -52,7 +53,6 @@ struct xe_device_desc {
 };
 
 struct xe_graphics_desc {
-	u8 vm_max_level;
 	u8 vram_flags;
 
 	u64 hw_engine_mask;	/* hardware engines provided by graphics IP */
-- 
2.51.0

[PATCH v4 05/23] drm/xe: Move 'vram_flags' flag back to platform descriptor

[Matt Roper]

Restrictions and requirements on VRAM alignment are something that
should be tracked at the platform level rather than the IP level.  Even
when mixing and matching various graphics, media, and display IP blocks,
the platform as a whole has to have consistent memory allocation
handling.  This is also a trait that should be tied to the platform even
if the graphics IP itself is not present (e.g., if we disable the
primary GT via configfs).

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c       | 8 ++++----
 drivers/gpu/drm/xe/xe_pci_types.h | 3 +--
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 8688f40f55d8..e0a28276c60a 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -63,7 +63,6 @@ static const struct xe_graphics_desc graphics_xehpg = {
 		BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
 
 	XE_HP_FEATURES,
-	.vram_flags = XE_VRAM_FLAGS_NEED64K,
 
 	.has_flat_ccs = 1,
 };
@@ -79,7 +78,6 @@ static const struct xe_graphics_desc graphics_xehpc = {
 		BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
 
 	XE_HP_FEATURES,
-	.vram_flags = XE_VRAM_FLAGS_NEED64K,
 
 	.has_asid = 1,
 	.has_atomic_enable_pte_bit = 1,
@@ -269,7 +267,8 @@ static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 };
 		{ } \
 	}, \
 	.va_bits = 48, \
-	.vm_max_level = 3
+	.vm_max_level = 3, \
+	.vram_flags = XE_VRAM_FLAGS_NEED64K
 
 static const struct xe_device_desc ats_m_desc = {
 	.pre_gmdid_graphics_ip = &graphics_ip_xehpg,
@@ -309,6 +308,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
 	.require_force_probe = true,
 	.va_bits = 57,
 	.vm_max_level = 4,
+	.vram_flags = XE_VRAM_FLAGS_NEED64K,
 	.has_mbx_power_limits = false,
 };
 
@@ -600,6 +600,7 @@ static int xe_info_init_early(struct xe_device *xe,
 	xe->info.dma_mask_size = desc->dma_mask_size;
 	xe->info.va_bits = desc->va_bits;
 	xe->info.vm_max_level = desc->vm_max_level;
+	xe->info.vram_flags = desc->vram_flags;
 
 	xe->info.is_dgfx = desc->is_dgfx;
 	xe->info.has_fan_control = desc->has_fan_control;
@@ -729,7 +730,6 @@ static int xe_info_init(struct xe_device *xe,
 		media_desc = NULL;
 	}
 
-	xe->info.vram_flags = graphics_desc->vram_flags;
 	xe->info.has_asid = graphics_desc->has_asid;
 	xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit;
 	if (xe->info.platform != XE_PVC)
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 6354280584d9..97a3abec8e3f 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -32,6 +32,7 @@ struct xe_device_desc {
 	u8 max_gt_per_tile:2;
 	u8 va_bits;
 	u8 vm_max_level;
+	u8 vram_flags;
 
 	u8 require_force_probe:1;
 	u8 is_dgfx:1;
@@ -53,8 +54,6 @@ struct xe_device_desc {
 };
 
 struct xe_graphics_desc {
-	u8 vram_flags;
-
 	u64 hw_engine_mask;	/* hardware engines provided by graphics IP */
 
 	u8 has_asid:1;
-- 
2.51.0

[PATCH v4 06/23] drm/xe: Move 'has_flatccs' flag back to platform descriptor

[Matt Roper]

FlatCCS presence/absence is a flag that should be tracked at the
platform level rather than the IP level.  FlatCCS affects the
device-wide memory initialization and reservations so its effects are
not confined to a single IP block or GT.  This is also a trait that
should be tied to the platform even if the graphics IP itself is not
present (e.g., if we disable the primary GT via configfs).

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c       | 12 ++++++------
 drivers/gpu/drm/xe/xe_pci_types.h |  2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index e0a28276c60a..37ae49f4b648 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -63,8 +63,6 @@ static const struct xe_graphics_desc graphics_xehpg = {
 		BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
 
 	XE_HP_FEATURES,
-
-	.has_flat_ccs = 1,
 };
 
 static const struct xe_graphics_desc graphics_xehpc = {
@@ -95,7 +93,6 @@ static const struct xe_graphics_desc graphics_xelpg = {
 #define XE2_GFX_FEATURES \
 	.has_asid = 1, \
 	.has_atomic_enable_pte_bit = 1, \
-	.has_flat_ccs = 1, \
 	.has_range_tlb_inval = 1, \
 	.has_usm = 1, \
 	.has_64bit_timestamp = 1, \
@@ -258,6 +255,7 @@ static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 };
 #define DG2_FEATURES \
 	DGFX_FEATURES, \
 	PLATFORM(DG2), \
+	.has_flat_ccs = 1, \
 	.has_gsc_nvm = 1, \
 	.has_heci_gscfi = 1, \
 	.subplatforms = (const struct xe_subplatform_desc[]) { \
@@ -328,6 +326,7 @@ static const struct xe_device_desc lnl_desc = {
 	PLATFORM(LUNARLAKE),
 	.dma_mask_size = 46,
 	.has_display = true,
+	.has_flat_ccs = 1,
 	.has_pxp = true,
 	.max_gt_per_tile = 2,
 	.needs_scratch = true,
@@ -341,6 +340,7 @@ static const struct xe_device_desc bmg_desc = {
 	.dma_mask_size = 46,
 	.has_display = true,
 	.has_fan_control = true,
+	.has_flat_ccs = 1,
 	.has_mbx_power_limits = true,
 	.has_gsc_nvm = 1,
 	.has_heci_cscfi = 1,
@@ -356,6 +356,7 @@ static const struct xe_device_desc ptl_desc = {
 	PLATFORM(PANTHERLAKE),
 	.dma_mask_size = 46,
 	.has_display = true,
+	.has_flat_ccs = 1,
 	.has_sriov = true,
 	.max_gt_per_tile = 2,
 	.needs_scratch = true,
@@ -604,6 +605,8 @@ static int xe_info_init_early(struct xe_device *xe,
 
 	xe->info.is_dgfx = desc->is_dgfx;
 	xe->info.has_fan_control = desc->has_fan_control;
+	/* runtime fusing may force flat_ccs to disabled later */
+	xe->info.has_flat_ccs = desc->has_flat_ccs;
 	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
 	xe->info.has_gsc_nvm = desc->has_gsc_nvm;
 	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
@@ -735,9 +738,6 @@ static int xe_info_init(struct xe_device *xe,
 	if (xe->info.platform != XE_PVC)
 		xe->info.has_device_atomics_on_smem = 1;
 
-	/* Runtime detection may change this later */
-	xe->info.has_flat_ccs = graphics_desc->has_flat_ccs;
-
 	xe->info.has_range_tlb_inval = graphics_desc->has_range_tlb_inval;
 	xe->info.has_usm = graphics_desc->has_usm;
 	xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 97a3abec8e3f..377588ffeb27 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -39,6 +39,7 @@ struct xe_device_desc {
 
 	u8 has_display:1;
 	u8 has_fan_control:1;
+	u8 has_flat_ccs:1;
 	u8 has_gsc_nvm:1;
 	u8 has_heci_gscfi:1;
 	u8 has_heci_cscfi:1;
@@ -58,7 +59,6 @@ struct xe_graphics_desc {
 
 	u8 has_asid:1;
 	u8 has_atomic_enable_pte_bit:1;
-	u8 has_flat_ccs:1;
 	u8 has_indirect_ring_state:1;
 	u8 has_range_tlb_inval:1;
 	u8 has_usm:1;
-- 
2.51.0

[PATCH v4 07/23] drm/xe: Read VF GMD_ID with a specifically-allocated dummy GT

[Matt Roper]

SRIOV VF initialization has a bit of a chicken and egg design problem.
Determining the IP version of the graphics and media IPs can't be done
via direct register reads as it is on PF or native and instead requires
querying the GuC.  However initialization of the GT, including its GuC,
needs to wait until after we know the IP versions so that the proper
initialization steps for the platform/IP are followed.

Currently the (somewhat hacky) solution is to manually fill out just
enough fields in tile 0's primary GT structure to make it look as if the
GT has been initialized so that the GuC can be partially initialized and
queried to obtain the GMD_ID values.  When the GT gets properly
initialized during the regular flows, the hacked-up values will get
overwritten as part of the general initialization flows.

Rather than using tile 0's primary GT structure to hold the hacked up
values for querying every GT on every tile, instead allocate a dedicated
dummy structure.  This will allow us to move the tile->primary_gt's
allocation to a more consistent place later in the initialization flow
in future patches (i.e., we shouldn't even allocate this GT structure if
the GT is disabled/unavailable).  It also helps ensure there can't be
any accidental leakage of initialization or state between the dummy
initialization for GMD_ID and the real driver initialization of the GT.

v2:
 - Initialize gt->tile for temporary GT.  (CI, Michal)
 - Use scope-based cleanup handler to free temp GT.  (Michal)
 - Propagate actual error code from xe_gt_sriov_vf_bootstrap() rather
   than just setting IP version to 0.0 now that read_gmdid() can return
   an error.  (Michal)

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/tests/xe_pci.c |  6 ++-
 drivers/gpu/drm/xe/xe_pci.c       | 70 ++++++++++++++++++-------------
 2 files changed, 45 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/xe/tests/xe_pci.c b/drivers/gpu/drm/xe/tests/xe_pci.c
index 0f136bc85b76..969f1dacade8 100644
--- a/drivers/gpu/drm/xe/tests/xe_pci.c
+++ b/drivers/gpu/drm/xe/tests/xe_pci.c
@@ -307,8 +307,8 @@ const void *xe_pci_id_gen_param(const void *prev, char *desc)
 }
 EXPORT_SYMBOL_IF_KUNIT(xe_pci_id_gen_param);
 
-static void fake_read_gmdid(struct xe_device *xe, enum xe_gmdid_type type,
-			    u32 *ver, u32 *revid)
+static int fake_read_gmdid(struct xe_device *xe, enum xe_gmdid_type type,
+			   u32 *ver, u32 *revid)
 {
 	struct kunit *test = kunit_get_current_test();
 	struct xe_pci_fake_data *data = test->priv;
@@ -320,6 +320,8 @@ static void fake_read_gmdid(struct xe_device *xe, enum xe_gmdid_type type,
 		*ver = data->graphics_verx100;
 		*revid = xe_step_to_gmdid(data->step.graphics);
 	}
+
+	return 0;
 }
 
 static void fake_xe_info_probe_tile_count(struct xe_device *xe)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 37ae49f4b648..02655cf9244d 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -464,7 +464,7 @@ enum xe_gmdid_type {
 	GMDID_MEDIA
 };
 
-static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid)
+static int read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid)
 {
 	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
 	struct xe_reg gmdid_reg = GMD_ID;
@@ -473,22 +473,24 @@ static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver,
 	KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid);
 
 	if (IS_SRIOV_VF(xe)) {
-		struct xe_gt *gt = xe_root_mmio_gt(xe);
-
 		/*
 		 * To get the value of the GMDID register, VFs must obtain it
 		 * from the GuC using MMIO communication.
 		 *
-		 * Note that at this point the xe_gt is not fully uninitialized
-		 * and only basic access to MMIO registers is possible. To use
-		 * our existing GuC communication functions we must perform at
-		 * least basic xe_gt and xe_guc initialization.
-		 *
-		 * Since to obtain the value of GMDID_MEDIA we need to use the
-		 * media GuC, temporarily tweak the gt type.
+		 * Note that at this point the GTs are not initialized and only
+		 * tile-level access to MMIO registers is possible. To use our
+		 * existing GuC communication functions we must create a dummy
+		 * GT structure and perform at least basic xe_gt and xe_guc
+		 * initialization.
 		 */
-		xe_gt_assert(gt, gt->info.type == XE_GT_TYPE_UNINITIALIZED);
+		struct xe_gt *gt __free(kfree);
+		int err;
 
+		gt = kzalloc(sizeof(*gt), GFP_KERNEL);
+		if (!gt)
+			return -ENOMEM;
+
+		gt->tile = &xe->tiles[0];
 		if (type == GMDID_MEDIA) {
 			gt->info.id = 1;
 			gt->info.type = XE_GT_TYPE_MEDIA;
@@ -500,15 +502,11 @@ static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver,
 		xe_gt_mmio_init(gt);
 		xe_guc_comm_init_early(&gt->uc.guc);
 
-		/* Don't bother with GMDID if failed to negotiate the GuC ABI */
-		val = xe_gt_sriov_vf_bootstrap(gt) ? 0 : xe_gt_sriov_vf_gmdid(gt);
+		err = xe_gt_sriov_vf_bootstrap(gt);
+		if (err)
+			return err;
 
-		/*
-		 * Only undo xe_gt.info here, the remaining changes made above
-		 * will be overwritten as part of the regular initialization.
-		 */
-		gt->info.id = 0;
-		gt->info.type = XE_GT_TYPE_UNINITIALIZED;
+		val = xe_gt_sriov_vf_gmdid(gt);
 	} else {
 		/*
 		 * GMD_ID is a GT register, but at this point in the driver
@@ -526,6 +524,8 @@ static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver,
 
 	*ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
 	*revid = REG_FIELD_GET(GMD_ID_REVID, val);
+
+	return 0;
 }
 
 static const struct xe_ip *find_graphics_ip(unsigned int verx100)
@@ -552,18 +552,21 @@ static const struct xe_ip *find_media_ip(unsigned int verx100)
  * Read IP version from hardware and select graphics/media IP descriptors
  * based on the result.
  */
-static void handle_gmdid(struct xe_device *xe,
-			 const struct xe_ip **graphics_ip,
-			 const struct xe_ip **media_ip,
-			 u32 *graphics_revid,
-			 u32 *media_revid)
+static int handle_gmdid(struct xe_device *xe,
+			const struct xe_ip **graphics_ip,
+			const struct xe_ip **media_ip,
+			u32 *graphics_revid,
+			u32 *media_revid)
 {
 	u32 ver;
+	int ret;
 
 	*graphics_ip = NULL;
 	*media_ip = NULL;
 
-	read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid);
+	ret = read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid);
+	if (ret)
+		return ret;
 
 	*graphics_ip = find_graphics_ip(ver);
 	if (!*graphics_ip) {
@@ -571,16 +574,21 @@ static void handle_gmdid(struct xe_device *xe,
 			ver / 100, ver % 100);
 	}
 
-	read_gmdid(xe, GMDID_MEDIA, &ver, media_revid);
+	ret = read_gmdid(xe, GMDID_MEDIA, &ver, media_revid);
+	if (ret)
+		return ret;
+
 	/* Media may legitimately be fused off / not present */
 	if (ver == 0)
-		return;
+		return 0;
 
 	*media_ip = find_media_ip(ver);
 	if (!*media_ip) {
 		drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n",
 			ver / 100, ver % 100);
 	}
+
+	return 0;
 }
 
 /*
@@ -690,6 +698,7 @@ static int xe_info_init(struct xe_device *xe,
 	const struct xe_media_desc *media_desc;
 	struct xe_tile *tile;
 	struct xe_gt *gt;
+	int ret;
 	u8 id;
 
 	/*
@@ -705,8 +714,11 @@ static int xe_info_init(struct xe_device *xe,
 		xe->info.step = xe_step_pre_gmdid_get(xe);
 	} else {
 		xe_assert(xe, !desc->pre_gmdid_media_ip);
-		handle_gmdid(xe, &graphics_ip, &media_ip,
-			     &graphics_gmdid_revid, &media_gmdid_revid);
+		ret = handle_gmdid(xe, &graphics_ip, &media_ip,
+				   &graphics_gmdid_revid, &media_gmdid_revid);
+		if (ret)
+			return ret;
+
 		xe->info.step = xe_step_gmdid_get(xe,
 						  graphics_gmdid_revid,
 						  media_gmdid_revid);
-- 
2.51.0

[PATCH v4 08/23] drm/xe: Move primary GT allocation from xe_tile_init_early to xe_tile_init

[Matt Roper]

During the early days of the Xe driver, there were cases where we
accessed some fields in the primary GT's xe_gt structure before the GT
itself was formally initialized; this required that the structure itself
be allocated during xe_tile_init_early().  A lot of refactoring of the
device probe has happened since that time and there's no longer a need
to allocate the primary GT early.  Move the allocation into
xe_info_init() where GT initialization happens and where we're doing the
allocation of the media GT.

v2:
 - Only make this change after a separate patch to perform VF GMD_ID
   lookup with a dummy GT instead of xe_root_mmio_gt().

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c  | 4 ++++
 drivers/gpu/drm/xe/xe_tile.c | 4 ----
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 02655cf9244d..a49e7cf8c73e 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -773,6 +773,10 @@ static int xe_info_init(struct xe_device *xe,
 	for_each_tile(tile, xe, id) {
 		int err;
 
+		tile->primary_gt = xe_gt_alloc(tile);
+		if (IS_ERR(tile->primary_gt))
+			return PTR_ERR(tile->primary_gt);
+
 		gt = tile->primary_gt;
 		gt->info.type = XE_GT_TYPE_MAIN;
 		gt->info.id = tile->id * xe->info.max_gt_per_tile;
diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
index 6edb5062c1da..786f085aaebd 100644
--- a/drivers/gpu/drm/xe/xe_tile.c
+++ b/drivers/gpu/drm/xe/xe_tile.c
@@ -157,10 +157,6 @@ int xe_tile_init_early(struct xe_tile *tile, struct xe_device *xe, u8 id)
 	if (err)
 		return err;
 
-	tile->primary_gt = xe_gt_alloc(tile);
-	if (IS_ERR(tile->primary_gt))
-		return PTR_ERR(tile->primary_gt);
-
 	xe_pcode_init(tile);
 
 	return 0;
-- 
2.51.0

[PATCH v4 09/23] drm/xe: Skip L2 / TDF cache flushes if primary GT is disabled

[Matt Roper]

If the primary GT is disabled via configfs, GT-side L2 and TD cache
flushes are unnecessary since nothing is using/filling these caches.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
 drivers/gpu/drm/xe/xe_device.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 386940323630..d42d03b8ab3a 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -1062,6 +1062,8 @@ void xe_device_l2_flush(struct xe_device *xe)
 	unsigned int fw_ref;
 
 	gt = xe_root_mmio_gt(xe);
+	if (!gt)
+		return;
 
 	if (!XE_GT_WA(gt, 16023588340))
 		return;
@@ -1107,6 +1109,9 @@ void xe_device_td_flush(struct xe_device *xe)
 		return;
 
 	root_gt = xe_root_mmio_gt(xe);
+	if (!root_gt)
+		return;
+
 	if (XE_GT_WA(root_gt, 16023588340)) {
 		/* A transient flush is not sufficient: flush the L2 */
 		xe_device_l2_flush(xe);
-- 
2.51.0

[PATCH v4 10/23] drm/xe/query: Report hwconfig size as 0 if primary GT is disabled

[Matt Roper]

The hwconfig table is part of the primary GT's GuC firmware.  If the
primary GT is disabled, the hwconfig is unavailable and should be
reported to userspace as having size 0.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
 drivers/gpu/drm/xe/xe_query.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
index 2e9ff33ed2fe..1c0915e2cc16 100644
--- a/drivers/gpu/drm/xe/xe_query.c
+++ b/drivers/gpu/drm/xe/xe_query.c
@@ -436,7 +436,7 @@ static int query_hwconfig(struct xe_device *xe,
 			  struct drm_xe_device_query *query)
 {
 	struct xe_gt *gt = xe_root_mmio_gt(xe);
-	size_t size = xe_guc_hwconfig_size(&gt->uc.guc);
+	size_t size = gt ? xe_guc_hwconfig_size(&gt->uc.guc) : 0;
 	void __user *query_ptr = u64_to_user_ptr(query->data);
 	void *hwconfig;
 
-- 
2.51.0

[PATCH v4 11/23] drm/xe/pmu: Initialize PMU event types based on first available GT

[Matt Roper]

GT ID#0 (primary GT on tile 0) may not always be available if the
primary GT has been disabled via configfs.  Instead use the first
available GT when determining which PMU events are supported.  If there
are no GTs, then don't advertise any GT-related events.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_pmu.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
index cab51d826345..c63335eb69e5 100644
--- a/drivers/gpu/drm/xe/xe_pmu.c
+++ b/drivers/gpu/drm/xe/xe_pmu.c
@@ -497,7 +497,12 @@ static const struct attribute_group *pmu_events_attr_update[] = {
 static void set_supported_events(struct xe_pmu *pmu)
 {
 	struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
-	struct xe_gt *gt = xe_device_get_gt(xe, 0);
+	struct xe_gt *gt;
+	int id;
+
+	/* If there are no GTs, don't support any GT-related events */
+	if (xe->info.gt_count == 0)
+		return;
 
 	if (!xe->info.skip_guc_pc) {
 		pmu->supported_events |= BIT_ULL(XE_PMU_EVENT_GT_C6_RESIDENCY);
@@ -505,6 +510,10 @@ static void set_supported_events(struct xe_pmu *pmu)
 		pmu->supported_events |= BIT_ULL(XE_PMU_EVENT_GT_REQUESTED_FREQUENCY);
 	}
 
+	/* Find the first available GT to query engine event capabilities */
+	for_each_gt(gt, xe, id)
+		break;
+
 	if (xe_guc_engine_activity_supported(&gt->uc.guc)) {
 		pmu->supported_events |= BIT_ULL(XE_PMU_EVENT_ENGINE_ACTIVE_TICKS);
 		pmu->supported_events |= BIT_ULL(XE_PMU_EVENT_ENGINE_TOTAL_TICKS);
-- 
2.51.0

[PATCH v4 12/23] drm/xe: Check for primary GT before looking up Wa_22019338487

[Matt Roper]

If the primary GT is disabled via configfs, we need to make sure that we
don't search for this workaround on a NULL xe_gt pointer.  Since we can
disable the primary GT only on igpu platforms, the media GT is the one
we'd want to check anyway for this workaround.

The ternary operators in ggtt_update_access_counter() were getting a bit
long/complicated, so rewrite them with regular if/else statements.
While we're at it, throw in a couple extra assertions to make sure that
we're truly picking the expected GT according to igpu/dgpu type.

v2:
 - Adjust indentation/wrapping; it's easier to read this with longer,
   unwrapped lines.  (Lucas)
 - Tweak wording of commit message to remove ambiguity.  (Gustavo)

Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_ggtt.c | 31 ++++++++++++++++++++++---------
 1 file changed, 22 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 7fdd0a97a628..9707c41539c8 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -107,10 +107,23 @@ static unsigned int probe_gsm_size(struct pci_dev *pdev)
 static void ggtt_update_access_counter(struct xe_ggtt *ggtt)
 {
 	struct xe_tile *tile = ggtt->tile;
-	struct xe_gt *affected_gt = XE_GT_WA(tile->primary_gt, 22019338487) ?
-		tile->primary_gt : tile->media_gt;
-	struct xe_mmio *mmio = &affected_gt->mmio;
-	u32 max_gtt_writes = XE_GT_WA(ggtt->tile->primary_gt, 22019338487) ? 1100 : 63;
+	struct xe_gt *affected_gt;
+	u32 max_gtt_writes;
+
+	if (tile->primary_gt && XE_GT_WA(tile->primary_gt, 22019338487)) {
+		affected_gt = tile->primary_gt;
+		max_gtt_writes = 1100;
+
+		/* Only expected to apply to primary GT on dgpu platforms */
+		xe_tile_assert(tile, IS_DGFX(tile_to_xe(tile)));
+	} else {
+		affected_gt = tile->media_gt;
+		max_gtt_writes = 63;
+
+		/* Only expected to apply to media GT on igpu platforms */
+		xe_tile_assert(tile, !IS_DGFX(tile_to_xe(tile)));
+	}
+
 	/*
 	 * Wa_22019338487: GMD_ID is a RO register, a dummy write forces gunit
 	 * to wait for completion of prior GTT writes before letting this through.
@@ -119,7 +132,7 @@ static void ggtt_update_access_counter(struct xe_ggtt *ggtt)
 	lockdep_assert_held(&ggtt->lock);
 
 	if ((++ggtt->access_count % max_gtt_writes) == 0) {
-		xe_mmio_write32(mmio, GMD_ID, 0x0);
+		xe_mmio_write32(&affected_gt->mmio, GMD_ID, 0x0);
 		ggtt->access_count = 0;
 	}
 }
@@ -284,10 +297,10 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt)
 		ggtt->size = GUC_GGTT_TOP;
 
 	if (GRAPHICS_VERx100(xe) >= 1270)
-		ggtt->pt_ops = (ggtt->tile->media_gt &&
-			       XE_GT_WA(ggtt->tile->media_gt, 22019338487)) ||
-			       XE_GT_WA(ggtt->tile->primary_gt, 22019338487) ?
-			       &xelpg_pt_wa_ops : &xelpg_pt_ops;
+		ggtt->pt_ops =
+			(ggtt->tile->media_gt && XE_GT_WA(ggtt->tile->media_gt, 22019338487)) ||
+			(ggtt->tile->primary_gt && XE_GT_WA(ggtt->tile->primary_gt, 22019338487)) ?
+			&xelpg_pt_wa_ops : &xelpg_pt_ops;
 	else
 		ggtt->pt_ops = &xelp_pt_ops;
 
-- 
2.51.0

[PATCH v4 13/23] drm/xe: Make display part of Wa_22019338487 a device workaround

[Matt Roper]

The display part of Wa_22019338487 (i.e., avoiding use of stolen memory)
is using a platform test rather than an graphics/media IP test.  Since
this workaround is focused on non-GT uses of stolen memory, it makes
sense that we'd want to still apply the workaround on affected platforms
even if the GTs themselves are disabled via configfs.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/display/intel_fbdev_fb.c   | 4 ++--
 drivers/gpu/drm/xe/display/xe_plane_initial.c | 4 ++--
 drivers/gpu/drm/xe/xe_device_wa_oob.rules     | 1 +
 drivers/gpu/drm/xe/xe_wa_oob.rules            | 1 -
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
index 35a5b07eeba4..af72f7305e5a 100644
--- a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
+++ b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
@@ -10,7 +10,7 @@
 #include "xe_ttm_stolen_mgr.h"
 #include "xe_wa.h"
 
-#include <generated/xe_wa_oob.h>
+#include <generated/xe_device_wa_oob.h>
 
 struct drm_gem_object *intel_fbdev_fb_bo_create(struct drm_device *drm, int size)
 {
@@ -19,7 +19,7 @@ struct drm_gem_object *intel_fbdev_fb_bo_create(struct drm_device *drm, int size
 
 	obj = ERR_PTR(-ENODEV);
 
-	if (!IS_DGFX(xe) && !XE_GT_WA(xe_root_mmio_gt(xe), 22019338487_display)) {
+	if (!IS_DGFX(xe) && !XE_DEVICE_WA(xe, 22019338487_display)) {
 		obj = xe_bo_create_pin_map_novm(xe, xe_device_get_root_tile(xe),
 						size,
 						ttm_bo_type_kernel, XE_BO_FLAG_SCANOUT |
diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c
index 94f00def811b..12d25c5290fd 100644
--- a/drivers/gpu/drm/xe/display/xe_plane_initial.c
+++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c
@@ -25,7 +25,7 @@
 #include "xe_vram_types.h"
 #include "xe_wa.h"
 
-#include <generated/xe_wa_oob.h>
+#include <generated/xe_device_wa_oob.h>
 
 void intel_plane_initial_vblank_wait(struct intel_crtc *crtc)
 {
@@ -123,7 +123,7 @@ initial_plane_bo(struct xe_device *xe,
 		phys_base = base;
 		flags |= XE_BO_FLAG_STOLEN;
 
-		if (XE_GT_WA(xe_root_mmio_gt(xe), 22019338487_display))
+		if (XE_DEVICE_WA(xe, 22019338487_display))
 			return NULL;
 
 		/*
diff --git a/drivers/gpu/drm/xe/xe_device_wa_oob.rules b/drivers/gpu/drm/xe/xe_device_wa_oob.rules
index 3a0c4ccc4224..3cc93f0e77f8 100644
--- a/drivers/gpu/drm/xe/xe_device_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_device_wa_oob.rules
@@ -1,2 +1,3 @@
 15015404425     PLATFORM(LUNARLAKE)
 		PLATFORM(PANTHERLAKE)
+22019338487_display	PLATFORM(LUNARLAKE)
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index f3a6d5d239ce..eb761d30e066 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -45,7 +45,6 @@
 22019338487	MEDIA_VERSION(2000)
 		GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_not_sriov_vf)
 		MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), FUNC(xe_rtp_match_not_sriov_vf)
-22019338487_display	PLATFORM(LUNARLAKE)
 16023588340	GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_not_sriov_vf)
 14019789679	GRAPHICS_VERSION(1255)
 		GRAPHICS_VERSION_RANGE(1270, 2004)
-- 
2.51.0

[PATCH v4 14/23] drm/xe/irq: Don't try to lookup engine masks for non-existent primary GT

[Matt Roper]

If the primary GT is disabled via configfs, we shouldn't try to access
it to lookup BCS/CCS engine masks.  For the purposes of IRQ reset (which
masks & disables interrupts in an sgunit register), assume all possible
instances are present.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
 drivers/gpu/drm/xe/xe_irq.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 5018a116852f..eaca56df08e4 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -494,11 +494,15 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
 static void gt_irq_reset(struct xe_tile *tile)
 {
 	struct xe_mmio *mmio = &tile->mmio;
+	u32 ccs_mask = ~0;
+	u32 bcs_mask = ~0;
 
-	u32 ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt,
-						   XE_ENGINE_CLASS_COMPUTE);
-	u32 bcs_mask = xe_hw_engine_mask_per_class(tile->primary_gt,
-						   XE_ENGINE_CLASS_COPY);
+	if (tile->primary_gt) {
+		ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt,
+						       XE_ENGINE_CLASS_COMPUTE);
+		bcs_mask = xe_hw_engine_mask_per_class(tile->primary_gt,
+						       XE_ENGINE_CLASS_COPY);
+	}
 
 	/* Disable RCS, BCS, VCS and VECS class engines. */
 	xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, 0);
-- 
2.51.0

[PATCH v4 15/23] drm/xe: Handle Wa_22010954014 and Wa_14022085890 as device workarounds

[Matt Roper]

When Wa_22010954014 and Wa_14022085890 were first implemented, we didn't
have a device workaround infrastructure so we hacked them into the GT
workaround list.  Now that we have proper device workaround support,
move them to the proper place.  Note that Wa_14022085890 specifically
applies to BMG-G21 platforms, so this requires defining a BMG
subplatform to capture the correct subset of device IDs.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_device_wa_oob.rules | 2 ++
 drivers/gpu/drm/xe/xe_guc_pc.c            | 3 ++-
 drivers/gpu/drm/xe/xe_pci.c               | 6 ++++++
 drivers/gpu/drm/xe/xe_platform_types.h    | 1 +
 drivers/gpu/drm/xe/xe_wa.c                | 2 +-
 drivers/gpu/drm/xe/xe_wa_oob.rules        | 5 -----
 include/drm/intel/pciids.h                | 7 +++++--
 7 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_device_wa_oob.rules b/drivers/gpu/drm/xe/xe_device_wa_oob.rules
index 3cc93f0e77f8..55ba01bc8f38 100644
--- a/drivers/gpu/drm/xe/xe_device_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_device_wa_oob.rules
@@ -1,3 +1,5 @@
+22010954014	PLATFORM(DG2)
 15015404425     PLATFORM(LUNARLAKE)
 		PLATFORM(PANTHERLAKE)
 22019338487_display	PLATFORM(LUNARLAKE)
+14022085890	SUBPLATFORM(BATTLEMAGE, G21)
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 3c0feb50a1e2..ff22235857f8 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -14,6 +14,7 @@
 
 #include <drm/drm_managed.h>
 #include <drm/drm_print.h>
+#include <generated/xe_device_wa_oob.h>
 #include <generated/xe_wa_oob.h>
 
 #include "abi/guc_actions_slpc_abi.h"
@@ -886,7 +887,7 @@ static int pc_adjust_freq_bounds(struct xe_guc_pc *pc)
 	if (pc_get_min_freq(pc) > pc->rp0_freq)
 		ret = pc_set_min_freq(pc, pc->rp0_freq);
 
-	if (XE_GT_WA(tile->primary_gt, 14022085890))
+	if (XE_DEVICE_WA(tile_to_xe(tile), 14022085890))
 		ret = pc_set_min_freq(pc, max(BMG_MIN_FREQ, pc_get_min_freq(pc)));
 
 out:
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index a49e7cf8c73e..f7aec1c5959b 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -334,6 +334,8 @@ static const struct xe_device_desc lnl_desc = {
 	.vm_max_level = 4,
 };
 
+static const u16 bmg_g21_ids[] = { INTEL_BMG_G21_IDS(NOP), 0 };
+
 static const struct xe_device_desc bmg_desc = {
 	DGFX_FEATURES,
 	PLATFORM(BATTLEMAGE),
@@ -348,6 +350,10 @@ static const struct xe_device_desc bmg_desc = {
 	.has_sriov = true,
 	.max_gt_per_tile = 2,
 	.needs_scratch = true,
+	.subplatforms = (const struct xe_subplatform_desc[]) {
+		{ XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids },
+		{ }
+	},
 	.va_bits = 48,
 	.vm_max_level = 4,
 };
diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
index d08574c4cdb8..3e332214c7bb 100644
--- a/drivers/gpu/drm/xe/xe_platform_types.h
+++ b/drivers/gpu/drm/xe/xe_platform_types.h
@@ -34,6 +34,7 @@ enum xe_subplatform {
 	XE_SUBPLATFORM_DG2_G10,
 	XE_SUBPLATFORM_DG2_G11,
 	XE_SUBPLATFORM_DG2_G12,
+	XE_SUBPLATFORM_BATTLEMAGE_G21,
 };
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index c60159a13001..aa1b69f48f6f 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -1138,6 +1138,6 @@ void xe_wa_apply_tile_workarounds(struct xe_tile *tile)
 	if (IS_SRIOV_VF(tile->xe))
 		return;
 
-	if (XE_GT_WA(tile->primary_gt, 22010954014))
+	if (XE_DEVICE_WA(tile->xe, 22010954014))
 		xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
 }
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index eb761d30e066..113a62f1b541 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -14,7 +14,6 @@
 14016763929	SUBPLATFORM(DG2, G10)
 		SUBPLATFORM(DG2, G12)
 16017236439	PLATFORM(PVC)
-22010954014	PLATFORM(DG2)
 14019821291	MEDIA_VERSION_RANGE(1300, 2000)
 14015076503	MEDIA_VERSION(1300)
 16020292621	GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)
@@ -74,9 +73,5 @@
 16023683509	MEDIA_VERSION(2000), FUNC(xe_rtp_match_psmi_enabled)
 		MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), FUNC(xe_rtp_match_psmi_enabled)
 
-# SoC workaround - currently applies to all platforms with the following
-# primary GT GMDID
-14022085890	GRAPHICS_VERSION(2001)
-
 15015404425_disable	PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER)
 16026007364    MEDIA_VERSION(3000)
diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
index 69d4ae92d822..452c1de606ff 100644
--- a/include/drm/intel/pciids.h
+++ b/include/drm/intel/pciids.h
@@ -849,7 +849,7 @@
 	MACRO__(0x64B0, ## __VA_ARGS__)
 
 /* BMG */
-#define INTEL_BMG_IDS(MACRO__, ...) \
+#define INTEL_BMG_G21_IDS(MACRO__, ...) \
 	MACRO__(0xE202, ## __VA_ARGS__), \
 	MACRO__(0xE209, ## __VA_ARGS__), \
 	MACRO__(0xE20B, ## __VA_ARGS__), \
@@ -858,7 +858,10 @@
 	MACRO__(0xE210, ## __VA_ARGS__), \
 	MACRO__(0xE211, ## __VA_ARGS__), \
 	MACRO__(0xE212, ## __VA_ARGS__), \
-	MACRO__(0xE216, ## __VA_ARGS__), \
+	MACRO__(0xE216, ## __VA_ARGS__)
+
+#define INTEL_BMG_IDS(MACRO__, ...) \
+	INTEL_BMG_G21_IDS(MACRO__, __VA_ARGS__), \
 	MACRO__(0xE220, ## __VA_ARGS__), \
 	MACRO__(0xE221, ## __VA_ARGS__), \
 	MACRO__(0xE222, ## __VA_ARGS__), \
-- 
2.51.0

[PATCH v4 16/23] drm/xe/rtp: Pass xe_device parameter to FUNC matches

[Matt Roper]

FUNC matches in RTP only pass the GT and hwe, preventing them from being
used effectively in device workarounds.  Add an additional xe_device
parameter so that we can use them in device workarounds where a GT may
not be available.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/tests/xe_rtp_test.c |  6 ++++--
 drivers/gpu/drm/xe/xe_hw_engine.c      | 10 ++++++----
 drivers/gpu/drm/xe/xe_reg_whitelist.c  |  3 ++-
 drivers/gpu/drm/xe/xe_rtp.c            | 24 +++++++++++++-----------
 drivers/gpu/drm/xe/xe_rtp.h            | 18 +++++++++++++-----
 drivers/gpu/drm/xe/xe_rtp_types.h      |  4 +++-
 6 files changed, 41 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
index b0254b014fe4..d2255a59e58f 100644
--- a/drivers/gpu/drm/xe/tests/xe_rtp_test.c
+++ b/drivers/gpu/drm/xe/tests/xe_rtp_test.c
@@ -48,12 +48,14 @@ struct rtp_test_case {
 	const struct xe_rtp_entry *entries;
 };
 
-static bool match_yes(const struct xe_gt *gt, const struct xe_hw_engine *hwe)
+static bool match_yes(const struct xe_device *xe, const struct xe_gt *gt,
+		      const struct xe_hw_engine *hwe)
 {
 	return true;
 }
 
-static bool match_no(const struct xe_gt *gt, const struct xe_hw_engine *hwe)
+static bool match_no(const struct xe_device *xe, const struct xe_gt *gt,
+		     const struct xe_hw_engine *hwe)
 {
 	return false;
 }
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 1cf623b4a5bc..cba4375525c7 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -346,17 +346,19 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
 	xe_hw_engine_mmio_read32(hwe, RING_MI_MODE(0));
 }
 
-static bool xe_hw_engine_match_fixed_cslice_mode(const struct xe_gt *gt,
+static bool xe_hw_engine_match_fixed_cslice_mode(const struct xe_device *xe,
+						 const struct xe_gt *gt,
 						 const struct xe_hw_engine *hwe)
 {
 	return xe_gt_ccs_mode_enabled(gt) &&
-	       xe_rtp_match_first_render_or_compute(gt, hwe);
+	       xe_rtp_match_first_render_or_compute(xe, gt, hwe);
 }
 
-static bool xe_rtp_cfeg_wmtp_disabled(const struct xe_gt *gt,
+static bool xe_rtp_cfeg_wmtp_disabled(const struct xe_device *xe,
+				      const struct xe_gt *gt,
 				      const struct xe_hw_engine *hwe)
 {
-	if (GRAPHICS_VER(gt_to_xe(gt)) < 20)
+	if (GRAPHICS_VER(xe) < 20)
 		return false;
 
 	if (hwe->class != XE_ENGINE_CLASS_COMPUTE &&
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index 23f6c81d9994..690bc327a363 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -19,7 +19,8 @@
 #undef XE_REG_MCR
 #define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
 
-static bool match_not_render(const struct xe_gt *gt,
+static bool match_not_render(const struct xe_device *xe,
+			     const struct xe_gt *gt,
 			     const struct xe_hw_engine *hwe)
 {
 	return hwe->class != XE_ENGINE_CLASS_RENDER;
diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
index b5f430d59f80..66707cc89ec9 100644
--- a/drivers/gpu/drm/xe/xe_rtp.c
+++ b/drivers/gpu/drm/xe/xe_rtp.c
@@ -133,10 +133,7 @@ static bool rule_matches(const struct xe_device *xe,
 			match = hwe->class != r->engine_class;
 			break;
 		case XE_RTP_MATCH_FUNC:
-			if (drm_WARN_ON(&xe->drm, !gt))
-				return false;
-
-			match = r->match_func(gt, hwe);
+			match = r->match_func(xe, gt, hwe);
 			break;
 		default:
 			drm_warn(&xe->drm, "Invalid RTP match %u\n",
@@ -343,13 +340,15 @@ void xe_rtp_process(struct xe_rtp_process_ctx *ctx,
 }
 EXPORT_SYMBOL_IF_KUNIT(xe_rtp_process);
 
-bool xe_rtp_match_even_instance(const struct xe_gt *gt,
+bool xe_rtp_match_even_instance(const struct xe_device *xe,
+				const struct xe_gt *gt,
 				const struct xe_hw_engine *hwe)
 {
 	return hwe->instance % 2 == 0;
 }
 
-bool xe_rtp_match_first_render_or_compute(const struct xe_gt *gt,
+bool xe_rtp_match_first_render_or_compute(const struct xe_device *xe,
+					  const struct xe_gt *gt,
 					  const struct xe_hw_engine *hwe)
 {
 	u64 render_compute_mask = gt->info.engine_mask &
@@ -359,19 +358,22 @@ bool xe_rtp_match_first_render_or_compute(const struct xe_gt *gt,
 		hwe->engine_id == __ffs(render_compute_mask);
 }
 
-bool xe_rtp_match_not_sriov_vf(const struct xe_gt *gt,
+bool xe_rtp_match_not_sriov_vf(const struct xe_device *xe,
+			       const struct xe_gt *gt,
 			       const struct xe_hw_engine *hwe)
 {
-	return !IS_SRIOV_VF(gt_to_xe(gt));
+	return !IS_SRIOV_VF(xe);
 }
 
-bool xe_rtp_match_psmi_enabled(const struct xe_gt *gt,
+bool xe_rtp_match_psmi_enabled(const struct xe_device *xe,
+			       const struct xe_gt *gt,
 			       const struct xe_hw_engine *hwe)
 {
-	return xe_configfs_get_psmi_enabled(to_pci_dev(gt_to_xe(gt)->drm.dev));
+	return xe_configfs_get_psmi_enabled(to_pci_dev(xe->drm.dev));
 }
 
-bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,
+bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_device *xe,
+						  const struct xe_gt *gt,
 						  const struct xe_hw_engine *hwe)
 {
 	return xe_gt_has_discontiguous_dss_groups(gt);
diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index ac12ddf6cde6..e5b8a9452e29 100644
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -440,18 +440,21 @@ void xe_rtp_process(struct xe_rtp_process_ctx *ctx,
 
 /**
  * xe_rtp_match_even_instance - Match if engine instance is even
+ * @xe: Device structure
  * @gt: GT structure
  * @hwe: Engine instance
  *
  * Returns: true if engine instance is even, false otherwise
  */
-bool xe_rtp_match_even_instance(const struct xe_gt *gt,
+bool xe_rtp_match_even_instance(const struct xe_device *xe,
+				const struct xe_gt *gt,
 				const struct xe_hw_engine *hwe);
 
 /*
  * xe_rtp_match_first_render_or_compute - Match if it's first render or compute
  * engine in the GT
  *
+ * @xe: Device structure
  * @gt: GT structure
  * @hwe: Engine instance
  *
@@ -463,24 +466,29 @@ bool xe_rtp_match_even_instance(const struct xe_gt *gt,
  * Returns: true if engine id is the first to match the render reset domain,
  * false otherwise.
  */
-bool xe_rtp_match_first_render_or_compute(const struct xe_gt *gt,
+bool xe_rtp_match_first_render_or_compute(const struct xe_device *xe,
+					  const struct xe_gt *gt,
 					  const struct xe_hw_engine *hwe);
 
 /*
  * xe_rtp_match_not_sriov_vf - Match when not on SR-IOV VF device
  *
+ * @xe: Device structure
  * @gt: GT structure
  * @hwe: Engine instance
  *
  * Returns: true if device is not VF, false otherwise.
  */
-bool xe_rtp_match_not_sriov_vf(const struct xe_gt *gt,
+bool xe_rtp_match_not_sriov_vf(const struct xe_device *xe,
+			       const struct xe_gt *gt,
 			       const struct xe_hw_engine *hwe);
 
-bool xe_rtp_match_psmi_enabled(const struct xe_gt *gt,
+bool xe_rtp_match_psmi_enabled(const struct xe_device *xe,
+			       const struct xe_gt *gt,
 			       const struct xe_hw_engine *hwe);
 
-bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,
+bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_device *xe,
+						  const struct xe_gt *gt,
 						  const struct xe_hw_engine *hwe);
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
index f4cf30e298cf..6ba7f226c227 100644
--- a/drivers/gpu/drm/xe/xe_rtp_types.h
+++ b/drivers/gpu/drm/xe/xe_rtp_types.h
@@ -10,6 +10,7 @@
 
 #include "regs/xe_reg_defs.h"
 
+struct xe_device;
 struct xe_hw_engine;
 struct xe_gt;
 
@@ -86,7 +87,8 @@ struct xe_rtp_rule {
 			u8 engine_class;
 		};
 		/* MATCH_FUNC */
-		bool (*match_func)(const struct xe_gt *gt,
+		bool (*match_func)(const struct xe_device *xe,
+				   const struct xe_gt *gt,
 				   const struct xe_hw_engine *hwe);
 	};
 };
-- 
2.51.0

[PATCH v4 17/23] drm/xe: Bypass Wa_14018094691 when primary GT is disabled

[Matt Roper]

Don't try to lookup Wa_14018094691 on a NULL GT when the primary GT is
disabled.  Since this whole workaround centers around mid-thread
preemption behavior, the workaround isn't relevant if the primary GT
(where the engines that can do MTP live) is disabled.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_gsc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gsc.c b/drivers/gpu/drm/xe/xe_gsc.c
index 83d61bf8ec62..dd69cb834f8e 100644
--- a/drivers/gpu/drm/xe/xe_gsc.c
+++ b/drivers/gpu/drm/xe/xe_gsc.c
@@ -266,7 +266,7 @@ static int gsc_upload_and_init(struct xe_gsc *gsc)
 	unsigned int fw_ref;
 	int ret;
 
-	if (XE_GT_WA(tile->primary_gt, 14018094691)) {
+	if (tile->primary_gt && XE_GT_WA(tile->primary_gt, 14018094691)) {
 		fw_ref = xe_force_wake_get(gt_to_fw(tile->primary_gt), XE_FORCEWAKE_ALL);
 
 		/*
@@ -281,7 +281,7 @@ static int gsc_upload_and_init(struct xe_gsc *gsc)
 
 	ret = gsc_upload(gsc);
 
-	if (XE_GT_WA(tile->primary_gt, 14018094691))
+	if (tile->primary_gt && XE_GT_WA(tile->primary_gt, 14018094691))
 		xe_force_wake_put(gt_to_fw(tile->primary_gt), fw_ref);
 
 	if (ret)
-- 
2.51.0

[PATCH v4 18/23] drm/xe: Correct lineage for Wa_22014953428 and only check with valid GT

[Matt Roper]

Wa_22014953428 was incorrectly labelled with a release-specific ID
number rather than the cross-platform lineage number; fix that.
Also check that the GT is not NULL before trying to lookup the
workaround in it.  Since this workaround only applies to DG2 discrete
GPUs (where the primary GT cannot be disabled), no coverage is lost.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_vm.c         | 3 ++-
 drivers/gpu/drm/xe/xe_wa_oob.rules | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 4e914928e0a9..b5e842faa613 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -1886,6 +1886,7 @@ int xe_vm_create_ioctl(struct drm_device *dev, void *data,
 	struct xe_device *xe = to_xe_device(dev);
 	struct xe_file *xef = to_xe_file(file);
 	struct drm_xe_vm_create *args = data;
+	struct xe_gt *wa_gt = xe_root_mmio_gt(xe);
 	struct xe_vm *vm;
 	u32 id;
 	int err;
@@ -1894,7 +1895,7 @@ int xe_vm_create_ioctl(struct drm_device *dev, void *data,
 	if (XE_IOCTL_DBG(xe, args->extensions))
 		return -EINVAL;
 
-	if (XE_GT_WA(xe_root_mmio_gt(xe), 14016763929))
+	if (wa_gt && XE_GT_WA(wa_gt, 22014953428))
 		args->flags |= DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE;
 
 	if (XE_IOCTL_DBG(xe, args->flags & DRM_XE_VM_CREATE_FLAG_FAULT_MODE &&
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 113a62f1b541..4bb94e5799ed 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -11,7 +11,7 @@
 18020744125	PLATFORM(PVC)
 1509372804	PLATFORM(PVC), GRAPHICS_STEP(A0, C0)
 1409600907	GRAPHICS_VERSION_RANGE(1200, 1250)
-14016763929	SUBPLATFORM(DG2, G10)
+22014953428	SUBPLATFORM(DG2, G10)
 		SUBPLATFORM(DG2, G12)
 16017236439	PLATFORM(PVC)
 14019821291	MEDIA_VERSION_RANGE(1300, 2000)
-- 
2.51.0

[PATCH v4 19/23] drm/xe: Check that GT is not NULL before testing Wa_16023588340

[Matt Roper]

If the primary GT is disabled, skip the check for this workaround (which
only applies to dgpu platforms where the primary GT cannot be NULL).

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
 drivers/gpu/drm/xe/display/xe_display_wa.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/display/xe_display_wa.c b/drivers/gpu/drm/xe/display/xe_display_wa.c
index 8ada1cbcb16c..2aa1b8c03411 100644
--- a/drivers/gpu/drm/xe/display/xe_display_wa.c
+++ b/drivers/gpu/drm/xe/display/xe_display_wa.c
@@ -13,6 +13,7 @@
 bool intel_display_needs_wa_16023588340(struct intel_display *display)
 {
 	struct xe_device *xe = to_xe_device(display->drm);
+	struct xe_gt *wa_gt = xe_root_mmio_gt(xe);
 
-	return XE_GT_WA(xe_root_mmio_gt(xe), 16023588340);
+	return wa_gt && XE_GT_WA(wa_gt, 16023588340);
 }
-- 
2.51.0

[PATCH v4 20/23] drm/xe: Don't check BIOS-disabled FlatCCS if primary GT is disabled

[Matt Roper]

If the primary is GT is disabled via configfs, we can't read the GT
registers that would tell us whether the BIOS has disabled FlatCCS on a
platform that would otherwise have it; we'll just proceed as if the
FlatCCS is still enabled.  This is similar to the situation seen by
SRIOV VFs and doesn't cause any functional problems since the hardware
will simply drop writes to the CCS region and reads will always come
back as 0 (indicating uncompressed data).  We'll simply miss out on the
chance to avoid some unnecessary overhead during BO creation and
migration.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_device.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index d42d03b8ab3a..82921d72ebfa 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -782,6 +782,8 @@ static int probe_has_flat_ccs(struct xe_device *xe)
 		return 0;
 
 	gt = xe_root_mmio_gt(xe);
+	if (!gt)
+		return 0;
 
 	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
 	if (!fw_ref)
-- 
2.51.0

[PATCH v4 21/23] drm/xe: Break GT setup out of xe_info_init()

[Matt Roper]

xe_info_init() is getting a bit long and hard to follow.  Break the
allocation and basic initialization of the xe_gt structures out to their
own functions.

v2:
 - Rename new functions from init_* to alloc_*.  (Gustavo)
 - Move early NULL return of media GT before allocation.  (Gustavo)

Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c | 88 +++++++++++++++++++++++--------------
 1 file changed, 54 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index f7aec1c5959b..a5932e4f4a23 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -688,6 +688,53 @@ static void xe_info_probe_tile_count(struct xe_device *xe)
 	}
 }
 
+static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
+				      const struct xe_graphics_desc *graphics_desc,
+				      const struct xe_media_desc *media_desc)
+{
+	struct xe_device *xe = tile_to_xe(tile);
+	struct xe_gt *gt;
+
+	gt = xe_gt_alloc(tile);
+	if (IS_ERR(gt))
+		return gt;
+
+	gt->info.type = XE_GT_TYPE_MAIN;
+	gt->info.id = tile->id * xe->info.max_gt_per_tile;
+	gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
+	gt->info.engine_mask = graphics_desc->hw_engine_mask;
+
+	/*
+	 * Before media version 13, the media IP was part of the primary GT
+	 * so we need to add the media engines to the primary GT's engine list.
+	 */
+	if (MEDIA_VER(xe) < 13 && media_desc)
+		gt->info.engine_mask |= media_desc->hw_engine_mask;
+
+	return gt;
+}
+
+static struct xe_gt *alloc_media_gt(struct xe_tile *tile,
+				    const struct xe_media_desc *media_desc)
+{
+	struct xe_device *xe = tile_to_xe(tile);
+	struct xe_gt *gt;
+
+	if (MEDIA_VER(xe) < 13 || !media_desc)
+		return NULL;
+
+	gt = xe_gt_alloc(tile);
+	if (IS_ERR(gt))
+		return gt;
+
+	gt->info.type = XE_GT_TYPE_MEDIA;
+	gt->info.id = tile->id * xe->info.max_gt_per_tile + 1;
+	gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state;
+	gt->info.engine_mask = media_desc->hw_engine_mask;
+
+	return gt;
+}
+
 /*
  * Initialize device info content that does require knowledge about
  * graphics / media IP version.
@@ -770,48 +817,21 @@ static int xe_info_init(struct xe_device *xe,
 			return err;
 	}
 
-	/*
-	 * All platforms have at least one primary GT.  Any platform with media
-	 * version 13 or higher has an additional dedicated media GT.  And
-	 * depending on the graphics IP there may be additional "remote tiles."
-	 * All of these together determine the overall GT count.
-	 */
+	/* Allocate any GT and VRAM structures necessary for the platform. */
 	for_each_tile(tile, xe, id) {
 		int err;
 
-		tile->primary_gt = xe_gt_alloc(tile);
+		err = xe_tile_alloc_vram(tile);
+		if (err)
+			return err;
+
+		tile->primary_gt = alloc_primary_gt(tile, graphics_desc, media_desc);
 		if (IS_ERR(tile->primary_gt))
 			return PTR_ERR(tile->primary_gt);
 
-		gt = tile->primary_gt;
-		gt->info.type = XE_GT_TYPE_MAIN;
-		gt->info.id = tile->id * xe->info.max_gt_per_tile;
-		gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
-		gt->info.engine_mask = graphics_desc->hw_engine_mask;
-
-		err = xe_tile_alloc_vram(tile);
-		if (err)
-			return err;
-
-		if (MEDIA_VER(xe) < 13 && media_desc)
-			gt->info.engine_mask |= media_desc->hw_engine_mask;
-
-		if (MEDIA_VER(xe) < 13 || !media_desc)
-			continue;
-
-		/*
-		 * Allocate and setup media GT for platforms with standalone
-		 * media.
-		 */
-		tile->media_gt = xe_gt_alloc(tile);
+		tile->media_gt = alloc_media_gt(tile, media_desc);
 		if (IS_ERR(tile->media_gt))
 			return PTR_ERR(tile->media_gt);
-
-		gt = tile->media_gt;
-		gt->info.type = XE_GT_TYPE_MEDIA;
-		gt->info.id = tile->id * xe->info.max_gt_per_tile + 1;
-		gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state;
-		gt->info.engine_mask = media_desc->hw_engine_mask;
 	}
 
 	/*
-- 
2.51.0

[PATCH v4 22/23] drm/xe/configfs: Add attribute to disable GT types

[Matt Roper]

Preventing the driver from initializing GTs of specific type(s) can be
useful for debugging and early hardware bringup.  Add a configfs
attribute to allow this kind of control for debugging.

With today's platforms and software design, this configuration setting
is only effective for disabling the media GT since the driver currently
requires that there always be a primary GT to probe the device.  However
this might change in the future ---  in theory it should be possible
(with some additional driver work) to allow an igpu device to come up
with only the media GT and no primary GT.  Or to allow an igpu device to
come up with no GTs at all (for display-only usage).  A primary GT will
likely always be required on dgpu platforms because we rely on the BCS
engines inside the primary GT for various vram operations.

v2:
 - Expand/clarify kerneldoc for configfs attribute.  (Gustavo)
 - Tighten type usage in gt_types[] structure.  (Gustavo)
 - Adjust string parsing/name matching to match exact GT names and not
   accept partial names.  (Gustavo)

v3:
 - Switch to scope-based cleanup in gt_types_allowed_store() to fix a
   leak if the device is already bound.  (Gustavo)
 - Switch configfs lookup interface to two boolean functions that
   specify whether primary/media are supported rather than one function
   that returns a mask.  This is simpler to use and understand.

Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_configfs.c | 145 +++++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_configfs.h |   4 +
 drivers/gpu/drm/xe/xe_pci.c      |  22 +++++
 3 files changed, 171 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
index 139663423185..e36cc5e1bc8f 100644
--- a/drivers/gpu/drm/xe/xe_configfs.c
+++ b/drivers/gpu/drm/xe/xe_configfs.c
@@ -15,6 +15,7 @@
 
 #include "instructions/xe_mi_commands.h"
 #include "xe_configfs.h"
+#include "xe_gt_types.h"
 #include "xe_hw_engine_types.h"
 #include "xe_module.h"
 #include "xe_pci_types.h"
@@ -56,6 +57,7 @@
  *	:
  *	└── 0000:03:00.0
  *	    ├── survivability_mode
+ *	    ├── gt_types_allowed
  *	    ├── engines_allowed
  *	    └── enable_psmi
  *
@@ -79,6 +81,44 @@
  *
  * This attribute can only be set before binding to the device.
  *
+ * Allowed GT types:
+ * -----------------
+ *
+ * Allow only specific types of GTs to be detected and initialized by the
+ * driver.  Any combination of GT types can be enabled/disabled, although
+ * some settings will cause the device to fail to probe.
+ *
+ * Writes support both comma- and newline-separated input format. Reads
+ * will always return one GT type per line. "primary" and "media" are the
+ * GT type names supported by this interface.
+ *
+ * This attribute can only be set before binding to the device.
+ *
+ * Examples:
+ *
+ * Allow both primary and media GTs to be initialized and used.  This matches
+ * the driver's default behavior::
+ *
+ *	# echo 'primary,media' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
+ *
+ * Allow only the primary GT of each tile to be initialized and used,
+ * effectively disabling the media GT if it exists on the platform::
+ *
+ *	# echo 'primary' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
+ *
+ * Allow only the media GT of each tile to be initialized and used,
+ * effectively disabling the primary GT.  **This configuration will cause
+ * device probe failure on all current platforms, but may be allowed on
+ * igpu platforms in the future**::
+ *
+ *	# echo 'media' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
+ *
+ * Disable all GTs.  Only other GPU IP (such as display) is potentially usable.
+ * **This configuration will cause device probe failure on all current
+ * platforms, but may be allowed on igpu platforms in the future**::
+ *
+ *	# echo '' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
+ *
  * Allowed engines:
  * ----------------
  *
@@ -187,6 +227,7 @@ struct xe_config_group_device {
 	struct config_group group;
 
 	struct xe_config_device {
+		u64 gt_types_allowed;
 		u64 engines_allowed;
 		struct wa_bb ctx_restore_post_bb[XE_ENGINE_CLASS_MAX];
 		struct wa_bb ctx_restore_mid_bb[XE_ENGINE_CLASS_MAX];
@@ -201,6 +242,7 @@ struct xe_config_group_device {
 };
 
 static const struct xe_config_device device_defaults = {
+	.gt_types_allowed = U64_MAX,
 	.engines_allowed = U64_MAX,
 	.survivability_mode = false,
 	.enable_psmi = false,
@@ -220,6 +262,7 @@ struct engine_info {
 /* Some helpful macros to aid on the sizing of buffer allocation when parsing */
 #define MAX_ENGINE_CLASS_CHARS 5
 #define MAX_ENGINE_INSTANCE_CHARS 2
+#define MAX_GT_TYPE_CHARS 7
 
 static const struct engine_info engine_info[] = {
 	{ .cls = "rcs", .mask = XE_HW_ENGINE_RCS_MASK, .engine_class = XE_ENGINE_CLASS_RENDER },
@@ -230,6 +273,14 @@ static const struct engine_info engine_info[] = {
 	{ .cls = "gsccs", .mask = XE_HW_ENGINE_GSCCS_MASK, .engine_class = XE_ENGINE_CLASS_OTHER },
 };
 
+static const struct {
+	const char name[MAX_GT_TYPE_CHARS + 1];
+	enum xe_gt_type type;
+} gt_types[] = {
+	{ .name = "primary", .type = XE_GT_TYPE_MAIN },
+	{ .name = "media", .type = XE_GT_TYPE_MEDIA },
+};
+
 static struct xe_config_group_device *to_xe_config_group_device(struct config_item *item)
 {
 	return container_of(to_config_group(item), struct xe_config_group_device, group);
@@ -292,6 +343,58 @@ static ssize_t survivability_mode_store(struct config_item *item, const char *pa
 	return len;
 }
 
+static ssize_t gt_types_allowed_show(struct config_item *item, char *page)
+{
+	struct xe_config_device *dev = to_xe_config_device(item);
+	char *p = page;
+
+	for (size_t i = 0; i < ARRAY_SIZE(gt_types); i++)
+		if (dev->gt_types_allowed & BIT_ULL(gt_types[i].type))
+			p += sprintf(p, "%s\n", gt_types[i].name);
+
+	return p - page;
+}
+
+static ssize_t gt_types_allowed_store(struct config_item *item, const char *page,
+				      size_t len)
+{
+	struct xe_config_group_device *dev = to_xe_config_group_device(item);
+	char *buf __free(kfree) = kstrdup(page, GFP_KERNEL);
+	char *p = buf;
+	u64 typemask = 0;
+
+	if (!buf)
+		return -ENOMEM;
+
+	while (p) {
+		char *typename = strsep(&p, ",\n");
+		bool matched = false;
+
+		if (typename[0] == '\0')
+			continue;
+
+		for (size_t i = 0; i < ARRAY_SIZE(gt_types); i++) {
+			if (strcmp(typename, gt_types[i].name) == 0) {
+				typemask |= BIT(gt_types[i].type);
+				matched = true;
+				break;
+			}
+		}
+
+		if (!matched)
+			return -EINVAL;
+	}
+
+	scoped_guard(mutex, &dev->lock) {
+		if (is_bound(dev))
+			return -EBUSY;
+
+		dev->config.gt_types_allowed = typemask;
+	}
+
+	return len;
+}
+
 static ssize_t engines_allowed_show(struct config_item *item, char *page)
 {
 	struct xe_config_device *dev = to_xe_config_device(item);
@@ -672,6 +775,7 @@ CONFIGFS_ATTR(, ctx_restore_mid_bb);
 CONFIGFS_ATTR(, ctx_restore_post_bb);
 CONFIGFS_ATTR(, enable_psmi);
 CONFIGFS_ATTR(, engines_allowed);
+CONFIGFS_ATTR(, gt_types_allowed);
 CONFIGFS_ATTR(, survivability_mode);
 
 static struct configfs_attribute *xe_config_device_attrs[] = {
@@ -679,6 +783,7 @@ static struct configfs_attribute *xe_config_device_attrs[] = {
 	&attr_ctx_restore_post_bb,
 	&attr_enable_psmi,
 	&attr_engines_allowed,
+	&attr_gt_types_allowed,
 	&attr_survivability_mode,
 	NULL,
 };
@@ -846,6 +951,7 @@ static void dump_custom_dev_config(struct pci_dev *pdev,
 				 dev->config.attr_); \
 	} while (0)
 
+	PRI_CUSTOM_ATTR("%llx", gt_types_allowed);
 	PRI_CUSTOM_ATTR("%llx", engines_allowed);
 	PRI_CUSTOM_ATTR("%d", enable_psmi);
 	PRI_CUSTOM_ATTR("%d", survivability_mode);
@@ -896,6 +1002,45 @@ bool xe_configfs_get_survivability_mode(struct pci_dev *pdev)
 	return mode;
 }
 
+static u64 get_gt_types_allowed(struct xe_device *xe)
+{
+	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+	struct xe_config_group_device *dev = find_xe_config_group_device(pdev);
+	u64 mask;
+
+	if (!dev)
+		return device_defaults.gt_types_allowed;
+
+	mask = dev->config.gt_types_allowed;
+	config_group_put(&dev->group);
+
+	return mask;
+}
+
+/**
+ * xe_configfs_primary_gt_supported - determine whether primary GTs are supported
+ * @xe: xe device
+ *
+ * Return: True if primary GTs are enabled, false if they have been disabled via
+ *     configfs.
+ */
+bool xe_configfs_primary_gt_supported(struct xe_device *xe)
+{
+	return (get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MAIN)) != 0;
+}
+
+/**
+ * xe_configfs_media_gt_supported - determine whether media GTs are supported
+ * @xe: xe device
+ *
+ * Return: True if the media GTs are enabled, false if they have been disabled
+ *     via configfs.
+ */
+bool xe_configfs_media_gt_supported(struct xe_device *xe)
+{
+	return (get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MEDIA)) != 0;
+}
+
 /**
  * xe_configfs_get_engines_allowed - get engine allowed mask from configfs
  * @pdev: pci device
diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h
index c61e0e47ed94..5624e965b911 100644
--- a/drivers/gpu/drm/xe/xe_configfs.h
+++ b/drivers/gpu/drm/xe/xe_configfs.h
@@ -17,6 +17,8 @@ int xe_configfs_init(void);
 void xe_configfs_exit(void);
 void xe_configfs_check_device(struct pci_dev *pdev);
 bool xe_configfs_get_survivability_mode(struct pci_dev *pdev);
+bool xe_configfs_primary_gt_supported(struct xe_device *xe);
+bool xe_configfs_media_gt_supported(struct xe_device *xe);
 u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev);
 bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev);
 u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
@@ -28,6 +30,8 @@ static inline int xe_configfs_init(void) { return 0; }
 static inline void xe_configfs_exit(void) { }
 static inline void xe_configfs_check_device(struct pci_dev *pdev) { }
 static inline bool xe_configfs_get_survivability_mode(struct pci_dev *pdev) { return false; }
+static inline bool xe_configfs_primary_gt_supported(struct xe_device *xe) { return true; }
+static inline bool xe_configfs_media_gt_supported(struct xe_device *xe) { return true; }
 static inline u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev) { return U64_MAX; }
 static inline bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev) { return false; }
 static inline u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index a5932e4f4a23..9c8ab2b41737 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -695,6 +695,11 @@ static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
 	struct xe_device *xe = tile_to_xe(tile);
 	struct xe_gt *gt;
 
+	if (!xe_configfs_primary_gt_supported(xe)) {
+		drm_info(&xe->drm, "Primary GT disabled via configfs\n");
+		return NULL;
+	}
+
 	gt = xe_gt_alloc(tile);
 	if (IS_ERR(gt))
 		return gt;
@@ -720,6 +725,11 @@ static struct xe_gt *alloc_media_gt(struct xe_tile *tile,
 	struct xe_device *xe = tile_to_xe(tile);
 	struct xe_gt *gt;
 
+	if (!xe_configfs_media_gt_supported(xe)) {
+		drm_info(&xe->drm, "Media GT disabled via configfs\n");
+		return NULL;
+	}
+
 	if (MEDIA_VER(xe) < 13 || !media_desc)
 		return NULL;
 
@@ -829,6 +839,18 @@ static int xe_info_init(struct xe_device *xe,
 		if (IS_ERR(tile->primary_gt))
 			return PTR_ERR(tile->primary_gt);
 
+		/*
+		 * It's not currently possible to probe a device with the
+		 * primary GT disabled.  With some work, this may be future in
+		 * the possible for igpu platforms (although probably not for
+		 * dgpu's since access to the primary GT's BCS engines is
+		 * required for VRAM management).
+		 */
+		if (!tile->primary_gt) {
+			drm_err(&xe->drm, "Cannot probe device with without a primary GT\n");
+			return -ENODEV;
+		}
+
 		tile->media_gt = alloc_media_gt(tile, media_desc);
 		if (IS_ERR(tile->media_gt))
 			return PTR_ERR(tile->media_gt);
-- 
2.51.0

[PATCH v4 23/23] drm/xe/sriov: Disable SR-IOV if primary GT is disabled via configfs

[Matt Roper]

SR-IOV operation relies on the primary GT's GuC to operate (in both PF
and VF mode).  If the primary GT is disabled in VF mode, fail the probe.
If the primary GT is disabled in PF mode, force the device back to
native (non-sriov) mode.

v2:
 - Move handling to xe_info_init().  (Michal)

v3:
 - Just update the .has_sriov flag in xe_info_init_early().  (Michal)

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 9c8ab2b41737..202894deba0e 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -628,7 +628,8 @@ static int xe_info_init_early(struct xe_device *xe,
 	xe->info.has_late_bind = desc->has_late_bind;
 	xe->info.has_llc = desc->has_llc;
 	xe->info.has_pxp = desc->has_pxp;
-	xe->info.has_sriov = desc->has_sriov;
+	/* SR-IOV depends on the primary GT's GuC; disable is primary GT is disabled */
+	xe->info.has_sriov = desc->has_sriov && xe_configfs_primary_gt_supported(xe);
 	xe->info.skip_guc_pc = desc->skip_guc_pc;
 	xe->info.skip_mtcfg = desc->skip_mtcfg;
 	xe->info.skip_pcode = desc->skip_pcode;
-- 
2.51.0

✗ CI.checkpatch: warning for Allow configfs to disable specific GT type(s) (rev4)

[Patchwork]

== Series Details ==

Series: Allow configfs to disable specific GT type(s) (rev4)
URL   : https://patchwork.freedesktop.org/series/154739/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
fbd08a78c3a3bb17964db2a326514c69c1dca660
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 1f64849d96a039296e0f69cbd0d68fd70c161136
Author: Matt Roper <matthew.d.roper@intel.com>
Date:   Tue Oct 7 13:48:53 2025 -0700

    drm/xe/sriov: Disable SR-IOV if primary GT is disabled via configfs
    
    SR-IOV operation relies on the primary GT's GuC to operate (in both PF
    and VF mode).  If the primary GT is disabled in VF mode, fail the probe.
    If the primary GT is disabled in PF mode, force the device back to
    native (non-sriov) mode.
    
    v2:
     - Move handling to xe_info_init().  (Michal)
    
    v3:
     - Just update the .has_sriov flag in xe_info_init_early().  (Michal)
    
    Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
    Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
+ /mt/dim checkpatch 679a7939422e7585cce7bf5d3350fc522e765343 drm-intel
0273e1c91fcd drm/xe/huc: Adjust HuC check on primary GT
2cb16cb539d7 drm/xe: Drop GT parameter to xe_display_irq_postinstall()
7d34eb011e3e drm/xe: Move 'va_bits' flag back to platform descriptor
7d8f5e70c8b3 drm/xe: Move 'vm_max_level' flag back to platform descriptor
c2c7a9b05548 drm/xe: Move 'vram_flags' flag back to platform descriptor
2d8849c6aaed drm/xe: Move 'has_flatccs' flag back to platform descriptor
ab1c933a19d9 drm/xe: Read VF GMD_ID with a specifically-allocated dummy GT
007545972d7e drm/xe: Move primary GT allocation from xe_tile_init_early to xe_tile_init
8e4c53d27faa drm/xe: Skip L2 / TDF cache flushes if primary GT is disabled
5b1a41b0cc3b drm/xe/query: Report hwconfig size as 0 if primary GT is disabled
96156b82870f drm/xe/pmu: Initialize PMU event types based on first available GT
d01a32713dd8 drm/xe: Check for primary GT before looking up Wa_22019338487
063c8597003b drm/xe: Make display part of Wa_22019338487 a device workaround
3d4d34fed764 drm/xe/irq: Don't try to lookup engine masks for non-existent primary GT
3367d1c221b0 drm/xe: Handle Wa_22010954014 and Wa_14022085890 as device workarounds
-:127: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#127: FILE: include/drm/intel/pciids.h:852:
+#define INTEL_BMG_G21_IDS(MACRO__, ...) \
 	MACRO__(0xE202, ## __VA_ARGS__), \
 	MACRO__(0xE209, ## __VA_ARGS__), \
 	MACRO__(0xE20B, ## __VA_ARGS__), \

BUT SEE:

   do {} while (0) advice is over-stated in a few situations:

   The more obvious case is macros, like MODULE_PARM_DESC, invoked at
   file-scope, where C disallows code (it must be in functions).  See
   $exceptions if you have one to add by name.

   More troublesome is declarative macros used at top of new scope,
   like DECLARE_PER_CPU.  These might just compile with a do-while-0
   wrapper, but would be incorrect.  Most of these are handled by
   detecting struct,union,etc declaration primitives in $exceptions.

   Theres also macros called inside an if (block), which "return" an
   expression.  These cannot do-while, and need a ({}) wrapper.

   Enjoy this qualification while we work to improve our heuristics.

-:127: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#127: FILE: include/drm/intel/pciids.h:852:
+#define INTEL_BMG_G21_IDS(MACRO__, ...) \
 	MACRO__(0xE202, ## __VA_ARGS__), \
 	MACRO__(0xE209, ## __VA_ARGS__), \
 	MACRO__(0xE20B, ## __VA_ARGS__), \

-:138: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#138: FILE: include/drm/intel/pciids.h:863:
+#define INTEL_BMG_IDS(MACRO__, ...) \
+	INTEL_BMG_G21_IDS(MACRO__, __VA_ARGS__), \
 	MACRO__(0xE220, ## __VA_ARGS__), \
 	MACRO__(0xE221, ## __VA_ARGS__), \
 	MACRO__(0xE222, ## __VA_ARGS__), \

BUT SEE:

   do {} while (0) advice is over-stated in a few situations:

   The more obvious case is macros, like MODULE_PARM_DESC, invoked at
   file-scope, where C disallows code (it must be in functions).  See
   $exceptions if you have one to add by name.

   More troublesome is declarative macros used at top of new scope,
   like DECLARE_PER_CPU.  These might just compile with a do-while-0
   wrapper, but would be incorrect.  Most of these are handled by
   detecting struct,union,etc declaration primitives in $exceptions.

   Theres also macros called inside an if (block), which "return" an
   expression.  These cannot do-while, and need a ({}) wrapper.

   Enjoy this qualification while we work to improve our heuristics.

-:138: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#138: FILE: include/drm/intel/pciids.h:863:
+#define INTEL_BMG_IDS(MACRO__, ...) \
+	INTEL_BMG_G21_IDS(MACRO__, __VA_ARGS__), \
 	MACRO__(0xE220, ## __VA_ARGS__), \
 	MACRO__(0xE221, ## __VA_ARGS__), \
 	MACRO__(0xE222, ## __VA_ARGS__), \

total: 2 errors, 0 warnings, 2 checks, 87 lines checked
35758afda2c2 drm/xe/rtp: Pass xe_device parameter to FUNC matches
e63bc24c7a29 drm/xe: Bypass Wa_14018094691 when primary GT is disabled
052371c69236 drm/xe: Correct lineage for Wa_22014953428 and only check with valid GT
240ab73f50a8 drm/xe: Check that GT is not NULL before testing Wa_16023588340
e68ea622e853 drm/xe: Don't check BIOS-disabled FlatCCS if primary GT is disabled
9714b82a09e6 drm/xe: Break GT setup out of xe_info_init()
fa0bed53a630 drm/xe/configfs: Add attribute to disable GT types
-:160: WARNING:LINE_SPACING: Missing a blank line after declarations
#160: FILE: drivers/gpu/drm/xe/xe_configfs.c:362:
+	struct xe_config_group_device *dev = to_xe_config_group_device(item);
+	char *buf __free(kfree) = kstrdup(page, GFP_KERNEL);

total: 0 errors, 1 warnings, 0 checks, 273 lines checked
1f64849d96a0 drm/xe/sriov: Disable SR-IOV if primary GT is disabled via configfs

✓ CI.KUnit: success for Allow configfs to disable specific GT type(s) (rev4)

[Patchwork]

== Series Details ==

Series: Allow configfs to disable specific GT type(s) (rev4)
URL   : https://patchwork.freedesktop.org/series/154739/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[20:56:15] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:56:20] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:56:49] Starting KUnit Kernel (1/1)...
[20:56:49] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:56:49] ================== guc_buf (11 subtests) ===================
[20:56:49] [PASSED] test_smallest
[20:56:49] [PASSED] test_largest
[20:56:49] [PASSED] test_granular
[20:56:49] [PASSED] test_unique
[20:56:49] [PASSED] test_overlap
[20:56:49] [PASSED] test_reusable
[20:56:49] [PASSED] test_too_big
[20:56:49] [PASSED] test_flush
[20:56:49] [PASSED] test_lookup
[20:56:49] [PASSED] test_data
[20:56:49] [PASSED] test_class
[20:56:49] ===================== [PASSED] guc_buf =====================
[20:56:49] =================== guc_dbm (7 subtests) ===================
[20:56:49] [PASSED] test_empty
[20:56:49] [PASSED] test_default
[20:56:49] ======================== test_size  ========================
[20:56:49] [PASSED] 4
[20:56:49] [PASSED] 8
[20:56:49] [PASSED] 32
[20:56:49] [PASSED] 256
[20:56:49] ==================== [PASSED] test_size ====================
[20:56:49] ======================= test_reuse  ========================
[20:56:49] [PASSED] 4
[20:56:49] [PASSED] 8
[20:56:49] [PASSED] 32
[20:56:49] [PASSED] 256
[20:56:49] =================== [PASSED] test_reuse ====================
[20:56:49] =================== test_range_overlap  ====================
[20:56:49] [PASSED] 4
[20:56:49] [PASSED] 8
[20:56:49] [PASSED] 32
[20:56:49] [PASSED] 256
[20:56:49] =============== [PASSED] test_range_overlap ================
[20:56:49] =================== test_range_compact  ====================
[20:56:49] [PASSED] 4
[20:56:49] [PASSED] 8
[20:56:49] [PASSED] 32
[20:56:49] [PASSED] 256
[20:56:49] =============== [PASSED] test_range_compact ================
[20:56:49] ==================== test_range_spare  =====================
[20:56:49] [PASSED] 4
[20:56:49] [PASSED] 8
[20:56:49] [PASSED] 32
[20:56:49] [PASSED] 256
[20:56:49] ================ [PASSED] test_range_spare =================
[20:56:49] ===================== [PASSED] guc_dbm =====================
[20:56:49] =================== guc_idm (6 subtests) ===================
[20:56:49] [PASSED] bad_init
[20:56:49] [PASSED] no_init
[20:56:49] [PASSED] init_fini
[20:56:49] [PASSED] check_used
[20:56:49] [PASSED] check_quota
[20:56:49] [PASSED] check_all
[20:56:49] ===================== [PASSED] guc_idm =====================
[20:56:49] ================== no_relay (3 subtests) ===================
[20:56:49] [PASSED] xe_drops_guc2pf_if_not_ready
[20:56:49] [PASSED] xe_drops_guc2vf_if_not_ready
[20:56:49] [PASSED] xe_rejects_send_if_not_ready
[20:56:49] ==================== [PASSED] no_relay =====================
[20:56:49] ================== pf_relay (14 subtests) ==================
[20:56:49] [PASSED] pf_rejects_guc2pf_too_short
[20:56:49] [PASSED] pf_rejects_guc2pf_too_long
[20:56:49] [PASSED] pf_rejects_guc2pf_no_payload
[20:56:49] [PASSED] pf_fails_no_payload
[20:56:49] [PASSED] pf_fails_bad_origin
[20:56:49] [PASSED] pf_fails_bad_type
[20:56:49] [PASSED] pf_txn_reports_error
[20:56:49] [PASSED] pf_txn_sends_pf2guc
[20:56:49] [PASSED] pf_sends_pf2guc
[20:56:49] [SKIPPED] pf_loopback_nop
[20:56:49] [SKIPPED] pf_loopback_echo
[20:56:49] [SKIPPED] pf_loopback_fail
[20:56:49] [SKIPPED] pf_loopback_busy
[20:56:49] [SKIPPED] pf_loopback_retry
[20:56:49] ==================== [PASSED] pf_relay =====================
[20:56:49] ================== vf_relay (3 subtests) ===================
[20:56:49] [PASSED] vf_rejects_guc2vf_too_short
[20:56:49] [PASSED] vf_rejects_guc2vf_too_long
[20:56:49] [PASSED] vf_rejects_guc2vf_no_payload
[20:56:49] ==================== [PASSED] vf_relay =====================
[20:56:49] ===================== lmtt (1 subtest) =====================
[20:56:49] ======================== test_ops  =========================
[20:56:49] [PASSED] 2-level
[20:56:49] [PASSED] multi-level
[20:56:49] ==================== [PASSED] test_ops =====================
[20:56:49] ====================== [PASSED] lmtt =======================
[20:56:49] ================= pf_service (11 subtests) =================
[20:56:49] [PASSED] pf_negotiate_any
[20:56:49] [PASSED] pf_negotiate_base_match
[20:56:49] [PASSED] pf_negotiate_base_newer
[20:56:49] [PASSED] pf_negotiate_base_next
[20:56:49] [SKIPPED] pf_negotiate_base_older
[20:56:49] [PASSED] pf_negotiate_base_prev
[20:56:49] [PASSED] pf_negotiate_latest_match
[20:56:49] [PASSED] pf_negotiate_latest_newer
[20:56:49] [PASSED] pf_negotiate_latest_next
[20:56:49] [SKIPPED] pf_negotiate_latest_older
[20:56:49] [SKIPPED] pf_negotiate_latest_prev
[20:56:49] =================== [PASSED] pf_service ====================
[20:56:49] ================= xe_guc_g2g (2 subtests) ==================
[20:56:49] ============== xe_live_guc_g2g_kunit_default  ==============
[20:56:49] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[20:56:49] ============== xe_live_guc_g2g_kunit_allmem  ===============
[20:56:49] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[20:56:49] =================== [SKIPPED] xe_guc_g2g ===================
[20:56:49] =================== xe_mocs (2 subtests) ===================
[20:56:49] ================ xe_live_mocs_kernel_kunit  ================
[20:56:49] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[20:56:49] ================ xe_live_mocs_reset_kunit  =================
[20:56:49] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[20:56:49] ==================== [SKIPPED] xe_mocs =====================
[20:56:49] ================= xe_migrate (2 subtests) ==================
[20:56:49] ================= xe_migrate_sanity_kunit  =================
[20:56:49] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[20:56:49] ================== xe_validate_ccs_kunit  ==================
[20:56:49] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[20:56:49] =================== [SKIPPED] xe_migrate ===================
[20:56:49] ================== xe_dma_buf (1 subtest) ==================
[20:56:49] ==================== xe_dma_buf_kunit  =====================
[20:56:49] ================ [SKIPPED] xe_dma_buf_kunit ================
[20:56:49] =================== [SKIPPED] xe_dma_buf ===================
[20:56:49] ================= xe_bo_shrink (1 subtest) =================
[20:56:49] =================== xe_bo_shrink_kunit  ====================
[20:56:49] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[20:56:49] ================== [SKIPPED] xe_bo_shrink ==================
[20:56:49] ==================== xe_bo (2 subtests) ====================
[20:56:49] ================== xe_ccs_migrate_kunit  ===================
[20:56:49] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[20:56:49] ==================== xe_bo_evict_kunit  ====================
[20:56:49] =============== [SKIPPED] xe_bo_evict_kunit ================
[20:56:49] ===================== [SKIPPED] xe_bo ======================
[20:56:49] ==================== args (11 subtests) ====================
[20:56:49] [PASSED] count_args_test
[20:56:49] [PASSED] call_args_example
[20:56:49] [PASSED] call_args_test
[20:56:49] [PASSED] drop_first_arg_example
[20:56:49] [PASSED] drop_first_arg_test
[20:56:49] [PASSED] first_arg_example
[20:56:49] [PASSED] first_arg_test
[20:56:49] [PASSED] last_arg_example
[20:56:49] [PASSED] last_arg_test
[20:56:49] [PASSED] pick_arg_example
[20:56:49] [PASSED] sep_comma_example
[20:56:49] ====================== [PASSED] args =======================
[20:56:49] =================== xe_pci (3 subtests) ====================
[20:56:49] ==================== check_graphics_ip  ====================
[20:56:49] [PASSED] 12.00 Xe_LP
[20:56:49] [PASSED] 12.10 Xe_LP+
[20:56:49] [PASSED] 12.55 Xe_HPG
[20:56:49] [PASSED] 12.60 Xe_HPC
[20:56:49] [PASSED] 12.70 Xe_LPG
[20:56:49] [PASSED] 12.71 Xe_LPG
[20:56:49] [PASSED] 12.74 Xe_LPG+
[20:56:49] [PASSED] 20.01 Xe2_HPG
[20:56:49] [PASSED] 20.02 Xe2_HPG
[20:56:49] [PASSED] 20.04 Xe2_LPG
[20:56:49] [PASSED] 30.00 Xe3_LPG
[20:56:49] [PASSED] 30.01 Xe3_LPG
[20:56:49] [PASSED] 30.03 Xe3_LPG
[20:56:49] ================ [PASSED] check_graphics_ip ================
[20:56:49] ===================== check_media_ip  ======================
[20:56:49] [PASSED] 12.00 Xe_M
[20:56:49] [PASSED] 12.55 Xe_HPM
[20:56:49] [PASSED] 13.00 Xe_LPM+
[20:56:49] [PASSED] 13.01 Xe2_HPM
[20:56:49] [PASSED] 20.00 Xe2_LPM
[20:56:49] [PASSED] 30.00 Xe3_LPM
[20:56:49] [PASSED] 30.02 Xe3_LPM
[20:56:49] ================= [PASSED] check_media_ip ==================
[20:56:49] ================= check_platform_gt_count  =================
[20:56:49] [PASSED] 0x9A60 (TIGERLAKE)
[20:56:49] [PASSED] 0x9A68 (TIGERLAKE)
[20:56:49] [PASSED] 0x9A70 (TIGERLAKE)
[20:56:49] [PASSED] 0x9A40 (TIGERLAKE)
[20:56:49] [PASSED] 0x9A49 (TIGERLAKE)
[20:56:49] [PASSED] 0x9A59 (TIGERLAKE)
[20:56:49] [PASSED] 0x9A78 (TIGERLAKE)
[20:56:49] [PASSED] 0x9AC0 (TIGERLAKE)
[20:56:49] [PASSED] 0x9AC9 (TIGERLAKE)
[20:56:49] [PASSED] 0x9AD9 (TIGERLAKE)
[20:56:49] [PASSED] 0x9AF8 (TIGERLAKE)
[20:56:49] [PASSED] 0x4C80 (ROCKETLAKE)
[20:56:49] [PASSED] 0x4C8A (ROCKETLAKE)
[20:56:49] [PASSED] 0x4C8B (ROCKETLAKE)
[20:56:49] [PASSED] 0x4C8C (ROCKETLAKE)
[20:56:49] [PASSED] 0x4C90 (ROCKETLAKE)
[20:56:49] [PASSED] 0x4C9A (ROCKETLAKE)
[20:56:49] [PASSED] 0x4680 (ALDERLAKE_S)
[20:56:49] [PASSED] 0x4682 (ALDERLAKE_S)
[20:56:49] [PASSED] 0x4688 (ALDERLAKE_S)
[20:56:49] [PASSED] 0x468A (ALDERLAKE_S)
[20:56:49] [PASSED] 0x468B (ALDERLAKE_S)
[20:56:49] [PASSED] 0x4690 (ALDERLAKE_S)
[20:56:49] [PASSED] 0x4692 (ALDERLAKE_S)
[20:56:49] [PASSED] 0x4693 (ALDERLAKE_S)
[20:56:49] [PASSED] 0x46A0 (ALDERLAKE_P)
[20:56:49] [PASSED] 0x46A1 (ALDERLAKE_P)
[20:56:49] [PASSED] 0x46A2 (ALDERLAKE_P)
[20:56:49] [PASSED] 0x46A3 (ALDERLAKE_P)
[20:56:49] [PASSED] 0x46A6 (ALDERLAKE_P)
[20:56:49] [PASSED] 0x46A8 (ALDERLAKE_P)
[20:56:49] [PASSED] 0x46AA (ALDERLAKE_P)
[20:56:49] [PASSED] 0x462A (ALDERLAKE_P)
[20:56:49] [PASSED] 0x4626 (ALDERLAKE_P)
[20:56:49] [PASSED] 0x4628 (ALDERLAKE_P)
[20:56:49] [PASSED] 0x46B0 (ALDERLAKE_P)
[20:56:49] [PASSED] 0x46B1 (ALDERLAKE_P)
[20:56:49] [PASSED] 0x46B2 (ALDERLAKE_P)
[20:56:49] [PASSED] 0x46B3 (ALDERLAKE_P)
[20:56:49] [PASSED] 0x46C0 (ALDERLAKE_P)
[20:56:49] [PASSED] 0x46C1 (ALDERLAKE_P)
[20:56:49] [PASSED] 0x46C2 (ALDERLAKE_P)
[20:56:49] [PASSED] 0x46C3 (ALDERLAKE_P)
[20:56:49] [PASSED] 0x46D0 (ALDERLAKE_N)
[20:56:49] [PASSED] 0x46D1 (ALDERLAKE_N)
[20:56:49] [PASSED] 0x46D2 (ALDERLAKE_N)
[20:56:49] [PASSED] 0x46D3 (ALDERLAKE_N)
[20:56:49] [PASSED] 0x46D4 (ALDERLAKE_N)
[20:56:49] [PASSED] 0xA721 (ALDERLAKE_P)
[20:56:49] [PASSED] 0xA7A1 (ALDERLAKE_P)
[20:56:49] [PASSED] 0xA7A9 (ALDERLAKE_P)
[20:56:49] [PASSED] 0xA7AC (ALDERLAKE_P)
[20:56:49] [PASSED] 0xA7AD (ALDERLAKE_P)
[20:56:49] [PASSED] 0xA720 (ALDERLAKE_P)
[20:56:49] [PASSED] 0xA7A0 (ALDERLAKE_P)
[20:56:49] [PASSED] 0xA7A8 (ALDERLAKE_P)
[20:56:49] [PASSED] 0xA7AA (ALDERLAKE_P)
[20:56:49] [PASSED] 0xA7AB (ALDERLAKE_P)
[20:56:49] [PASSED] 0xA780 (ALDERLAKE_S)
[20:56:49] [PASSED] 0xA781 (ALDERLAKE_S)
[20:56:49] [PASSED] 0xA782 (ALDERLAKE_S)
[20:56:49] [PASSED] 0xA783 (ALDERLAKE_S)
[20:56:49] [PASSED] 0xA788 (ALDERLAKE_S)
[20:56:49] [PASSED] 0xA789 (ALDERLAKE_S)
[20:56:49] [PASSED] 0xA78A (ALDERLAKE_S)
[20:56:49] [PASSED] 0xA78B (ALDERLAKE_S)
[20:56:49] [PASSED] 0x4905 (DG1)
[20:56:49] [PASSED] 0x4906 (DG1)
[20:56:49] [PASSED] 0x4907 (DG1)
[20:56:49] [PASSED] 0x4908 (DG1)
[20:56:49] [PASSED] 0x4909 (DG1)
[20:56:49] [PASSED] 0x56C0 (DG2)
[20:56:49] [PASSED] 0x56C2 (DG2)
[20:56:49] [PASSED] 0x56C1 (DG2)
[20:56:49] [PASSED] 0x7D51 (METEORLAKE)
[20:56:49] [PASSED] 0x7DD1 (METEORLAKE)
[20:56:49] [PASSED] 0x7D41 (METEORLAKE)
[20:56:49] [PASSED] 0x7D67 (METEORLAKE)
[20:56:49] [PASSED] 0xB640 (METEORLAKE)
[20:56:49] [PASSED] 0x56A0 (DG2)
[20:56:49] [PASSED] 0x56A1 (DG2)
[20:56:49] [PASSED] 0x56A2 (DG2)
[20:56:49] [PASSED] 0x56BE (DG2)
[20:56:49] [PASSED] 0x56BF (DG2)
[20:56:49] [PASSED] 0x5690 (DG2)
[20:56:49] [PASSED] 0x5691 (DG2)
[20:56:49] [PASSED] 0x5692 (DG2)
[20:56:49] [PASSED] 0x56A5 (DG2)
[20:56:49] [PASSED] 0x56A6 (DG2)
[20:56:49] [PASSED] 0x56B0 (DG2)
[20:56:49] [PASSED] 0x56B1 (DG2)
[20:56:49] [PASSED] 0x56BA (DG2)
[20:56:49] [PASSED] 0x56BB (DG2)
[20:56:49] [PASSED] 0x56BC (DG2)
[20:56:49] [PASSED] 0x56BD (DG2)
[20:56:49] [PASSED] 0x5693 (DG2)
[20:56:49] [PASSED] 0x5694 (DG2)
[20:56:49] [PASSED] 0x5695 (DG2)
[20:56:49] [PASSED] 0x56A3 (DG2)
[20:56:49] [PASSED] 0x56A4 (DG2)
[20:56:49] [PASSED] 0x56B2 (DG2)
[20:56:49] [PASSED] 0x56B3 (DG2)
[20:56:49] [PASSED] 0x5696 (DG2)
[20:56:49] [PASSED] 0x5697 (DG2)
[20:56:49] [PASSED] 0xB69 (PVC)
[20:56:49] [PASSED] 0xB6E (PVC)
[20:56:49] [PASSED] 0xBD4 (PVC)
[20:56:49] [PASSED] 0xBD5 (PVC)
[20:56:49] [PASSED] 0xBD6 (PVC)
[20:56:49] [PASSED] 0xBD7 (PVC)
[20:56:49] [PASSED] 0xBD8 (PVC)
[20:56:49] [PASSED] 0xBD9 (PVC)
[20:56:49] [PASSED] 0xBDA (PVC)
[20:56:49] [PASSED] 0xBDB (PVC)
[20:56:49] [PASSED] 0xBE0 (PVC)
[20:56:49] [PASSED] 0xBE1 (PVC)
[20:56:49] [PASSED] 0xBE5 (PVC)
[20:56:49] [PASSED] 0x7D40 (METEORLAKE)
[20:56:49] [PASSED] 0x7D45 (METEORLAKE)
[20:56:49] [PASSED] 0x7D55 (METEORLAKE)
[20:56:49] [PASSED] 0x7D60 (METEORLAKE)
[20:56:49] [PASSED] 0x7DD5 (METEORLAKE)
[20:56:49] [PASSED] 0x6420 (LUNARLAKE)
[20:56:49] [PASSED] 0x64A0 (LUNARLAKE)
[20:56:49] [PASSED] 0x64B0 (LUNARLAKE)
[20:56:49] [PASSED] 0xE202 (BATTLEMAGE)
[20:56:49] [PASSED] 0xE209 (BATTLEMAGE)
[20:56:49] [PASSED] 0xE20B (BATTLEMAGE)
[20:56:49] [PASSED] 0xE20C (BATTLEMAGE)
[20:56:49] [PASSED] 0xE20D (BATTLEMAGE)
[20:56:49] [PASSED] 0xE210 (BATTLEMAGE)
[20:56:49] [PASSED] 0xE211 (BATTLEMAGE)
[20:56:49] [PASSED] 0xE212 (BATTLEMAGE)
[20:56:49] [PASSED] 0xE216 (BATTLEMAGE)
[20:56:49] [PASSED] 0xE220 (BATTLEMAGE)
[20:56:49] [PASSED] 0xE221 (BATTLEMAGE)
[20:56:49] [PASSED] 0xE222 (BATTLEMAGE)
[20:56:49] [PASSED] 0xE223 (BATTLEMAGE)
[20:56:49] [PASSED] 0xB080 (PANTHERLAKE)
[20:56:49] [PASSED] 0xB081 (PANTHERLAKE)
[20:56:49] [PASSED] 0xB082 (PANTHERLAKE)
[20:56:49] [PASSED] 0xB083 (PANTHERLAKE)
[20:56:49] [PASSED] 0xB084 (PANTHERLAKE)
[20:56:49] [PASSED] 0xB085 (PANTHERLAKE)
[20:56:49] [PASSED] 0xB086 (PANTHERLAKE)
[20:56:49] [PASSED] 0xB087 (PANTHERLAKE)
[20:56:49] [PASSED] 0xB08F (PANTHERLAKE)
[20:56:49] [PASSED] 0xB090 (PANTHERLAKE)
[20:56:49] [PASSED] 0xB0A0 (PANTHERLAKE)
[20:56:49] [PASSED] 0xB0B0 (PANTHERLAKE)
[20:56:49] [PASSED] 0xFD80 (PANTHERLAKE)
[20:56:49] [PASSED] 0xFD81 (PANTHERLAKE)
[20:56:49] ============= [PASSED] check_platform_gt_count =============
[20:56:49] ===================== [PASSED] xe_pci ======================
[20:56:49] =================== xe_rtp (2 subtests) ====================
[20:56:49] =============== xe_rtp_process_to_sr_tests  ================
[20:56:49] [PASSED] coalesce-same-reg
[20:56:49] [PASSED] no-match-no-add
[20:56:49] [PASSED] match-or
[20:56:49] [PASSED] match-or-xfail
[20:56:49] [PASSED] no-match-no-add-multiple-rules
[20:56:49] [PASSED] two-regs-two-entries
[20:56:49] [PASSED] clr-one-set-other
[20:56:49] [PASSED] set-field
[20:56:49] [PASSED] conflict-duplicate
[20:56:49] [PASSED] conflict-not-disjoint
[20:56:49] [PASSED] conflict-reg-type
[20:56:49] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[20:56:49] ================== xe_rtp_process_tests  ===================
[20:56:49] [PASSED] active1
[20:56:49] [PASSED] active2
[20:56:49] [PASSED] active-inactive
[20:56:49] [PASSED] inactive-active
[20:56:49] [PASSED] inactive-1st_or_active-inactive
[20:56:49] [PASSED] inactive-2nd_or_active-inactive
[20:56:49] [PASSED] inactive-last_or_active-inactive
[20:56:49] [PASSED] inactive-no_or_active-inactive
[20:56:49] ============== [PASSED] xe_rtp_process_tests ===============
[20:56:49] ===================== [PASSED] xe_rtp ======================
[20:56:49] ==================== xe_wa (1 subtest) =====================
[20:56:49] ======================== xe_wa_gt  =========================
[20:56:49] [PASSED] TIGERLAKE B0
[20:56:49] [PASSED] DG1 A0
[20:56:49] [PASSED] DG1 B0
[20:56:49] [PASSED] ALDERLAKE_S A0
[20:56:49] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[20:56:49] [PASSED] ALDERLAKE_S C0
[20:56:49] [PASSED] ALDERLAKE_S D0
[20:56:49] [PASSED] ALDERLAKE_P A0
[20:56:49] [PASSED] ALDERLAKE_P B0
[20:56:49] [PASSED] ALDERLAKE_P C0
[20:56:49] [PASSED] ALDERLAKE_S RPLS D0
[20:56:49] [PASSED] ALDERLAKE_P RPLU E0
[20:56:49] [PASSED] DG2 G10 C0
[20:56:49] [PASSED] DG2 G11 B1
[20:56:49] [PASSED] DG2 G12 A1
[20:56:49] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:56:49] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:56:49] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[20:56:49] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[20:56:49] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[20:56:49] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[20:56:49] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[20:56:49] ==================== [PASSED] xe_wa_gt =====================
[20:56:49] ====================== [PASSED] xe_wa ======================
[20:56:49] ============================================================
[20:56:49] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[20:56:49] Elapsed time: 33.772s total, 4.300s configuring, 29.106s building, 0.325s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[20:56:49] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:56:51] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:57:14] Starting KUnit Kernel (1/1)...
[20:57:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:57:15] ============ drm_test_pick_cmdline (2 subtests) ============
[20:57:15] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[20:57:15] =============== drm_test_pick_cmdline_named  ===============
[20:57:15] [PASSED] NTSC
[20:57:15] [PASSED] NTSC-J
[20:57:15] [PASSED] PAL
[20:57:15] [PASSED] PAL-M
[20:57:15] =========== [PASSED] drm_test_pick_cmdline_named ===========
[20:57:15] ============== [PASSED] drm_test_pick_cmdline ==============
[20:57:15] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[20:57:15] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[20:57:15] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[20:57:15] =========== drm_validate_clone_mode (2 subtests) ===========
[20:57:15] ============== drm_test_check_in_clone_mode  ===============
[20:57:15] [PASSED] in_clone_mode
[20:57:15] [PASSED] not_in_clone_mode
[20:57:15] ========== [PASSED] drm_test_check_in_clone_mode ===========
[20:57:15] =============== drm_test_check_valid_clones  ===============
[20:57:15] [PASSED] not_in_clone_mode
[20:57:15] [PASSED] valid_clone
[20:57:15] [PASSED] invalid_clone
[20:57:15] =========== [PASSED] drm_test_check_valid_clones ===========
[20:57:15] ============= [PASSED] drm_validate_clone_mode =============
[20:57:15] ============= drm_validate_modeset (1 subtest) =============
[20:57:15] [PASSED] drm_test_check_connector_changed_modeset
[20:57:15] ============== [PASSED] drm_validate_modeset ===============
[20:57:15] ====== drm_test_bridge_get_current_state (2 subtests) ======
[20:57:15] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[20:57:15] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[20:57:15] ======== [PASSED] drm_test_bridge_get_current_state ========
[20:57:15] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[20:57:15] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[20:57:15] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[20:57:15] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[20:57:15] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[20:57:15] ============== drm_bridge_alloc (2 subtests) ===============
[20:57:15] [PASSED] drm_test_drm_bridge_alloc_basic
[20:57:15] [PASSED] drm_test_drm_bridge_alloc_get_put
[20:57:15] ================ [PASSED] drm_bridge_alloc =================
[20:57:15] ================== drm_buddy (8 subtests) ==================
[20:57:15] [PASSED] drm_test_buddy_alloc_limit
[20:57:15] [PASSED] drm_test_buddy_alloc_optimistic
[20:57:15] [PASSED] drm_test_buddy_alloc_pessimistic
[20:57:15] [PASSED] drm_test_buddy_alloc_pathological
[20:57:15] [PASSED] drm_test_buddy_alloc_contiguous
[20:57:15] [PASSED] drm_test_buddy_alloc_clear
[20:57:15] [PASSED] drm_test_buddy_alloc_range_bias
[20:57:15] [PASSED] drm_test_buddy_fragmentation_performance
[20:57:15] ==================== [PASSED] drm_buddy ====================
[20:57:15] ============= drm_cmdline_parser (40 subtests) =============
[20:57:15] [PASSED] drm_test_cmdline_force_d_only
[20:57:15] [PASSED] drm_test_cmdline_force_D_only_dvi
[20:57:15] [PASSED] drm_test_cmdline_force_D_only_hdmi
[20:57:15] [PASSED] drm_test_cmdline_force_D_only_not_digital
[20:57:15] [PASSED] drm_test_cmdline_force_e_only
[20:57:15] [PASSED] drm_test_cmdline_res
[20:57:15] [PASSED] drm_test_cmdline_res_vesa
[20:57:15] [PASSED] drm_test_cmdline_res_vesa_rblank
[20:57:15] [PASSED] drm_test_cmdline_res_rblank
[20:57:15] [PASSED] drm_test_cmdline_res_bpp
[20:57:15] [PASSED] drm_test_cmdline_res_refresh
[20:57:15] [PASSED] drm_test_cmdline_res_bpp_refresh
[20:57:15] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[20:57:15] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[20:57:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[20:57:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[20:57:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[20:57:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[20:57:15] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[20:57:15] [PASSED] drm_test_cmdline_res_margins_force_on
[20:57:15] [PASSED] drm_test_cmdline_res_vesa_margins
[20:57:15] [PASSED] drm_test_cmdline_name
[20:57:15] [PASSED] drm_test_cmdline_name_bpp
[20:57:15] [PASSED] drm_test_cmdline_name_option
[20:57:15] [PASSED] drm_test_cmdline_name_bpp_option
[20:57:15] [PASSED] drm_test_cmdline_rotate_0
[20:57:15] [PASSED] drm_test_cmdline_rotate_90
[20:57:15] [PASSED] drm_test_cmdline_rotate_180
[20:57:15] [PASSED] drm_test_cmdline_rotate_270
[20:57:15] [PASSED] drm_test_cmdline_hmirror
[20:57:15] [PASSED] drm_test_cmdline_vmirror
[20:57:15] [PASSED] drm_test_cmdline_margin_options
[20:57:15] [PASSED] drm_test_cmdline_multiple_options
[20:57:15] [PASSED] drm_test_cmdline_bpp_extra_and_option
[20:57:15] [PASSED] drm_test_cmdline_extra_and_option
[20:57:15] [PASSED] drm_test_cmdline_freestanding_options
[20:57:15] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[20:57:15] [PASSED] drm_test_cmdline_panel_orientation
[20:57:15] ================ drm_test_cmdline_invalid  =================
[20:57:15] [PASSED] margin_only
[20:57:15] [PASSED] interlace_only
[20:57:15] [PASSED] res_missing_x
[20:57:15] [PASSED] res_missing_y
[20:57:15] [PASSED] res_bad_y
[20:57:15] [PASSED] res_missing_y_bpp
[20:57:15] [PASSED] res_bad_bpp
[20:57:15] [PASSED] res_bad_refresh
[20:57:15] [PASSED] res_bpp_refresh_force_on_off
[20:57:15] [PASSED] res_invalid_mode
[20:57:15] [PASSED] res_bpp_wrong_place_mode
[20:57:15] [PASSED] name_bpp_refresh
[20:57:15] [PASSED] name_refresh
[20:57:15] [PASSED] name_refresh_wrong_mode
[20:57:15] [PASSED] name_refresh_invalid_mode
[20:57:15] [PASSED] rotate_multiple
[20:57:15] [PASSED] rotate_invalid_val
[20:57:15] [PASSED] rotate_truncated
[20:57:15] [PASSED] invalid_option
[20:57:15] [PASSED] invalid_tv_option
[20:57:15] [PASSED] truncated_tv_option
[20:57:15] ============ [PASSED] drm_test_cmdline_invalid =============
[20:57:15] =============== drm_test_cmdline_tv_options  ===============
[20:57:15] [PASSED] NTSC
[20:57:15] [PASSED] NTSC_443
[20:57:15] [PASSED] NTSC_J
[20:57:15] [PASSED] PAL
[20:57:15] [PASSED] PAL_M
[20:57:15] [PASSED] PAL_N
[20:57:15] [PASSED] SECAM
[20:57:15] [PASSED] MONO_525
[20:57:15] [PASSED] MONO_625
[20:57:15] =========== [PASSED] drm_test_cmdline_tv_options ===========
[20:57:15] =============== [PASSED] drm_cmdline_parser ================
[20:57:15] ========== drmm_connector_hdmi_init (20 subtests) ==========
[20:57:15] [PASSED] drm_test_connector_hdmi_init_valid
[20:57:15] [PASSED] drm_test_connector_hdmi_init_bpc_8
[20:57:15] [PASSED] drm_test_connector_hdmi_init_bpc_10
[20:57:15] [PASSED] drm_test_connector_hdmi_init_bpc_12
[20:57:15] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[20:57:15] [PASSED] drm_test_connector_hdmi_init_bpc_null
[20:57:15] [PASSED] drm_test_connector_hdmi_init_formats_empty
[20:57:15] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[20:57:15] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[20:57:15] [PASSED] supported_formats=0x9 yuv420_allowed=1
[20:57:15] [PASSED] supported_formats=0x9 yuv420_allowed=0
[20:57:15] [PASSED] supported_formats=0x3 yuv420_allowed=1
[20:57:15] [PASSED] supported_formats=0x3 yuv420_allowed=0
[20:57:15] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:57:15] [PASSED] drm_test_connector_hdmi_init_null_ddc
[20:57:15] [PASSED] drm_test_connector_hdmi_init_null_product
[20:57:15] [PASSED] drm_test_connector_hdmi_init_null_vendor
[20:57:15] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[20:57:15] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[20:57:15] [PASSED] drm_test_connector_hdmi_init_product_valid
[20:57:15] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[20:57:15] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[20:57:15] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[20:57:15] ========= drm_test_connector_hdmi_init_type_valid  =========
[20:57:15] [PASSED] HDMI-A
[20:57:15] [PASSED] HDMI-B
[20:57:15] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[20:57:15] ======== drm_test_connector_hdmi_init_type_invalid  ========
[20:57:15] [PASSED] Unknown
[20:57:15] [PASSED] VGA
[20:57:15] [PASSED] DVI-I
[20:57:15] [PASSED] DVI-D
[20:57:15] [PASSED] DVI-A
[20:57:15] [PASSED] Composite
[20:57:15] [PASSED] SVIDEO
[20:57:15] [PASSED] LVDS
[20:57:15] [PASSED] Component
[20:57:15] [PASSED] DIN
[20:57:15] [PASSED] DP
[20:57:15] [PASSED] TV
[20:57:15] [PASSED] eDP
[20:57:15] [PASSED] Virtual
[20:57:15] [PASSED] DSI
[20:57:15] [PASSED] DPI
[20:57:15] [PASSED] Writeback
[20:57:15] [PASSED] SPI
[20:57:15] [PASSED] USB
[20:57:15] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[20:57:15] ============ [PASSED] drmm_connector_hdmi_init =============
[20:57:15] ============= drmm_connector_init (3 subtests) =============
[20:57:15] [PASSED] drm_test_drmm_connector_init
[20:57:15] [PASSED] drm_test_drmm_connector_init_null_ddc
[20:57:15] ========= drm_test_drmm_connector_init_type_valid  =========
[20:57:15] [PASSED] Unknown
[20:57:15] [PASSED] VGA
[20:57:15] [PASSED] DVI-I
[20:57:15] [PASSED] DVI-D
[20:57:15] [PASSED] DVI-A
[20:57:15] [PASSED] Composite
[20:57:15] [PASSED] SVIDEO
[20:57:15] [PASSED] LVDS
[20:57:15] [PASSED] Component
[20:57:15] [PASSED] DIN
[20:57:15] [PASSED] DP
[20:57:15] [PASSED] HDMI-A
[20:57:15] [PASSED] HDMI-B
[20:57:15] [PASSED] TV
[20:57:15] [PASSED] eDP
[20:57:15] [PASSED] Virtual
[20:57:15] [PASSED] DSI
[20:57:15] [PASSED] DPI
[20:57:15] [PASSED] Writeback
[20:57:15] [PASSED] SPI
[20:57:15] [PASSED] USB
[20:57:15] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[20:57:15] =============== [PASSED] drmm_connector_init ===============
[20:57:15] ========= drm_connector_dynamic_init (6 subtests) ==========
[20:57:15] [PASSED] drm_test_drm_connector_dynamic_init
[20:57:15] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[20:57:15] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[20:57:15] [PASSED] drm_test_drm_connector_dynamic_init_properties
[20:57:15] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[20:57:15] [PASSED] Unknown
[20:57:15] [PASSED] VGA
[20:57:15] [PASSED] DVI-I
[20:57:15] [PASSED] DVI-D
[20:57:15] [PASSED] DVI-A
[20:57:15] [PASSED] Composite
[20:57:15] [PASSED] SVIDEO
[20:57:15] [PASSED] LVDS
[20:57:15] [PASSED] Component
[20:57:15] [PASSED] DIN
[20:57:15] [PASSED] DP
[20:57:15] [PASSED] HDMI-A
[20:57:15] [PASSED] HDMI-B
[20:57:15] [PASSED] TV
[20:57:15] [PASSED] eDP
[20:57:15] [PASSED] Virtual
[20:57:15] [PASSED] DSI
[20:57:15] [PASSED] DPI
[20:57:15] [PASSED] Writeback
[20:57:15] [PASSED] SPI
[20:57:15] [PASSED] USB
[20:57:15] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[20:57:15] ======== drm_test_drm_connector_dynamic_init_name  =========
[20:57:15] [PASSED] Unknown
[20:57:15] [PASSED] VGA
[20:57:15] [PASSED] DVI-I
[20:57:15] [PASSED] DVI-D
[20:57:15] [PASSED] DVI-A
[20:57:15] [PASSED] Composite
[20:57:15] [PASSED] SVIDEO
[20:57:15] [PASSED] LVDS
[20:57:15] [PASSED] Component
[20:57:15] [PASSED] DIN
[20:57:15] [PASSED] DP
[20:57:15] [PASSED] HDMI-A
[20:57:15] [PASSED] HDMI-B
[20:57:15] [PASSED] TV
[20:57:15] [PASSED] eDP
[20:57:15] [PASSED] Virtual
[20:57:15] [PASSED] DSI
[20:57:15] [PASSED] DPI
[20:57:15] [PASSED] Writeback
[20:57:15] [PASSED] SPI
[20:57:15] [PASSED] USB
[20:57:15] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[20:57:15] =========== [PASSED] drm_connector_dynamic_init ============
[20:57:15] ==== drm_connector_dynamic_register_early (4 subtests) =====
[20:57:15] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[20:57:15] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[20:57:15] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[20:57:15] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[20:57:15] ====== [PASSED] drm_connector_dynamic_register_early =======
[20:57:15] ======= drm_connector_dynamic_register (7 subtests) ========
[20:57:15] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[20:57:15] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[20:57:15] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[20:57:15] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[20:57:15] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[20:57:15] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[20:57:15] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[20:57:15] ========= [PASSED] drm_connector_dynamic_register ==========
[20:57:15] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[20:57:15] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[20:57:15] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[20:57:15] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[20:57:15] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[20:57:15] ========== drm_test_get_tv_mode_from_name_valid  ===========
[20:57:15] [PASSED] NTSC
[20:57:15] [PASSED] NTSC-443
[20:57:15] [PASSED] NTSC-J
[20:57:15] [PASSED] PAL
[20:57:15] [PASSED] PAL-M
[20:57:15] [PASSED] PAL-N
[20:57:15] [PASSED] SECAM
[20:57:15] [PASSED] Mono
[20:57:15] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[20:57:15] [PASSED] drm_test_get_tv_mode_from_name_truncated
[20:57:15] ============ [PASSED] drm_get_tv_mode_from_name ============
[20:57:15] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[20:57:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[20:57:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[20:57:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[20:57:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[20:57:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[20:57:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[20:57:15] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[20:57:15] [PASSED] VIC 96
[20:57:15] [PASSED] VIC 97
[20:57:15] [PASSED] VIC 101
[20:57:15] [PASSED] VIC 102
[20:57:15] [PASSED] VIC 106
[20:57:15] [PASSED] VIC 107
[20:57:15] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[20:57:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[20:57:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[20:57:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[20:57:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[20:57:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[20:57:15] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[20:57:15] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[20:57:15] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[20:57:15] [PASSED] Automatic
[20:57:15] [PASSED] Full
[20:57:15] [PASSED] Limited 16:235
[20:57:15] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[20:57:15] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[20:57:15] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[20:57:15] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[20:57:15] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[20:57:15] [PASSED] RGB
[20:57:15] [PASSED] YUV 4:2:0
[20:57:15] [PASSED] YUV 4:2:2
[20:57:15] [PASSED] YUV 4:4:4
[20:57:15] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[20:57:15] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[20:57:15] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[20:57:15] ============= drm_damage_helper (21 subtests) ==============
[20:57:15] [PASSED] drm_test_damage_iter_no_damage
[20:57:15] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[20:57:15] [PASSED] drm_test_damage_iter_no_damage_src_moved
[20:57:15] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[20:57:15] [PASSED] drm_test_damage_iter_no_damage_not_visible
[20:57:15] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[20:57:15] [PASSED] drm_test_damage_iter_no_damage_no_fb
[20:57:15] [PASSED] drm_test_damage_iter_simple_damage
[20:57:15] [PASSED] drm_test_damage_iter_single_damage
[20:57:15] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[20:57:15] [PASSED] drm_test_damage_iter_single_damage_outside_src
[20:57:15] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[20:57:15] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[20:57:15] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[20:57:15] [PASSED] drm_test_damage_iter_single_damage_src_moved
[20:57:15] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[20:57:15] [PASSED] drm_test_damage_iter_damage
[20:57:15] [PASSED] drm_test_damage_iter_damage_one_intersect
[20:57:15] [PASSED] drm_test_damage_iter_damage_one_outside
[20:57:15] [PASSED] drm_test_damage_iter_damage_src_moved
[20:57:15] [PASSED] drm_test_damage_iter_damage_not_visible
[20:57:15] ================ [PASSED] drm_damage_helper ================
[20:57:15] ============== drm_dp_mst_helper (3 subtests) ==============
[20:57:15] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[20:57:15] [PASSED] Clock 154000 BPP 30 DSC disabled
[20:57:15] [PASSED] Clock 234000 BPP 30 DSC disabled
[20:57:15] [PASSED] Clock 297000 BPP 24 DSC disabled
[20:57:15] [PASSED] Clock 332880 BPP 24 DSC enabled
[20:57:15] [PASSED] Clock 324540 BPP 24 DSC enabled
[20:57:15] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[20:57:15] ============== drm_test_dp_mst_calc_pbn_div  ===============
[20:57:15] [PASSED] Link rate 2000000 lane count 4
[20:57:15] [PASSED] Link rate 2000000 lane count 2
[20:57:15] [PASSED] Link rate 2000000 lane count 1
[20:57:15] [PASSED] Link rate 1350000 lane count 4
[20:57:15] [PASSED] Link rate 1350000 lane count 2
[20:57:15] [PASSED] Link rate 1350000 lane count 1
[20:57:15] [PASSED] Link rate 1000000 lane count 4
[20:57:15] [PASSED] Link rate 1000000 lane count 2
[20:57:15] [PASSED] Link rate 1000000 lane count 1
[20:57:15] [PASSED] Link rate 810000 lane count 4
[20:57:15] [PASSED] Link rate 810000 lane count 2
[20:57:15] [PASSED] Link rate 810000 lane count 1
[20:57:15] [PASSED] Link rate 540000 lane count 4
[20:57:15] [PASSED] Link rate 540000 lane count 2
[20:57:15] [PASSED] Link rate 540000 lane count 1
[20:57:15] [PASSED] Link rate 270000 lane count 4
[20:57:15] [PASSED] Link rate 270000 lane count 2
[20:57:15] [PASSED] Link rate 270000 lane count 1
[20:57:15] [PASSED] Link rate 162000 lane count 4
[20:57:15] [PASSED] Link rate 162000 lane count 2
[20:57:15] [PASSED] Link rate 162000 lane count 1
[20:57:15] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[20:57:15] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[20:57:15] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[20:57:15] [PASSED] DP_POWER_UP_PHY with port number
[20:57:15] [PASSED] DP_POWER_DOWN_PHY with port number
[20:57:15] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[20:57:15] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[20:57:15] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[20:57:15] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[20:57:15] [PASSED] DP_QUERY_PAYLOAD with port number
[20:57:15] [PASSED] DP_QUERY_PAYLOAD with VCPI
[20:57:15] [PASSED] DP_REMOTE_DPCD_READ with port number
[20:57:15] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[20:57:15] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[20:57:15] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[20:57:15] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[20:57:15] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[20:57:15] [PASSED] DP_REMOTE_I2C_READ with port number
[20:57:15] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[20:57:15] [PASSED] DP_REMOTE_I2C_READ with transactions array
[20:57:15] [PASSED] DP_REMOTE_I2C_WRITE with port number
[20:57:15] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[20:57:15] [PASSED] DP_REMOTE_I2C_WRITE with data array
[20:57:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[20:57:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[20:57:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[20:57:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[20:57:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[20:57:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[20:57:15] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[20:57:15] ================ [PASSED] drm_dp_mst_helper ================
[20:57:15] ================== drm_exec (7 subtests) ===================
[20:57:15] [PASSED] sanitycheck
[20:57:15] [PASSED] test_lock
[20:57:15] [PASSED] test_lock_unlock
[20:57:15] [PASSED] test_duplicates
[20:57:15] [PASSED] test_prepare
[20:57:15] [PASSED] test_prepare_array
[20:57:15] [PASSED] test_multiple_loops
[20:57:15] ==================== [PASSED] drm_exec =====================
[20:57:15] =========== drm_format_helper_test (17 subtests) ===========
[20:57:15] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[20:57:15] [PASSED] single_pixel_source_buffer
[20:57:15] [PASSED] single_pixel_clip_rectangle
[20:57:15] [PASSED] well_known_colors
[20:57:15] [PASSED] destination_pitch
[20:57:15] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[20:57:15] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[20:57:15] [PASSED] single_pixel_source_buffer
[20:57:15] [PASSED] single_pixel_clip_rectangle
[20:57:15] [PASSED] well_known_colors
[20:57:15] [PASSED] destination_pitch
[20:57:15] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[20:57:15] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[20:57:15] [PASSED] single_pixel_source_buffer
[20:57:15] [PASSED] single_pixel_clip_rectangle
[20:57:15] [PASSED] well_known_colors
[20:57:15] [PASSED] destination_pitch
[20:57:15] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[20:57:15] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[20:57:15] [PASSED] single_pixel_source_buffer
[20:57:15] [PASSED] single_pixel_clip_rectangle
[20:57:15] [PASSED] well_known_colors
[20:57:15] [PASSED] destination_pitch
[20:57:15] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[20:57:15] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[20:57:15] [PASSED] single_pixel_source_buffer
[20:57:15] [PASSED] single_pixel_clip_rectangle
[20:57:15] [PASSED] well_known_colors
[20:57:15] [PASSED] destination_pitch
[20:57:15] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[20:57:15] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[20:57:15] [PASSED] single_pixel_source_buffer
[20:57:15] [PASSED] single_pixel_clip_rectangle
[20:57:15] [PASSED] well_known_colors
[20:57:15] [PASSED] destination_pitch
[20:57:15] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[20:57:15] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[20:57:15] [PASSED] single_pixel_source_buffer
[20:57:15] [PASSED] single_pixel_clip_rectangle
[20:57:15] [PASSED] well_known_colors
[20:57:15] [PASSED] destination_pitch
[20:57:15] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[20:57:15] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[20:57:15] [PASSED] single_pixel_source_buffer
[20:57:15] [PASSED] single_pixel_clip_rectangle
[20:57:15] [PASSED] well_known_colors
[20:57:15] [PASSED] destination_pitch
[20:57:15] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[20:57:15] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[20:57:15] [PASSED] single_pixel_source_buffer
[20:57:15] [PASSED] single_pixel_clip_rectangle
[20:57:15] [PASSED] well_known_colors
[20:57:15] [PASSED] destination_pitch
[20:57:15] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[20:57:15] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[20:57:15] [PASSED] single_pixel_source_buffer
[20:57:15] [PASSED] single_pixel_clip_rectangle
[20:57:15] [PASSED] well_known_colors
[20:57:15] [PASSED] destination_pitch
[20:57:15] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[20:57:15] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[20:57:15] [PASSED] single_pixel_source_buffer
[20:57:15] [PASSED] single_pixel_clip_rectangle
[20:57:15] [PASSED] well_known_colors
[20:57:15] [PASSED] destination_pitch
[20:57:15] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[20:57:15] ============== drm_test_fb_xrgb8888_to_mono  ===============
[20:57:15] [PASSED] single_pixel_source_buffer
[20:57:15] [PASSED] single_pixel_clip_rectangle
[20:57:15] [PASSED] well_known_colors
[20:57:15] [PASSED] destination_pitch
[20:57:15] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[20:57:15] ==================== drm_test_fb_swab  =====================
[20:57:15] [PASSED] single_pixel_source_buffer
[20:57:15] [PASSED] single_pixel_clip_rectangle
[20:57:15] [PASSED] well_known_colors
[20:57:15] [PASSED] destination_pitch
[20:57:15] ================ [PASSED] drm_test_fb_swab =================
[20:57:15] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[20:57:15] [PASSED] single_pixel_source_buffer
[20:57:15] [PASSED] single_pixel_clip_rectangle
[20:57:15] [PASSED] well_known_colors
[20:57:15] [PASSED] destination_pitch
[20:57:15] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[20:57:15] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[20:57:15] [PASSED] single_pixel_source_buffer
[20:57:15] [PASSED] single_pixel_clip_rectangle
[20:57:15] [PASSED] well_known_colors
[20:57:15] [PASSED] destination_pitch
[20:57:15] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[20:57:15] ================= drm_test_fb_clip_offset  =================
[20:57:15] [PASSED] pass through
[20:57:15] [PASSED] horizontal offset
[20:57:15] [PASSED] vertical offset
[20:57:15] [PASSED] horizontal and vertical offset
[20:57:15] [PASSED] horizontal offset (custom pitch)
[20:57:15] [PASSED] vertical offset (custom pitch)
[20:57:15] [PASSED] horizontal and vertical offset (custom pitch)
[20:57:15] ============= [PASSED] drm_test_fb_clip_offset =============
[20:57:15] =================== drm_test_fb_memcpy  ====================
[20:57:15] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[20:57:15] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[20:57:15] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[20:57:15] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[20:57:15] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[20:57:15] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[20:57:15] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[20:57:15] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[20:57:15] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[20:57:15] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[20:57:15] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[20:57:15] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[20:57:15] =============== [PASSED] drm_test_fb_memcpy ================
[20:57:15] ============= [PASSED] drm_format_helper_test ==============
[20:57:15] ================= drm_format (18 subtests) =================
[20:57:15] [PASSED] drm_test_format_block_width_invalid
[20:57:15] [PASSED] drm_test_format_block_width_one_plane
[20:57:15] [PASSED] drm_test_format_block_width_two_plane
[20:57:15] [PASSED] drm_test_format_block_width_three_plane
[20:57:15] [PASSED] drm_test_format_block_width_tiled
[20:57:15] [PASSED] drm_test_format_block_height_invalid
[20:57:15] [PASSED] drm_test_format_block_height_one_plane
[20:57:15] [PASSED] drm_test_format_block_height_two_plane
[20:57:15] [PASSED] drm_test_format_block_height_three_plane
[20:57:15] [PASSED] drm_test_format_block_height_tiled
[20:57:15] [PASSED] drm_test_format_min_pitch_invalid
[20:57:15] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[20:57:15] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[20:57:15] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[20:57:15] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[20:57:15] [PASSED] drm_test_format_min_pitch_two_plane
[20:57:15] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[20:57:15] [PASSED] drm_test_format_min_pitch_tiled
[20:57:15] =================== [PASSED] drm_format ====================
[20:57:15] ============== drm_framebuffer (10 subtests) ===============
[20:57:15] ========== drm_test_framebuffer_check_src_coords  ==========
[20:57:15] [PASSED] Success: source fits into fb
[20:57:15] [PASSED] Fail: overflowing fb with x-axis coordinate
[20:57:15] [PASSED] Fail: overflowing fb with y-axis coordinate
[20:57:15] [PASSED] Fail: overflowing fb with source width
[20:57:15] [PASSED] Fail: overflowing fb with source height
[20:57:15] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[20:57:15] [PASSED] drm_test_framebuffer_cleanup
[20:57:15] =============== drm_test_framebuffer_create  ===============
[20:57:15] [PASSED] ABGR8888 normal sizes
[20:57:15] [PASSED] ABGR8888 max sizes
[20:57:15] [PASSED] ABGR8888 pitch greater than min required
[20:57:15] [PASSED] ABGR8888 pitch less than min required
[20:57:15] [PASSED] ABGR8888 Invalid width
[20:57:15] [PASSED] ABGR8888 Invalid buffer handle
[20:57:15] [PASSED] No pixel format
[20:57:15] [PASSED] ABGR8888 Width 0
[20:57:15] [PASSED] ABGR8888 Height 0
[20:57:15] [PASSED] ABGR8888 Out of bound height * pitch combination
[20:57:15] [PASSED] ABGR8888 Large buffer offset
[20:57:15] [PASSED] ABGR8888 Buffer offset for inexistent plane
[20:57:15] [PASSED] ABGR8888 Invalid flag
[20:57:15] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[20:57:15] [PASSED] ABGR8888 Valid buffer modifier
[20:57:15] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[20:57:15] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[20:57:15] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[20:57:15] [PASSED] NV12 Normal sizes
[20:57:15] [PASSED] NV12 Max sizes
[20:57:15] [PASSED] NV12 Invalid pitch
[20:57:15] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[20:57:15] [PASSED] NV12 different  modifier per-plane
[20:57:15] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[20:57:15] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[20:57:15] [PASSED] NV12 Modifier for inexistent plane
[20:57:15] [PASSED] NV12 Handle for inexistent plane
[20:57:15] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[20:57:15] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[20:57:15] [PASSED] YVU420 Normal sizes
[20:57:15] [PASSED] YVU420 Max sizes
[20:57:15] [PASSED] YVU420 Invalid pitch
[20:57:15] [PASSED] YVU420 Different pitches
[20:57:15] [PASSED] YVU420 Different buffer offsets/pitches
[20:57:15] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[20:57:15] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[20:57:15] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[20:57:15] [PASSED] YVU420 Valid modifier
[20:57:15] [PASSED] YVU420 Different modifiers per plane
[20:57:15] [PASSED] YVU420 Modifier for inexistent plane
[20:57:15] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[20:57:15] [PASSED] X0L2 Normal sizes
[20:57:15] [PASSED] X0L2 Max sizes
[20:57:15] [PASSED] X0L2 Invalid pitch
[20:57:15] [PASSED] X0L2 Pitch greater than minimum required
[20:57:15] [PASSED] X0L2 Handle for inexistent plane
[20:57:15] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[20:57:15] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[20:57:15] [PASSED] X0L2 Valid modifier
[20:57:15] [PASSED] X0L2 Modifier for inexistent plane
[20:57:15] =========== [PASSED] drm_test_framebuffer_create ===========
[20:57:15] [PASSED] drm_test_framebuffer_free
[20:57:15] [PASSED] drm_test_framebuffer_init
[20:57:15] [PASSED] drm_test_framebuffer_init_bad_format
[20:57:15] [PASSED] drm_test_framebuffer_init_dev_mismatch
[20:57:15] [PASSED] drm_test_framebuffer_lookup
[20:57:15] [PASSED] drm_test_framebuffer_lookup_inexistent
[20:57:15] [PASSED] drm_test_framebuffer_modifiers_not_supported
[20:57:15] ================= [PASSED] drm_framebuffer =================
[20:57:15] ================ drm_gem_shmem (8 subtests) ================
[20:57:15] [PASSED] drm_gem_shmem_test_obj_create
[20:57:15] [PASSED] drm_gem_shmem_test_obj_create_private
[20:57:15] [PASSED] drm_gem_shmem_test_pin_pages
[20:57:15] [PASSED] drm_gem_shmem_test_vmap
[20:57:15] [PASSED] drm_gem_shmem_test_get_pages_sgt
[20:57:15] [PASSED] drm_gem_shmem_test_get_sg_table
[20:57:15] [PASSED] drm_gem_shmem_test_madvise
[20:57:15] [PASSED] drm_gem_shmem_test_purge
[20:57:15] ================== [PASSED] drm_gem_shmem ==================
[20:57:15] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[20:57:15] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[20:57:15] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[20:57:15] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[20:57:15] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[20:57:15] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[20:57:15] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[20:57:15] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[20:57:15] [PASSED] Automatic
[20:57:15] [PASSED] Full
[20:57:15] [PASSED] Limited 16:235
[20:57:15] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[20:57:15] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[20:57:15] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[20:57:15] [PASSED] drm_test_check_disable_connector
[20:57:15] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[20:57:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[20:57:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[20:57:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[20:57:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[20:57:15] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[20:57:15] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[20:57:15] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[20:57:15] [PASSED] drm_test_check_output_bpc_dvi
[20:57:15] [PASSED] drm_test_check_output_bpc_format_vic_1
[20:57:15] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[20:57:15] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[20:57:15] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[20:57:15] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[20:57:15] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[20:57:15] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[20:57:15] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[20:57:15] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[20:57:15] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[20:57:15] [PASSED] drm_test_check_broadcast_rgb_value
[20:57:15] [PASSED] drm_test_check_bpc_8_value
[20:57:15] [PASSED] drm_test_check_bpc_10_value
[20:57:15] [PASSED] drm_test_check_bpc_12_value
[20:57:15] [PASSED] drm_test_check_format_value
[20:57:15] [PASSED] drm_test_check_tmds_char_value
[20:57:15] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[20:57:15] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[20:57:15] [PASSED] drm_test_check_mode_valid
[20:57:15] [PASSED] drm_test_check_mode_valid_reject
[20:57:15] [PASSED] drm_test_check_mode_valid_reject_rate
[20:57:15] [PASSED] drm_test_check_mode_valid_reject_max_clock
[20:57:15] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[20:57:15] ================= drm_managed (2 subtests) =================
[20:57:15] [PASSED] drm_test_managed_release_action
[20:57:15] [PASSED] drm_test_managed_run_action
[20:57:15] =================== [PASSED] drm_managed ===================
[20:57:15] =================== drm_mm (6 subtests) ====================
[20:57:15] [PASSED] drm_test_mm_init
[20:57:15] [PASSED] drm_test_mm_debug
[20:57:15] [PASSED] drm_test_mm_align32
[20:57:15] [PASSED] drm_test_mm_align64
[20:57:15] [PASSED] drm_test_mm_lowest
[20:57:15] [PASSED] drm_test_mm_highest
[20:57:15] ===================== [PASSED] drm_mm ======================
[20:57:15] ============= drm_modes_analog_tv (5 subtests) =============
[20:57:15] [PASSED] drm_test_modes_analog_tv_mono_576i
[20:57:15] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[20:57:15] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[20:57:15] [PASSED] drm_test_modes_analog_tv_pal_576i
[20:57:15] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[20:57:15] =============== [PASSED] drm_modes_analog_tv ===============
[20:57:15] ============== drm_plane_helper (2 subtests) ===============
[20:57:15] =============== drm_test_check_plane_state  ================
[20:57:15] [PASSED] clipping_simple
[20:57:15] [PASSED] clipping_rotate_reflect
[20:57:15] [PASSED] positioning_simple
[20:57:15] [PASSED] upscaling
[20:57:15] [PASSED] downscaling
[20:57:15] [PASSED] rounding1
[20:57:15] [PASSED] rounding2
[20:57:15] [PASSED] rounding3
[20:57:15] [PASSED] rounding4
[20:57:15] =========== [PASSED] drm_test_check_plane_state ============
[20:57:15] =========== drm_test_check_invalid_plane_state  ============
[20:57:15] [PASSED] positioning_invalid
[20:57:15] [PASSED] upscaling_invalid
[20:57:15] [PASSED] downscaling_invalid
[20:57:15] ======= [PASSED] drm_test_check_invalid_plane_state ========
[20:57:15] ================ [PASSED] drm_plane_helper =================
[20:57:15] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[20:57:15] ====== drm_test_connector_helper_tv_get_modes_check  =======
[20:57:15] [PASSED] None
[20:57:15] [PASSED] PAL
[20:57:15] [PASSED] NTSC
[20:57:15] [PASSED] Both, NTSC Default
[20:57:15] [PASSED] Both, PAL Default
[20:57:15] [PASSED] Both, NTSC Default, with PAL on command-line
[20:57:15] [PASSED] Both, PAL Default, with NTSC on command-line
[20:57:15] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[20:57:15] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[20:57:15] ================== drm_rect (9 subtests) ===================
[20:57:15] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[20:57:15] [PASSED] drm_test_rect_clip_scaled_not_clipped
[20:57:15] [PASSED] drm_test_rect_clip_scaled_clipped
[20:57:15] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[20:57:15] ================= drm_test_rect_intersect  =================
[20:57:15] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[20:57:15] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[20:57:15] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[20:57:15] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[20:57:15] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[20:57:15] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[20:57:15] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[20:57:15] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[20:57:15] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[20:57:15] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[20:57:15] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[20:57:15] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[20:57:15] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[20:57:15] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[20:57:15] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[20:57:15] ============= [PASSED] drm_test_rect_intersect =============
[20:57:15] ================ drm_test_rect_calc_hscale  ================
[20:57:15] [PASSED] normal use
[20:57:15] [PASSED] out of max range
[20:57:15] [PASSED] out of min range
[20:57:15] [PASSED] zero dst
[20:57:15] [PASSED] negative src
[20:57:15] [PASSED] negative dst
[20:57:15] ============ [PASSED] drm_test_rect_calc_hscale ============
[20:57:15] ================ drm_test_rect_calc_vscale  ================
[20:57:15] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[20:57:15] [PASSED] out of max range
[20:57:15] [PASSED] out of min range
[20:57:15] [PASSED] zero dst
[20:57:15] [PASSED] negative src
[20:57:15] [PASSED] negative dst
[20:57:15] ============ [PASSED] drm_test_rect_calc_vscale ============
[20:57:15] ================== drm_test_rect_rotate  ===================
[20:57:15] [PASSED] reflect-x
[20:57:15] [PASSED] reflect-y
[20:57:15] [PASSED] rotate-0
[20:57:15] [PASSED] rotate-90
[20:57:15] [PASSED] rotate-180
[20:57:15] [PASSED] rotate-270
[20:57:15] ============== [PASSED] drm_test_rect_rotate ===============
[20:57:15] ================ drm_test_rect_rotate_inv  =================
[20:57:15] [PASSED] reflect-x
[20:57:15] [PASSED] reflect-y
[20:57:15] [PASSED] rotate-0
[20:57:15] [PASSED] rotate-90
[20:57:15] [PASSED] rotate-180
[20:57:15] [PASSED] rotate-270
[20:57:15] ============ [PASSED] drm_test_rect_rotate_inv =============
[20:57:15] ==================== [PASSED] drm_rect =====================
[20:57:15] ============ drm_sysfb_modeset_test (1 subtest) ============
[20:57:15] ============ drm_test_sysfb_build_fourcc_list  =============
[20:57:15] [PASSED] no native formats
[20:57:15] [PASSED] XRGB8888 as native format
[20:57:15] [PASSED] remove duplicates
[20:57:15] [PASSED] convert alpha formats
[20:57:15] [PASSED] random formats
[20:57:15] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[20:57:15] ============= [PASSED] drm_sysfb_modeset_test ==============
[20:57:15] ============================================================
[20:57:15] Testing complete. Ran 622 tests: passed: 622
[20:57:15] Elapsed time: 25.734s total, 1.795s configuring, 23.518s building, 0.376s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[20:57:15] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:57:17] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:57:26] Starting KUnit Kernel (1/1)...
[20:57:26] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:57:26] ================= ttm_device (5 subtests) ==================
[20:57:26] [PASSED] ttm_device_init_basic
[20:57:26] [PASSED] ttm_device_init_multiple
[20:57:26] [PASSED] ttm_device_fini_basic
[20:57:26] [PASSED] ttm_device_init_no_vma_man
[20:57:26] ================== ttm_device_init_pools  ==================
[20:57:26] [PASSED] No DMA allocations, no DMA32 required
[20:57:26] [PASSED] DMA allocations, DMA32 required
[20:57:26] [PASSED] No DMA allocations, DMA32 required
[20:57:26] [PASSED] DMA allocations, no DMA32 required
[20:57:26] ============== [PASSED] ttm_device_init_pools ==============
[20:57:26] =================== [PASSED] ttm_device ====================
[20:57:26] ================== ttm_pool (8 subtests) ===================
[20:57:26] ================== ttm_pool_alloc_basic  ===================
[20:57:26] [PASSED] One page
[20:57:26] [PASSED] More than one page
[20:57:26] [PASSED] Above the allocation limit
[20:57:26] [PASSED] One page, with coherent DMA mappings enabled
[20:57:26] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:57:26] ============== [PASSED] ttm_pool_alloc_basic ===============
[20:57:26] ============== ttm_pool_alloc_basic_dma_addr  ==============
[20:57:26] [PASSED] One page
[20:57:26] [PASSED] More than one page
[20:57:26] [PASSED] Above the allocation limit
[20:57:26] [PASSED] One page, with coherent DMA mappings enabled
[20:57:26] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:57:26] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[20:57:26] [PASSED] ttm_pool_alloc_order_caching_match
[20:57:26] [PASSED] ttm_pool_alloc_caching_mismatch
[20:57:26] [PASSED] ttm_pool_alloc_order_mismatch
[20:57:26] [PASSED] ttm_pool_free_dma_alloc
[20:57:26] [PASSED] ttm_pool_free_no_dma_alloc
[20:57:26] [PASSED] ttm_pool_fini_basic
[20:57:26] ==================== [PASSED] ttm_pool =====================
[20:57:26] ================ ttm_resource (8 subtests) =================
[20:57:26] ================= ttm_resource_init_basic  =================
[20:57:26] [PASSED] Init resource in TTM_PL_SYSTEM
[20:57:26] [PASSED] Init resource in TTM_PL_VRAM
[20:57:26] [PASSED] Init resource in a private placement
[20:57:26] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[20:57:26] ============= [PASSED] ttm_resource_init_basic =============
[20:57:26] [PASSED] ttm_resource_init_pinned
[20:57:26] [PASSED] ttm_resource_fini_basic
[20:57:26] [PASSED] ttm_resource_manager_init_basic
[20:57:26] [PASSED] ttm_resource_manager_usage_basic
[20:57:26] [PASSED] ttm_resource_manager_set_used_basic
[20:57:26] [PASSED] ttm_sys_man_alloc_basic
[20:57:26] [PASSED] ttm_sys_man_free_basic
[20:57:26] ================== [PASSED] ttm_resource ===================
[20:57:26] =================== ttm_tt (15 subtests) ===================
[20:57:26] ==================== ttm_tt_init_basic  ====================
[20:57:26] [PASSED] Page-aligned size
[20:57:26] [PASSED] Extra pages requested
[20:57:26] ================ [PASSED] ttm_tt_init_basic ================
[20:57:26] [PASSED] ttm_tt_init_misaligned
[20:57:26] [PASSED] ttm_tt_fini_basic
[20:57:26] [PASSED] ttm_tt_fini_sg
[20:57:26] [PASSED] ttm_tt_fini_shmem
[20:57:26] [PASSED] ttm_tt_create_basic
[20:57:26] [PASSED] ttm_tt_create_invalid_bo_type
[20:57:26] [PASSED] ttm_tt_create_ttm_exists
[20:57:26] [PASSED] ttm_tt_create_failed
[20:57:26] [PASSED] ttm_tt_destroy_basic
[20:57:26] [PASSED] ttm_tt_populate_null_ttm
[20:57:26] [PASSED] ttm_tt_populate_populated_ttm
[20:57:26] [PASSED] ttm_tt_unpopulate_basic
[20:57:26] [PASSED] ttm_tt_unpopulate_empty_ttm
[20:57:26] [PASSED] ttm_tt_swapin_basic
[20:57:26] ===================== [PASSED] ttm_tt ======================
[20:57:26] =================== ttm_bo (14 subtests) ===================
[20:57:26] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[20:57:26] [PASSED] Cannot be interrupted and sleeps
[20:57:26] [PASSED] Cannot be interrupted, locks straight away
[20:57:26] [PASSED] Can be interrupted, sleeps
[20:57:26] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[20:57:26] [PASSED] ttm_bo_reserve_locked_no_sleep
[20:57:26] [PASSED] ttm_bo_reserve_no_wait_ticket
[20:57:26] [PASSED] ttm_bo_reserve_double_resv
[20:57:26] [PASSED] ttm_bo_reserve_interrupted
[20:57:26] [PASSED] ttm_bo_reserve_deadlock
[20:57:26] [PASSED] ttm_bo_unreserve_basic
[20:57:26] [PASSED] ttm_bo_unreserve_pinned
[20:57:26] [PASSED] ttm_bo_unreserve_bulk
[20:57:26] [PASSED] ttm_bo_fini_basic
[20:57:26] [PASSED] ttm_bo_fini_shared_resv
[20:57:26] [PASSED] ttm_bo_pin_basic
[20:57:26] [PASSED] ttm_bo_pin_unpin_resource
[20:57:26] [PASSED] ttm_bo_multiple_pin_one_unpin
[20:57:26] ===================== [PASSED] ttm_bo ======================
[20:57:26] ============== ttm_bo_validate (21 subtests) ===============
[20:57:26] ============== ttm_bo_init_reserved_sys_man  ===============
[20:57:26] [PASSED] Buffer object for userspace
[20:57:26] [PASSED] Kernel buffer object
[20:57:26] [PASSED] Shared buffer object
[20:57:26] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[20:57:26] ============== ttm_bo_init_reserved_mock_man  ==============
[20:57:26] [PASSED] Buffer object for userspace
[20:57:26] [PASSED] Kernel buffer object
[20:57:26] [PASSED] Shared buffer object
[20:57:26] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[20:57:26] [PASSED] ttm_bo_init_reserved_resv
[20:57:26] ================== ttm_bo_validate_basic  ==================
[20:57:26] [PASSED] Buffer object for userspace
[20:57:26] [PASSED] Kernel buffer object
[20:57:26] [PASSED] Shared buffer object
[20:57:26] ============== [PASSED] ttm_bo_validate_basic ==============
[20:57:26] [PASSED] ttm_bo_validate_invalid_placement
[20:57:26] ============= ttm_bo_validate_same_placement  ==============
[20:57:26] [PASSED] System manager
[20:57:26] [PASSED] VRAM manager
[20:57:26] ========= [PASSED] ttm_bo_validate_same_placement ==========
[20:57:26] [PASSED] ttm_bo_validate_failed_alloc
[20:57:26] [PASSED] ttm_bo_validate_pinned
[20:57:26] [PASSED] ttm_bo_validate_busy_placement
[20:57:26] ================ ttm_bo_validate_multihop  =================
[20:57:26] [PASSED] Buffer object for userspace
[20:57:26] [PASSED] Kernel buffer object
[20:57:26] [PASSED] Shared buffer object
[20:57:26] ============ [PASSED] ttm_bo_validate_multihop =============
[20:57:26] ========== ttm_bo_validate_no_placement_signaled  ==========
[20:57:26] [PASSED] Buffer object in system domain, no page vector
[20:57:26] [PASSED] Buffer object in system domain with an existing page vector
[20:57:26] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[20:57:26] ======== ttm_bo_validate_no_placement_not_signaled  ========
[20:57:26] [PASSED] Buffer object for userspace
[20:57:26] [PASSED] Kernel buffer object
[20:57:26] [PASSED] Shared buffer object
[20:57:26] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[20:57:26] [PASSED] ttm_bo_validate_move_fence_signaled
[20:57:26] ========= ttm_bo_validate_move_fence_not_signaled  =========
[20:57:26] [PASSED] Waits for GPU
[20:57:26] [PASSED] Tries to lock straight away
[20:57:26] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[20:57:26] [PASSED] ttm_bo_validate_happy_evict
[20:57:26] [PASSED] ttm_bo_validate_all_pinned_evict
[20:57:26] [PASSED] ttm_bo_validate_allowed_only_evict
[20:57:26] [PASSED] ttm_bo_validate_deleted_evict
[20:57:26] [PASSED] ttm_bo_validate_busy_domain_evict
[20:57:26] [PASSED] ttm_bo_validate_evict_gutting
[20:57:26] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[20:57:26] ================= [PASSED] ttm_bo_validate =================
[20:57:26] ============================================================
[20:57:26] Testing complete. Ran 101 tests: passed: 101
[20:57:26] Elapsed time: 11.386s total, 1.787s configuring, 9.383s building, 0.186s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Allow configfs to disable specific GT type(s) (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2498 bytes --]

== Series Details ==

Series: Allow configfs to disable specific GT type(s) (rev4)
URL   : https://patchwork.freedesktop.org/series/154739/
State : success

== Summary ==

CI Bug Log - changes from xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4_BAT -> xe-pw-154739v4_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-154739v4_BAT:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@sriov_basic@enable-vfs-autoprobe-on:
    - {bat-ptl-1}:        [PASS][1] -> [ABORT][2] +1 other test abort
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/bat-ptl-1/igt@sriov_basic@enable-vfs-autoprobe-on.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/bat-ptl-1/igt@sriov_basic@enable-vfs-autoprobe-on.html

  * igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-1:
    - {bat-ptl-2}:        [PASS][3] -> [ABORT][4] +1 other test abort
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/bat-ptl-2/igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-1.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/bat-ptl-2/igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-1.html

  * igt@xe_module_load@load:
    - {bat-ptl-vm}:       [PASS][5] -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/bat-ptl-vm/igt@xe_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/bat-ptl-vm/igt@xe_module_load@load.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).



Build changes
-------------

  * Linux: xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4 -> xe-pw-154739v4

  IGT_8575: 7efc313da1339df43a1b11bba57fef6c1257e65f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4: 90c02675d5fedea7f1d28c4e5c45f958de9bfee4
  xe-pw-154739v4: 154739v4

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/index.html

[-- Attachment #2: Type: text/html, Size: 3156 bytes --]

Re: [PATCH v4 04/23] drm/xe: Move 'vm_max_level' flag back to platform descriptor

[Lucas De Marchi]

On Tue, Oct 07, 2025 at 01:48:34PM -0700, Matt Roper wrote:
>The number of page table levels for PPGTT virtual addresses is something
>that should be tracked at the platform level rather than the IP level.
>Even when mixing and matching various graphics, media, and display IP
>blocks, the platform as a whole has to have consistent page table
>handling.  This is also a trait that should be tied to the platform even
>if the graphics IP itself is not present (e.g., if we disable the
>primary GT via configfs).
>
>v2:
> - Drop default value of 4 and explicitly set the value in each platform
>   descriptor.  (Lucas)
>v3:
> - Drop outdated code comment and commit message paragraph about default
>   value.  (Gustavo)
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Gustavo Sousa <gustavo.sousa@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

thanks
Lucas De Marchi

Re: [PATCH v4 03/23] drm/xe: Move 'va_bits' flag back to platform descriptor

[Lucas De Marchi]

On Tue, Oct 07, 2025 at 01:48:33PM -0700, Matt Roper wrote:
>The number of virtual address bits is something that should be tracked
>at the platform level rather than the IP level.  Even when mixing and
>matching various graphics, media, and display IP blocks, the platform as
>a whole has to have consistent page table handling.  This is also a
>trait that should be tied to the platform even if the graphics IP itself
>is not present (e.g., if we disable the primary GT via configfs).
>
>v2:
> - Drop the default value of 48 and explicitly set it in each relevant
>   descriptor.  (Lucas, Michal)
>v3:
> - Drop an outdated comment about default value.  (Michal)
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/xe/xe_pci.c       | 21 +++++++++++++++------
> drivers/gpu/drm/xe/xe_pci_types.h |  2 +-
> 2 files changed, 16 insertions(+), 7 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index 3f42b91efa28..69ed987fef67 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -52,13 +52,11 @@ __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
> static const struct xe_graphics_desc graphics_xelp = {
> 	.hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0),
>
>-	.va_bits = 48,
> 	.vm_max_level = 3,
> };
>
> #define XE_HP_FEATURES \
> 	.has_range_tlb_inval = true, \
>-	.va_bits = 48, \
> 	.vm_max_level = 3
>
> static const struct xe_graphics_desc graphics_xehpg = {
>@@ -84,7 +82,6 @@ static const struct xe_graphics_desc graphics_xehpc = {
> 		BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
>
> 	XE_HP_FEATURES,
>-	.va_bits = 57,
> 	.vm_max_level = 4,
> 	.vram_flags = XE_VRAM_FLAGS_NEED64K,
>
>@@ -108,7 +105,6 @@ static const struct xe_graphics_desc graphics_xelpg = {
> 	.has_range_tlb_inval = 1, \
> 	.has_usm = 1, \
> 	.has_64bit_timestamp = 1, \
>-	.va_bits = 48, \
> 	.vm_max_level = 4, \
> 	.hw_engine_mask = \
> 		BIT(XE_HW_ENGINE_RCS0) | \
>@@ -174,6 +170,7 @@ static const struct xe_device_desc tgl_desc = {
> 	.has_sriov = true,
> 	.max_gt_per_tile = 1,
> 	.require_force_probe = true,
>+	.va_bits = 48,
> };
>
> static const struct xe_device_desc rkl_desc = {
>@@ -185,6 +182,7 @@ static const struct xe_device_desc rkl_desc = {
> 	.has_llc = true,
> 	.max_gt_per_tile = 1,
> 	.require_force_probe = true,
>+	.va_bits = 48,
> };
>
> static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 };
>@@ -203,6 +201,7 @@ static const struct xe_device_desc adl_s_desc = {
> 		{ XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
> 		{},
> 	},
>+	.va_bits = 48,
> };
>
> static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 };
>@@ -221,6 +220,7 @@ static const struct xe_device_desc adl_p_desc = {
> 		{ XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
> 		{},
> 	},
>+	.va_bits = 48,
> };
>
> static const struct xe_device_desc adl_n_desc = {
>@@ -233,6 +233,7 @@ static const struct xe_device_desc adl_n_desc = {
> 	.has_sriov = true,
> 	.max_gt_per_tile = 1,
> 	.require_force_probe = true,
>+	.va_bits = 48,
> };
>
> #define DGFX_FEATURES \
>@@ -249,6 +250,7 @@ static const struct xe_device_desc dg1_desc = {
> 	.has_heci_gscfi = 1,
> 	.max_gt_per_tile = 1,
> 	.require_force_probe = true,
>+	.va_bits = 48,
> };
>
> static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 };
>@@ -265,7 +267,8 @@ static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 };
> 		{ XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \
> 		{ XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \
> 		{ } \
>-	}
>+	}, \
>+	.va_bits = 48
>
> static const struct xe_device_desc ats_m_desc = {
> 	.pre_gmdid_graphics_ip = &graphics_ip_xehpg,
>@@ -303,6 +306,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
> 	.max_gt_per_tile = 1,
> 	.max_remote_tiles = 1,
> 	.require_force_probe = true,
>+	.va_bits = 57,
> 	.has_mbx_power_limits = false,
> };
>
>@@ -314,6 +318,7 @@ static const struct xe_device_desc mtl_desc = {
> 	.has_display = true,
> 	.has_pxp = true,
> 	.max_gt_per_tile = 2,
>+	.va_bits = 48,
> };
>
> static const struct xe_device_desc lnl_desc = {
>@@ -323,6 +328,7 @@ static const struct xe_device_desc lnl_desc = {
> 	.has_pxp = true,
> 	.max_gt_per_tile = 2,
> 	.needs_scratch = true,
>+	.va_bits = 48,

as a follow up, maybe do a s/dma_mask_size/pa_bits/, so it's easy for
people enabling new platforms to reference e.g. bspec 70817 where they
are noted as "Virtual Address Range" and "Physical Address Range".


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

> };
>
> static const struct xe_device_desc bmg_desc = {
>@@ -338,6 +344,7 @@ static const struct xe_device_desc bmg_desc = {
> 	.has_sriov = true,
> 	.max_gt_per_tile = 2,
> 	.needs_scratch = true,
>+	.va_bits = 48,
> };
>
> static const struct xe_device_desc ptl_desc = {
>@@ -347,6 +354,7 @@ static const struct xe_device_desc ptl_desc = {
> 	.has_sriov = true,
> 	.max_gt_per_tile = 2,
> 	.needs_scratch = true,
>+	.va_bits = 48,
> };
>
> #undef PLATFORM
>@@ -584,6 +592,8 @@ static int xe_info_init_early(struct xe_device *xe,
> 		subplatform_desc->subplatform : XE_SUBPLATFORM_NONE;
>
> 	xe->info.dma_mask_size = desc->dma_mask_size;
>+	xe->info.va_bits = desc->va_bits;
>+
> 	xe->info.is_dgfx = desc->is_dgfx;
> 	xe->info.has_fan_control = desc->has_fan_control;
> 	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
>@@ -713,7 +723,6 @@ static int xe_info_init(struct xe_device *xe,
> 	}
>
> 	xe->info.vram_flags = graphics_desc->vram_flags;
>-	xe->info.va_bits = graphics_desc->va_bits;
> 	xe->info.vm_max_level = graphics_desc->vm_max_level;
> 	xe->info.has_asid = graphics_desc->has_asid;
> 	xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit;
>diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
>index 9b9766a3baa3..796439571abe 100644
>--- a/drivers/gpu/drm/xe/xe_pci_types.h
>+++ b/drivers/gpu/drm/xe/xe_pci_types.h
>@@ -30,6 +30,7 @@ struct xe_device_desc {
> 	u8 dma_mask_size;
> 	u8 max_remote_tiles:2;
> 	u8 max_gt_per_tile:2;
>+	u8 va_bits;
>
> 	u8 require_force_probe:1;
> 	u8 is_dgfx:1;
>@@ -51,7 +52,6 @@ struct xe_device_desc {
> };
>
> struct xe_graphics_desc {
>-	u8 va_bits;
> 	u8 vm_max_level;
> 	u8 vram_flags;
>
>-- 
>2.51.0
>

Re: [PATCH v4 03/23] drm/xe: Move 'va_bits' flag back to platform descriptor

[Matt Roper]

On Tue, Oct 07, 2025 at 05:02:57PM -0500, Lucas De Marchi wrote:
> On Tue, Oct 07, 2025 at 01:48:33PM -0700, Matt Roper wrote:
> > The number of virtual address bits is something that should be tracked
> > at the platform level rather than the IP level.  Even when mixing and
> > matching various graphics, media, and display IP blocks, the platform as
> > a whole has to have consistent page table handling.  This is also a
> > trait that should be tied to the platform even if the graphics IP itself
> > is not present (e.g., if we disable the primary GT via configfs).
> > 
> > v2:
> > - Drop the default value of 48 and explicitly set it in each relevant
> >   descriptor.  (Lucas, Michal)
> > v3:
> > - Drop an outdated comment about default value.  (Michal)
> > 
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_pci.c       | 21 +++++++++++++++------
> > drivers/gpu/drm/xe/xe_pci_types.h |  2 +-
> > 2 files changed, 16 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> > index 3f42b91efa28..69ed987fef67 100644
> > --- a/drivers/gpu/drm/xe/xe_pci.c
> > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > @@ -52,13 +52,11 @@ __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
> > static const struct xe_graphics_desc graphics_xelp = {
> > 	.hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0),
> > 
> > -	.va_bits = 48,
> > 	.vm_max_level = 3,
> > };
> > 
> > #define XE_HP_FEATURES \
> > 	.has_range_tlb_inval = true, \
> > -	.va_bits = 48, \
> > 	.vm_max_level = 3
> > 
> > static const struct xe_graphics_desc graphics_xehpg = {
> > @@ -84,7 +82,6 @@ static const struct xe_graphics_desc graphics_xehpc = {
> > 		BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
> > 
> > 	XE_HP_FEATURES,
> > -	.va_bits = 57,
> > 	.vm_max_level = 4,
> > 	.vram_flags = XE_VRAM_FLAGS_NEED64K,
> > 
> > @@ -108,7 +105,6 @@ static const struct xe_graphics_desc graphics_xelpg = {
> > 	.has_range_tlb_inval = 1, \
> > 	.has_usm = 1, \
> > 	.has_64bit_timestamp = 1, \
> > -	.va_bits = 48, \
> > 	.vm_max_level = 4, \
> > 	.hw_engine_mask = \
> > 		BIT(XE_HW_ENGINE_RCS0) | \
> > @@ -174,6 +170,7 @@ static const struct xe_device_desc tgl_desc = {
> > 	.has_sriov = true,
> > 	.max_gt_per_tile = 1,
> > 	.require_force_probe = true,
> > +	.va_bits = 48,
> > };
> > 
> > static const struct xe_device_desc rkl_desc = {
> > @@ -185,6 +182,7 @@ static const struct xe_device_desc rkl_desc = {
> > 	.has_llc = true,
> > 	.max_gt_per_tile = 1,
> > 	.require_force_probe = true,
> > +	.va_bits = 48,
> > };
> > 
> > static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 };
> > @@ -203,6 +201,7 @@ static const struct xe_device_desc adl_s_desc = {
> > 		{ XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
> > 		{},
> > 	},
> > +	.va_bits = 48,
> > };
> > 
> > static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 };
> > @@ -221,6 +220,7 @@ static const struct xe_device_desc adl_p_desc = {
> > 		{ XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
> > 		{},
> > 	},
> > +	.va_bits = 48,
> > };
> > 
> > static const struct xe_device_desc adl_n_desc = {
> > @@ -233,6 +233,7 @@ static const struct xe_device_desc adl_n_desc = {
> > 	.has_sriov = true,
> > 	.max_gt_per_tile = 1,
> > 	.require_force_probe = true,
> > +	.va_bits = 48,
> > };
> > 
> > #define DGFX_FEATURES \
> > @@ -249,6 +250,7 @@ static const struct xe_device_desc dg1_desc = {
> > 	.has_heci_gscfi = 1,
> > 	.max_gt_per_tile = 1,
> > 	.require_force_probe = true,
> > +	.va_bits = 48,
> > };
> > 
> > static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 };
> > @@ -265,7 +267,8 @@ static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 };
> > 		{ XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \
> > 		{ XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \
> > 		{ } \
> > -	}
> > +	}, \
> > +	.va_bits = 48
> > 
> > static const struct xe_device_desc ats_m_desc = {
> > 	.pre_gmdid_graphics_ip = &graphics_ip_xehpg,
> > @@ -303,6 +306,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
> > 	.max_gt_per_tile = 1,
> > 	.max_remote_tiles = 1,
> > 	.require_force_probe = true,
> > +	.va_bits = 57,
> > 	.has_mbx_power_limits = false,
> > };
> > 
> > @@ -314,6 +318,7 @@ static const struct xe_device_desc mtl_desc = {
> > 	.has_display = true,
> > 	.has_pxp = true,
> > 	.max_gt_per_tile = 2,
> > +	.va_bits = 48,
> > };
> > 
> > static const struct xe_device_desc lnl_desc = {
> > @@ -323,6 +328,7 @@ static const struct xe_device_desc lnl_desc = {
> > 	.has_pxp = true,
> > 	.max_gt_per_tile = 2,
> > 	.needs_scratch = true,
> > +	.va_bits = 48,
> 
> as a follow up, maybe do a s/dma_mask_size/pa_bits/, so it's easy for
> people enabling new platforms to reference e.g. bspec 70817 where they
> are noted as "Virtual Address Range" and "Physical Address Range".

I'm a little bit hesitant about making that rename, because the reality
is more complicated and confusing than that.  For example, bspec 53650
will tell you the physical address range of ADL-S is 46-bits, but we
still need to limit ourselves to 39 bits in the driver.  We were
confused during early ADL-S enabling because we thought the 46-bit
address space in the spec meant we should just set the mask size to
46-bits, but that caused a bunch of DMAR faults.

Rodrigo eventually tracked down a hardware architect who gave us some
more insight into what it all means at the platform level.  If I
understand correctly, the host physical addresses are indeed 46-bits
when MKTME + IOMMU is in use (HPA[45:42] is a MKTME key ID and
HPA[41:39] is always 0).  However that's only really relevant to the
IOMMU and hypervisor in those specific configurations.  Guest physical
addresses are still 39-bits, and when MKTME is disabled the platform is
limited to 39-bit addresses.

Basically the real details here wind up being a platform-level thing
that isn't always clearly documented or explained in the bspec.  Simply
taking the single value that the bspec calls "physical address range"
(with no other explanation) and plugging that into the driver sometimes
isn't the right thing to do.

dma_mask_size probably isn't the most descriptive structure field name
either, but at least it matches the Linux DMA mapping functions that we
need to call during init.


Matt

> 
> 
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> 
> Lucas De Marchi
> 
> > };
> > 
> > static const struct xe_device_desc bmg_desc = {
> > @@ -338,6 +344,7 @@ static const struct xe_device_desc bmg_desc = {
> > 	.has_sriov = true,
> > 	.max_gt_per_tile = 2,
> > 	.needs_scratch = true,
> > +	.va_bits = 48,
> > };
> > 
> > static const struct xe_device_desc ptl_desc = {
> > @@ -347,6 +354,7 @@ static const struct xe_device_desc ptl_desc = {
> > 	.has_sriov = true,
> > 	.max_gt_per_tile = 2,
> > 	.needs_scratch = true,
> > +	.va_bits = 48,
> > };
> > 
> > #undef PLATFORM
> > @@ -584,6 +592,8 @@ static int xe_info_init_early(struct xe_device *xe,
> > 		subplatform_desc->subplatform : XE_SUBPLATFORM_NONE;
> > 
> > 	xe->info.dma_mask_size = desc->dma_mask_size;
> > +	xe->info.va_bits = desc->va_bits;
> > +
> > 	xe->info.is_dgfx = desc->is_dgfx;
> > 	xe->info.has_fan_control = desc->has_fan_control;
> > 	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
> > @@ -713,7 +723,6 @@ static int xe_info_init(struct xe_device *xe,
> > 	}
> > 
> > 	xe->info.vram_flags = graphics_desc->vram_flags;
> > -	xe->info.va_bits = graphics_desc->va_bits;
> > 	xe->info.vm_max_level = graphics_desc->vm_max_level;
> > 	xe->info.has_asid = graphics_desc->has_asid;
> > 	xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit;
> > diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> > index 9b9766a3baa3..796439571abe 100644
> > --- a/drivers/gpu/drm/xe/xe_pci_types.h
> > +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> > @@ -30,6 +30,7 @@ struct xe_device_desc {
> > 	u8 dma_mask_size;
> > 	u8 max_remote_tiles:2;
> > 	u8 max_gt_per_tile:2;
> > +	u8 va_bits;
> > 
> > 	u8 require_force_probe:1;
> > 	u8 is_dgfx:1;
> > @@ -51,7 +52,6 @@ struct xe_device_desc {
> > };
> > 
> > struct xe_graphics_desc {
> > -	u8 va_bits;
> > 	u8 vm_max_level;
> > 	u8 vram_flags;
> > 
> > -- 
> > 2.51.0
> > 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

✗ Xe.CI.Full: failure for Allow configfs to disable specific GT type(s) (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 34897 bytes --]

== Series Details ==

Series: Allow configfs to disable specific GT type(s) (rev4)
URL   : https://patchwork.freedesktop.org/series/154739/
State : failure

== Summary ==

CI Bug Log - changes from xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4_FULL -> xe-pw-154739v4_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-154739v4_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-154739v4_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-154739v4_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_exec_system_allocator@many-execqueues-mmap-shared-remap:
    - shard-lnl:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-lnl-8/igt@xe_exec_system_allocator@many-execqueues-mmap-shared-remap.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-lnl-7/igt@xe_exec_system_allocator@many-execqueues-mmap-shared-remap.html

  
Known issues
------------

  Here are the changes found in xe-pw-154739v4_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@crc-atomic@pipe-c-hdmi-a-1:
    - shard-adlp:         [PASS][3] -> [FAIL][4] ([Intel XE#3884])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-adlp-1/igt@kms_async_flips@crc-atomic@pipe-c-hdmi-a-1.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-adlp-4/igt@kms_async_flips@crc-atomic@pipe-c-hdmi-a-1.html

  * igt@kms_atomic@atomic-plane-damage:
    - shard-adlp:         [PASS][5] -> [DMESG-WARN][6] ([Intel XE#2953] / [Intel XE#4173]) +2 other tests dmesg-warn
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-adlp-3/igt@kms_atomic@atomic-plane-damage.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-adlp-1/igt@kms_atomic@atomic-plane-damage.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][7] ([Intel XE#316]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-435/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_bw@linear-tiling-3-displays-3840x2160p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][8] ([Intel XE#367])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-435/igt@kms_bw@linear-tiling-3-displays-3840x2160p.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][9] ([Intel XE#787]) +97 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-463/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [PASS][10] -> [INCOMPLETE][11] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][12] ([Intel XE#6168])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][13] ([Intel XE#1727] / [Intel XE#3113])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][14] ([Intel XE#2705] / [Intel XE#4212] / [Intel XE#4522])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][15] ([Intel XE#455] / [Intel XE#787]) +15 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-2.html

  * igt@kms_cdclk@plane-scaling@pipe-b-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][16] ([Intel XE#4416]) +3 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-435/igt@kms_cdclk@plane-scaling@pipe-b-dp-4.html

  * igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k:
    - shard-dg2-set2:     NOTRUN -> [SKIP][17] ([Intel XE#373])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-435/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2-set2:     NOTRUN -> [FAIL][18] ([Intel XE#1178]) +2 other tests fail
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-435/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][19] ([Intel XE#307])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-435/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@srm@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][20] ([Intel XE#1178])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-1/igt@kms_content_protection@srm@pipe-a-dp-2.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-bmg:          [PASS][21] -> [SKIP][22] ([Intel XE#2291])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-1/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-bmg:          [PASS][23] -> [FAIL][24] ([Intel XE#1475])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
    - shard-bmg:          [PASS][25] -> [SKIP][26] ([Intel XE#2316]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-1/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-6/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
    - shard-adlp:         [PASS][27] -> [DMESG-WARN][28] ([Intel XE#4543]) +5 other tests dmesg-warn
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-adlp-2/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-adlp-8/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend@d-hdmi-a3:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][29] ([Intel XE#2049] / [Intel XE#2597])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-6/igt@kms_flip@flip-vs-suspend@d-hdmi-a3.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-y:
    - shard-adlp:         [PASS][30] -> [DMESG-FAIL][31] ([Intel XE#4543])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-y.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-y.html

  * igt@kms_frontbuffer_tracking@drrs-suspend:
    - shard-dg2-set2:     NOTRUN -> [SKIP][32] ([Intel XE#651]) +6 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-435/igt@kms_frontbuffer_tracking@drrs-suspend.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][33] ([Intel XE#653]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-435/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][34] -> [SKIP][35] ([Intel XE#1503])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-8/igt@kms_hdr@invalid-hdr.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-1/igt@kms_hdr@invalid-hdr.html

  * igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256:
    - shard-dg2-set2:     NOTRUN -> [FAIL][36] ([Intel XE#616]) +2 other tests fail
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-463/igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256.html

  * igt@kms_pm_rpm@universal-planes-dpms:
    - shard-adlp:         [PASS][37] -> [DMESG-WARN][38] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#5750])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-adlp-4/igt@kms_pm_rpm@universal-planes-dpms.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-adlp-9/igt@kms_pm_rpm@universal-planes-dpms.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][39] ([Intel XE#1406] / [Intel XE#1489])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-435/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-pr-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][40] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-435/igt@kms_psr@fbc-pr-dpms.html

  * igt@xe_eudebug@basic-vm-access-parameters-userptr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][41] ([Intel XE#4837])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-435/igt@xe_eudebug@basic-vm-access-parameters-userptr.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind:
    - shard-dg2-set2:     NOTRUN -> [SKIP][42] ([Intel XE#1392])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race:
    - shard-dg2-set2:     [PASS][43] -> [SKIP][44] ([Intel XE#1392]) +3 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-dg2-433/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_fault_mode@twice-userptr-invalidate-race-imm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][45] ([Intel XE#288]) +3 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-435/igt@xe_exec_fault_mode@twice-userptr-invalidate-race-imm.html

  * igt@xe_exec_system_allocator@threads-many-stride-malloc-bo-unmap:
    - shard-dg2-set2:     NOTRUN -> [SKIP][46] ([Intel XE#4915]) +24 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-435/igt@xe_exec_system_allocator@threads-many-stride-malloc-bo-unmap.html

  * igt@xe_module_load@force-load:
    - shard-dg2-set2:     NOTRUN -> [SKIP][47] ([Intel XE#378])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-435/igt@xe_module_load@force-load.html

  * igt@xe_oa@non-privileged-access-vaddr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][48] ([Intel XE#3573])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-435/igt@xe_oa@non-privileged-access-vaddr.html

  * igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p:
    - shard-dg2-set2:     NOTRUN -> [FAIL][49] ([Intel XE#1173])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-464/igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p.html

  * igt@xe_pm@s2idle-basic-exec:
    - shard-adlp:         [PASS][50] -> [DMESG-WARN][51] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4504])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-adlp-4/igt@xe_pm@s2idle-basic-exec.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-adlp-9/igt@xe_pm@s2idle-basic-exec.html

  * igt@xe_pmu@gt-frequency:
    - shard-dg2-set2:     [PASS][52] -> [FAIL][53] ([Intel XE#4819]) +1 other test fail
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-dg2-436/igt@xe_pmu@gt-frequency.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-435/igt@xe_pmu@gt-frequency.html
    - shard-lnl:          [PASS][54] -> [FAIL][55] ([Intel XE#5841]) +1 other test fail
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-lnl-3/igt@xe_pmu@gt-frequency.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-lnl-2/igt@xe_pmu@gt-frequency.html

  
#### Possible fixes ####

  * igt@kms_atomic_transition@plane-toggle-modeset-transition:
    - shard-adlp:         [FAIL][56] ([Intel XE#3908]) -> [PASS][57] +1 other test pass
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-adlp-4/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-adlp-9/igt@kms_atomic_transition@plane-toggle-modeset-transition.html

  * igt@kms_big_fb@linear-32bpp-rotate-0:
    - shard-adlp:         [DMESG-WARN][58] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][59]
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-adlp-6/igt@kms_big_fb@linear-32bpp-rotate-0.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-adlp-2/igt@kms_big_fb@linear-32bpp-rotate-0.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][60] ([Intel XE#4345]) -> [PASS][61]
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [INCOMPLETE][62] ([Intel XE#1727] / [Intel XE#3113]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-bmg:          [SKIP][64] ([Intel XE#2291]) -> [PASS][65] +5 other tests pass
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [FAIL][66] ([Intel XE#4633]) -> [PASS][67]
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-bmg:          [SKIP][68] ([Intel XE#4354]) -> [PASS][69]
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-6/igt@kms_dp_link_training@non-uhbr-sst.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-4/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-bmg:          [SKIP][70] ([Intel XE#4294]) -> [PASS][71]
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-6/igt@kms_dp_linktrain_fallback@dp-fallback.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-1/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@cd-dp2-hdmi-a3:
    - shard-bmg:          [FAIL][72] ([Intel XE#3321]) -> [PASS][73] +1 other test pass
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-2/igt@kms_flip@2x-flip-vs-expired-vblank@cd-dp2-hdmi-a3.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-7/igt@kms_flip@2x-flip-vs-expired-vblank@cd-dp2-hdmi-a3.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-bmg:          [SKIP][74] ([Intel XE#2316]) -> [PASS][75] +3 other tests pass
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-4/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][76] ([Intel XE#4543]) -> [PASS][77] +6 other tests pass
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-adlp-2/igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a1.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-adlp-8/igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a3:
    - shard-bmg:          [INCOMPLETE][78] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][79]
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-1/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-6/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y:
    - shard-adlp:         [DMESG-FAIL][80] ([Intel XE#4543]) -> [PASS][81]
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-x:
    - shard-adlp:         [FAIL][82] ([Intel XE#1874]) -> [PASS][83]
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-x.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-x.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-bmg:          [SKIP][84] ([Intel XE#1503]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-6/igt@kms_hdr@invalid-metadata-sizes.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-1/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-bmg:          [SKIP][86] ([Intel XE#3012]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-6/igt@kms_joiner@basic-force-big-joiner.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-4/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_plane_scaling@2x-scaler-multi-pipe:
    - shard-bmg:          [SKIP][88] ([Intel XE#2571]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-6/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-4/igt@kms_plane_scaling@2x-scaler-multi-pipe.html

  * igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap:
    - shard-dg2-set2:     [SKIP][90] ([Intel XE#1392]) -> [PASS][91] +6 other tests pass
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-463/igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap.html

  * igt@xe_exec_reset@cm-close-fd:
    - shard-adlp:         [DMESG-WARN][92] ([Intel XE#3868]) -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-adlp-3/igt@xe_exec_reset@cm-close-fd.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-adlp-1/igt@xe_exec_reset@cm-close-fd.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv:
    - shard-dg2-set2:     [DMESG-WARN][94] ([Intel XE#5893]) -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-dg2-435/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-436/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html

  
#### Warnings ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [INCOMPLETE][96] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345]) -> [INCOMPLETE][97] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_content_protection@srm:
    - shard-bmg:          [SKIP][98] ([Intel XE#2341]) -> [FAIL][99] ([Intel XE#1178])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-6/igt@kms_content_protection@srm.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-1/igt@kms_content_protection@srm.html

  * igt@kms_flip@flip-vs-rmfb:
    - shard-adlp:         [DMESG-WARN][100] ([Intel XE#4543] / [Intel XE#5208]) -> [DMESG-WARN][101] ([Intel XE#5208])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-adlp-8/igt@kms_flip@flip-vs-rmfb.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-adlp-3/igt@kms_flip@flip-vs-rmfb.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][102] ([Intel XE#2312]) -> [SKIP][103] ([Intel XE#5390]) +4 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          [SKIP][104] ([Intel XE#5390]) -> [SKIP][105] ([Intel XE#2312]) +6 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][106] ([Intel XE#2311]) -> [SKIP][107] ([Intel XE#2312]) +8 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][108] ([Intel XE#2312]) -> [SKIP][109] ([Intel XE#2311]) +8 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-msflip-blt:
    - shard-bmg:          [SKIP][110] ([Intel XE#2313]) -> [SKIP][111] ([Intel XE#2312]) +8 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-msflip-blt.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff:
    - shard-bmg:          [SKIP][112] ([Intel XE#2312]) -> [SKIP][113] ([Intel XE#2313]) +12 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][114] ([Intel XE#2426]) -> [SKIP][115] ([Intel XE#2509])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
    - shard-dg2-set2:     [SKIP][116] ([Intel XE#362]) -> [SKIP][117] ([Intel XE#1500])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-432/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-dg2-set2:     [ABORT][118] ([Intel XE#5466]) -> [ABORT][119] ([Intel XE#4917] / [Intel XE#5466])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-dg2-463/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-432/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  * igt@xe_peer2peer@write:
    - shard-dg2-set2:     [SKIP][120] ([Intel XE#1061]) -> [FAIL][121] ([Intel XE#1173])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4/shard-dg2-432/igt@xe_peer2peer@write.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/shard-dg2-464/igt@xe_peer2peer@write.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1475]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1475
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2571
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
  [Intel XE#3884]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3884
  [Intel XE#3908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3908
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4294
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4416
  [Intel XE#4504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4504
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
  [Intel XE#4819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4819
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5300
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
  [Intel XE#5750]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5750
  [Intel XE#5841]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5841
  [Intel XE#5893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5893
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929


Build changes
-------------

  * Linux: xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4 -> xe-pw-154739v4

  IGT_8575: 7efc313da1339df43a1b11bba57fef6c1257e65f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3882-90c02675d5fedea7f1d28c4e5c45f958de9bfee4: 90c02675d5fedea7f1d28c4e5c45f958de9bfee4
  xe-pw-154739v4: 154739v4

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154739v4/index.html

[-- Attachment #2: Type: text/html, Size: 40120 bytes --]

Re: [PATCH v4 07/23] drm/xe: Read VF GMD_ID with a specifically-allocated dummy GT

[Lucas De Marchi]

On Tue, Oct 07, 2025 at 01:48:37PM -0700, Matt Roper wrote:
>SRIOV VF initialization has a bit of a chicken and egg design problem.
>Determining the IP version of the graphics and media IPs can't be done
>via direct register reads as it is on PF or native and instead requires
>querying the GuC.  However initialization of the GT, including its GuC,
>needs to wait until after we know the IP versions so that the proper
>initialization steps for the platform/IP are followed.
>
>Currently the (somewhat hacky) solution is to manually fill out just
>enough fields in tile 0's primary GT structure to make it look as if the
>GT has been initialized so that the GuC can be partially initialized and
>queried to obtain the GMD_ID values.  When the GT gets properly
>initialized during the regular flows, the hacked-up values will get
>overwritten as part of the general initialization flows.
>
>Rather than using tile 0's primary GT structure to hold the hacked up
>values for querying every GT on every tile, instead allocate a dedicated
>dummy structure.  This will allow us to move the tile->primary_gt's
>allocation to a more consistent place later in the initialization flow
>in future patches (i.e., we shouldn't even allocate this GT structure if
>the GT is disabled/unavailable).  It also helps ensure there can't be
>any accidental leakage of initialization or state between the dummy
>initialization for GMD_ID and the real driver initialization of the GT.
>
>v2:
> - Initialize gt->tile for temporary GT.  (CI, Michal)
> - Use scope-based cleanup handler to free temp GT.  (Michal)
> - Propagate actual error code from xe_gt_sriov_vf_bootstrap() rather
>   than just setting IP version to 0.0 now that read_gmdid() can return
>   an error.  (Michal)
>
>Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/xe/tests/xe_pci.c |  6 ++-
> drivers/gpu/drm/xe/xe_pci.c       | 70 ++++++++++++++++++-------------
> 2 files changed, 45 insertions(+), 31 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/tests/xe_pci.c b/drivers/gpu/drm/xe/tests/xe_pci.c
>index 0f136bc85b76..969f1dacade8 100644
>--- a/drivers/gpu/drm/xe/tests/xe_pci.c
>+++ b/drivers/gpu/drm/xe/tests/xe_pci.c
>@@ -307,8 +307,8 @@ const void *xe_pci_id_gen_param(const void *prev, char *desc)
> }
> EXPORT_SYMBOL_IF_KUNIT(xe_pci_id_gen_param);
>
>-static void fake_read_gmdid(struct xe_device *xe, enum xe_gmdid_type type,
>-			    u32 *ver, u32 *revid)
>+static int fake_read_gmdid(struct xe_device *xe, enum xe_gmdid_type type,
>+			   u32 *ver, u32 *revid)
> {
> 	struct kunit *test = kunit_get_current_test();
> 	struct xe_pci_fake_data *data = test->priv;
>@@ -320,6 +320,8 @@ static void fake_read_gmdid(struct xe_device *xe, enum xe_gmdid_type type,
> 		*ver = data->graphics_verx100;
> 		*revid = xe_step_to_gmdid(data->step.graphics);
> 	}
>+
>+	return 0;
> }
>
> static void fake_xe_info_probe_tile_count(struct xe_device *xe)
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index 37ae49f4b648..02655cf9244d 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -464,7 +464,7 @@ enum xe_gmdid_type {
> 	GMDID_MEDIA
> };
>
>-static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid)
>+static int read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid)
> {
> 	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
> 	struct xe_reg gmdid_reg = GMD_ID;
>@@ -473,22 +473,24 @@ static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver,
> 	KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid);
>
> 	if (IS_SRIOV_VF(xe)) {
>-		struct xe_gt *gt = xe_root_mmio_gt(xe);
>-
> 		/*
> 		 * To get the value of the GMDID register, VFs must obtain it
> 		 * from the GuC using MMIO communication.
> 		 *
>-		 * Note that at this point the xe_gt is not fully uninitialized
>-		 * and only basic access to MMIO registers is possible. To use
>-		 * our existing GuC communication functions we must perform at
>-		 * least basic xe_gt and xe_guc initialization.
>-		 *
>-		 * Since to obtain the value of GMDID_MEDIA we need to use the
>-		 * media GuC, temporarily tweak the gt type.
>+		 * Note that at this point the GTs are not initialized and only
>+		 * tile-level access to MMIO registers is possible. To use our
>+		 * existing GuC communication functions we must create a dummy
>+		 * GT structure and perform at least basic xe_gt and xe_guc
>+		 * initialization.
> 		 */
>-		xe_gt_assert(gt, gt->info.type == XE_GT_TYPE_UNINITIALIZED);
>+		struct xe_gt *gt __free(kfree);

I think it's bad practice to leave it unassigned. Either assign it to
NULL or do the kzalloc() call here to avoid it having garbage if in
future the gt assignment is not the first thing in this scope.

other than that,  Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>+		int err;
>
>+		gt = kzalloc(sizeof(*gt), GFP_KERNEL);
>+		if (!gt)
>+			return -ENOMEM;
>+
>+		gt->tile = &xe->tiles[0];
> 		if (type == GMDID_MEDIA) {
> 			gt->info.id = 1;
> 			gt->info.type = XE_GT_TYPE_MEDIA;
>@@ -500,15 +502,11 @@ static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver,
> 		xe_gt_mmio_init(gt);
> 		xe_guc_comm_init_early(&gt->uc.guc);
>
>-		/* Don't bother with GMDID if failed to negotiate the GuC ABI */
>-		val = xe_gt_sriov_vf_bootstrap(gt) ? 0 : xe_gt_sriov_vf_gmdid(gt);
>+		err = xe_gt_sriov_vf_bootstrap(gt);
>+		if (err)
>+			return err;
>
>-		/*
>-		 * Only undo xe_gt.info here, the remaining changes made above
>-		 * will be overwritten as part of the regular initialization.
>-		 */
>-		gt->info.id = 0;
>-		gt->info.type = XE_GT_TYPE_UNINITIALIZED;
>+		val = xe_gt_sriov_vf_gmdid(gt);
> 	} else {
> 		/*
> 		 * GMD_ID is a GT register, but at this point in the driver
>@@ -526,6 +524,8 @@ static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver,
>
> 	*ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
> 	*revid = REG_FIELD_GET(GMD_ID_REVID, val);
>+
>+	return 0;
> }
>
> static const struct xe_ip *find_graphics_ip(unsigned int verx100)
>@@ -552,18 +552,21 @@ static const struct xe_ip *find_media_ip(unsigned int verx100)
>  * Read IP version from hardware and select graphics/media IP descriptors
>  * based on the result.
>  */
>-static void handle_gmdid(struct xe_device *xe,
>-			 const struct xe_ip **graphics_ip,
>-			 const struct xe_ip **media_ip,
>-			 u32 *graphics_revid,
>-			 u32 *media_revid)
>+static int handle_gmdid(struct xe_device *xe,
>+			const struct xe_ip **graphics_ip,
>+			const struct xe_ip **media_ip,
>+			u32 *graphics_revid,
>+			u32 *media_revid)
> {
> 	u32 ver;
>+	int ret;
>
> 	*graphics_ip = NULL;
> 	*media_ip = NULL;
>
>-	read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid);
>+	ret = read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid);
>+	if (ret)
>+		return ret;
>
> 	*graphics_ip = find_graphics_ip(ver);
> 	if (!*graphics_ip) {
>@@ -571,16 +574,21 @@ static void handle_gmdid(struct xe_device *xe,
> 			ver / 100, ver % 100);
> 	}
>
>-	read_gmdid(xe, GMDID_MEDIA, &ver, media_revid);
>+	ret = read_gmdid(xe, GMDID_MEDIA, &ver, media_revid);
>+	if (ret)
>+		return ret;
>+
> 	/* Media may legitimately be fused off / not present */
> 	if (ver == 0)
>-		return;
>+		return 0;
>
> 	*media_ip = find_media_ip(ver);
> 	if (!*media_ip) {
> 		drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n",
> 			ver / 100, ver % 100);
> 	}
>+
>+	return 0;
> }
>
> /*
>@@ -690,6 +698,7 @@ static int xe_info_init(struct xe_device *xe,
> 	const struct xe_media_desc *media_desc;
> 	struct xe_tile *tile;
> 	struct xe_gt *gt;
>+	int ret;
> 	u8 id;
>
> 	/*
>@@ -705,8 +714,11 @@ static int xe_info_init(struct xe_device *xe,
> 		xe->info.step = xe_step_pre_gmdid_get(xe);
> 	} else {
> 		xe_assert(xe, !desc->pre_gmdid_media_ip);
>-		handle_gmdid(xe, &graphics_ip, &media_ip,
>-			     &graphics_gmdid_revid, &media_gmdid_revid);
>+		ret = handle_gmdid(xe, &graphics_ip, &media_ip,
>+				   &graphics_gmdid_revid, &media_gmdid_revid);
>+		if (ret)
>+			return ret;
>+
> 		xe->info.step = xe_step_gmdid_get(xe,
> 						  graphics_gmdid_revid,
> 						  media_gmdid_revid);
>-- 
>2.51.0
>

Re: [PATCH v4 21/23] drm/xe: Break GT setup out of xe_info_init()

[Lucas De Marchi]

On Tue, Oct 07, 2025 at 01:48:51PM -0700, Matt Roper wrote:
>xe_info_init() is getting a bit long and hard to follow.  Break the
>allocation and basic initialization of the xe_gt structures out to their
>own functions.
>
>v2:
> - Rename new functions from init_* to alloc_*.  (Gustavo)
> - Move early NULL return of media GT before allocation.  (Gustavo)
>
>Cc: Gustavo Sousa <gustavo.sousa@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/xe/xe_pci.c | 88 +++++++++++++++++++++++--------------
> 1 file changed, 54 insertions(+), 34 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index f7aec1c5959b..a5932e4f4a23 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -688,6 +688,53 @@ static void xe_info_probe_tile_count(struct xe_device *xe)
> 	}
> }
>
>+static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
>+				      const struct xe_graphics_desc *graphics_desc,
>+				      const struct xe_media_desc *media_desc)
>+{
>+	struct xe_device *xe = tile_to_xe(tile);
>+	struct xe_gt *gt;
>+
>+	gt = xe_gt_alloc(tile);

Eventually I think it makes sense to move the desc defines to the
corresponding _types.h header and then leave this to be done by
xe_gt_alloc().

But that is a (potential) separate cleanup. This looks good.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

thanks
Lucas De Marchi


>+	if (IS_ERR(gt))
>+		return gt;
>+
>+	gt->info.type = XE_GT_TYPE_MAIN;
>+	gt->info.id = tile->id * xe->info.max_gt_per_tile;
>+	gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
>+	gt->info.engine_mask = graphics_desc->hw_engine_mask;
>+
>+	/*
>+	 * Before media version 13, the media IP was part of the primary GT
>+	 * so we need to add the media engines to the primary GT's engine list.
>+	 */
>+	if (MEDIA_VER(xe) < 13 && media_desc)
>+		gt->info.engine_mask |= media_desc->hw_engine_mask;
>+
>+	return gt;
>+}
>+
>+static struct xe_gt *alloc_media_gt(struct xe_tile *tile,
>+				    const struct xe_media_desc *media_desc)
>+{
>+	struct xe_device *xe = tile_to_xe(tile);
>+	struct xe_gt *gt;
>+
>+	if (MEDIA_VER(xe) < 13 || !media_desc)
>+		return NULL;
>+
>+	gt = xe_gt_alloc(tile);
>+	if (IS_ERR(gt))
>+		return gt;
>+
>+	gt->info.type = XE_GT_TYPE_MEDIA;
>+	gt->info.id = tile->id * xe->info.max_gt_per_tile + 1;
>+	gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state;
>+	gt->info.engine_mask = media_desc->hw_engine_mask;
>+
>+	return gt;
>+}
>+
> /*
>  * Initialize device info content that does require knowledge about
>  * graphics / media IP version.
>@@ -770,48 +817,21 @@ static int xe_info_init(struct xe_device *xe,
> 			return err;
> 	}
>
>-	/*
>-	 * All platforms have at least one primary GT.  Any platform with media
>-	 * version 13 or higher has an additional dedicated media GT.  And
>-	 * depending on the graphics IP there may be additional "remote tiles."
>-	 * All of these together determine the overall GT count.
>-	 */
>+	/* Allocate any GT and VRAM structures necessary for the platform. */
> 	for_each_tile(tile, xe, id) {
> 		int err;
>
>-		tile->primary_gt = xe_gt_alloc(tile);
>+		err = xe_tile_alloc_vram(tile);
>+		if (err)
>+			return err;
>+
>+		tile->primary_gt = alloc_primary_gt(tile, graphics_desc, media_desc);
> 		if (IS_ERR(tile->primary_gt))
> 			return PTR_ERR(tile->primary_gt);
>
>-		gt = tile->primary_gt;
>-		gt->info.type = XE_GT_TYPE_MAIN;
>-		gt->info.id = tile->id * xe->info.max_gt_per_tile;
>-		gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
>-		gt->info.engine_mask = graphics_desc->hw_engine_mask;
>-
>-		err = xe_tile_alloc_vram(tile);
>-		if (err)
>-			return err;
>-
>-		if (MEDIA_VER(xe) < 13 && media_desc)
>-			gt->info.engine_mask |= media_desc->hw_engine_mask;
>-
>-		if (MEDIA_VER(xe) < 13 || !media_desc)
>-			continue;
>-
>-		/*
>-		 * Allocate and setup media GT for platforms with standalone
>-		 * media.
>-		 */
>-		tile->media_gt = xe_gt_alloc(tile);
>+		tile->media_gt = alloc_media_gt(tile, media_desc);
> 		if (IS_ERR(tile->media_gt))
> 			return PTR_ERR(tile->media_gt);
>-
>-		gt = tile->media_gt;
>-		gt->info.type = XE_GT_TYPE_MEDIA;
>-		gt->info.id = tile->id * xe->info.max_gt_per_tile + 1;
>-		gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state;
>-		gt->info.engine_mask = media_desc->hw_engine_mask;
> 	}
>
> 	/*
>-- 
>2.51.0
>

Re: [PATCH v4 22/23] drm/xe/configfs: Add attribute to disable GT types

[Lucas De Marchi]

On Tue, Oct 07, 2025 at 01:48:52PM -0700, Matt Roper wrote:
>Preventing the driver from initializing GTs of specific type(s) can be
>useful for debugging and early hardware bringup.  Add a configfs
>attribute to allow this kind of control for debugging.
>
>With today's platforms and software design, this configuration setting
>is only effective for disabling the media GT since the driver currently
>requires that there always be a primary GT to probe the device.  However
>this might change in the future ---  in theory it should be possible
>(with some additional driver work) to allow an igpu device to come up
>with only the media GT and no primary GT.  Or to allow an igpu device to
>come up with no GTs at all (for display-only usage).  A primary GT will
>likely always be required on dgpu platforms because we rely on the BCS
>engines inside the primary GT for various vram operations.
>
>v2:
> - Expand/clarify kerneldoc for configfs attribute.  (Gustavo)
> - Tighten type usage in gt_types[] structure.  (Gustavo)
> - Adjust string parsing/name matching to match exact GT names and not
>   accept partial names.  (Gustavo)
>
>v3:
> - Switch to scope-based cleanup in gt_types_allowed_store() to fix a
>   leak if the device is already bound.  (Gustavo)
> - Switch configfs lookup interface to two boolean functions that
>   specify whether primary/media are supported rather than one function
>   that returns a mask.  This is simpler to use and understand.
>
>Cc: Gustavo Sousa <gustavo.sousa@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/xe/xe_configfs.c | 145 +++++++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_configfs.h |   4 +
> drivers/gpu/drm/xe/xe_pci.c      |  22 +++++
> 3 files changed, 171 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
>index 139663423185..e36cc5e1bc8f 100644
>--- a/drivers/gpu/drm/xe/xe_configfs.c
>+++ b/drivers/gpu/drm/xe/xe_configfs.c
>@@ -15,6 +15,7 @@
>
> #include "instructions/xe_mi_commands.h"
> #include "xe_configfs.h"
>+#include "xe_gt_types.h"
> #include "xe_hw_engine_types.h"
> #include "xe_module.h"
> #include "xe_pci_types.h"
>@@ -56,6 +57,7 @@
>  *	:
>  *	└── 0000:03:00.0
>  *	    ├── survivability_mode
>+ *	    ├── gt_types_allowed
>  *	    ├── engines_allowed
>  *	    └── enable_psmi
>  *
>@@ -79,6 +81,44 @@
>  *
>  * This attribute can only be set before binding to the device.
>  *
>+ * Allowed GT types:
>+ * -----------------
>+ *
>+ * Allow only specific types of GTs to be detected and initialized by the
>+ * driver.  Any combination of GT types can be enabled/disabled, although
>+ * some settings will cause the device to fail to probe.
>+ *
>+ * Writes support both comma- and newline-separated input format. Reads
>+ * will always return one GT type per line. "primary" and "media" are the
>+ * GT type names supported by this interface.
>+ *
>+ * This attribute can only be set before binding to the device.
>+ *
>+ * Examples:
>+ *
>+ * Allow both primary and media GTs to be initialized and used.  This matches
>+ * the driver's default behavior::
>+ *
>+ *	# echo 'primary,media' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
>+ *
>+ * Allow only the primary GT of each tile to be initialized and used,
>+ * effectively disabling the media GT if it exists on the platform::
>+ *
>+ *	# echo 'primary' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
>+ *
>+ * Allow only the media GT of each tile to be initialized and used,
>+ * effectively disabling the primary GT.  **This configuration will cause
>+ * device probe failure on all current platforms, but may be allowed on
>+ * igpu platforms in the future**::
>+ *
>+ *	# echo 'media' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
>+ *
>+ * Disable all GTs.  Only other GPU IP (such as display) is potentially usable.
>+ * **This configuration will cause device probe failure on all current
>+ * platforms, but may be allowed on igpu platforms in the future**::
>+ *
>+ *	# echo '' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
>+ *
>  * Allowed engines:
>  * ----------------
>  *
>@@ -187,6 +227,7 @@ struct xe_config_group_device {
> 	struct config_group group;
>
> 	struct xe_config_device {
>+		u64 gt_types_allowed;
> 		u64 engines_allowed;
> 		struct wa_bb ctx_restore_post_bb[XE_ENGINE_CLASS_MAX];
> 		struct wa_bb ctx_restore_mid_bb[XE_ENGINE_CLASS_MAX];
>@@ -201,6 +242,7 @@ struct xe_config_group_device {
> };
>
> static const struct xe_config_device device_defaults = {
>+	.gt_types_allowed = U64_MAX,
> 	.engines_allowed = U64_MAX,
> 	.survivability_mode = false,
> 	.enable_psmi = false,
>@@ -220,6 +262,7 @@ struct engine_info {
> /* Some helpful macros to aid on the sizing of buffer allocation when parsing */
> #define MAX_ENGINE_CLASS_CHARS 5
> #define MAX_ENGINE_INSTANCE_CHARS 2
>+#define MAX_GT_TYPE_CHARS 7
>
> static const struct engine_info engine_info[] = {
> 	{ .cls = "rcs", .mask = XE_HW_ENGINE_RCS_MASK, .engine_class = XE_ENGINE_CLASS_RENDER },
>@@ -230,6 +273,14 @@ static const struct engine_info engine_info[] = {
> 	{ .cls = "gsccs", .mask = XE_HW_ENGINE_GSCCS_MASK, .engine_class = XE_ENGINE_CLASS_OTHER },
> };
>
>+static const struct {
>+	const char name[MAX_GT_TYPE_CHARS + 1];
>+	enum xe_gt_type type;
>+} gt_types[] = {
>+	{ .name = "primary", .type = XE_GT_TYPE_MAIN },
>+	{ .name = "media", .type = XE_GT_TYPE_MEDIA },
>+};
>+
> static struct xe_config_group_device *to_xe_config_group_device(struct config_item *item)
> {
> 	return container_of(to_config_group(item), struct xe_config_group_device, group);
>@@ -292,6 +343,58 @@ static ssize_t survivability_mode_store(struct config_item *item, const char *pa
> 	return len;
> }
>
>+static ssize_t gt_types_allowed_show(struct config_item *item, char *page)
>+{
>+	struct xe_config_device *dev = to_xe_config_device(item);
>+	char *p = page;
>+
>+	for (size_t i = 0; i < ARRAY_SIZE(gt_types); i++)
>+		if (dev->gt_types_allowed & BIT_ULL(gt_types[i].type))
>+			p += sprintf(p, "%s\n", gt_types[i].name);
>+
>+	return p - page;
>+}
>+
>+static ssize_t gt_types_allowed_store(struct config_item *item, const char *page,
>+				      size_t len)
>+{
>+	struct xe_config_group_device *dev = to_xe_config_group_device(item);
>+	char *buf __free(kfree) = kstrdup(page, GFP_KERNEL);
>+	char *p = buf;
>+	u64 typemask = 0;
>+
>+	if (!buf)
>+		return -ENOMEM;
>+
>+	while (p) {
>+		char *typename = strsep(&p, ",\n");
>+		bool matched = false;
>+
>+		if (typename[0] == '\0')
>+			continue;
>+
>+		for (size_t i = 0; i < ARRAY_SIZE(gt_types); i++) {
>+			if (strcmp(typename, gt_types[i].name) == 0) {
>+				typemask |= BIT(gt_types[i].type);
>+				matched = true;
>+				break;
>+			}
>+		}
>+
>+		if (!matched)
>+			return -EINVAL;
>+	}
>+
>+	scoped_guard(mutex, &dev->lock) {
>+		if (is_bound(dev))
>+			return -EBUSY;
>+
>+		dev->config.gt_types_allowed = typemask;
>+	}
>+
>+	return len;
>+}
>+
> static ssize_t engines_allowed_show(struct config_item *item, char *page)
> {
> 	struct xe_config_device *dev = to_xe_config_device(item);
>@@ -672,6 +775,7 @@ CONFIGFS_ATTR(, ctx_restore_mid_bb);
> CONFIGFS_ATTR(, ctx_restore_post_bb);
> CONFIGFS_ATTR(, enable_psmi);
> CONFIGFS_ATTR(, engines_allowed);
>+CONFIGFS_ATTR(, gt_types_allowed);
> CONFIGFS_ATTR(, survivability_mode);
>
> static struct configfs_attribute *xe_config_device_attrs[] = {
>@@ -679,6 +783,7 @@ static struct configfs_attribute *xe_config_device_attrs[] = {
> 	&attr_ctx_restore_post_bb,
> 	&attr_enable_psmi,
> 	&attr_engines_allowed,
>+	&attr_gt_types_allowed,
> 	&attr_survivability_mode,
> 	NULL,
> };
>@@ -846,6 +951,7 @@ static void dump_custom_dev_config(struct pci_dev *pdev,
> 				 dev->config.attr_); \
> 	} while (0)
>
>+	PRI_CUSTOM_ATTR("%llx", gt_types_allowed);
> 	PRI_CUSTOM_ATTR("%llx", engines_allowed);
> 	PRI_CUSTOM_ATTR("%d", enable_psmi);
> 	PRI_CUSTOM_ATTR("%d", survivability_mode);
>@@ -896,6 +1002,45 @@ bool xe_configfs_get_survivability_mode(struct pci_dev *pdev)
> 	return mode;
> }
>
>+static u64 get_gt_types_allowed(struct xe_device *xe)
>+{
>+	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
>+	struct xe_config_group_device *dev = find_xe_config_group_device(pdev);
>+	u64 mask;
>+
>+	if (!dev)
>+		return device_defaults.gt_types_allowed;
>+
>+	mask = dev->config.gt_types_allowed;
>+	config_group_put(&dev->group);
>+
>+	return mask;
>+}
>+
>+/**
>+ * xe_configfs_primary_gt_supported - determine whether primary GTs are supported
>+ * @xe: xe device
>+ *
>+ * Return: True if primary GTs are enabled, false if they have been disabled via
>+ *     configfs.
>+ */
>+bool xe_configfs_primary_gt_supported(struct xe_device *xe)
>+{
>+	return (get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MAIN)) != 0;
>+}
>+
>+/**
>+ * xe_configfs_media_gt_supported - determine whether media GTs are supported
>+ * @xe: xe device
>+ *
>+ * Return: True if the media GTs are enabled, false if they have been disabled
>+ *     via configfs.
>+ */
>+bool xe_configfs_media_gt_supported(struct xe_device *xe)
>+{
>+	return (get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MEDIA)) != 0;
>+}
>+
> /**
>  * xe_configfs_get_engines_allowed - get engine allowed mask from configfs
>  * @pdev: pci device
>diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h
>index c61e0e47ed94..5624e965b911 100644
>--- a/drivers/gpu/drm/xe/xe_configfs.h
>+++ b/drivers/gpu/drm/xe/xe_configfs.h
>@@ -17,6 +17,8 @@ int xe_configfs_init(void);
> void xe_configfs_exit(void);
> void xe_configfs_check_device(struct pci_dev *pdev);
> bool xe_configfs_get_survivability_mode(struct pci_dev *pdev);
>+bool xe_configfs_primary_gt_supported(struct xe_device *xe);
>+bool xe_configfs_media_gt_supported(struct xe_device *xe);
> u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev);
> bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev);
> u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
>@@ -28,6 +30,8 @@ static inline int xe_configfs_init(void) { return 0; }
> static inline void xe_configfs_exit(void) { }
> static inline void xe_configfs_check_device(struct pci_dev *pdev) { }
> static inline bool xe_configfs_get_survivability_mode(struct pci_dev *pdev) { return false; }
>+static inline bool xe_configfs_primary_gt_supported(struct xe_device *xe) { return true; }
>+static inline bool xe_configfs_media_gt_supported(struct xe_device *xe) { return true; }
> static inline u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev) { return U64_MAX; }
> static inline bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev) { return false; }
> static inline u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index a5932e4f4a23..9c8ab2b41737 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -695,6 +695,11 @@ static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
> 	struct xe_device *xe = tile_to_xe(tile);
> 	struct xe_gt *gt;
>
>+	if (!xe_configfs_primary_gt_supported(xe)) {
>+		drm_info(&xe->drm, "Primary GT disabled via configfs\n");
>+		return NULL;
>+	}
>+
> 	gt = xe_gt_alloc(tile);
> 	if (IS_ERR(gt))
> 		return gt;
>@@ -720,6 +725,11 @@ static struct xe_gt *alloc_media_gt(struct xe_tile *tile,
> 	struct xe_device *xe = tile_to_xe(tile);
> 	struct xe_gt *gt;
>
>+	if (!xe_configfs_media_gt_supported(xe)) {
>+		drm_info(&xe->drm, "Media GT disabled via configfs\n");
>+		return NULL;
>+	}
>+
> 	if (MEDIA_VER(xe) < 13 || !media_desc)
> 		return NULL;
>
>@@ -829,6 +839,18 @@ static int xe_info_init(struct xe_device *xe,
> 		if (IS_ERR(tile->primary_gt))
> 			return PTR_ERR(tile->primary_gt);
>
>+		/*
>+		 * It's not currently possible to probe a device with the
>+		 * primary GT disabled.  With some work, this may be future in
>+		 * the possible for igpu platforms (although probably not for
>+		 * dgpu's since access to the primary GT's BCS engines is
>+		 * required for VRAM management).
>+		 */
>+		if (!tile->primary_gt) {
>+			drm_err(&xe->drm, "Cannot probe device with without a primary GT\n");
>+			return -ENODEV;


I think "fail to probe" should be ok. Advanced user using this interface should know what
to do. I was thinking about blocking this at the configfs level, so the
user is not allowed to do it until that path is cleared. Any particular
reason to do it here?

Lucas De Marchi

>+		}
>+
> 		tile->media_gt = alloc_media_gt(tile, media_desc);
> 		if (IS_ERR(tile->media_gt))
> 			return PTR_ERR(tile->media_gt);
>-- 
>2.51.0
>

Re: [PATCH v4 22/23] drm/xe/configfs: Add attribute to disable GT types

[Michal Wajdeczko]

On 10/7/2025 10:48 PM, Matt Roper wrote:
> Preventing the driver from initializing GTs of specific type(s) can be
> useful for debugging and early hardware bringup.  Add a configfs
> attribute to allow this kind of control for debugging.
> 
> With today's platforms and software design, this configuration setting
> is only effective for disabling the media GT since the driver currently
> requires that there always be a primary GT to probe the device.  However
> this might change in the future ---  in theory it should be possible
> (with some additional driver work) to allow an igpu device to come up
> with only the media GT and no primary GT.  Or to allow an igpu device to
> come up with no GTs at all (for display-only usage).  A primary GT will
> likely always be required on dgpu platforms because we rely on the BCS
> engines inside the primary GT for various vram operations.
> 
> v2:
>  - Expand/clarify kerneldoc for configfs attribute.  (Gustavo)
>  - Tighten type usage in gt_types[] structure.  (Gustavo)
>  - Adjust string parsing/name matching to match exact GT names and not
>    accept partial names.  (Gustavo)
> 
> v3:
>  - Switch to scope-based cleanup in gt_types_allowed_store() to fix a
>    leak if the device is already bound.  (Gustavo)
>  - Switch configfs lookup interface to two boolean functions that
>    specify whether primary/media are supported rather than one function
>    that returns a mask.  This is simpler to use and understand.
> 
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_configfs.c | 145 +++++++++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_configfs.h |   4 +
>  drivers/gpu/drm/xe/xe_pci.c      |  22 +++++
>  3 files changed, 171 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
> index 139663423185..e36cc5e1bc8f 100644
> --- a/drivers/gpu/drm/xe/xe_configfs.c
> +++ b/drivers/gpu/drm/xe/xe_configfs.c
> @@ -15,6 +15,7 @@
>  
>  #include "instructions/xe_mi_commands.h"
>  #include "xe_configfs.h"
> +#include "xe_gt_types.h"
>  #include "xe_hw_engine_types.h"
>  #include "xe_module.h"
>  #include "xe_pci_types.h"
> @@ -56,6 +57,7 @@
>   *	:
>   *	└── 0000:03:00.0
>   *	    ├── survivability_mode
> + *	    ├── gt_types_allowed

I'm wondering if we want to keep such advance knobs at the same level as others?
maybe create sub-group for them, like I did for sriov?

	    └── tweaks
	        ├── gt_types_allowed
	        ├── engines_allowed


>   *	    ├── engines_allowed
>   *	    └── enable_psmi

oops, and it looks that I missed to update this part of the doc when adding max_vfs with:

	    └── sriov
	        ├── max_vfs

>   *
> @@ -79,6 +81,44 @@
>   *
>   * This attribute can only be set before binding to the device.
>   *
> + * Allowed GT types:
> + * -----------------
> + *
> + * Allow only specific types of GTs to be detected and initialized by the
> + * driver.  Any combination of GT types can be enabled/disabled, although
> + * some settings will cause the device to fail to probe.
> + *
> + * Writes support both comma- and newline-separated input format. Reads
> + * will always return one GT type per line. "primary" and "media" are the
> + * GT type names supported by this interface.
> + *
> + * This attribute can only be set before binding to the device.
> + *
> + * Examples:
> + *
> + * Allow both primary and media GTs to be initialized and used.  This matches
> + * the driver's default behavior::
> + *
> + *	# echo 'primary,media' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed

maybe "all" as an alias?

> + *
> + * Allow only the primary GT of each tile to be initialized and used,
> + * effectively disabling the media GT if it exists on the platform::
> + *
> + *	# echo 'primary' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
> + *
> + * Allow only the media GT of each tile to be initialized and used,
> + * effectively disabling the primary GT.  **This configuration will cause
> + * device probe failure on all current platforms, but may be allowed on
> + * igpu platforms in the future**::
> + *
> + *	# echo 'media' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
> + *
> + * Disable all GTs.  Only other GPU IP (such as display) is potentially usable.
> + * **This configuration will cause device probe failure on all current
> + * platforms, but may be allowed on igpu platforms in the future**::
> + *
> + *	# echo '' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed

maybe "none" as an alias?

> + *
>   * Allowed engines:
>   * ----------------
>   *
> @@ -187,6 +227,7 @@ struct xe_config_group_device {
>  	struct config_group group;
>  
>  	struct xe_config_device {
> +		u64 gt_types_allowed;
>  		u64 engines_allowed;
>  		struct wa_bb ctx_restore_post_bb[XE_ENGINE_CLASS_MAX];
>  		struct wa_bb ctx_restore_mid_bb[XE_ENGINE_CLASS_MAX];
> @@ -201,6 +242,7 @@ struct xe_config_group_device {
>  };
>  
>  static const struct xe_config_device device_defaults = {
> +	.gt_types_allowed = U64_MAX,
>  	.engines_allowed = U64_MAX,
>  	.survivability_mode = false,
>  	.enable_psmi = false,
> @@ -220,6 +262,7 @@ struct engine_info {
>  /* Some helpful macros to aid on the sizing of buffer allocation when parsing */
>  #define MAX_ENGINE_CLASS_CHARS 5
>  #define MAX_ENGINE_INSTANCE_CHARS 2
> +#define MAX_GT_TYPE_CHARS 7
>  
>  static const struct engine_info engine_info[] = {
>  	{ .cls = "rcs", .mask = XE_HW_ENGINE_RCS_MASK, .engine_class = XE_ENGINE_CLASS_RENDER },
> @@ -230,6 +273,14 @@ static const struct engine_info engine_info[] = {
>  	{ .cls = "gsccs", .mask = XE_HW_ENGINE_GSCCS_MASK, .engine_class = XE_ENGINE_CLASS_OTHER },
>  };
>  
> +static const struct {
> +	const char name[MAX_GT_TYPE_CHARS + 1];
> +	enum xe_gt_type type;
> +} gt_types[] = {
> +	{ .name = "primary", .type = XE_GT_TYPE_MAIN },
> +	{ .name = "media", .type = XE_GT_TYPE_MEDIA },
> +};
> +
>  static struct xe_config_group_device *to_xe_config_group_device(struct config_item *item)
>  {
>  	return container_of(to_config_group(item), struct xe_config_group_device, group);
> @@ -292,6 +343,58 @@ static ssize_t survivability_mode_store(struct config_item *item, const char *pa
>  	return len;
>  }
>  
> +static ssize_t gt_types_allowed_show(struct config_item *item, char *page)
> +{
> +	struct xe_config_device *dev = to_xe_config_device(item);
> +	char *p = page;
> +
> +	for (size_t i = 0; i < ARRAY_SIZE(gt_types); i++)
> +		if (dev->gt_types_allowed & BIT_ULL(gt_types[i].type))
> +			p += sprintf(p, "%s\n", gt_types[i].name);
> +
> +	return p - page;
> +}
> +
> +static ssize_t gt_types_allowed_store(struct config_item *item, const char *page,
> +				      size_t len)
> +{
> +	struct xe_config_group_device *dev = to_xe_config_group_device(item);
> +	char *buf __free(kfree) = kstrdup(page, GFP_KERNEL);
> +	char *p = buf;
> +	u64 typemask = 0;
> +
> +	if (!buf)
> +		return -ENOMEM;
> +
> +	while (p) {
> +		char *typename = strsep(&p, ",\n");
> +		bool matched = false;
> +
> +		if (typename[0] == '\0')
> +			continue;
> +
> +		for (size_t i = 0; i < ARRAY_SIZE(gt_types); i++) {
> +			if (strcmp(typename, gt_types[i].name) == 0) {
> +				typemask |= BIT(gt_types[i].type);
> +				matched = true;
> +				break;
> +			}
> +		}
> +
> +		if (!matched)
> +			return -EINVAL;
> +	}
> +
> +	scoped_guard(mutex, &dev->lock) {

probably plain guard(mutex) will work here too

> +		if (is_bound(dev))
> +			return -EBUSY;

then we can take a lock and return earlier, before parsing input

> +
> +		dev->config.gt_types_allowed = typemask;
> +	}
> +
> +	return len;
> +}
> +
>  static ssize_t engines_allowed_show(struct config_item *item, char *page)
>  {
>  	struct xe_config_device *dev = to_xe_config_device(item);
> @@ -672,6 +775,7 @@ CONFIGFS_ATTR(, ctx_restore_mid_bb);
>  CONFIGFS_ATTR(, ctx_restore_post_bb);
>  CONFIGFS_ATTR(, enable_psmi);
>  CONFIGFS_ATTR(, engines_allowed);
> +CONFIGFS_ATTR(, gt_types_allowed);
>  CONFIGFS_ATTR(, survivability_mode);
>  
>  static struct configfs_attribute *xe_config_device_attrs[] = {
> @@ -679,6 +783,7 @@ static struct configfs_attribute *xe_config_device_attrs[] = {
>  	&attr_ctx_restore_post_bb,
>  	&attr_enable_psmi,
>  	&attr_engines_allowed,
> +	&attr_gt_types_allowed,
>  	&attr_survivability_mode,
>  	NULL,
>  };
> @@ -846,6 +951,7 @@ static void dump_custom_dev_config(struct pci_dev *pdev,
>  				 dev->config.attr_); \
>  	} while (0)
>  
> +	PRI_CUSTOM_ATTR("%llx", gt_types_allowed);
>  	PRI_CUSTOM_ATTR("%llx", engines_allowed);
>  	PRI_CUSTOM_ATTR("%d", enable_psmi);
>  	PRI_CUSTOM_ATTR("%d", survivability_mode);
> @@ -896,6 +1002,45 @@ bool xe_configfs_get_survivability_mode(struct pci_dev *pdev)
>  	return mode;
>  }
>  
> +static u64 get_gt_types_allowed(struct xe_device *xe)
> +{
> +	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> +	struct xe_config_group_device *dev = find_xe_config_group_device(pdev);
> +	u64 mask;
> +
> +	if (!dev)
> +		return device_defaults.gt_types_allowed;
> +
> +	mask = dev->config.gt_types_allowed;

btw, as we are using guard during write, shouldn't we also guard during read?

> +	config_group_put(&dev->group);
> +
> +	return mask;
> +}
> +
> +/**
> + * xe_configfs_primary_gt_supported - determine whether primary GTs are supported
> + * @xe: xe device
> + *
> + * Return: True if primary GTs are enabled, false if they have been disabled via
> + *     configfs.
> + */
> +bool xe_configfs_primary_gt_supported(struct xe_device *xe)
> +{
> +	return (get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MAIN)) != 0;

can't we just rely on the promotion to bool?

	return get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MAIN);

> +}
> +
> +/**
> + * xe_configfs_media_gt_supported - determine whether media GTs are supported
> + * @xe: xe device
> + *
> + * Return: True if the media GTs are enabled, false if they have been disabled
> + *     via configfs.
> + */
> +bool xe_configfs_media_gt_supported(struct xe_device *xe)
> +{
> +	return (get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MEDIA)) != 0;
> +}
> +
>  /**
>   * xe_configfs_get_engines_allowed - get engine allowed mask from configfs
>   * @pdev: pci device
> diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h
> index c61e0e47ed94..5624e965b911 100644
> --- a/drivers/gpu/drm/xe/xe_configfs.h
> +++ b/drivers/gpu/drm/xe/xe_configfs.h
> @@ -17,6 +17,8 @@ int xe_configfs_init(void);
>  void xe_configfs_exit(void);
>  void xe_configfs_check_device(struct pci_dev *pdev);
>  bool xe_configfs_get_survivability_mode(struct pci_dev *pdev);
> +bool xe_configfs_primary_gt_supported(struct xe_device *xe);
> +bool xe_configfs_media_gt_supported(struct xe_device *xe);

I guess we need decide now whether we want to continue to pass pdev or switch to xe as argument for all xe_configfs functions

>  u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev);
>  bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev);
>  u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
> @@ -28,6 +30,8 @@ static inline int xe_configfs_init(void) { return 0; }
>  static inline void xe_configfs_exit(void) { }
>  static inline void xe_configfs_check_device(struct pci_dev *pdev) { }
>  static inline bool xe_configfs_get_survivability_mode(struct pci_dev *pdev) { return false; }
> +static inline bool xe_configfs_primary_gt_supported(struct xe_device *xe) { return true; }
> +static inline bool xe_configfs_media_gt_supported(struct xe_device *xe) { return true; }
>  static inline u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev) { return U64_MAX; }
>  static inline bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev) { return false; }
>  static inline u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index a5932e4f4a23..9c8ab2b41737 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -695,6 +695,11 @@ static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
>  	struct xe_device *xe = tile_to_xe(tile);
>  	struct xe_gt *gt;
>  
> +	if (!xe_configfs_primary_gt_supported(xe)) {
> +		drm_info(&xe->drm, "Primary GT disabled via configfs\n");

nit: you can use xe_info(xe, "...") now

> +		return NULL;
> +	}
> +
>  	gt = xe_gt_alloc(tile);
>  	if (IS_ERR(gt))
>  		return gt;
> @@ -720,6 +725,11 @@ static struct xe_gt *alloc_media_gt(struct xe_tile *tile,
>  	struct xe_device *xe = tile_to_xe(tile);
>  	struct xe_gt *gt;
>  
> +	if (!xe_configfs_media_gt_supported(xe)) {
> +		drm_info(&xe->drm, "Media GT disabled via configfs\n");
> +		return NULL;
> +	}
> +
>  	if (MEDIA_VER(xe) < 13 || !media_desc)
>  		return NULL;
>  
> @@ -829,6 +839,18 @@ static int xe_info_init(struct xe_device *xe,
>  		if (IS_ERR(tile->primary_gt))
>  			return PTR_ERR(tile->primary_gt);
>  
> +		/*
> +		 * It's not currently possible to probe a device with the
> +		 * primary GT disabled.  With some work, this may be future in
> +		 * the possible for igpu platforms (although probably not for
> +		 * dgpu's since access to the primary GT's BCS engines is
> +		 * required for VRAM management).
> +		 */
> +		if (!tile->primary_gt) {
> +			drm_err(&xe->drm, "Cannot probe device with without a primary GT\n");
> +			return -ENODEV;
> +		}
> +
>  		tile->media_gt = alloc_media_gt(tile, media_desc);
>  		if (IS_ERR(tile->media_gt))
>  			return PTR_ERR(tile->media_gt);

Re: [PATCH v4 04/23] drm/xe: Move 'vm_max_level' flag back to platform descriptor

[Gustavo Sousa]

Quoting Matt Roper (2025-10-07 17:48:34-03:00)
>The number of page table levels for PPGTT virtual addresses is something
>that should be tracked at the platform level rather than the IP level.
>Even when mixing and matching various graphics, media, and display IP
>blocks, the platform as a whole has to have consistent page table
>handling.  This is also a trait that should be tied to the platform even
>if the graphics IP itself is not present (e.g., if we disable the
>primary GT via configfs).
>
>v2:
> - Drop default value of 4 and explicitly set the value in each platform
>   descriptor.  (Lucas)
>v3:
> - Drop outdated code comment and commit message paragraph about default
>   value.  (Gustavo)
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Gustavo Sousa <gustavo.sousa@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/xe/xe_pci.c       | 22 ++++++++++++++--------
> drivers/gpu/drm/xe/xe_pci_types.h |  2 +-
> 2 files changed, 15 insertions(+), 9 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index 69ed987fef67..8688f40f55d8 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -51,13 +51,10 @@ __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
> 
> static const struct xe_graphics_desc graphics_xelp = {
>         .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0),
>-
>-        .vm_max_level = 3,
> };
> 
> #define XE_HP_FEATURES \
>-        .has_range_tlb_inval = true, \
>-        .vm_max_level = 3
>+        .has_range_tlb_inval = true
> 
> static const struct xe_graphics_desc graphics_xehpg = {
>         .hw_engine_mask =
>@@ -82,7 +79,6 @@ static const struct xe_graphics_desc graphics_xehpc = {
>                 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
> 
>         XE_HP_FEATURES,
>-        .vm_max_level = 4,
>         .vram_flags = XE_VRAM_FLAGS_NEED64K,
> 
>         .has_asid = 1,
>@@ -105,7 +101,6 @@ static const struct xe_graphics_desc graphics_xelpg = {
>         .has_range_tlb_inval = 1, \
>         .has_usm = 1, \
>         .has_64bit_timestamp = 1, \
>-        .vm_max_level = 4, \
>         .hw_engine_mask = \
>                 BIT(XE_HW_ENGINE_RCS0) | \
>                 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \
>@@ -183,6 +178,7 @@ static const struct xe_device_desc rkl_desc = {
>         .max_gt_per_tile = 1,
>         .require_force_probe = true,
>         .va_bits = 48,
>+        .vm_max_level = 3,
> };

I think we are missing setting ".vm_max_level = 3" for tgl_desc as well.
With that fixed,

    Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

> 
> static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 };
>@@ -202,6 +198,7 @@ static const struct xe_device_desc adl_s_desc = {
>                 {},
>         },
>         .va_bits = 48,
>+        .vm_max_level = 3,
> };
> 
> static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 };
>@@ -221,6 +218,7 @@ static const struct xe_device_desc adl_p_desc = {
>                 {},
>         },
>         .va_bits = 48,
>+        .vm_max_level = 3,
> };
> 
> static const struct xe_device_desc adl_n_desc = {
>@@ -234,6 +232,7 @@ static const struct xe_device_desc adl_n_desc = {
>         .max_gt_per_tile = 1,
>         .require_force_probe = true,
>         .va_bits = 48,
>+        .vm_max_level = 3,
> };
> 
> #define DGFX_FEATURES \
>@@ -251,6 +250,7 @@ static const struct xe_device_desc dg1_desc = {
>         .max_gt_per_tile = 1,
>         .require_force_probe = true,
>         .va_bits = 48,
>+        .vm_max_level = 3,
> };
> 
> static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 };
>@@ -268,7 +268,8 @@ static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 };
>                 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \
>                 { } \
>         }, \
>-        .va_bits = 48
>+        .va_bits = 48, \
>+        .vm_max_level = 3
> 
> static const struct xe_device_desc ats_m_desc = {
>         .pre_gmdid_graphics_ip = &graphics_ip_xehpg,
>@@ -307,6 +308,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
>         .max_remote_tiles = 1,
>         .require_force_probe = true,
>         .va_bits = 57,
>+        .vm_max_level = 4,
>         .has_mbx_power_limits = false,
> };
> 
>@@ -319,6 +321,7 @@ static const struct xe_device_desc mtl_desc = {
>         .has_pxp = true,
>         .max_gt_per_tile = 2,
>         .va_bits = 48,
>+        .vm_max_level = 4,
> };
> 
> static const struct xe_device_desc lnl_desc = {
>@@ -329,6 +332,7 @@ static const struct xe_device_desc lnl_desc = {
>         .max_gt_per_tile = 2,
>         .needs_scratch = true,
>         .va_bits = 48,
>+        .vm_max_level = 4,
> };
> 
> static const struct xe_device_desc bmg_desc = {
>@@ -345,6 +349,7 @@ static const struct xe_device_desc bmg_desc = {
>         .max_gt_per_tile = 2,
>         .needs_scratch = true,
>         .va_bits = 48,
>+        .vm_max_level = 4,
> };
> 
> static const struct xe_device_desc ptl_desc = {
>@@ -355,6 +360,7 @@ static const struct xe_device_desc ptl_desc = {
>         .max_gt_per_tile = 2,
>         .needs_scratch = true,
>         .va_bits = 48,
>+        .vm_max_level = 4,
> };
> 
> #undef PLATFORM
>@@ -593,6 +599,7 @@ static int xe_info_init_early(struct xe_device *xe,
> 
>         xe->info.dma_mask_size = desc->dma_mask_size;
>         xe->info.va_bits = desc->va_bits;
>+        xe->info.vm_max_level = desc->vm_max_level;
> 
>         xe->info.is_dgfx = desc->is_dgfx;
>         xe->info.has_fan_control = desc->has_fan_control;
>@@ -723,7 +730,6 @@ static int xe_info_init(struct xe_device *xe,
>         }
> 
>         xe->info.vram_flags = graphics_desc->vram_flags;
>-        xe->info.vm_max_level = graphics_desc->vm_max_level;
>         xe->info.has_asid = graphics_desc->has_asid;
>         xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit;
>         if (xe->info.platform != XE_PVC)
>diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
>index 796439571abe..6354280584d9 100644
>--- a/drivers/gpu/drm/xe/xe_pci_types.h
>+++ b/drivers/gpu/drm/xe/xe_pci_types.h
>@@ -31,6 +31,7 @@ struct xe_device_desc {
>         u8 max_remote_tiles:2;
>         u8 max_gt_per_tile:2;
>         u8 va_bits;
>+        u8 vm_max_level;
> 
>         u8 require_force_probe:1;
>         u8 is_dgfx:1;
>@@ -52,7 +53,6 @@ struct xe_device_desc {
> };
> 
> struct xe_graphics_desc {
>-        u8 vm_max_level;
>         u8 vram_flags;
> 
>         u64 hw_engine_mask;        /* hardware engines provided by graphics IP */
>-- 
>2.51.0
>

Re: [PATCH v4 12/23] drm/xe: Check for primary GT before looking up Wa_22019338487

[Gustavo Sousa]

Quoting Matt Roper (2025-10-07 17:48:42-03:00)
>If the primary GT is disabled via configfs, we need to make sure that we
>don't search for this workaround on a NULL xe_gt pointer.  Since we can
>disable the primary GT only on igpu platforms, the media GT is the one
>we'd want to check anyway for this workaround.
>
>The ternary operators in ggtt_update_access_counter() were getting a bit
>long/complicated, so rewrite them with regular if/else statements.
>While we're at it, throw in a couple extra assertions to make sure that
>we're truly picking the expected GT according to igpu/dgpu type.
>
>v2:
> - Adjust indentation/wrapping; it's easier to read this with longer,
>   unwrapped lines.  (Lucas)
> - Tweak wording of commit message to remove ambiguity.  (Gustavo)
>
>Cc: Gustavo Sousa <gustavo.sousa@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

>---
> drivers/gpu/drm/xe/xe_ggtt.c | 31 ++++++++++++++++++++++---------
> 1 file changed, 22 insertions(+), 9 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
>index 7fdd0a97a628..9707c41539c8 100644
>--- a/drivers/gpu/drm/xe/xe_ggtt.c
>+++ b/drivers/gpu/drm/xe/xe_ggtt.c
>@@ -107,10 +107,23 @@ static unsigned int probe_gsm_size(struct pci_dev *pdev)
> static void ggtt_update_access_counter(struct xe_ggtt *ggtt)
> {
>         struct xe_tile *tile = ggtt->tile;
>-        struct xe_gt *affected_gt = XE_GT_WA(tile->primary_gt, 22019338487) ?
>-                tile->primary_gt : tile->media_gt;
>-        struct xe_mmio *mmio = &affected_gt->mmio;
>-        u32 max_gtt_writes = XE_GT_WA(ggtt->tile->primary_gt, 22019338487) ? 1100 : 63;
>+        struct xe_gt *affected_gt;
>+        u32 max_gtt_writes;
>+
>+        if (tile->primary_gt && XE_GT_WA(tile->primary_gt, 22019338487)) {
>+                affected_gt = tile->primary_gt;
>+                max_gtt_writes = 1100;
>+
>+                /* Only expected to apply to primary GT on dgpu platforms */
>+                xe_tile_assert(tile, IS_DGFX(tile_to_xe(tile)));
>+        } else {
>+                affected_gt = tile->media_gt;
>+                max_gtt_writes = 63;
>+
>+                /* Only expected to apply to media GT on igpu platforms */
>+                xe_tile_assert(tile, !IS_DGFX(tile_to_xe(tile)));
>+        }
>+
>         /*
>          * Wa_22019338487: GMD_ID is a RO register, a dummy write forces gunit
>          * to wait for completion of prior GTT writes before letting this through.
>@@ -119,7 +132,7 @@ static void ggtt_update_access_counter(struct xe_ggtt *ggtt)
>         lockdep_assert_held(&ggtt->lock);
> 
>         if ((++ggtt->access_count % max_gtt_writes) == 0) {
>-                xe_mmio_write32(mmio, GMD_ID, 0x0);
>+                xe_mmio_write32(&affected_gt->mmio, GMD_ID, 0x0);
>                 ggtt->access_count = 0;
>         }
> }
>@@ -284,10 +297,10 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt)
>                 ggtt->size = GUC_GGTT_TOP;
> 
>         if (GRAPHICS_VERx100(xe) >= 1270)
>-                ggtt->pt_ops = (ggtt->tile->media_gt &&
>-                               XE_GT_WA(ggtt->tile->media_gt, 22019338487)) ||
>-                               XE_GT_WA(ggtt->tile->primary_gt, 22019338487) ?
>-                               &xelpg_pt_wa_ops : &xelpg_pt_ops;
>+                ggtt->pt_ops =
>+                        (ggtt->tile->media_gt && XE_GT_WA(ggtt->tile->media_gt, 22019338487)) ||
>+                        (ggtt->tile->primary_gt && XE_GT_WA(ggtt->tile->primary_gt, 22019338487)) ?
>+                        &xelpg_pt_wa_ops : &xelpg_pt_ops;
>         else
>                 ggtt->pt_ops = &xelp_pt_ops;
> 
>-- 
>2.51.0
>

Re: [PATCH v4 21/23] drm/xe: Break GT setup out of xe_info_init()

[Gustavo Sousa]

Quoting Matt Roper (2025-10-07 17:48:51-03:00)
>xe_info_init() is getting a bit long and hard to follow.  Break the
>allocation and basic initialization of the xe_gt structures out to their
>own functions.
>
>v2:
> - Rename new functions from init_* to alloc_*.  (Gustavo)
> - Move early NULL return of media GT before allocation.  (Gustavo)
>
>Cc: Gustavo Sousa <gustavo.sousa@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

>---
> drivers/gpu/drm/xe/xe_pci.c | 88 +++++++++++++++++++++++--------------
> 1 file changed, 54 insertions(+), 34 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index f7aec1c5959b..a5932e4f4a23 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -688,6 +688,53 @@ static void xe_info_probe_tile_count(struct xe_device *xe)
>         }
> }
> 
>+static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
>+                                      const struct xe_graphics_desc *graphics_desc,
>+                                      const struct xe_media_desc *media_desc)
>+{
>+        struct xe_device *xe = tile_to_xe(tile);
>+        struct xe_gt *gt;
>+
>+        gt = xe_gt_alloc(tile);
>+        if (IS_ERR(gt))
>+                return gt;
>+
>+        gt->info.type = XE_GT_TYPE_MAIN;
>+        gt->info.id = tile->id * xe->info.max_gt_per_tile;
>+        gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
>+        gt->info.engine_mask = graphics_desc->hw_engine_mask;
>+
>+        /*
>+         * Before media version 13, the media IP was part of the primary GT
>+         * so we need to add the media engines to the primary GT's engine list.
>+         */
>+        if (MEDIA_VER(xe) < 13 && media_desc)
>+                gt->info.engine_mask |= media_desc->hw_engine_mask;
>+
>+        return gt;
>+}
>+
>+static struct xe_gt *alloc_media_gt(struct xe_tile *tile,
>+                                    const struct xe_media_desc *media_desc)
>+{
>+        struct xe_device *xe = tile_to_xe(tile);
>+        struct xe_gt *gt;
>+
>+        if (MEDIA_VER(xe) < 13 || !media_desc)
>+                return NULL;
>+
>+        gt = xe_gt_alloc(tile);
>+        if (IS_ERR(gt))
>+                return gt;
>+
>+        gt->info.type = XE_GT_TYPE_MEDIA;
>+        gt->info.id = tile->id * xe->info.max_gt_per_tile + 1;
>+        gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state;
>+        gt->info.engine_mask = media_desc->hw_engine_mask;
>+
>+        return gt;
>+}
>+
> /*
>  * Initialize device info content that does require knowledge about
>  * graphics / media IP version.
>@@ -770,48 +817,21 @@ static int xe_info_init(struct xe_device *xe,
>                         return err;
>         }
> 
>-        /*
>-         * All platforms have at least one primary GT.  Any platform with media
>-         * version 13 or higher has an additional dedicated media GT.  And
>-         * depending on the graphics IP there may be additional "remote tiles."
>-         * All of these together determine the overall GT count.
>-         */
>+        /* Allocate any GT and VRAM structures necessary for the platform. */
>         for_each_tile(tile, xe, id) {
>                 int err;
> 
>-                tile->primary_gt = xe_gt_alloc(tile);
>+                err = xe_tile_alloc_vram(tile);
>+                if (err)
>+                        return err;
>+
>+                tile->primary_gt = alloc_primary_gt(tile, graphics_desc, media_desc);
>                 if (IS_ERR(tile->primary_gt))
>                         return PTR_ERR(tile->primary_gt);
> 
>-                gt = tile->primary_gt;
>-                gt->info.type = XE_GT_TYPE_MAIN;
>-                gt->info.id = tile->id * xe->info.max_gt_per_tile;
>-                gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
>-                gt->info.engine_mask = graphics_desc->hw_engine_mask;
>-
>-                err = xe_tile_alloc_vram(tile);
>-                if (err)
>-                        return err;
>-
>-                if (MEDIA_VER(xe) < 13 && media_desc)
>-                        gt->info.engine_mask |= media_desc->hw_engine_mask;
>-
>-                if (MEDIA_VER(xe) < 13 || !media_desc)
>-                        continue;
>-
>-                /*
>-                 * Allocate and setup media GT for platforms with standalone
>-                 * media.
>-                 */
>-                tile->media_gt = xe_gt_alloc(tile);
>+                tile->media_gt = alloc_media_gt(tile, media_desc);
>                 if (IS_ERR(tile->media_gt))
>                         return PTR_ERR(tile->media_gt);
>-
>-                gt = tile->media_gt;
>-                gt->info.type = XE_GT_TYPE_MEDIA;
>-                gt->info.id = tile->id * xe->info.max_gt_per_tile + 1;
>-                gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state;
>-                gt->info.engine_mask = media_desc->hw_engine_mask;
>         }
> 
>         /*
>-- 
>2.51.0
>

Re: [PATCH v4 22/23] drm/xe/configfs: Add attribute to disable GT types

[Gustavo Sousa]

Quoting Matt Roper (2025-10-07 17:48:52-03:00)
>Preventing the driver from initializing GTs of specific type(s) can be
>useful for debugging and early hardware bringup.  Add a configfs
>attribute to allow this kind of control for debugging.
>
>With today's platforms and software design, this configuration setting
>is only effective for disabling the media GT since the driver currently
>requires that there always be a primary GT to probe the device.  However
>this might change in the future ---  in theory it should be possible
>(with some additional driver work) to allow an igpu device to come up
>with only the media GT and no primary GT.  Or to allow an igpu device to
>come up with no GTs at all (for display-only usage).  A primary GT will
>likely always be required on dgpu platforms because we rely on the BCS
>engines inside the primary GT for various vram operations.
>
>v2:
> - Expand/clarify kerneldoc for configfs attribute.  (Gustavo)
> - Tighten type usage in gt_types[] structure.  (Gustavo)
> - Adjust string parsing/name matching to match exact GT names and not
>   accept partial names.  (Gustavo)
>
>v3:
> - Switch to scope-based cleanup in gt_types_allowed_store() to fix a
>   leak if the device is already bound.  (Gustavo)
> - Switch configfs lookup interface to two boolean functions that
>   specify whether primary/media are supported rather than one function
>   that returns a mask.  This is simpler to use and understand.
>
>Cc: Gustavo Sousa <gustavo.sousa@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/xe/xe_configfs.c | 145 +++++++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_configfs.h |   4 +
> drivers/gpu/drm/xe/xe_pci.c      |  22 +++++
> 3 files changed, 171 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
>index 139663423185..e36cc5e1bc8f 100644
>--- a/drivers/gpu/drm/xe/xe_configfs.c
>+++ b/drivers/gpu/drm/xe/xe_configfs.c
>@@ -15,6 +15,7 @@
> 
> #include "instructions/xe_mi_commands.h"
> #include "xe_configfs.h"
>+#include "xe_gt_types.h"
> #include "xe_hw_engine_types.h"
> #include "xe_module.h"
> #include "xe_pci_types.h"
>@@ -56,6 +57,7 @@
>  *        :
>  *        └── 0000:03:00.0
>  *            ├── survivability_mode
>+ *            ├── gt_types_allowed
>  *            ├── engines_allowed
>  *            └── enable_psmi
>  *
>@@ -79,6 +81,44 @@
>  *
>  * This attribute can only be set before binding to the device.
>  *
>+ * Allowed GT types:
>+ * -----------------
>+ *
>+ * Allow only specific types of GTs to be detected and initialized by the
>+ * driver.  Any combination of GT types can be enabled/disabled, although
>+ * some settings will cause the device to fail to probe.
>+ *
>+ * Writes support both comma- and newline-separated input format. Reads
>+ * will always return one GT type per line. "primary" and "media" are the
>+ * GT type names supported by this interface.
>+ *
>+ * This attribute can only be set before binding to the device.
>+ *
>+ * Examples:
>+ *
>+ * Allow both primary and media GTs to be initialized and used.  This matches
>+ * the driver's default behavior::
>+ *
>+ *        # echo 'primary,media' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
>+ *
>+ * Allow only the primary GT of each tile to be initialized and used,
>+ * effectively disabling the media GT if it exists on the platform::
>+ *
>+ *        # echo 'primary' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
>+ *
>+ * Allow only the media GT of each tile to be initialized and used,
>+ * effectively disabling the primary GT.  **This configuration will cause
>+ * device probe failure on all current platforms, but may be allowed on
>+ * igpu platforms in the future**::
>+ *
>+ *        # echo 'media' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
>+ *
>+ * Disable all GTs.  Only other GPU IP (such as display) is potentially usable.
>+ * **This configuration will cause device probe failure on all current
>+ * platforms, but may be allowed on igpu platforms in the future**::
>+ *
>+ *        # echo '' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
>+ *
>  * Allowed engines:
>  * ----------------
>  *
>@@ -187,6 +227,7 @@ struct xe_config_group_device {
>         struct config_group group;
> 
>         struct xe_config_device {
>+                u64 gt_types_allowed;
>                 u64 engines_allowed;
>                 struct wa_bb ctx_restore_post_bb[XE_ENGINE_CLASS_MAX];
>                 struct wa_bb ctx_restore_mid_bb[XE_ENGINE_CLASS_MAX];
>@@ -201,6 +242,7 @@ struct xe_config_group_device {
> };
> 
> static const struct xe_config_device device_defaults = {
>+        .gt_types_allowed = U64_MAX,
>         .engines_allowed = U64_MAX,
>         .survivability_mode = false,
>         .enable_psmi = false,
>@@ -220,6 +262,7 @@ struct engine_info {
> /* Some helpful macros to aid on the sizing of buffer allocation when parsing */
> #define MAX_ENGINE_CLASS_CHARS 5
> #define MAX_ENGINE_INSTANCE_CHARS 2
>+#define MAX_GT_TYPE_CHARS 7
> 
> static const struct engine_info engine_info[] = {
>         { .cls = "rcs", .mask = XE_HW_ENGINE_RCS_MASK, .engine_class = XE_ENGINE_CLASS_RENDER },
>@@ -230,6 +273,14 @@ static const struct engine_info engine_info[] = {
>         { .cls = "gsccs", .mask = XE_HW_ENGINE_GSCCS_MASK, .engine_class = XE_ENGINE_CLASS_OTHER },
> };
> 
>+static const struct {
>+        const char name[MAX_GT_TYPE_CHARS + 1];
>+        enum xe_gt_type type;
>+} gt_types[] = {
>+        { .name = "primary", .type = XE_GT_TYPE_MAIN },
>+        { .name = "media", .type = XE_GT_TYPE_MEDIA },
>+};
>+
> static struct xe_config_group_device *to_xe_config_group_device(struct config_item *item)
> {
>         return container_of(to_config_group(item), struct xe_config_group_device, group);
>@@ -292,6 +343,58 @@ static ssize_t survivability_mode_store(struct config_item *item, const char *pa
>         return len;
> }
> 
>+static ssize_t gt_types_allowed_show(struct config_item *item, char *page)
>+{
>+        struct xe_config_device *dev = to_xe_config_device(item);
>+        char *p = page;
>+
>+        for (size_t i = 0; i < ARRAY_SIZE(gt_types); i++)
>+                if (dev->gt_types_allowed & BIT_ULL(gt_types[i].type))
>+                        p += sprintf(p, "%s\n", gt_types[i].name);
>+
>+        return p - page;
>+}
>+
>+static ssize_t gt_types_allowed_store(struct config_item *item, const char *page,
>+                                      size_t len)
>+{
>+        struct xe_config_group_device *dev = to_xe_config_group_device(item);
>+        char *buf __free(kfree) = kstrdup(page, GFP_KERNEL);
>+        char *p = buf;
>+        u64 typemask = 0;
>+
>+        if (!buf)
>+                return -ENOMEM;
>+
>+        while (p) {
>+                char *typename = strsep(&p, ",\n");
>+                bool matched = false;
>+
>+                if (typename[0] == '\0')
>+                        continue;
>+
>+                for (size_t i = 0; i < ARRAY_SIZE(gt_types); i++) {
>+                        if (strcmp(typename, gt_types[i].name) == 0) {
>+                                typemask |= BIT(gt_types[i].type);
>+                                matched = true;
>+                                break;
>+                        }
>+                }
>+
>+                if (!matched)
>+                        return -EINVAL;
>+        }
>+
>+        scoped_guard(mutex, &dev->lock) {
>+                if (is_bound(dev))
>+                        return -EBUSY;
>+
>+                dev->config.gt_types_allowed = typemask;
>+        }
>+
>+        return len;
>+}
>+
> static ssize_t engines_allowed_show(struct config_item *item, char *page)
> {
>         struct xe_config_device *dev = to_xe_config_device(item);
>@@ -672,6 +775,7 @@ CONFIGFS_ATTR(, ctx_restore_mid_bb);
> CONFIGFS_ATTR(, ctx_restore_post_bb);
> CONFIGFS_ATTR(, enable_psmi);
> CONFIGFS_ATTR(, engines_allowed);
>+CONFIGFS_ATTR(, gt_types_allowed);
> CONFIGFS_ATTR(, survivability_mode);
> 
> static struct configfs_attribute *xe_config_device_attrs[] = {
>@@ -679,6 +783,7 @@ static struct configfs_attribute *xe_config_device_attrs[] = {
>         &attr_ctx_restore_post_bb,
>         &attr_enable_psmi,
>         &attr_engines_allowed,
>+        &attr_gt_types_allowed,
>         &attr_survivability_mode,
>         NULL,
> };
>@@ -846,6 +951,7 @@ static void dump_custom_dev_config(struct pci_dev *pdev,
>                                  dev->config.attr_); \
>         } while (0)
> 
>+        PRI_CUSTOM_ATTR("%llx", gt_types_allowed);
>         PRI_CUSTOM_ATTR("%llx", engines_allowed);
>         PRI_CUSTOM_ATTR("%d", enable_psmi);
>         PRI_CUSTOM_ATTR("%d", survivability_mode);
>@@ -896,6 +1002,45 @@ bool xe_configfs_get_survivability_mode(struct pci_dev *pdev)
>         return mode;
> }
> 
>+static u64 get_gt_types_allowed(struct xe_device *xe)
>+{
>+        struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
>+        struct xe_config_group_device *dev = find_xe_config_group_device(pdev);
>+        u64 mask;
>+
>+        if (!dev)
>+                return device_defaults.gt_types_allowed;
>+
>+        mask = dev->config.gt_types_allowed;
>+        config_group_put(&dev->group);
>+
>+        return mask;
>+}
>+
>+/**
>+ * xe_configfs_primary_gt_supported - determine whether primary GTs are supported
>+ * @xe: xe device
>+ *
>+ * Return: True if primary GTs are enabled, false if they have been disabled via
>+ *     configfs.
>+ */
>+bool xe_configfs_primary_gt_supported(struct xe_device *xe)

Nitpick: I think it would be more precise if we used _allowed instead of
_supported here...

I see there are some feedback from Lucas and Michal that could be
incorporated.  That said, the patch at its current state already looks
good to me, so:

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

Feel free to keep the r-b when applying any of their suggestions.

--
Gustavo Sousa

>+{
>+        return (get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MAIN)) != 0;
>+}
>+
>+/**
>+ * xe_configfs_media_gt_supported - determine whether media GTs are supported
>+ * @xe: xe device
>+ *
>+ * Return: True if the media GTs are enabled, false if they have been disabled
>+ *     via configfs.
>+ */
>+bool xe_configfs_media_gt_supported(struct xe_device *xe)
>+{
>+        return (get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MEDIA)) != 0;
>+}
>+
> /**
>  * xe_configfs_get_engines_allowed - get engine allowed mask from configfs
>  * @pdev: pci device
>diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h
>index c61e0e47ed94..5624e965b911 100644
>--- a/drivers/gpu/drm/xe/xe_configfs.h
>+++ b/drivers/gpu/drm/xe/xe_configfs.h
>@@ -17,6 +17,8 @@ int xe_configfs_init(void);
> void xe_configfs_exit(void);
> void xe_configfs_check_device(struct pci_dev *pdev);
> bool xe_configfs_get_survivability_mode(struct pci_dev *pdev);
>+bool xe_configfs_primary_gt_supported(struct xe_device *xe);
>+bool xe_configfs_media_gt_supported(struct xe_device *xe);
> u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev);
> bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev);
> u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
>@@ -28,6 +30,8 @@ static inline int xe_configfs_init(void) { return 0; }
> static inline void xe_configfs_exit(void) { }
> static inline void xe_configfs_check_device(struct pci_dev *pdev) { }
> static inline bool xe_configfs_get_survivability_mode(struct pci_dev *pdev) { return false; }
>+static inline bool xe_configfs_primary_gt_supported(struct xe_device *xe) { return true; }
>+static inline bool xe_configfs_media_gt_supported(struct xe_device *xe) { return true; }
> static inline u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev) { return U64_MAX; }
> static inline bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev) { return false; }
> static inline u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index a5932e4f4a23..9c8ab2b41737 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -695,6 +695,11 @@ static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
>         struct xe_device *xe = tile_to_xe(tile);
>         struct xe_gt *gt;
> 
>+        if (!xe_configfs_primary_gt_supported(xe)) {
>+                drm_info(&xe->drm, "Primary GT disabled via configfs\n");
>+                return NULL;
>+        }
>+
>         gt = xe_gt_alloc(tile);
>         if (IS_ERR(gt))
>                 return gt;
>@@ -720,6 +725,11 @@ static struct xe_gt *alloc_media_gt(struct xe_tile *tile,
>         struct xe_device *xe = tile_to_xe(tile);
>         struct xe_gt *gt;
> 
>+        if (!xe_configfs_media_gt_supported(xe)) {
>+                drm_info(&xe->drm, "Media GT disabled via configfs\n");
>+                return NULL;
>+        }
>+
>         if (MEDIA_VER(xe) < 13 || !media_desc)
>                 return NULL;
> 
>@@ -829,6 +839,18 @@ static int xe_info_init(struct xe_device *xe,
>                 if (IS_ERR(tile->primary_gt))
>                         return PTR_ERR(tile->primary_gt);
> 
>+                /*
>+                 * It's not currently possible to probe a device with the
>+                 * primary GT disabled.  With some work, this may be future in
>+                 * the possible for igpu platforms (although probably not for
>+                 * dgpu's since access to the primary GT's BCS engines is
>+                 * required for VRAM management).
>+                 */
>+                if (!tile->primary_gt) {
>+                        drm_err(&xe->drm, "Cannot probe device with without a primary GT\n");
>+                        return -ENODEV;
>+                }
>+
>                 tile->media_gt = alloc_media_gt(tile, media_desc);
>                 if (IS_ERR(tile->media_gt))
>                         return PTR_ERR(tile->media_gt);
>-- 
>2.51.0
>

Re: [PATCH v4 22/23] drm/xe/configfs: Add attribute to disable GT types

[Matt Roper]

On Tue, Oct 07, 2025 at 10:37:32PM -0500, Lucas De Marchi wrote:
> On Tue, Oct 07, 2025 at 01:48:52PM -0700, Matt Roper wrote:
> > Preventing the driver from initializing GTs of specific type(s) can be
> > useful for debugging and early hardware bringup.  Add a configfs
> > attribute to allow this kind of control for debugging.
> > 
> > With today's platforms and software design, this configuration setting
> > is only effective for disabling the media GT since the driver currently
> > requires that there always be a primary GT to probe the device.  However
> > this might change in the future ---  in theory it should be possible
> > (with some additional driver work) to allow an igpu device to come up
> > with only the media GT and no primary GT.  Or to allow an igpu device to
> > come up with no GTs at all (for display-only usage).  A primary GT will
> > likely always be required on dgpu platforms because we rely on the BCS
> > engines inside the primary GT for various vram operations.
> > 
> > v2:
> > - Expand/clarify kerneldoc for configfs attribute.  (Gustavo)
> > - Tighten type usage in gt_types[] structure.  (Gustavo)
> > - Adjust string parsing/name matching to match exact GT names and not
> >   accept partial names.  (Gustavo)
> > 
> > v3:
> > - Switch to scope-based cleanup in gt_types_allowed_store() to fix a
> >   leak if the device is already bound.  (Gustavo)
> > - Switch configfs lookup interface to two boolean functions that
> >   specify whether primary/media are supported rather than one function
> >   that returns a mask.  This is simpler to use and understand.
> > 
> > Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_configfs.c | 145 +++++++++++++++++++++++++++++++
> > drivers/gpu/drm/xe/xe_configfs.h |   4 +
> > drivers/gpu/drm/xe/xe_pci.c      |  22 +++++
> > 3 files changed, 171 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
> > index 139663423185..e36cc5e1bc8f 100644
> > --- a/drivers/gpu/drm/xe/xe_configfs.c
> > +++ b/drivers/gpu/drm/xe/xe_configfs.c
> > @@ -15,6 +15,7 @@
> > 
> > #include "instructions/xe_mi_commands.h"
> > #include "xe_configfs.h"
> > +#include "xe_gt_types.h"
> > #include "xe_hw_engine_types.h"
> > #include "xe_module.h"
> > #include "xe_pci_types.h"
> > @@ -56,6 +57,7 @@
> >  *	:
> >  *	└── 0000:03:00.0
> >  *	    ├── survivability_mode
> > + *	    ├── gt_types_allowed
> >  *	    ├── engines_allowed
> >  *	    └── enable_psmi
> >  *
> > @@ -79,6 +81,44 @@
> >  *
> >  * This attribute can only be set before binding to the device.
> >  *
> > + * Allowed GT types:
> > + * -----------------
> > + *
> > + * Allow only specific types of GTs to be detected and initialized by the
> > + * driver.  Any combination of GT types can be enabled/disabled, although
> > + * some settings will cause the device to fail to probe.
> > + *
> > + * Writes support both comma- and newline-separated input format. Reads
> > + * will always return one GT type per line. "primary" and "media" are the
> > + * GT type names supported by this interface.
> > + *
> > + * This attribute can only be set before binding to the device.
> > + *
> > + * Examples:
> > + *
> > + * Allow both primary and media GTs to be initialized and used.  This matches
> > + * the driver's default behavior::
> > + *
> > + *	# echo 'primary,media' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
> > + *
> > + * Allow only the primary GT of each tile to be initialized and used,
> > + * effectively disabling the media GT if it exists on the platform::
> > + *
> > + *	# echo 'primary' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
> > + *
> > + * Allow only the media GT of each tile to be initialized and used,
> > + * effectively disabling the primary GT.  **This configuration will cause
> > + * device probe failure on all current platforms, but may be allowed on
> > + * igpu platforms in the future**::
> > + *
> > + *	# echo 'media' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
> > + *
> > + * Disable all GTs.  Only other GPU IP (such as display) is potentially usable.
> > + * **This configuration will cause device probe failure on all current
> > + * platforms, but may be allowed on igpu platforms in the future**::
> > + *
> > + *	# echo '' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
> > + *
> >  * Allowed engines:
> >  * ----------------
> >  *
> > @@ -187,6 +227,7 @@ struct xe_config_group_device {
> > 	struct config_group group;
> > 
> > 	struct xe_config_device {
> > +		u64 gt_types_allowed;
> > 		u64 engines_allowed;
> > 		struct wa_bb ctx_restore_post_bb[XE_ENGINE_CLASS_MAX];
> > 		struct wa_bb ctx_restore_mid_bb[XE_ENGINE_CLASS_MAX];
> > @@ -201,6 +242,7 @@ struct xe_config_group_device {
> > };
> > 
> > static const struct xe_config_device device_defaults = {
> > +	.gt_types_allowed = U64_MAX,
> > 	.engines_allowed = U64_MAX,
> > 	.survivability_mode = false,
> > 	.enable_psmi = false,
> > @@ -220,6 +262,7 @@ struct engine_info {
> > /* Some helpful macros to aid on the sizing of buffer allocation when parsing */
> > #define MAX_ENGINE_CLASS_CHARS 5
> > #define MAX_ENGINE_INSTANCE_CHARS 2
> > +#define MAX_GT_TYPE_CHARS 7
> > 
> > static const struct engine_info engine_info[] = {
> > 	{ .cls = "rcs", .mask = XE_HW_ENGINE_RCS_MASK, .engine_class = XE_ENGINE_CLASS_RENDER },
> > @@ -230,6 +273,14 @@ static const struct engine_info engine_info[] = {
> > 	{ .cls = "gsccs", .mask = XE_HW_ENGINE_GSCCS_MASK, .engine_class = XE_ENGINE_CLASS_OTHER },
> > };
> > 
> > +static const struct {
> > +	const char name[MAX_GT_TYPE_CHARS + 1];
> > +	enum xe_gt_type type;
> > +} gt_types[] = {
> > +	{ .name = "primary", .type = XE_GT_TYPE_MAIN },
> > +	{ .name = "media", .type = XE_GT_TYPE_MEDIA },
> > +};
> > +
> > static struct xe_config_group_device *to_xe_config_group_device(struct config_item *item)
> > {
> > 	return container_of(to_config_group(item), struct xe_config_group_device, group);
> > @@ -292,6 +343,58 @@ static ssize_t survivability_mode_store(struct config_item *item, const char *pa
> > 	return len;
> > }
> > 
> > +static ssize_t gt_types_allowed_show(struct config_item *item, char *page)
> > +{
> > +	struct xe_config_device *dev = to_xe_config_device(item);
> > +	char *p = page;
> > +
> > +	for (size_t i = 0; i < ARRAY_SIZE(gt_types); i++)
> > +		if (dev->gt_types_allowed & BIT_ULL(gt_types[i].type))
> > +			p += sprintf(p, "%s\n", gt_types[i].name);
> > +
> > +	return p - page;
> > +}
> > +
> > +static ssize_t gt_types_allowed_store(struct config_item *item, const char *page,
> > +				      size_t len)
> > +{
> > +	struct xe_config_group_device *dev = to_xe_config_group_device(item);
> > +	char *buf __free(kfree) = kstrdup(page, GFP_KERNEL);
> > +	char *p = buf;
> > +	u64 typemask = 0;
> > +
> > +	if (!buf)
> > +		return -ENOMEM;
> > +
> > +	while (p) {
> > +		char *typename = strsep(&p, ",\n");
> > +		bool matched = false;
> > +
> > +		if (typename[0] == '\0')
> > +			continue;
> > +
> > +		for (size_t i = 0; i < ARRAY_SIZE(gt_types); i++) {
> > +			if (strcmp(typename, gt_types[i].name) == 0) {
> > +				typemask |= BIT(gt_types[i].type);
> > +				matched = true;
> > +				break;
> > +			}
> > +		}
> > +
> > +		if (!matched)
> > +			return -EINVAL;
> > +	}
> > +
> > +	scoped_guard(mutex, &dev->lock) {
> > +		if (is_bound(dev))
> > +			return -EBUSY;
> > +
> > +		dev->config.gt_types_allowed = typemask;
> > +	}
> > +
> > +	return len;
> > +}
> > +
> > static ssize_t engines_allowed_show(struct config_item *item, char *page)
> > {
> > 	struct xe_config_device *dev = to_xe_config_device(item);
> > @@ -672,6 +775,7 @@ CONFIGFS_ATTR(, ctx_restore_mid_bb);
> > CONFIGFS_ATTR(, ctx_restore_post_bb);
> > CONFIGFS_ATTR(, enable_psmi);
> > CONFIGFS_ATTR(, engines_allowed);
> > +CONFIGFS_ATTR(, gt_types_allowed);
> > CONFIGFS_ATTR(, survivability_mode);
> > 
> > static struct configfs_attribute *xe_config_device_attrs[] = {
> > @@ -679,6 +783,7 @@ static struct configfs_attribute *xe_config_device_attrs[] = {
> > 	&attr_ctx_restore_post_bb,
> > 	&attr_enable_psmi,
> > 	&attr_engines_allowed,
> > +	&attr_gt_types_allowed,
> > 	&attr_survivability_mode,
> > 	NULL,
> > };
> > @@ -846,6 +951,7 @@ static void dump_custom_dev_config(struct pci_dev *pdev,
> > 				 dev->config.attr_); \
> > 	} while (0)
> > 
> > +	PRI_CUSTOM_ATTR("%llx", gt_types_allowed);
> > 	PRI_CUSTOM_ATTR("%llx", engines_allowed);
> > 	PRI_CUSTOM_ATTR("%d", enable_psmi);
> > 	PRI_CUSTOM_ATTR("%d", survivability_mode);
> > @@ -896,6 +1002,45 @@ bool xe_configfs_get_survivability_mode(struct pci_dev *pdev)
> > 	return mode;
> > }
> > 
> > +static u64 get_gt_types_allowed(struct xe_device *xe)
> > +{
> > +	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> > +	struct xe_config_group_device *dev = find_xe_config_group_device(pdev);
> > +	u64 mask;
> > +
> > +	if (!dev)
> > +		return device_defaults.gt_types_allowed;
> > +
> > +	mask = dev->config.gt_types_allowed;
> > +	config_group_put(&dev->group);
> > +
> > +	return mask;
> > +}
> > +
> > +/**
> > + * xe_configfs_primary_gt_supported - determine whether primary GTs are supported
> > + * @xe: xe device
> > + *
> > + * Return: True if primary GTs are enabled, false if they have been disabled via
> > + *     configfs.
> > + */
> > +bool xe_configfs_primary_gt_supported(struct xe_device *xe)
> > +{
> > +	return (get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MAIN)) != 0;
> > +}
> > +
> > +/**
> > + * xe_configfs_media_gt_supported - determine whether media GTs are supported
> > + * @xe: xe device
> > + *
> > + * Return: True if the media GTs are enabled, false if they have been disabled
> > + *     via configfs.
> > + */
> > +bool xe_configfs_media_gt_supported(struct xe_device *xe)
> > +{
> > +	return (get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MEDIA)) != 0;
> > +}
> > +
> > /**
> >  * xe_configfs_get_engines_allowed - get engine allowed mask from configfs
> >  * @pdev: pci device
> > diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h
> > index c61e0e47ed94..5624e965b911 100644
> > --- a/drivers/gpu/drm/xe/xe_configfs.h
> > +++ b/drivers/gpu/drm/xe/xe_configfs.h
> > @@ -17,6 +17,8 @@ int xe_configfs_init(void);
> > void xe_configfs_exit(void);
> > void xe_configfs_check_device(struct pci_dev *pdev);
> > bool xe_configfs_get_survivability_mode(struct pci_dev *pdev);
> > +bool xe_configfs_primary_gt_supported(struct xe_device *xe);
> > +bool xe_configfs_media_gt_supported(struct xe_device *xe);
> > u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev);
> > bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev);
> > u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
> > @@ -28,6 +30,8 @@ static inline int xe_configfs_init(void) { return 0; }
> > static inline void xe_configfs_exit(void) { }
> > static inline void xe_configfs_check_device(struct pci_dev *pdev) { }
> > static inline bool xe_configfs_get_survivability_mode(struct pci_dev *pdev) { return false; }
> > +static inline bool xe_configfs_primary_gt_supported(struct xe_device *xe) { return true; }
> > +static inline bool xe_configfs_media_gt_supported(struct xe_device *xe) { return true; }
> > static inline u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev) { return U64_MAX; }
> > static inline bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev) { return false; }
> > static inline u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
> > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> > index a5932e4f4a23..9c8ab2b41737 100644
> > --- a/drivers/gpu/drm/xe/xe_pci.c
> > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > @@ -695,6 +695,11 @@ static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
> > 	struct xe_device *xe = tile_to_xe(tile);
> > 	struct xe_gt *gt;
> > 
> > +	if (!xe_configfs_primary_gt_supported(xe)) {
> > +		drm_info(&xe->drm, "Primary GT disabled via configfs\n");
> > +		return NULL;
> > +	}
> > +
> > 	gt = xe_gt_alloc(tile);
> > 	if (IS_ERR(gt))
> > 		return gt;
> > @@ -720,6 +725,11 @@ static struct xe_gt *alloc_media_gt(struct xe_tile *tile,
> > 	struct xe_device *xe = tile_to_xe(tile);
> > 	struct xe_gt *gt;
> > 
> > +	if (!xe_configfs_media_gt_supported(xe)) {
> > +		drm_info(&xe->drm, "Media GT disabled via configfs\n");
> > +		return NULL;
> > +	}
> > +
> > 	if (MEDIA_VER(xe) < 13 || !media_desc)
> > 		return NULL;
> > 
> > @@ -829,6 +839,18 @@ static int xe_info_init(struct xe_device *xe,
> > 		if (IS_ERR(tile->primary_gt))
> > 			return PTR_ERR(tile->primary_gt);
> > 
> > +		/*
> > +		 * It's not currently possible to probe a device with the
> > +		 * primary GT disabled.  With some work, this may be future in
> > +		 * the possible for igpu platforms (although probably not for
> > +		 * dgpu's since access to the primary GT's BCS engines is
> > +		 * required for VRAM management).
> > +		 */
> > +		if (!tile->primary_gt) {
> > +			drm_err(&xe->drm, "Cannot probe device with without a primary GT\n");
> > +			return -ENODEV;
> 
> 
> I think "fail to probe" should be ok. Advanced user using this interface should know what
> to do. I was thinking about blocking this at the configfs level, so the
> user is not allowed to do it until that path is cleared. Any particular
> reason to do it here?

You mean as opposed to doing it somewhere like gt_types_allowed_store()?
The main reason is because I expect the condition to eventually get
relaxed and need to be combined with other device-specific information
that we don't know pre-probe (e.g., dgpu vs igpu type).


Matt

> 
> Lucas De Marchi
> 
> > +		}
> > +
> > 		tile->media_gt = alloc_media_gt(tile, media_desc);
> > 		if (IS_ERR(tile->media_gt))
> > 			return PTR_ERR(tile->media_gt);
> > -- 
> > 2.51.0
> > 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v4 22/23] drm/xe/configfs: Add attribute to disable GT types

[Lucas De Marchi]

On Wed, Oct 08, 2025 at 12:10:14PM -0700, Matt Roper wrote:
>On Tue, Oct 07, 2025 at 10:37:32PM -0500, Lucas De Marchi wrote:
>> On Tue, Oct 07, 2025 at 01:48:52PM -0700, Matt Roper wrote:
>> > Preventing the driver from initializing GTs of specific type(s) can be
>> > useful for debugging and early hardware bringup.  Add a configfs
>> > attribute to allow this kind of control for debugging.
>> >
>> > With today's platforms and software design, this configuration setting
>> > is only effective for disabling the media GT since the driver currently
>> > requires that there always be a primary GT to probe the device.  However
>> > this might change in the future ---  in theory it should be possible
>> > (with some additional driver work) to allow an igpu device to come up
>> > with only the media GT and no primary GT.  Or to allow an igpu device to
>> > come up with no GTs at all (for display-only usage).  A primary GT will
>> > likely always be required on dgpu platforms because we rely on the BCS
>> > engines inside the primary GT for various vram operations.
>> >
>> > v2:
>> > - Expand/clarify kerneldoc for configfs attribute.  (Gustavo)
>> > - Tighten type usage in gt_types[] structure.  (Gustavo)
>> > - Adjust string parsing/name matching to match exact GT names and not
>> >   accept partial names.  (Gustavo)
>> >
>> > v3:
>> > - Switch to scope-based cleanup in gt_types_allowed_store() to fix a
>> >   leak if the device is already bound.  (Gustavo)
>> > - Switch configfs lookup interface to two boolean functions that
>> >   specify whether primary/media are supported rather than one function
>> >   that returns a mask.  This is simpler to use and understand.
>> >
>> > Cc: Gustavo Sousa <gustavo.sousa@intel.com>
>> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> > ---
>> > drivers/gpu/drm/xe/xe_configfs.c | 145 +++++++++++++++++++++++++++++++
>> > drivers/gpu/drm/xe/xe_configfs.h |   4 +
>> > drivers/gpu/drm/xe/xe_pci.c      |  22 +++++
>> > 3 files changed, 171 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
>> > index 139663423185..e36cc5e1bc8f 100644
>> > --- a/drivers/gpu/drm/xe/xe_configfs.c
>> > +++ b/drivers/gpu/drm/xe/xe_configfs.c
>> > @@ -15,6 +15,7 @@
>> >
>> > #include "instructions/xe_mi_commands.h"
>> > #include "xe_configfs.h"
>> > +#include "xe_gt_types.h"
>> > #include "xe_hw_engine_types.h"
>> > #include "xe_module.h"
>> > #include "xe_pci_types.h"
>> > @@ -56,6 +57,7 @@
>> >  *	:
>> >  *	└── 0000:03:00.0
>> >  *	    ├── survivability_mode
>> > + *	    ├── gt_types_allowed
>> >  *	    ├── engines_allowed
>> >  *	    └── enable_psmi
>> >  *
>> > @@ -79,6 +81,44 @@
>> >  *
>> >  * This attribute can only be set before binding to the device.
>> >  *
>> > + * Allowed GT types:
>> > + * -----------------
>> > + *
>> > + * Allow only specific types of GTs to be detected and initialized by the
>> > + * driver.  Any combination of GT types can be enabled/disabled, although
>> > + * some settings will cause the device to fail to probe.
>> > + *
>> > + * Writes support both comma- and newline-separated input format. Reads
>> > + * will always return one GT type per line. "primary" and "media" are the
>> > + * GT type names supported by this interface.
>> > + *
>> > + * This attribute can only be set before binding to the device.
>> > + *
>> > + * Examples:
>> > + *
>> > + * Allow both primary and media GTs to be initialized and used.  This matches
>> > + * the driver's default behavior::
>> > + *
>> > + *	# echo 'primary,media' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
>> > + *
>> > + * Allow only the primary GT of each tile to be initialized and used,
>> > + * effectively disabling the media GT if it exists on the platform::
>> > + *
>> > + *	# echo 'primary' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
>> > + *
>> > + * Allow only the media GT of each tile to be initialized and used,
>> > + * effectively disabling the primary GT.  **This configuration will cause
>> > + * device probe failure on all current platforms, but may be allowed on
>> > + * igpu platforms in the future**::
>> > + *
>> > + *	# echo 'media' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
>> > + *
>> > + * Disable all GTs.  Only other GPU IP (such as display) is potentially usable.
>> > + * **This configuration will cause device probe failure on all current
>> > + * platforms, but may be allowed on igpu platforms in the future**::
>> > + *
>> > + *	# echo '' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
>> > + *
>> >  * Allowed engines:
>> >  * ----------------
>> >  *
>> > @@ -187,6 +227,7 @@ struct xe_config_group_device {
>> > 	struct config_group group;
>> >
>> > 	struct xe_config_device {
>> > +		u64 gt_types_allowed;
>> > 		u64 engines_allowed;
>> > 		struct wa_bb ctx_restore_post_bb[XE_ENGINE_CLASS_MAX];
>> > 		struct wa_bb ctx_restore_mid_bb[XE_ENGINE_CLASS_MAX];
>> > @@ -201,6 +242,7 @@ struct xe_config_group_device {
>> > };
>> >
>> > static const struct xe_config_device device_defaults = {
>> > +	.gt_types_allowed = U64_MAX,
>> > 	.engines_allowed = U64_MAX,
>> > 	.survivability_mode = false,
>> > 	.enable_psmi = false,
>> > @@ -220,6 +262,7 @@ struct engine_info {
>> > /* Some helpful macros to aid on the sizing of buffer allocation when parsing */
>> > #define MAX_ENGINE_CLASS_CHARS 5
>> > #define MAX_ENGINE_INSTANCE_CHARS 2
>> > +#define MAX_GT_TYPE_CHARS 7
>> >
>> > static const struct engine_info engine_info[] = {
>> > 	{ .cls = "rcs", .mask = XE_HW_ENGINE_RCS_MASK, .engine_class = XE_ENGINE_CLASS_RENDER },
>> > @@ -230,6 +273,14 @@ static const struct engine_info engine_info[] = {
>> > 	{ .cls = "gsccs", .mask = XE_HW_ENGINE_GSCCS_MASK, .engine_class = XE_ENGINE_CLASS_OTHER },
>> > };
>> >
>> > +static const struct {
>> > +	const char name[MAX_GT_TYPE_CHARS + 1];
>> > +	enum xe_gt_type type;
>> > +} gt_types[] = {
>> > +	{ .name = "primary", .type = XE_GT_TYPE_MAIN },
>> > +	{ .name = "media", .type = XE_GT_TYPE_MEDIA },
>> > +};
>> > +
>> > static struct xe_config_group_device *to_xe_config_group_device(struct config_item *item)
>> > {
>> > 	return container_of(to_config_group(item), struct xe_config_group_device, group);
>> > @@ -292,6 +343,58 @@ static ssize_t survivability_mode_store(struct config_item *item, const char *pa
>> > 	return len;
>> > }
>> >
>> > +static ssize_t gt_types_allowed_show(struct config_item *item, char *page)
>> > +{
>> > +	struct xe_config_device *dev = to_xe_config_device(item);
>> > +	char *p = page;
>> > +
>> > +	for (size_t i = 0; i < ARRAY_SIZE(gt_types); i++)
>> > +		if (dev->gt_types_allowed & BIT_ULL(gt_types[i].type))
>> > +			p += sprintf(p, "%s\n", gt_types[i].name);
>> > +
>> > +	return p - page;
>> > +}
>> > +
>> > +static ssize_t gt_types_allowed_store(struct config_item *item, const char *page,
>> > +				      size_t len)
>> > +{
>> > +	struct xe_config_group_device *dev = to_xe_config_group_device(item);
>> > +	char *buf __free(kfree) = kstrdup(page, GFP_KERNEL);
>> > +	char *p = buf;
>> > +	u64 typemask = 0;
>> > +
>> > +	if (!buf)
>> > +		return -ENOMEM;
>> > +
>> > +	while (p) {
>> > +		char *typename = strsep(&p, ",\n");
>> > +		bool matched = false;
>> > +
>> > +		if (typename[0] == '\0')
>> > +			continue;
>> > +
>> > +		for (size_t i = 0; i < ARRAY_SIZE(gt_types); i++) {
>> > +			if (strcmp(typename, gt_types[i].name) == 0) {
>> > +				typemask |= BIT(gt_types[i].type);
>> > +				matched = true;
>> > +				break;
>> > +			}
>> > +		}
>> > +
>> > +		if (!matched)
>> > +			return -EINVAL;
>> > +	}
>> > +
>> > +	scoped_guard(mutex, &dev->lock) {
>> > +		if (is_bound(dev))
>> > +			return -EBUSY;
>> > +
>> > +		dev->config.gt_types_allowed = typemask;
>> > +	}
>> > +
>> > +	return len;
>> > +}
>> > +
>> > static ssize_t engines_allowed_show(struct config_item *item, char *page)
>> > {
>> > 	struct xe_config_device *dev = to_xe_config_device(item);
>> > @@ -672,6 +775,7 @@ CONFIGFS_ATTR(, ctx_restore_mid_bb);
>> > CONFIGFS_ATTR(, ctx_restore_post_bb);
>> > CONFIGFS_ATTR(, enable_psmi);
>> > CONFIGFS_ATTR(, engines_allowed);
>> > +CONFIGFS_ATTR(, gt_types_allowed);
>> > CONFIGFS_ATTR(, survivability_mode);
>> >
>> > static struct configfs_attribute *xe_config_device_attrs[] = {
>> > @@ -679,6 +783,7 @@ static struct configfs_attribute *xe_config_device_attrs[] = {
>> > 	&attr_ctx_restore_post_bb,
>> > 	&attr_enable_psmi,
>> > 	&attr_engines_allowed,
>> > +	&attr_gt_types_allowed,
>> > 	&attr_survivability_mode,
>> > 	NULL,
>> > };
>> > @@ -846,6 +951,7 @@ static void dump_custom_dev_config(struct pci_dev *pdev,
>> > 				 dev->config.attr_); \
>> > 	} while (0)
>> >
>> > +	PRI_CUSTOM_ATTR("%llx", gt_types_allowed);
>> > 	PRI_CUSTOM_ATTR("%llx", engines_allowed);
>> > 	PRI_CUSTOM_ATTR("%d", enable_psmi);
>> > 	PRI_CUSTOM_ATTR("%d", survivability_mode);
>> > @@ -896,6 +1002,45 @@ bool xe_configfs_get_survivability_mode(struct pci_dev *pdev)
>> > 	return mode;
>> > }
>> >
>> > +static u64 get_gt_types_allowed(struct xe_device *xe)
>> > +{
>> > +	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
>> > +	struct xe_config_group_device *dev = find_xe_config_group_device(pdev);
>> > +	u64 mask;
>> > +
>> > +	if (!dev)
>> > +		return device_defaults.gt_types_allowed;
>> > +
>> > +	mask = dev->config.gt_types_allowed;
>> > +	config_group_put(&dev->group);
>> > +
>> > +	return mask;
>> > +}
>> > +
>> > +/**
>> > + * xe_configfs_primary_gt_supported - determine whether primary GTs are supported
>> > + * @xe: xe device
>> > + *
>> > + * Return: True if primary GTs are enabled, false if they have been disabled via
>> > + *     configfs.
>> > + */
>> > +bool xe_configfs_primary_gt_supported(struct xe_device *xe)
>> > +{
>> > +	return (get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MAIN)) != 0;
>> > +}
>> > +
>> > +/**
>> > + * xe_configfs_media_gt_supported - determine whether media GTs are supported
>> > + * @xe: xe device
>> > + *
>> > + * Return: True if the media GTs are enabled, false if they have been disabled
>> > + *     via configfs.
>> > + */
>> > +bool xe_configfs_media_gt_supported(struct xe_device *xe)
>> > +{
>> > +	return (get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MEDIA)) != 0;
>> > +}
>> > +
>> > /**
>> >  * xe_configfs_get_engines_allowed - get engine allowed mask from configfs
>> >  * @pdev: pci device
>> > diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h
>> > index c61e0e47ed94..5624e965b911 100644
>> > --- a/drivers/gpu/drm/xe/xe_configfs.h
>> > +++ b/drivers/gpu/drm/xe/xe_configfs.h
>> > @@ -17,6 +17,8 @@ int xe_configfs_init(void);
>> > void xe_configfs_exit(void);
>> > void xe_configfs_check_device(struct pci_dev *pdev);
>> > bool xe_configfs_get_survivability_mode(struct pci_dev *pdev);
>> > +bool xe_configfs_primary_gt_supported(struct xe_device *xe);
>> > +bool xe_configfs_media_gt_supported(struct xe_device *xe);
>> > u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev);
>> > bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev);
>> > u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
>> > @@ -28,6 +30,8 @@ static inline int xe_configfs_init(void) { return 0; }
>> > static inline void xe_configfs_exit(void) { }
>> > static inline void xe_configfs_check_device(struct pci_dev *pdev) { }
>> > static inline bool xe_configfs_get_survivability_mode(struct pci_dev *pdev) { return false; }
>> > +static inline bool xe_configfs_primary_gt_supported(struct xe_device *xe) { return true; }
>> > +static inline bool xe_configfs_media_gt_supported(struct xe_device *xe) { return true; }
>> > static inline u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev) { return U64_MAX; }
>> > static inline bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev) { return false; }
>> > static inline u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
>> > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>> > index a5932e4f4a23..9c8ab2b41737 100644
>> > --- a/drivers/gpu/drm/xe/xe_pci.c
>> > +++ b/drivers/gpu/drm/xe/xe_pci.c
>> > @@ -695,6 +695,11 @@ static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
>> > 	struct xe_device *xe = tile_to_xe(tile);
>> > 	struct xe_gt *gt;
>> >
>> > +	if (!xe_configfs_primary_gt_supported(xe)) {
>> > +		drm_info(&xe->drm, "Primary GT disabled via configfs\n");
>> > +		return NULL;
>> > +	}
>> > +
>> > 	gt = xe_gt_alloc(tile);
>> > 	if (IS_ERR(gt))
>> > 		return gt;
>> > @@ -720,6 +725,11 @@ static struct xe_gt *alloc_media_gt(struct xe_tile *tile,
>> > 	struct xe_device *xe = tile_to_xe(tile);
>> > 	struct xe_gt *gt;
>> >
>> > +	if (!xe_configfs_media_gt_supported(xe)) {
>> > +		drm_info(&xe->drm, "Media GT disabled via configfs\n");
>> > +		return NULL;
>> > +	}
>> > +
>> > 	if (MEDIA_VER(xe) < 13 || !media_desc)
>> > 		return NULL;
>> >
>> > @@ -829,6 +839,18 @@ static int xe_info_init(struct xe_device *xe,
>> > 		if (IS_ERR(tile->primary_gt))
>> > 			return PTR_ERR(tile->primary_gt);
>> >
>> > +		/*
>> > +		 * It's not currently possible to probe a device with the
>> > +		 * primary GT disabled.  With some work, this may be future in
>> > +		 * the possible for igpu platforms (although probably not for
>> > +		 * dgpu's since access to the primary GT's BCS engines is
>> > +		 * required for VRAM management).
>> > +		 */
>> > +		if (!tile->primary_gt) {
>> > +			drm_err(&xe->drm, "Cannot probe device with without a primary GT\n");
>> > +			return -ENODEV;
>>
>>
>> I think "fail to probe" should be ok. Advanced user using this interface should know what
>> to do. I was thinking about blocking this at the configfs level, so the
>> user is not allowed to do it until that path is cleared. Any particular
>> reason to do it here?
>
>You mean as opposed to doing it somewhere like gt_types_allowed_store()?

yes

>The main reason is because I expect the condition to eventually get
>relaxed and need to be combined with other device-specific information
>that we don't know pre-probe (e.g., dgpu vs igpu type).

ok, fair enough.

Lucas De Marchi

Re: [PATCH v4 22/23] drm/xe/configfs: Add attribute to disable GT types

[Matt Roper]

On Wed, Oct 08, 2025 at 12:12:37PM +0200, Michal Wajdeczko wrote:
> 
> 
> On 10/7/2025 10:48 PM, Matt Roper wrote:
> > Preventing the driver from initializing GTs of specific type(s) can be
> > useful for debugging and early hardware bringup.  Add a configfs
> > attribute to allow this kind of control for debugging.
> > 
> > With today's platforms and software design, this configuration setting
> > is only effective for disabling the media GT since the driver currently
> > requires that there always be a primary GT to probe the device.  However
> > this might change in the future ---  in theory it should be possible
> > (with some additional driver work) to allow an igpu device to come up
> > with only the media GT and no primary GT.  Or to allow an igpu device to
> > come up with no GTs at all (for display-only usage).  A primary GT will
> > likely always be required on dgpu platforms because we rely on the BCS
> > engines inside the primary GT for various vram operations.
> > 
> > v2:
> >  - Expand/clarify kerneldoc for configfs attribute.  (Gustavo)
> >  - Tighten type usage in gt_types[] structure.  (Gustavo)
> >  - Adjust string parsing/name matching to match exact GT names and not
> >    accept partial names.  (Gustavo)
> > 
> > v3:
> >  - Switch to scope-based cleanup in gt_types_allowed_store() to fix a
> >    leak if the device is already bound.  (Gustavo)
> >  - Switch configfs lookup interface to two boolean functions that
> >    specify whether primary/media are supported rather than one function
> >    that returns a mask.  This is simpler to use and understand.
> > 
> > Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_configfs.c | 145 +++++++++++++++++++++++++++++++
> >  drivers/gpu/drm/xe/xe_configfs.h |   4 +
> >  drivers/gpu/drm/xe/xe_pci.c      |  22 +++++
> >  3 files changed, 171 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
> > index 139663423185..e36cc5e1bc8f 100644
> > --- a/drivers/gpu/drm/xe/xe_configfs.c
> > +++ b/drivers/gpu/drm/xe/xe_configfs.c
> > @@ -15,6 +15,7 @@
> >  
> >  #include "instructions/xe_mi_commands.h"
> >  #include "xe_configfs.h"
> > +#include "xe_gt_types.h"
> >  #include "xe_hw_engine_types.h"
> >  #include "xe_module.h"
> >  #include "xe_pci_types.h"
> > @@ -56,6 +57,7 @@
> >   *	:
> >   *	└── 0000:03:00.0
> >   *	    ├── survivability_mode
> > + *	    ├── gt_types_allowed
> 
> I'm wondering if we want to keep such advance knobs at the same level as others?
> maybe create sub-group for them, like I did for sriov?
> 
> 	    └── tweaks
> 	        ├── gt_types_allowed
> 	        ├── engines_allowed

That makes sense to me, although I'm not sure if it's too late to make
this change now since I think 'engines_allowed' is already part of
v6.17.  Are these configfs settings considered ABI that we can't change
now, even though they're explicitly intended for driver developers?

+Cc Lucas to see what he thinks.

> 
> 
> >   *	    ├── engines_allowed
> >   *	    └── enable_psmi
> 
> oops, and it looks that I missed to update this part of the doc when adding max_vfs with:
> 
> 	    └── sriov
> 	        ├── max_vfs
> 
> >   *
> > @@ -79,6 +81,44 @@
> >   *
> >   * This attribute can only be set before binding to the device.
> >   *
> > + * Allowed GT types:
> > + * -----------------
> > + *
> > + * Allow only specific types of GTs to be detected and initialized by the
> > + * driver.  Any combination of GT types can be enabled/disabled, although
> > + * some settings will cause the device to fail to probe.
> > + *
> > + * Writes support both comma- and newline-separated input format. Reads
> > + * will always return one GT type per line. "primary" and "media" are the
> > + * GT type names supported by this interface.
> > + *
> > + * This attribute can only be set before binding to the device.
> > + *
> > + * Examples:
> > + *
> > + * Allow both primary and media GTs to be initialized and used.  This matches
> > + * the driver's default behavior::
> > + *
> > + *	# echo 'primary,media' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
> 
> maybe "all" as an alias?
> 
> > + *
> > + * Allow only the primary GT of each tile to be initialized and used,
> > + * effectively disabling the media GT if it exists on the platform::
> > + *
> > + *	# echo 'primary' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
> > + *
> > + * Allow only the media GT of each tile to be initialized and used,
> > + * effectively disabling the primary GT.  **This configuration will cause
> > + * device probe failure on all current platforms, but may be allowed on
> > + * igpu platforms in the future**::
> > + *
> > + *	# echo 'media' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
> > + *
> > + * Disable all GTs.  Only other GPU IP (such as display) is potentially usable.
> > + * **This configuration will cause device probe failure on all current
> > + * platforms, but may be allowed on igpu platforms in the future**::
> > + *
> > + *	# echo '' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
> 
> maybe "none" as an alias?

While we could add the all/none aliases, I'm not sure it's worth the
extra parsing hassle, since then we also need to check for nonsense
settings like "primary,none" and such.  Since only a small subset of
driver developers are expected to ever use these, we don't need to worry
too much about convenience aliases.

> 
> > + *
> >   * Allowed engines:
> >   * ----------------
> >   *
> > @@ -187,6 +227,7 @@ struct xe_config_group_device {
> >  	struct config_group group;
> >  
> >  	struct xe_config_device {
> > +		u64 gt_types_allowed;
> >  		u64 engines_allowed;
> >  		struct wa_bb ctx_restore_post_bb[XE_ENGINE_CLASS_MAX];
> >  		struct wa_bb ctx_restore_mid_bb[XE_ENGINE_CLASS_MAX];
> > @@ -201,6 +242,7 @@ struct xe_config_group_device {
> >  };
> >  
> >  static const struct xe_config_device device_defaults = {
> > +	.gt_types_allowed = U64_MAX,
> >  	.engines_allowed = U64_MAX,
> >  	.survivability_mode = false,
> >  	.enable_psmi = false,
> > @@ -220,6 +262,7 @@ struct engine_info {
> >  /* Some helpful macros to aid on the sizing of buffer allocation when parsing */
> >  #define MAX_ENGINE_CLASS_CHARS 5
> >  #define MAX_ENGINE_INSTANCE_CHARS 2
> > +#define MAX_GT_TYPE_CHARS 7
> >  
> >  static const struct engine_info engine_info[] = {
> >  	{ .cls = "rcs", .mask = XE_HW_ENGINE_RCS_MASK, .engine_class = XE_ENGINE_CLASS_RENDER },
> > @@ -230,6 +273,14 @@ static const struct engine_info engine_info[] = {
> >  	{ .cls = "gsccs", .mask = XE_HW_ENGINE_GSCCS_MASK, .engine_class = XE_ENGINE_CLASS_OTHER },
> >  };
> >  
> > +static const struct {
> > +	const char name[MAX_GT_TYPE_CHARS + 1];
> > +	enum xe_gt_type type;
> > +} gt_types[] = {
> > +	{ .name = "primary", .type = XE_GT_TYPE_MAIN },
> > +	{ .name = "media", .type = XE_GT_TYPE_MEDIA },
> > +};
> > +
> >  static struct xe_config_group_device *to_xe_config_group_device(struct config_item *item)
> >  {
> >  	return container_of(to_config_group(item), struct xe_config_group_device, group);
> > @@ -292,6 +343,58 @@ static ssize_t survivability_mode_store(struct config_item *item, const char *pa
> >  	return len;
> >  }
> >  
> > +static ssize_t gt_types_allowed_show(struct config_item *item, char *page)
> > +{
> > +	struct xe_config_device *dev = to_xe_config_device(item);
> > +	char *p = page;
> > +
> > +	for (size_t i = 0; i < ARRAY_SIZE(gt_types); i++)
> > +		if (dev->gt_types_allowed & BIT_ULL(gt_types[i].type))
> > +			p += sprintf(p, "%s\n", gt_types[i].name);
> > +
> > +	return p - page;
> > +}
> > +
> > +static ssize_t gt_types_allowed_store(struct config_item *item, const char *page,
> > +				      size_t len)
> > +{
> > +	struct xe_config_group_device *dev = to_xe_config_group_device(item);
> > +	char *buf __free(kfree) = kstrdup(page, GFP_KERNEL);
> > +	char *p = buf;
> > +	u64 typemask = 0;
> > +
> > +	if (!buf)
> > +		return -ENOMEM;
> > +
> > +	while (p) {
> > +		char *typename = strsep(&p, ",\n");
> > +		bool matched = false;
> > +
> > +		if (typename[0] == '\0')
> > +			continue;
> > +
> > +		for (size_t i = 0; i < ARRAY_SIZE(gt_types); i++) {
> > +			if (strcmp(typename, gt_types[i].name) == 0) {
> > +				typemask |= BIT(gt_types[i].type);
> > +				matched = true;
> > +				break;
> > +			}
> > +		}
> > +
> > +		if (!matched)
> > +			return -EINVAL;
> > +	}
> > +
> > +	scoped_guard(mutex, &dev->lock) {
> 
> probably plain guard(mutex) will work here too
> 
> > +		if (is_bound(dev))
> > +			return -EBUSY;
> 
> then we can take a lock and return earlier, before parsing input
> 
> > +
> > +		dev->config.gt_types_allowed = typemask;
> > +	}
> > +
> > +	return len;
> > +}
> > +
> >  static ssize_t engines_allowed_show(struct config_item *item, char *page)
> >  {
> >  	struct xe_config_device *dev = to_xe_config_device(item);
> > @@ -672,6 +775,7 @@ CONFIGFS_ATTR(, ctx_restore_mid_bb);
> >  CONFIGFS_ATTR(, ctx_restore_post_bb);
> >  CONFIGFS_ATTR(, enable_psmi);
> >  CONFIGFS_ATTR(, engines_allowed);
> > +CONFIGFS_ATTR(, gt_types_allowed);
> >  CONFIGFS_ATTR(, survivability_mode);
> >  
> >  static struct configfs_attribute *xe_config_device_attrs[] = {
> > @@ -679,6 +783,7 @@ static struct configfs_attribute *xe_config_device_attrs[] = {
> >  	&attr_ctx_restore_post_bb,
> >  	&attr_enable_psmi,
> >  	&attr_engines_allowed,
> > +	&attr_gt_types_allowed,
> >  	&attr_survivability_mode,
> >  	NULL,
> >  };
> > @@ -846,6 +951,7 @@ static void dump_custom_dev_config(struct pci_dev *pdev,
> >  				 dev->config.attr_); \
> >  	} while (0)
> >  
> > +	PRI_CUSTOM_ATTR("%llx", gt_types_allowed);
> >  	PRI_CUSTOM_ATTR("%llx", engines_allowed);
> >  	PRI_CUSTOM_ATTR("%d", enable_psmi);
> >  	PRI_CUSTOM_ATTR("%d", survivability_mode);
> > @@ -896,6 +1002,45 @@ bool xe_configfs_get_survivability_mode(struct pci_dev *pdev)
> >  	return mode;
> >  }
> >  
> > +static u64 get_gt_types_allowed(struct xe_device *xe)
> > +{
> > +	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> > +	struct xe_config_group_device *dev = find_xe_config_group_device(pdev);
> > +	u64 mask;
> > +
> > +	if (!dev)
> > +		return device_defaults.gt_types_allowed;
> > +
> > +	mask = dev->config.gt_types_allowed;
> 
> btw, as we are using guard during write, shouldn't we also guard during read?

I'm not sure; is there something racy you see on the read path that we
need to avoid?  An individual get_gt_types_allowed() call racing with a
configfs write doesn't seem like it would matter; rather the problems of
a racing configfs write would be if it happened while a device was in
the middle of getting probed (so some calls to get_gt_types_allowed()
see the old value and others see the new one, leading to inconsistent
device intialization).  But given this is a low-level kernel hacking
interface intended for driver developers, I'm not sure how much we need
to worry about them shooting themselves in the foot.  Maybe I'm
overlooking something?


Matt

> 
> > +	config_group_put(&dev->group);
> > +
> > +	return mask;
> > +}
> > +
> > +/**
> > + * xe_configfs_primary_gt_supported - determine whether primary GTs are supported
> > + * @xe: xe device
> > + *
> > + * Return: True if primary GTs are enabled, false if they have been disabled via
> > + *     configfs.
> > + */
> > +bool xe_configfs_primary_gt_supported(struct xe_device *xe)
> > +{
> > +	return (get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MAIN)) != 0;
> 
> can't we just rely on the promotion to bool?
> 
> 	return get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MAIN);
> 
> > +}
> > +
> > +/**
> > + * xe_configfs_media_gt_supported - determine whether media GTs are supported
> > + * @xe: xe device
> > + *
> > + * Return: True if the media GTs are enabled, false if they have been disabled
> > + *     via configfs.
> > + */
> > +bool xe_configfs_media_gt_supported(struct xe_device *xe)
> > +{
> > +	return (get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MEDIA)) != 0;
> > +}
> > +
> >  /**
> >   * xe_configfs_get_engines_allowed - get engine allowed mask from configfs
> >   * @pdev: pci device
> > diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h
> > index c61e0e47ed94..5624e965b911 100644
> > --- a/drivers/gpu/drm/xe/xe_configfs.h
> > +++ b/drivers/gpu/drm/xe/xe_configfs.h
> > @@ -17,6 +17,8 @@ int xe_configfs_init(void);
> >  void xe_configfs_exit(void);
> >  void xe_configfs_check_device(struct pci_dev *pdev);
> >  bool xe_configfs_get_survivability_mode(struct pci_dev *pdev);
> > +bool xe_configfs_primary_gt_supported(struct xe_device *xe);
> > +bool xe_configfs_media_gt_supported(struct xe_device *xe);
> 
> I guess we need decide now whether we want to continue to pass pdev or switch to xe as argument for all xe_configfs functions
> 
> >  u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev);
> >  bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev);
> >  u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
> > @@ -28,6 +30,8 @@ static inline int xe_configfs_init(void) { return 0; }
> >  static inline void xe_configfs_exit(void) { }
> >  static inline void xe_configfs_check_device(struct pci_dev *pdev) { }
> >  static inline bool xe_configfs_get_survivability_mode(struct pci_dev *pdev) { return false; }
> > +static inline bool xe_configfs_primary_gt_supported(struct xe_device *xe) { return true; }
> > +static inline bool xe_configfs_media_gt_supported(struct xe_device *xe) { return true; }
> >  static inline u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev) { return U64_MAX; }
> >  static inline bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev) { return false; }
> >  static inline u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
> > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> > index a5932e4f4a23..9c8ab2b41737 100644
> > --- a/drivers/gpu/drm/xe/xe_pci.c
> > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > @@ -695,6 +695,11 @@ static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
> >  	struct xe_device *xe = tile_to_xe(tile);
> >  	struct xe_gt *gt;
> >  
> > +	if (!xe_configfs_primary_gt_supported(xe)) {
> > +		drm_info(&xe->drm, "Primary GT disabled via configfs\n");
> 
> nit: you can use xe_info(xe, "...") now
> 
> > +		return NULL;
> > +	}
> > +
> >  	gt = xe_gt_alloc(tile);
> >  	if (IS_ERR(gt))
> >  		return gt;
> > @@ -720,6 +725,11 @@ static struct xe_gt *alloc_media_gt(struct xe_tile *tile,
> >  	struct xe_device *xe = tile_to_xe(tile);
> >  	struct xe_gt *gt;
> >  
> > +	if (!xe_configfs_media_gt_supported(xe)) {
> > +		drm_info(&xe->drm, "Media GT disabled via configfs\n");
> > +		return NULL;
> > +	}
> > +
> >  	if (MEDIA_VER(xe) < 13 || !media_desc)
> >  		return NULL;
> >  
> > @@ -829,6 +839,18 @@ static int xe_info_init(struct xe_device *xe,
> >  		if (IS_ERR(tile->primary_gt))
> >  			return PTR_ERR(tile->primary_gt);
> >  
> > +		/*
> > +		 * It's not currently possible to probe a device with the
> > +		 * primary GT disabled.  With some work, this may be future in
> > +		 * the possible for igpu platforms (although probably not for
> > +		 * dgpu's since access to the primary GT's BCS engines is
> > +		 * required for VRAM management).
> > +		 */
> > +		if (!tile->primary_gt) {
> > +			drm_err(&xe->drm, "Cannot probe device with without a primary GT\n");
> > +			return -ENODEV;
> > +		}
> > +
> >  		tile->media_gt = alloc_media_gt(tile, media_desc);
> >  		if (IS_ERR(tile->media_gt))
> >  			return PTR_ERR(tile->media_gt);
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v4 22/23] drm/xe/configfs: Add attribute to disable GT types

[Lucas De Marchi]

On Wed, Oct 08, 2025 at 01:08:53PM -0700, Matt Roper wrote:
>On Wed, Oct 08, 2025 at 12:12:37PM +0200, Michal Wajdeczko wrote:
>>
>>
>> On 10/7/2025 10:48 PM, Matt Roper wrote:
>> > Preventing the driver from initializing GTs of specific type(s) can be
>> > useful for debugging and early hardware bringup.  Add a configfs
>> > attribute to allow this kind of control for debugging.
>> >
>> > With today's platforms and software design, this configuration setting
>> > is only effective for disabling the media GT since the driver currently
>> > requires that there always be a primary GT to probe the device.  However
>> > this might change in the future ---  in theory it should be possible
>> > (with some additional driver work) to allow an igpu device to come up
>> > with only the media GT and no primary GT.  Or to allow an igpu device to
>> > come up with no GTs at all (for display-only usage).  A primary GT will
>> > likely always be required on dgpu platforms because we rely on the BCS
>> > engines inside the primary GT for various vram operations.
>> >
>> > v2:
>> >  - Expand/clarify kerneldoc for configfs attribute.  (Gustavo)
>> >  - Tighten type usage in gt_types[] structure.  (Gustavo)
>> >  - Adjust string parsing/name matching to match exact GT names and not
>> >    accept partial names.  (Gustavo)
>> >
>> > v3:
>> >  - Switch to scope-based cleanup in gt_types_allowed_store() to fix a
>> >    leak if the device is already bound.  (Gustavo)
>> >  - Switch configfs lookup interface to two boolean functions that
>> >    specify whether primary/media are supported rather than one function
>> >    that returns a mask.  This is simpler to use and understand.
>> >
>> > Cc: Gustavo Sousa <gustavo.sousa@intel.com>
>> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> > ---
>> >  drivers/gpu/drm/xe/xe_configfs.c | 145 +++++++++++++++++++++++++++++++
>> >  drivers/gpu/drm/xe/xe_configfs.h |   4 +
>> >  drivers/gpu/drm/xe/xe_pci.c      |  22 +++++
>> >  3 files changed, 171 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
>> > index 139663423185..e36cc5e1bc8f 100644
>> > --- a/drivers/gpu/drm/xe/xe_configfs.c
>> > +++ b/drivers/gpu/drm/xe/xe_configfs.c
>> > @@ -15,6 +15,7 @@
>> >
>> >  #include "instructions/xe_mi_commands.h"
>> >  #include "xe_configfs.h"
>> > +#include "xe_gt_types.h"
>> >  #include "xe_hw_engine_types.h"
>> >  #include "xe_module.h"
>> >  #include "xe_pci_types.h"
>> > @@ -56,6 +57,7 @@
>> >   *	:
>> >   *	└── 0000:03:00.0
>> >   *	    ├── survivability_mode
>> > + *	    ├── gt_types_allowed
>>
>> I'm wondering if we want to keep such advance knobs at the same level as others?
>> maybe create sub-group for them, like I did for sriov?
>>
>> 	    └── tweaks
>> 	        ├── gt_types_allowed
>> 	        ├── engines_allowed
>
>That makes sense to me, although I'm not sure if it's too late to make
>this change now since I think 'engines_allowed' is already part of
>v6.17.  Are these configfs settings considered ABI that we can't change
>now, even though they're explicitly intended for driver developers?
>
>+Cc Lucas to see what he thinks.

I think we are pretty safe to say nobody but developers doing bringup of
a platform are using this. I wouldn't be much concerned at this point
that this would break anything outside of our own muscle memory.

However I don't like the tweaks dir. These are all tweaks to how the
driver interacts with the HW. For the really dangerous ones, we taint
the kernel and document them as such.

Lucas De Marchi

>
>>
>>
>> >   *	    ├── engines_allowed
>> >   *	    └── enable_psmi
>>
>> oops, and it looks that I missed to update this part of the doc when adding max_vfs with:
>>
>> 	    └── sriov
>> 	        ├── max_vfs
>>
>> >   *
>> > @@ -79,6 +81,44 @@
>> >   *
>> >   * This attribute can only be set before binding to the device.
>> >   *
>> > + * Allowed GT types:
>> > + * -----------------
>> > + *
>> > + * Allow only specific types of GTs to be detected and initialized by the
>> > + * driver.  Any combination of GT types can be enabled/disabled, although
>> > + * some settings will cause the device to fail to probe.
>> > + *
>> > + * Writes support both comma- and newline-separated input format. Reads
>> > + * will always return one GT type per line. "primary" and "media" are the
>> > + * GT type names supported by this interface.
>> > + *
>> > + * This attribute can only be set before binding to the device.
>> > + *
>> > + * Examples:
>> > + *
>> > + * Allow both primary and media GTs to be initialized and used.  This matches
>> > + * the driver's default behavior::
>> > + *
>> > + *	# echo 'primary,media' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
>>
>> maybe "all" as an alias?
>>
>> > + *
>> > + * Allow only the primary GT of each tile to be initialized and used,
>> > + * effectively disabling the media GT if it exists on the platform::
>> > + *
>> > + *	# echo 'primary' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
>> > + *
>> > + * Allow only the media GT of each tile to be initialized and used,
>> > + * effectively disabling the primary GT.  **This configuration will cause
>> > + * device probe failure on all current platforms, but may be allowed on
>> > + * igpu platforms in the future**::
>> > + *
>> > + *	# echo 'media' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
>> > + *
>> > + * Disable all GTs.  Only other GPU IP (such as display) is potentially usable.
>> > + * **This configuration will cause device probe failure on all current
>> > + * platforms, but may be allowed on igpu platforms in the future**::
>> > + *
>> > + *	# echo '' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed
>>
>> maybe "none" as an alias?
>
>While we could add the all/none aliases, I'm not sure it's worth the
>extra parsing hassle, since then we also need to check for nonsense
>settings like "primary,none" and such.  Since only a small subset of
>driver developers are expected to ever use these, we don't need to worry
>too much about convenience aliases.
>
>>
>> > + *
>> >   * Allowed engines:
>> >   * ----------------
>> >   *
>> > @@ -187,6 +227,7 @@ struct xe_config_group_device {
>> >  	struct config_group group;
>> >
>> >  	struct xe_config_device {
>> > +		u64 gt_types_allowed;
>> >  		u64 engines_allowed;
>> >  		struct wa_bb ctx_restore_post_bb[XE_ENGINE_CLASS_MAX];
>> >  		struct wa_bb ctx_restore_mid_bb[XE_ENGINE_CLASS_MAX];
>> > @@ -201,6 +242,7 @@ struct xe_config_group_device {
>> >  };
>> >
>> >  static const struct xe_config_device device_defaults = {
>> > +	.gt_types_allowed = U64_MAX,
>> >  	.engines_allowed = U64_MAX,
>> >  	.survivability_mode = false,
>> >  	.enable_psmi = false,
>> > @@ -220,6 +262,7 @@ struct engine_info {
>> >  /* Some helpful macros to aid on the sizing of buffer allocation when parsing */
>> >  #define MAX_ENGINE_CLASS_CHARS 5
>> >  #define MAX_ENGINE_INSTANCE_CHARS 2
>> > +#define MAX_GT_TYPE_CHARS 7
>> >
>> >  static const struct engine_info engine_info[] = {
>> >  	{ .cls = "rcs", .mask = XE_HW_ENGINE_RCS_MASK, .engine_class = XE_ENGINE_CLASS_RENDER },
>> > @@ -230,6 +273,14 @@ static const struct engine_info engine_info[] = {
>> >  	{ .cls = "gsccs", .mask = XE_HW_ENGINE_GSCCS_MASK, .engine_class = XE_ENGINE_CLASS_OTHER },
>> >  };
>> >
>> > +static const struct {
>> > +	const char name[MAX_GT_TYPE_CHARS + 1];
>> > +	enum xe_gt_type type;
>> > +} gt_types[] = {
>> > +	{ .name = "primary", .type = XE_GT_TYPE_MAIN },
>> > +	{ .name = "media", .type = XE_GT_TYPE_MEDIA },
>> > +};
>> > +
>> >  static struct xe_config_group_device *to_xe_config_group_device(struct config_item *item)
>> >  {
>> >  	return container_of(to_config_group(item), struct xe_config_group_device, group);
>> > @@ -292,6 +343,58 @@ static ssize_t survivability_mode_store(struct config_item *item, const char *pa
>> >  	return len;
>> >  }
>> >
>> > +static ssize_t gt_types_allowed_show(struct config_item *item, char *page)
>> > +{
>> > +	struct xe_config_device *dev = to_xe_config_device(item);
>> > +	char *p = page;
>> > +
>> > +	for (size_t i = 0; i < ARRAY_SIZE(gt_types); i++)
>> > +		if (dev->gt_types_allowed & BIT_ULL(gt_types[i].type))
>> > +			p += sprintf(p, "%s\n", gt_types[i].name);
>> > +
>> > +	return p - page;
>> > +}
>> > +
>> > +static ssize_t gt_types_allowed_store(struct config_item *item, const char *page,
>> > +				      size_t len)
>> > +{
>> > +	struct xe_config_group_device *dev = to_xe_config_group_device(item);
>> > +	char *buf __free(kfree) = kstrdup(page, GFP_KERNEL);
>> > +	char *p = buf;
>> > +	u64 typemask = 0;
>> > +
>> > +	if (!buf)
>> > +		return -ENOMEM;
>> > +
>> > +	while (p) {
>> > +		char *typename = strsep(&p, ",\n");
>> > +		bool matched = false;
>> > +
>> > +		if (typename[0] == '\0')
>> > +			continue;
>> > +
>> > +		for (size_t i = 0; i < ARRAY_SIZE(gt_types); i++) {
>> > +			if (strcmp(typename, gt_types[i].name) == 0) {
>> > +				typemask |= BIT(gt_types[i].type);
>> > +				matched = true;
>> > +				break;
>> > +			}
>> > +		}
>> > +
>> > +		if (!matched)
>> > +			return -EINVAL;
>> > +	}
>> > +
>> > +	scoped_guard(mutex, &dev->lock) {
>>
>> probably plain guard(mutex) will work here too
>>
>> > +		if (is_bound(dev))
>> > +			return -EBUSY;
>>
>> then we can take a lock and return earlier, before parsing input
>>
>> > +
>> > +		dev->config.gt_types_allowed = typemask;
>> > +	}
>> > +
>> > +	return len;
>> > +}
>> > +
>> >  static ssize_t engines_allowed_show(struct config_item *item, char *page)
>> >  {
>> >  	struct xe_config_device *dev = to_xe_config_device(item);
>> > @@ -672,6 +775,7 @@ CONFIGFS_ATTR(, ctx_restore_mid_bb);
>> >  CONFIGFS_ATTR(, ctx_restore_post_bb);
>> >  CONFIGFS_ATTR(, enable_psmi);
>> >  CONFIGFS_ATTR(, engines_allowed);
>> > +CONFIGFS_ATTR(, gt_types_allowed);
>> >  CONFIGFS_ATTR(, survivability_mode);
>> >
>> >  static struct configfs_attribute *xe_config_device_attrs[] = {
>> > @@ -679,6 +783,7 @@ static struct configfs_attribute *xe_config_device_attrs[] = {
>> >  	&attr_ctx_restore_post_bb,
>> >  	&attr_enable_psmi,
>> >  	&attr_engines_allowed,
>> > +	&attr_gt_types_allowed,
>> >  	&attr_survivability_mode,
>> >  	NULL,
>> >  };
>> > @@ -846,6 +951,7 @@ static void dump_custom_dev_config(struct pci_dev *pdev,
>> >  				 dev->config.attr_); \
>> >  	} while (0)
>> >
>> > +	PRI_CUSTOM_ATTR("%llx", gt_types_allowed);
>> >  	PRI_CUSTOM_ATTR("%llx", engines_allowed);
>> >  	PRI_CUSTOM_ATTR("%d", enable_psmi);
>> >  	PRI_CUSTOM_ATTR("%d", survivability_mode);
>> > @@ -896,6 +1002,45 @@ bool xe_configfs_get_survivability_mode(struct pci_dev *pdev)
>> >  	return mode;
>> >  }
>> >
>> > +static u64 get_gt_types_allowed(struct xe_device *xe)
>> > +{
>> > +	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
>> > +	struct xe_config_group_device *dev = find_xe_config_group_device(pdev);
>> > +	u64 mask;
>> > +
>> > +	if (!dev)
>> > +		return device_defaults.gt_types_allowed;
>> > +
>> > +	mask = dev->config.gt_types_allowed;
>>
>> btw, as we are using guard during write, shouldn't we also guard during read?
>
>I'm not sure; is there something racy you see on the read path that we
>need to avoid?  An individual get_gt_types_allowed() call racing with a
>configfs write doesn't seem like it would matter; rather the problems of
>a racing configfs write would be if it happened while a device was in
>the middle of getting probed (so some calls to get_gt_types_allowed()
>see the old value and others see the new one, leading to inconsistent
>device intialization).  But given this is a low-level kernel hacking
>interface intended for driver developers, I'm not sure how much we need
>to worry about them shooting themselves in the foot.  Maybe I'm
>overlooking something?
>
>
>Matt
>
>>
>> > +	config_group_put(&dev->group);
>> > +
>> > +	return mask;
>> > +}
>> > +
>> > +/**
>> > + * xe_configfs_primary_gt_supported - determine whether primary GTs are supported
>> > + * @xe: xe device
>> > + *
>> > + * Return: True if primary GTs are enabled, false if they have been disabled via
>> > + *     configfs.
>> > + */
>> > +bool xe_configfs_primary_gt_supported(struct xe_device *xe)
>> > +{
>> > +	return (get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MAIN)) != 0;
>>
>> can't we just rely on the promotion to bool?
>>
>> 	return get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MAIN);
>>
>> > +}
>> > +
>> > +/**
>> > + * xe_configfs_media_gt_supported - determine whether media GTs are supported
>> > + * @xe: xe device
>> > + *
>> > + * Return: True if the media GTs are enabled, false if they have been disabled
>> > + *     via configfs.
>> > + */
>> > +bool xe_configfs_media_gt_supported(struct xe_device *xe)
>> > +{
>> > +	return (get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MEDIA)) != 0;
>> > +}
>> > +
>> >  /**
>> >   * xe_configfs_get_engines_allowed - get engine allowed mask from configfs
>> >   * @pdev: pci device
>> > diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h
>> > index c61e0e47ed94..5624e965b911 100644
>> > --- a/drivers/gpu/drm/xe/xe_configfs.h
>> > +++ b/drivers/gpu/drm/xe/xe_configfs.h
>> > @@ -17,6 +17,8 @@ int xe_configfs_init(void);
>> >  void xe_configfs_exit(void);
>> >  void xe_configfs_check_device(struct pci_dev *pdev);
>> >  bool xe_configfs_get_survivability_mode(struct pci_dev *pdev);
>> > +bool xe_configfs_primary_gt_supported(struct xe_device *xe);
>> > +bool xe_configfs_media_gt_supported(struct xe_device *xe);
>>
>> I guess we need decide now whether we want to continue to pass pdev or switch to xe as argument for all xe_configfs functions
>>
>> >  u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev);
>> >  bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev);
>> >  u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
>> > @@ -28,6 +30,8 @@ static inline int xe_configfs_init(void) { return 0; }
>> >  static inline void xe_configfs_exit(void) { }
>> >  static inline void xe_configfs_check_device(struct pci_dev *pdev) { }
>> >  static inline bool xe_configfs_get_survivability_mode(struct pci_dev *pdev) { return false; }
>> > +static inline bool xe_configfs_primary_gt_supported(struct xe_device *xe) { return true; }
>> > +static inline bool xe_configfs_media_gt_supported(struct xe_device *xe) { return true; }
>> >  static inline u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev) { return U64_MAX; }
>> >  static inline bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev) { return false; }
>> >  static inline u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
>> > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>> > index a5932e4f4a23..9c8ab2b41737 100644
>> > --- a/drivers/gpu/drm/xe/xe_pci.c
>> > +++ b/drivers/gpu/drm/xe/xe_pci.c
>> > @@ -695,6 +695,11 @@ static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
>> >  	struct xe_device *xe = tile_to_xe(tile);
>> >  	struct xe_gt *gt;
>> >
>> > +	if (!xe_configfs_primary_gt_supported(xe)) {
>> > +		drm_info(&xe->drm, "Primary GT disabled via configfs\n");
>>
>> nit: you can use xe_info(xe, "...") now
>>
>> > +		return NULL;
>> > +	}
>> > +
>> >  	gt = xe_gt_alloc(tile);
>> >  	if (IS_ERR(gt))
>> >  		return gt;
>> > @@ -720,6 +725,11 @@ static struct xe_gt *alloc_media_gt(struct xe_tile *tile,
>> >  	struct xe_device *xe = tile_to_xe(tile);
>> >  	struct xe_gt *gt;
>> >
>> > +	if (!xe_configfs_media_gt_supported(xe)) {
>> > +		drm_info(&xe->drm, "Media GT disabled via configfs\n");
>> > +		return NULL;
>> > +	}
>> > +
>> >  	if (MEDIA_VER(xe) < 13 || !media_desc)
>> >  		return NULL;
>> >
>> > @@ -829,6 +839,18 @@ static int xe_info_init(struct xe_device *xe,
>> >  		if (IS_ERR(tile->primary_gt))
>> >  			return PTR_ERR(tile->primary_gt);
>> >
>> > +		/*
>> > +		 * It's not currently possible to probe a device with the
>> > +		 * primary GT disabled.  With some work, this may be future in
>> > +		 * the possible for igpu platforms (although probably not for
>> > +		 * dgpu's since access to the primary GT's BCS engines is
>> > +		 * required for VRAM management).
>> > +		 */
>> > +		if (!tile->primary_gt) {
>> > +			drm_err(&xe->drm, "Cannot probe device with without a primary GT\n");
>> > +			return -ENODEV;
>> > +		}
>> > +
>> >  		tile->media_gt = alloc_media_gt(tile, media_desc);
>> >  		if (IS_ERR(tile->media_gt))
>> >  			return PTR_ERR(tile->media_gt);
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [PATCH v4 06/23] drm/xe: Move 'has_flatccs' flag back to platform descriptor

[Jani Nikula]

On Tue, 07 Oct 2025, Matt Roper <matthew.d.roper@intel.com> wrote:
> @@ -604,6 +605,8 @@ static int xe_info_init_early(struct xe_device *xe,
>  
>  	xe->info.is_dgfx = desc->is_dgfx;
>  	xe->info.has_fan_control = desc->has_fan_control;
> +	/* runtime fusing may force flat_ccs to disabled later */
> +	xe->info.has_flat_ccs = desc->has_flat_ccs;

Related, but not specific to this patch:

I'm looking at bspec 59255 and it seems to me the fusing is about CCS in
general, not about aux vs flat.

Should the runtime fusing be separated from has_flat_ccs? Am I missing
something here?


BR,
Jani.

-- 
Jani Nikula, Intel

Re: [PATCH v4 06/23] drm/xe: Move 'has_flatccs' flag back to platform descriptor

[Matt Roper]

On Fri, Oct 10, 2025 at 01:50:11PM +0300, Jani Nikula wrote:
> On Tue, 07 Oct 2025, Matt Roper <matthew.d.roper@intel.com> wrote:
> > @@ -604,6 +605,8 @@ static int xe_info_init_early(struct xe_device *xe,
> >  
> >  	xe->info.is_dgfx = desc->is_dgfx;
> >  	xe->info.has_fan_control = desc->has_fan_control;
> > +	/* runtime fusing may force flat_ccs to disabled later */
> > +	xe->info.has_flat_ccs = desc->has_flat_ccs;
> 
> Related, but not specific to this patch:
> 
> I'm looking at bspec 59255 and it seems to me the fusing is about CCS in
> general, not about aux vs flat.

FlatCCS is the only kind of CCS that exists anymore from Xe2 onward;
AuxCCS ended with Xe1.  Both igpu and dgpu use FlatCCS now, although it
may be disabled by the BIOS, which is what that register reports.


Matt

> 
> Should the runtime fusing be separated from has_flat_ccs? Am I missing
> something here?
> 
> 
> BR,
> Jani.
> 
> -- 
> Jani Nikula, Intel

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation