* ✗ CI.checkpatch: warning for Add CPER logging support for CRI (rev5)
2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
@ 2026-10-23 4:24 ` Patchwork
2026-10-23 4:26 ` ✓ CI.KUnit: success " Patchwork
` (15 subsequent siblings)
16 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2026-10-23 4:24 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-xe
== Series Details ==
Series: Add CPER logging support for CRI (rev5)
URL : https://patchwork.freedesktop.org/series/169692/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
3009867cd31863246e4afc138520a7a8bd37bb11
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 8fc148746b056924861ffa8fb544607761544555
Author: Badal Nilawar <badal.nilawar@intel.com>
Date: Fri Oct 23 10:04:35 2026 +0530
drm/xe/cper: Prepare Intel CPER info records
Prepare xe_cper_intel_info records from RAS info queue data. Depending
on the error class type, detail or aggregate, one or more info records
may be generated and embedded in the CPER record.
Assisted-by: LLM
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
+ /mt/dim checkpatch 55c6bb0b4d006ee415abe9f048014f7bcc90ae6f drm-intel
a08e56366500 drm/xe/cper: Add CPER reporting entry point for xe_log
-:29: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#29:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 99 lines checked
a467793412c0 drm/xe/cper: Retrieve the error counter record for CPER reporting
dbb96b6ea55f drm/xe/cper: Initialize Intel-specific section header
-:95: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#95:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 127 lines checked
87c8b6f7828b drm/xe/cper: Construct CPER record for hardware errors
a443be8b82e9 drm/xe/cper: Log CPER records for aggregate counter retrieval
-:13: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#13:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 266 lines checked
f90c838af9a7 drm/xe/cper: Emit cper record to trace buf
-:69: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#69:
new file mode 100644
-:116: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#116: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:28:
+ TP_STRUCT__entry(
-:126: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#126: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:38:
+ TP_fast_assign(
-:151: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#151: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:63:
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
^
-:151: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#151: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:63:
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
^
-:151: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#151: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:63:
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
^
-:151: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#151: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:63:
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
^
-:151: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#151: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:63:
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
^
total: 0 errors, 1 warnings, 7 checks, 116 lines checked
a61f5eedf180 drm/xe/xe_ras: Report device memory errors using SIGID
fde5658527cb drm/xe/xe_ras: Report core compute errors using SIGID
b1849d585a94 drm/xe/xe_ras: Report soc internal errors using SIGID
6fe21ac0d813 drm/xe/xe_ras: Report correctable errors using SIGID
581f6201f446 drm/xe/xe_ras: Report unknown errors using SIGID
7c1ffae6c25d drm/xe/xe_ras: Add support to retrieve info queue data
8fc148746b05 drm/xe/cper: Prepare Intel CPER info records
^ permalink raw reply [flat|nested] 37+ messages in thread
* ✓ CI.KUnit: success for Add CPER logging support for CRI (rev5)
2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
2026-10-23 4:24 ` ✗ CI.checkpatch: warning for Add CPER logging support for CRI (rev5) Patchwork
@ 2026-10-23 4:26 ` Patchwork
2026-10-23 4:34 ` [PATCH v5 01/13] drm/xe/cper: Add CPER reporting entry point for xe_log Badal Nilawar
` (14 subsequent siblings)
16 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2026-10-23 4:26 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-xe
== Series Details ==
Series: Add CPER logging support for CRI (rev5)
URL : https://patchwork.freedesktop.org/series/169692/
State : success
== Summary ==
+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[04:24:44] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:24:49] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:25:09] Starting KUnit Kernel (1/1)...
[04:25:09] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:25:09] ================= gpu_buddy (14 subtests) ==================
[04:25:09] [PASSED] gpu_test_buddy_alloc_limit
[04:25:09] [PASSED] gpu_test_buddy_alloc_optimistic
[04:25:09] [PASSED] gpu_test_buddy_alloc_pessimistic
[04:25:09] [PASSED] gpu_test_buddy_alloc_pathological
[04:25:09] [PASSED] gpu_test_buddy_alloc_contiguous
[04:25:09] [PASSED] gpu_test_buddy_alloc_clear
[04:25:09] [PASSED] gpu_test_buddy_alloc_range
[04:25:09] [PASSED] gpu_test_buddy_alloc_range_bias
[04:25:10] [PASSED] gpu_test_buddy_fragmentation_performance
[04:25:10] [PASSED] gpu_test_buddy_dirty_tracker_performance
[04:25:10] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[04:25:10] [PASSED] gpu_test_buddy_offset_aligned_allocation
[04:25:10] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[04:25:10] [PASSED] gpu_test_buddy_addr_to_block
[04:25:10] ==================== [PASSED] gpu_buddy ====================
[04:25:10] ============================================================
[04:25:10] Testing complete. Ran 14 tests: passed: 14
[04:25:11] Elapsed time: 26.180s total, 4.496s configuring, 19.816s building, 1.803s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[04:25:11] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:25:13] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:25:51] Starting KUnit Kernel (1/1)...
[04:25:51] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:25:51] ================== guc_buf (11 subtests) ===================
[04:25:51] [PASSED] test_smallest
[04:25:51] [PASSED] test_largest
[04:25:51] [PASSED] test_granular
[04:25:51] [PASSED] test_unique
[04:25:51] [PASSED] test_overlap
[04:25:51] [PASSED] test_reusable
[04:25:52] [PASSED] test_too_big
[04:25:52] [PASSED] test_flush
[04:25:52] [PASSED] test_lookup
[04:25:52] [PASSED] test_data
[04:25:52] [PASSED] test_class
[04:25:52] ===================== [PASSED] guc_buf =====================
[04:25:52] =================== guc_dbm (7 subtests) ===================
[04:25:52] [PASSED] test_empty
[04:25:52] [PASSED] test_default
[04:25:52] ======================== test_size ========================
[04:25:52] [PASSED] 4
[04:25:52] [PASSED] 8
[04:25:52] [PASSED] 32
[04:25:52] [PASSED] 256
[04:25:52] ==================== [PASSED] test_size ====================
[04:25:52] ======================= test_reuse ========================
[04:25:52] [PASSED] 4
[04:25:52] [PASSED] 8
[04:25:52] [PASSED] 32
[04:25:52] [PASSED] 256
[04:25:52] =================== [PASSED] test_reuse ====================
[04:25:52] =================== test_range_overlap ====================
[04:25:52] [PASSED] 4
[04:25:52] [PASSED] 8
[04:25:52] [PASSED] 32
[04:25:52] [PASSED] 256
[04:25:52] =============== [PASSED] test_range_overlap ================
[04:25:52] =================== test_range_compact ====================
[04:25:52] [PASSED] 4
[04:25:52] [PASSED] 8
[04:25:52] [PASSED] 32
[04:25:52] [PASSED] 256
[04:25:52] =============== [PASSED] test_range_compact ================
[04:25:52] ==================== test_range_spare =====================
[04:25:52] [PASSED] 4
[04:25:52] [PASSED] 8
[04:25:52] [PASSED] 32
[04:25:52] [PASSED] 256
[04:25:52] ================ [PASSED] test_range_spare =================
[04:25:52] ===================== [PASSED] guc_dbm =====================
[04:25:52] ================== guc_idm (22 subtests) ===================
[04:25:52] [PASSED] bad_init
[04:25:52] [PASSED] no_init
[04:25:52] [PASSED] init_fini
[04:25:52] [PASSED] check_init_small
[04:25:52] [PASSED] check_init_shared
[04:25:52] [PASSED] check_used
[04:25:52] [PASSED] check_quota
[04:25:52] [PASSED] check_all
[04:25:52] [PASSED] check_limits
[04:25:52] [PASSED] check_overlap
[04:25:52] [PASSED] check_overlap_alloc
[04:25:52] [PASSED] check_overlap_release
[04:25:52] [PASSED] check_overlap_partial_init
[04:25:52] [PASSED] check_overlap_partial_shared_range_blocking
[04:25:52] [PASSED] check_used_usable
[04:25:52] [PASSED] check_used_shareable
[04:25:52] [PASSED] check_used_mixed
[04:25:52] [PASSED] check_release_usable_range
[04:25:52] [PASSED] check_release_shareable_range
[04:25:52] [PASSED] check_split_boundaries
[04:25:52] [PASSED] check_shareable_spare
[04:25:52] [PASSED] check_shareable_spare_fragmented_tail
[04:25:52] ===================== [PASSED] guc_idm =====================
[04:25:52] ============== guc_klv_helpers (13 subtests) ===============
[04:25:52] [PASSED] test_count
[04:25:52] [PASSED] test_encode_u32
[04:25:52] [PASSED] test_encode_u64
[04:25:52] [PASSED] test_encode_string
[04:25:52] [PASSED] test_encode_object_raw
[04:25:52] [PASSED] test_encode_object_klv
[04:25:52] [PASSED] test_encode_object_nested
[04:25:52] [PASSED] test_encode_object_basic
[04:25:52] ===================== test_decode_u16 =====================
[04:25:52] [PASSED] empty
[04:25:52] [PASSED] valid
[04:25:52] [PASSED] max
[04:25:52] [PASSED] big
[04:25:52] [PASSED] long
[04:25:52] ================= [PASSED] test_decode_u16 =================
[04:25:52] ===================== test_decode_u32 =====================
[04:25:52] [PASSED] empty
[04:25:52] [PASSED] valid
[04:25:52] [PASSED] max
[04:25:52] [PASSED] long
[04:25:52] ================= [PASSED] test_decode_u32 =================
[04:25:52] ===================== test_decode_u64 =====================
[04:25:52] [PASSED] empty
[04:25:52] [PASSED] short
[04:25:52] [PASSED] valid
[04:25:52] [PASSED] max
[04:25:52] [PASSED] long
[04:25:52] ================= [PASSED] test_decode_u64 =================
[04:25:52] ===================== test_decode_str =====================
[04:25:52] [PASSED] empty
[04:25:52] [PASSED] one
[04:25:52] [PASSED] one_trash
[04:25:52] [PASSED] two
[04:25:52] [PASSED] two_trash
[04:25:52] [PASSED] three
[04:25:52] [PASSED] dword
[04:25:52] [PASSED] four
[04:25:52] [PASSED] five
[04:25:52] [PASSED] six
[04:25:52] [PASSED] seven
[04:25:52] [PASSED] qword
[04:25:52] ================= [PASSED] test_decode_str =================
[04:25:52] [PASSED] test_print
[04:25:52] ================= [PASSED] guc_klv_helpers =================
[04:25:52] =================== xe_log (4 subtests) ====================
[04:25:52] [PASSED] demo_cper
[04:25:52] [PASSED] demo_dmesg
[04:25:52] ======================= test_dmesg ========================
[04:25:52] [PASSED] test_fatal
[04:25:52] [PASSED] test_fatal_tile
[04:25:52] [PASSED] test_fatal_gt
[04:25:52] [PASSED] test_fatal_comp
[04:25:52] [PASSED] test_fatal_comp_tile
[04:25:52] [PASSED] test_fatal_comp_gt
[04:25:52] [PASSED] test_fatal_all
[04:25:52] [PASSED] test_recoverable
[04:25:52] [PASSED] test_recoverable_tile
[04:25:52] [PASSED] test_recoverable_gt
[04:25:52] [PASSED] test_recoverable_comp
[04:25:52] [PASSED] test_recoverable_comp_tile
[04:25:52] [PASSED] test_recoverable_comp_gt
[04:25:52] [PASSED] test_recoverable_all
[04:25:52] [PASSED] test_info
[04:25:52] [PASSED] test_info_tile
[04:25:52] [PASSED] test_info_gt
[04:25:52] [PASSED] test_info_err
[04:25:52] [PASSED] test_info_comp
[04:25:52] [PASSED] test_info_comp_tile
[04:25:52] [PASSED] test_info_comp_gt
[04:25:52] [PASSED] test_info_all
[04:25:52] [PASSED] test_hw_fatal
[04:25:52] [PASSED] test_hw_recoverable
[04:25:52] [PASSED] test_hw_corrected
[04:25:52] [PASSED] test_hw_informational
[04:25:52] =================== [PASSED] test_dmesg ====================
[04:25:52] ====================== test_invalid =======================
[04:25:52] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[04:25:52] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[04:25:52] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[04:25:52] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[04:25:52] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[04:25:52] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[04:25:52] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[04:25:52] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[04:25:52] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[04:25:52] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[04:25:52] ================== [SKIPPED] test_invalid ==================
[04:25:52] ===================== [PASSED] xe_log ======================
[04:25:52] ================== no_relay (3 subtests) ===================
[04:25:52] [PASSED] xe_drops_guc2pf_if_not_ready
[04:25:52] [PASSED] xe_drops_guc2vf_if_not_ready
[04:25:52] [PASSED] xe_rejects_send_if_not_ready
[04:25:52] ==================== [PASSED] no_relay =====================
[04:25:52] ================== pf_relay (14 subtests) ==================
[04:25:52] [PASSED] pf_rejects_guc2pf_too_short
[04:25:52] [PASSED] pf_rejects_guc2pf_too_long
[04:25:52] [PASSED] pf_rejects_guc2pf_no_payload
[04:25:52] [PASSED] pf_fails_no_payload
[04:25:52] [PASSED] pf_fails_bad_origin
[04:25:52] [PASSED] pf_fails_bad_type
[04:25:52] [PASSED] pf_txn_reports_error
[04:25:52] [PASSED] pf_txn_sends_pf2guc
[04:25:52] [PASSED] pf_sends_pf2guc
[04:25:52] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[04:25:52] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[04:25:52] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[04:25:52] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[04:25:52] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[04:25:52] ==================== [PASSED] pf_relay =====================
[04:25:52] ================== vf_relay (3 subtests) ===================
[04:25:52] [PASSED] vf_rejects_guc2vf_too_short
[04:25:52] [PASSED] vf_rejects_guc2vf_too_long
[04:25:52] [PASSED] vf_rejects_guc2vf_no_payload
[04:25:52] ==================== [PASSED] vf_relay =====================
[04:25:52] ================ pf_gt_config (9 subtests) =================
[04:25:52] [PASSED] fair_contexts_1vf
[04:25:52] [PASSED] fair_doorbells_1vf
[04:25:52] [PASSED] fair_ggtt_1vf
[04:25:52] ====================== fair_vram_1vf ======================
[04:25:52] [PASSED] 3.50 GiB
[04:25:52] [PASSED] 11.5 GiB
[04:25:52] [PASSED] 15.5 GiB
[04:25:52] [PASSED] 31.5 GiB
[04:25:52] [PASSED] 63.5 GiB
[04:25:52] [PASSED] 1.91 GiB
[04:25:52] ================== [PASSED] fair_vram_1vf ==================
[04:25:52] ================ fair_vram_1vf_admin_only =================
[04:25:52] [PASSED] 3.50 GiB
[04:25:52] [PASSED] 11.5 GiB
[04:25:52] [PASSED] 15.5 GiB
[04:25:52] [PASSED] 31.5 GiB
[04:25:52] [PASSED] 63.5 GiB
[04:25:52] [PASSED] 1.91 GiB
[04:25:52] ============ [PASSED] fair_vram_1vf_admin_only =============
[04:25:52] ====================== fair_contexts ======================
[04:25:52] [PASSED] 1 VF
[04:25:52] [PASSED] 2 VFs
[04:25:52] [PASSED] 3 VFs
[04:25:52] [PASSED] 4 VFs
[04:25:52] [PASSED] 5 VFs
[04:25:52] [PASSED] 6 VFs
[04:25:52] [PASSED] 7 VFs
[04:25:52] [PASSED] 8 VFs
[04:25:52] [PASSED] 9 VFs
[04:25:52] [PASSED] 10 VFs
[04:25:52] [PASSED] 11 VFs
[04:25:52] [PASSED] 12 VFs
[04:25:52] [PASSED] 13 VFs
[04:25:52] [PASSED] 14 VFs
[04:25:52] [PASSED] 15 VFs
[04:25:52] [PASSED] 16 VFs
[04:25:52] [PASSED] 17 VFs
[04:25:52] [PASSED] 18 VFs
[04:25:52] [PASSED] 19 VFs
[04:25:52] [PASSED] 20 VFs
[04:25:52] [PASSED] 21 VFs
[04:25:52] [PASSED] 22 VFs
[04:25:52] [PASSED] 23 VFs
[04:25:52] [PASSED] 24 VFs
[04:25:52] [PASSED] 25 VFs
[04:25:52] [PASSED] 26 VFs
[04:25:52] [PASSED] 27 VFs
[04:25:52] [PASSED] 28 VFs
[04:25:52] [PASSED] 29 VFs
[04:25:52] [PASSED] 30 VFs
[04:25:52] [PASSED] 31 VFs
[04:25:52] [PASSED] 32 VFs
[04:25:52] [PASSED] 33 VFs
[04:25:52] [PASSED] 34 VFs
[04:25:52] [PASSED] 35 VFs
[04:25:52] [PASSED] 36 VFs
[04:25:52] [PASSED] 37 VFs
[04:25:52] [PASSED] 38 VFs
[04:25:52] [PASSED] 39 VFs
[04:25:52] [PASSED] 40 VFs
[04:25:52] [PASSED] 41 VFs
[04:25:52] [PASSED] 42 VFs
[04:25:52] [PASSED] 43 VFs
[04:25:52] [PASSED] 44 VFs
[04:25:52] [PASSED] 45 VFs
[04:25:52] [PASSED] 46 VFs
[04:25:52] [PASSED] 47 VFs
[04:25:52] [PASSED] 48 VFs
[04:25:52] [PASSED] 49 VFs
[04:25:52] [PASSED] 50 VFs
[04:25:52] [PASSED] 51 VFs
[04:25:52] [PASSED] 52 VFs
[04:25:52] [PASSED] 53 VFs
[04:25:52] [PASSED] 54 VFs
[04:25:52] [PASSED] 55 VFs
[04:25:52] [PASSED] 56 VFs
[04:25:52] [PASSED] 57 VFs
[04:25:52] [PASSED] 58 VFs
[04:25:52] [PASSED] 59 VFs
[04:25:52] [PASSED] 60 VFs
[04:25:52] [PASSED] 61 VFs
[04:25:52] [PASSED] 62 VFs
[04:25:52] [PASSED] 63 VFs
[04:25:52] ================== [PASSED] fair_contexts ==================
[04:25:52] ===================== fair_doorbells ======================
[04:25:52] [PASSED] 1 VF
[04:25:52] [PASSED] 2 VFs
[04:25:52] [PASSED] 3 VFs
[04:25:52] [PASSED] 4 VFs
[04:25:52] [PASSED] 5 VFs
[04:25:52] [PASSED] 6 VFs
[04:25:52] [PASSED] 7 VFs
[04:25:52] [PASSED] 8 VFs
[04:25:52] [PASSED] 9 VFs
[04:25:52] [PASSED] 10 VFs
[04:25:52] [PASSED] 11 VFs
[04:25:52] [PASSED] 12 VFs
[04:25:52] [PASSED] 13 VFs
[04:25:52] [PASSED] 14 VFs
[04:25:52] [PASSED] 15 VFs
[04:25:52] [PASSED] 16 VFs
[04:25:52] [PASSED] 17 VFs
[04:25:52] [PASSED] 18 VFs
[04:25:52] [PASSED] 19 VFs
[04:25:52] [PASSED] 20 VFs
[04:25:52] [PASSED] 21 VFs
[04:25:52] [PASSED] 22 VFs
[04:25:52] [PASSED] 23 VFs
[04:25:52] [PASSED] 24 VFs
[04:25:52] [PASSED] 25 VFs
[04:25:52] [PASSED] 26 VFs
[04:25:52] [PASSED] 27 VFs
[04:25:52] [PASSED] 28 VFs
[04:25:52] [PASSED] 29 VFs
[04:25:52] [PASSED] 30 VFs
[04:25:52] [PASSED] 31 VFs
[04:25:52] [PASSED] 32 VFs
[04:25:52] [PASSED] 33 VFs
[04:25:52] [PASSED] 34 VFs
[04:25:52] [PASSED] 35 VFs
[04:25:52] [PASSED] 36 VFs
[04:25:52] [PASSED] 37 VFs
[04:25:52] [PASSED] 38 VFs
[04:25:52] [PASSED] 39 VFs
[04:25:52] [PASSED] 40 VFs
[04:25:52] [PASSED] 41 VFs
[04:25:52] [PASSED] 42 VFs
[04:25:52] [PASSED] 43 VFs
[04:25:52] [PASSED] 44 VFs
[04:25:52] [PASSED] 45 VFs
[04:25:52] [PASSED] 46 VFs
[04:25:52] [PASSED] 47 VFs
[04:25:52] [PASSED] 48 VFs
[04:25:52] [PASSED] 49 VFs
[04:25:52] [PASSED] 50 VFs
[04:25:52] [PASSED] 51 VFs
[04:25:52] [PASSED] 52 VFs
[04:25:52] [PASSED] 53 VFs
[04:25:52] [PASSED] 54 VFs
[04:25:52] [PASSED] 55 VFs
[04:25:52] [PASSED] 56 VFs
[04:25:52] [PASSED] 57 VFs
[04:25:52] [PASSED] 58 VFs
[04:25:52] [PASSED] 59 VFs
[04:25:52] [PASSED] 60 VFs
[04:25:52] [PASSED] 61 VFs
[04:25:52] [PASSED] 62 VFs
[04:25:52] [PASSED] 63 VFs
[04:25:52] ================= [PASSED] fair_doorbells ==================
[04:25:52] ======================== fair_ggtt ========================
[04:25:52] [PASSED] 1 VF
[04:25:52] [PASSED] 2 VFs
[04:25:52] [PASSED] 3 VFs
[04:25:52] [PASSED] 4 VFs
[04:25:52] [PASSED] 5 VFs
[04:25:52] [PASSED] 6 VFs
[04:25:52] [PASSED] 7 VFs
[04:25:52] [PASSED] 8 VFs
[04:25:52] [PASSED] 9 VFs
[04:25:52] [PASSED] 10 VFs
[04:25:52] [PASSED] 11 VFs
[04:25:52] [PASSED] 12 VFs
[04:25:52] [PASSED] 13 VFs
[04:25:52] [PASSED] 14 VFs
[04:25:52] [PASSED] 15 VFs
[04:25:52] [PASSED] 16 VFs
[04:25:52] [PASSED] 17 VFs
[04:25:52] [PASSED] 18 VFs
[04:25:52] [PASSED] 19 VFs
[04:25:52] [PASSED] 20 VFs
[04:25:52] [PASSED] 21 VFs
[04:25:52] [PASSED] 22 VFs
[04:25:52] [PASSED] 23 VFs
[04:25:52] [PASSED] 24 VFs
[04:25:52] [PASSED] 25 VFs
[04:25:52] [PASSED] 26 VFs
[04:25:52] [PASSED] 27 VFs
[04:25:52] [PASSED] 28 VFs
[04:25:52] [PASSED] 29 VFs
[04:25:52] [PASSED] 30 VFs
[04:25:52] [PASSED] 31 VFs
[04:25:52] [PASSED] 32 VFs
[04:25:52] [PASSED] 33 VFs
[04:25:52] [PASSED] 34 VFs
[04:25:52] [PASSED] 35 VFs
[04:25:52] [PASSED] 36 VFs
[04:25:52] [PASSED] 37 VFs
[04:25:52] [PASSED] 38 VFs
[04:25:52] [PASSED] 39 VFs
[04:25:52] [PASSED] 40 VFs
[04:25:52] [PASSED] 41 VFs
[04:25:52] [PASSED] 42 VFs
[04:25:52] [PASSED] 43 VFs
[04:25:52] [PASSED] 44 VFs
[04:25:52] [PASSED] 45 VFs
[04:25:52] [PASSED] 46 VFs
[04:25:52] [PASSED] 47 VFs
[04:25:52] [PASSED] 48 VFs
[04:25:52] [PASSED] 49 VFs
[04:25:52] [PASSED] 50 VFs
[04:25:52] [PASSED] 51 VFs
[04:25:52] [PASSED] 52 VFs
[04:25:52] [PASSED] 53 VFs
[04:25:52] [PASSED] 54 VFs
[04:25:52] [PASSED] 55 VFs
[04:25:52] [PASSED] 56 VFs
[04:25:52] [PASSED] 57 VFs
[04:25:52] [PASSED] 58 VFs
[04:25:52] [PASSED] 59 VFs
[04:25:52] [PASSED] 60 VFs
[04:25:52] [PASSED] 61 VFs
[04:25:52] [PASSED] 62 VFs
[04:25:52] [PASSED] 63 VFs
[04:25:52] ==================== [PASSED] fair_ggtt ====================
[04:25:52] ======================== fair_vram ========================
[04:25:52] [PASSED] 1 VF
[04:25:52] [PASSED] 2 VFs
[04:25:52] [PASSED] 3 VFs
[04:25:52] [PASSED] 4 VFs
[04:25:52] [PASSED] 5 VFs
[04:25:52] [PASSED] 6 VFs
[04:25:52] [PASSED] 7 VFs
[04:25:52] [PASSED] 8 VFs
[04:25:52] [PASSED] 9 VFs
[04:25:52] [PASSED] 10 VFs
[04:25:52] [PASSED] 11 VFs
[04:25:52] [PASSED] 12 VFs
[04:25:52] [PASSED] 13 VFs
[04:25:52] [PASSED] 14 VFs
[04:25:52] [PASSED] 15 VFs
[04:25:52] [PASSED] 16 VFs
[04:25:52] [PASSED] 17 VFs
[04:25:52] [PASSED] 18 VFs
[04:25:52] [PASSED] 19 VFs
[04:25:52] [PASSED] 20 VFs
[04:25:52] [PASSED] 21 VFs
[04:25:52] [PASSED] 22 VFs
[04:25:52] [PASSED] 23 VFs
[04:25:52] [PASSED] 24 VFs
[04:25:52] [PASSED] 25 VFs
[04:25:52] [PASSED] 26 VFs
[04:25:52] [PASSED] 27 VFs
[04:25:52] [PASSED] 28 VFs
[04:25:52] [PASSED] 29 VFs
[04:25:52] [PASSED] 30 VFs
[04:25:52] [PASSED] 31 VFs
[04:25:52] [PASSED] 32 VFs
[04:25:52] [PASSED] 33 VFs
[04:25:52] [PASSED] 34 VFs
[04:25:52] [PASSED] 35 VFs
[04:25:52] [PASSED] 36 VFs
[04:25:52] [PASSED] 37 VFs
[04:25:52] [PASSED] 38 VFs
[04:25:52] [PASSED] 39 VFs
[04:25:52] [PASSED] 40 VFs
[04:25:52] [PASSED] 41 VFs
[04:25:52] [PASSED] 42 VFs
[04:25:52] [PASSED] 43 VFs
[04:25:52] [PASSED] 44 VFs
[04:25:52] [PASSED] 45 VFs
[04:25:52] [PASSED] 46 VFs
[04:25:52] [PASSED] 47 VFs
[04:25:52] [PASSED] 48 VFs
[04:25:52] [PASSED] 49 VFs
[04:25:52] [PASSED] 50 VFs
[04:25:52] [PASSED] 51 VFs
[04:25:52] [PASSED] 52 VFs
[04:25:52] [PASSED] 53 VFs
[04:25:52] [PASSED] 54 VFs
[04:25:52] [PASSED] 55 VFs
[04:25:52] [PASSED] 56 VFs
[04:25:52] [PASSED] 57 VFs
[04:25:52] [PASSED] 58 VFs
[04:25:52] [PASSED] 59 VFs
[04:25:52] [PASSED] 60 VFs
[04:25:52] [PASSED] 61 VFs
[04:25:52] [PASSED] 62 VFs
[04:25:52] [PASSED] 63 VFs
[04:25:52] ==================== [PASSED] fair_vram ====================
[04:25:52] ================== [PASSED] pf_gt_config ===================
[04:25:52] ===================== lmtt (1 subtest) =====================
[04:25:52] ======================== test_ops =========================
[04:25:52] [PASSED] 2-level
[04:25:52] [PASSED] multi-level
[04:25:52] ==================== [PASSED] test_ops =====================
[04:25:52] ====================== [PASSED] lmtt =======================
[04:25:52] ================= sriov_packet (1 subtest) =================
[04:25:52] [PASSED] test_descriptor_init
[04:25:52] ================== [PASSED] sriov_packet ===================
[04:25:52] ================= pf_service (11 subtests) =================
[04:25:52] [PASSED] pf_negotiate_any
[04:25:52] [PASSED] pf_negotiate_base_match
[04:25:52] [PASSED] pf_negotiate_base_newer
[04:25:52] [PASSED] pf_negotiate_base_next
[04:25:52] [SKIPPED] pf_negotiate_base_older (no older minor)
[04:25:52] [PASSED] pf_negotiate_base_prev
[04:25:52] [PASSED] pf_negotiate_latest_match
[04:25:52] [PASSED] pf_negotiate_latest_newer
[04:25:52] [PASSED] pf_negotiate_latest_next
[04:25:52] [SKIPPED] pf_negotiate_latest_older (no older minor)
[04:25:52] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[04:25:52] =================== [PASSED] pf_service ====================
[04:25:52] ================= xe_guc_g2g (2 subtests) ==================
[04:25:52] ============== xe_live_guc_g2g_kunit_default ==============
[04:25:52] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[04:25:52] ============== xe_live_guc_g2g_kunit_allmem ===============
[04:25:52] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[04:25:52] =================== [SKIPPED] xe_guc_g2g ===================
[04:25:52] =================== xe_mocs (2 subtests) ===================
[04:25:52] ================ xe_live_mocs_kernel_kunit ================
[04:25:52] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[04:25:52] ================ xe_live_mocs_reset_kunit =================
[04:25:52] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[04:25:52] ==================== [SKIPPED] xe_mocs =====================
[04:25:52] ================= xe_migrate (3 subtests) ==================
[04:25:52] ================= xe_migrate_sanity_kunit =================
[04:25:52] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[04:25:52] ================== xe_validate_ccs_kunit ==================
[04:25:52] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[04:25:52] ============= xe_migrate_access_memory_kunit ==============
[04:25:52] ========= [SKIPPED] xe_migrate_access_memory_kunit =========
[04:25:52] =================== [SKIPPED] xe_migrate ===================
[04:25:52] ================== xe_dma_buf (1 subtest) ==================
[04:25:52] ==================== xe_dma_buf_kunit =====================
[04:25:52] ================ [SKIPPED] xe_dma_buf_kunit ================
[04:25:52] =================== [SKIPPED] xe_dma_buf ===================
[04:25:52] ================= xe_bo_shrink (1 subtest) =================
[04:25:52] =================== xe_bo_shrink_kunit ====================
[04:25:52] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[04:25:52] ================== [SKIPPED] xe_bo_shrink ==================
[04:25:52] ==================== xe_bo (2 subtests) ====================
[04:25:52] ================== xe_ccs_migrate_kunit ===================
[04:25:52] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[04:25:52] ==================== xe_bo_evict_kunit ====================
[04:25:52] =============== [SKIPPED] xe_bo_evict_kunit ================
[04:25:52] ===================== [SKIPPED] xe_bo ======================
[04:25:52] =================== xe_any (9 subtests) ====================
[04:25:52] [PASSED] test_to_xe
[04:25:52] [PASSED] test_to_dev
[04:25:52] [PASSED] test_to_pdev
[04:25:52] [PASSED] test_to_drm
[04:25:52] [PASSED] test_if_pdev
[04:25:52] [PASSED] test_if_xe
[04:25:52] [PASSED] test_if_tile
[04:25:52] [PASSED] test_if_gt
[04:25:52] [PASSED] test_to_id
[04:25:52] ===================== [PASSED] xe_any ======================
[04:25:52] ==================== args (13 subtests) ====================
[04:25:52] [PASSED] count_args_test
[04:25:52] [PASSED] call_args_example
[04:25:52] [PASSED] call_args_test
[04:25:52] [PASSED] drop_first_arg_example
[04:25:52] [PASSED] drop_first_arg_test
[04:25:52] [PASSED] first_arg_example
[04:25:52] [PASSED] first_arg_test
[04:25:52] [PASSED] last_arg_example
[04:25:52] [PASSED] last_arg_test
[04:25:52] [PASSED] pick_arg_example
[04:25:52] [PASSED] if_args_example
[04:25:52] [PASSED] if_args_test
[04:25:52] [PASSED] sep_comma_example
[04:25:52] ====================== [PASSED] args =======================
[04:25:52] =================== xe_pci (3 subtests) ====================
[04:25:52] ==================== check_graphics_ip ====================
[04:25:52] [PASSED] 12.00 Xe_LP
[04:25:52] [PASSED] 12.10 Xe_LP+
[04:25:52] [PASSED] 12.55 Xe_HPG
[04:25:52] [PASSED] 12.60 Xe_HPC
[04:25:52] [PASSED] 12.70 Xe_LPG
[04:25:52] [PASSED] 12.71 Xe_LPG
[04:25:52] [PASSED] 12.74 Xe_LPG+
[04:25:52] [PASSED] 20.01 Xe2_HPG
[04:25:52] [PASSED] 20.02 Xe2_HPG
[04:25:52] [PASSED] 20.04 Xe2_LPG
[04:25:52] [PASSED] 30.00 Xe3_LPG
[04:25:52] [PASSED] 30.01 Xe3_LPG
[04:25:52] [PASSED] 30.03 Xe3_LPG
[04:25:52] [PASSED] 30.04 Xe3_LPG
[04:25:52] [PASSED] 30.05 Xe3_LPG
[04:25:52] [PASSED] 35.10 Xe3p_LPG
[04:25:52] [PASSED] 35.11 Xe3p_XPC
[04:25:52] ================ [PASSED] check_graphics_ip ================
[04:25:52] ===================== check_media_ip ======================
[04:25:52] [PASSED] 12.00 Xe_M
[04:25:52] [PASSED] 12.55 Xe_HPM
[04:25:52] [PASSED] 13.00 Xe_LPM+
[04:25:52] [PASSED] 13.01 Xe2_HPM
[04:25:52] [PASSED] 20.00 Xe2_LPM
[04:25:52] [PASSED] 30.00 Xe3_LPM
[04:25:52] [PASSED] 30.02 Xe3_LPM
[04:25:52] [PASSED] 35.00 Xe3p_LPM
[04:25:52] [PASSED] 35.03 Xe3p_HPM
[04:25:52] ================= [PASSED] check_media_ip ==================
[04:25:52] =================== check_platform_desc ===================
[04:25:52] [PASSED] 0x9A60 (TIGERLAKE)
[04:25:52] [PASSED] 0x9A68 (TIGERLAKE)
[04:25:52] [PASSED] 0x9A70 (TIGERLAKE)
[04:25:52] [PASSED] 0x9A40 (TIGERLAKE)
[04:25:52] [PASSED] 0x9A49 (TIGERLAKE)
[04:25:52] [PASSED] 0x9A59 (TIGERLAKE)
[04:25:52] [PASSED] 0x9A78 (TIGERLAKE)
[04:25:52] [PASSED] 0x9AC0 (TIGERLAKE)
[04:25:52] [PASSED] 0x9AC9 (TIGERLAKE)
[04:25:52] [PASSED] 0x9AD9 (TIGERLAKE)
[04:25:52] [PASSED] 0x9AF8 (TIGERLAKE)
[04:25:52] [PASSED] 0x4C80 (ROCKETLAKE)
[04:25:52] [PASSED] 0x4C8A (ROCKETLAKE)
[04:25:52] [PASSED] 0x4C8B (ROCKETLAKE)
[04:25:52] [PASSED] 0x4C8C (ROCKETLAKE)
[04:25:52] [PASSED] 0x4C90 (ROCKETLAKE)
[04:25:52] [PASSED] 0x4C9A (ROCKETLAKE)
[04:25:52] [PASSED] 0x4680 (ALDERLAKE_S)
[04:25:52] [PASSED] 0x4682 (ALDERLAKE_S)
[04:25:52] [PASSED] 0x4688 (ALDERLAKE_S)
[04:25:52] [PASSED] 0x468A (ALDERLAKE_S)
[04:25:52] [PASSED] 0x468B (ALDERLAKE_S)
[04:25:52] [PASSED] 0x4690 (ALDERLAKE_S)
[04:25:52] [PASSED] 0x4692 (ALDERLAKE_S)
[04:25:52] [PASSED] 0x4693 (ALDERLAKE_S)
[04:25:52] [PASSED] 0x46A0 (ALDERLAKE_P)
[04:25:52] [PASSED] 0x46A1 (ALDERLAKE_P)
[04:25:52] [PASSED] 0x46A2 (ALDERLAKE_P)
[04:25:52] [PASSED] 0x46A3 (ALDERLAKE_P)
[04:25:52] [PASSED] 0x46A6 (ALDERLAKE_P)
[04:25:52] [PASSED] 0x46A8 (ALDERLAKE_P)
[04:25:52] [PASSED] 0x46AA (ALDERLAKE_P)
[04:25:52] [PASSED] 0x462A (ALDERLAKE_P)
[04:25:52] [PASSED] 0x4626 (ALDERLAKE_P)
[04:25:52] [PASSED] 0x4628 (ALDERLAKE_P)
[04:25:52] [PASSED] 0x46B0 (ALDERLAKE_P)
[04:25:52] [PASSED] 0x46B1 (ALDERLAKE_P)
[04:25:52] [PASSED] 0x46B2 (ALDERLAKE_P)
[04:25:52] [PASSED] 0x46B3 (ALDERLAKE_P)
[04:25:52] [PASSED] 0x46C0 (ALDERLAKE_P)
[04:25:52] [PASSED] 0x46C1 (ALDERLAKE_P)
[04:25:52] [PASSED] 0x46C2 (ALDERLAKE_P)
[04:25:52] [PASSED] 0x46C3 (ALDERLAKE_P)
[04:25:52] [PASSED] 0x46D0 (ALDERLAKE_N)
[04:25:52] [PASSED] 0x46D1 (ALDERLAKE_N)
[04:25:52] [PASSED] 0x46D2 (ALDERLAKE_N)
[04:25:52] [PASSED] 0x46D3 (ALDERLAKE_N)
[04:25:52] [PASSED] 0x46D4 (ALDERLAKE_N)
[04:25:52] [PASSED] 0xA721 (ALDERLAKE_P)
[04:25:52] [PASSED] 0xA7A1 (ALDERLAKE_P)
[04:25:52] [PASSED] 0xA7A9 (ALDERLAKE_P)
[04:25:52] [PASSED] 0xA7AC (ALDERLAKE_P)
[04:25:52] [PASSED] 0xA7AD (ALDERLAKE_P)
[04:25:52] [PASSED] 0xA720 (ALDERLAKE_P)
[04:25:52] [PASSED] 0xA7A0 (ALDERLAKE_P)
[04:25:52] [PASSED] 0xA7A8 (ALDERLAKE_P)
[04:25:52] [PASSED] 0xA7AA (ALDERLAKE_P)
[04:25:52] [PASSED] 0xA7AB (ALDERLAKE_P)
[04:25:52] [PASSED] 0xA780 (ALDERLAKE_S)
[04:25:52] [PASSED] 0xA781 (ALDERLAKE_S)
[04:25:52] [PASSED] 0xA782 (ALDERLAKE_S)
[04:25:52] [PASSED] 0xA783 (ALDERLAKE_S)
[04:25:52] [PASSED] 0xA788 (ALDERLAKE_S)
[04:25:52] [PASSED] 0xA789 (ALDERLAKE_S)
[04:25:52] [PASSED] 0xA78A (ALDERLAKE_S)
[04:25:52] [PASSED] 0xA78B (ALDERLAKE_S)
[04:25:52] [PASSED] 0x4905 (DG1)
[04:25:52] [PASSED] 0x4906 (DG1)
[04:25:52] [PASSED] 0x4907 (DG1)
[04:25:52] [PASSED] 0x4908 (DG1)
[04:25:52] [PASSED] 0x4909 (DG1)
[04:25:52] [PASSED] 0x56C0 (DG2)
[04:25:52] [PASSED] 0x56C2 (DG2)
[04:25:52] [PASSED] 0x56C1 (DG2)
[04:25:52] [PASSED] 0x7D51 (METEORLAKE)
[04:25:52] [PASSED] 0x7DD1 (METEORLAKE)
[04:25:52] [PASSED] 0x7D41 (METEORLAKE)
[04:25:52] [PASSED] 0x7D67 (METEORLAKE)
[04:25:52] [PASSED] 0xB640 (METEORLAKE)
[04:25:52] [PASSED] 0x56A0 (DG2)
[04:25:52] [PASSED] 0x56A1 (DG2)
[04:25:52] [PASSED] 0x56A2 (DG2)
[04:25:52] [PASSED] 0x56BE (DG2)
[04:25:52] [PASSED] 0x56BF (DG2)
[04:25:52] [PASSED] 0x5690 (DG2)
[04:25:52] [PASSED] 0x5691 (DG2)
[04:25:52] [PASSED] 0x5692 (DG2)
[04:25:52] [PASSED] 0x56A5 (DG2)
[04:25:52] [PASSED] 0x56A6 (DG2)
[04:25:52] [PASSED] 0x56B0 (DG2)
[04:25:52] [PASSED] 0x56B1 (DG2)
[04:25:52] [PASSED] 0x56BA (DG2)
[04:25:52] [PASSED] 0x56BB (DG2)
[04:25:52] [PASSED] 0x56BC (DG2)
[04:25:52] [PASSED] 0x56BD (DG2)
[04:25:52] [PASSED] 0x5693 (DG2)
[04:25:52] [PASSED] 0x5694 (DG2)
[04:25:52] [PASSED] 0x5695 (DG2)
[04:25:52] [PASSED] 0x56A3 (DG2)
[04:25:52] [PASSED] 0x56A4 (DG2)
[04:25:52] [PASSED] 0x56B2 (DG2)
[04:25:52] [PASSED] 0x56B3 (DG2)
[04:25:52] [PASSED] 0x5696 (DG2)
[04:25:52] [PASSED] 0x5697 (DG2)
[04:25:52] [PASSED] 0xB69 (PVC)
[04:25:52] [PASSED] 0xB6E (PVC)
[04:25:52] [PASSED] 0xBD4 (PVC)
[04:25:52] [PASSED] 0xBD5 (PVC)
[04:25:52] [PASSED] 0xBD6 (PVC)
[04:25:52] [PASSED] 0xBD7 (PVC)
[04:25:52] [PASSED] 0xBD8 (PVC)
[04:25:52] [PASSED] 0xBD9 (PVC)
[04:25:52] [PASSED] 0xBDA (PVC)
[04:25:52] [PASSED] 0xBDB (PVC)
[04:25:52] [PASSED] 0xBE0 (PVC)
[04:25:52] [PASSED] 0xBE1 (PVC)
[04:25:52] [PASSED] 0xBE5 (PVC)
[04:25:52] [PASSED] 0x7D40 (METEORLAKE)
[04:25:52] [PASSED] 0x7D45 (METEORLAKE)
[04:25:52] [PASSED] 0x7D55 (METEORLAKE)
[04:25:52] [PASSED] 0x7D60 (METEORLAKE)
[04:25:52] [PASSED] 0x7DD5 (METEORLAKE)
[04:25:52] [PASSED] 0x6420 (LUNARLAKE)
[04:25:52] [PASSED] 0x64A0 (LUNARLAKE)
[04:25:52] [PASSED] 0x64B0 (LUNARLAKE)
[04:25:52] [PASSED] 0xE202 (BATTLEMAGE)
[04:25:52] [PASSED] 0xE209 (BATTLEMAGE)
[04:25:52] [PASSED] 0xE20B (BATTLEMAGE)
[04:25:52] [PASSED] 0xE20C (BATTLEMAGE)
[04:25:52] [PASSED] 0xE20D (BATTLEMAGE)
[04:25:52] [PASSED] 0xE210 (BATTLEMAGE)
[04:25:52] [PASSED] 0xE211 (BATTLEMAGE)
[04:25:52] [PASSED] 0xE212 (BATTLEMAGE)
[04:25:52] [PASSED] 0xE216 (BATTLEMAGE)
[04:25:52] [PASSED] 0xE220 (BATTLEMAGE)
[04:25:52] [PASSED] 0xE221 (BATTLEMAGE)
[04:25:52] [PASSED] 0xE222 (BATTLEMAGE)
[04:25:52] [PASSED] 0xE223 (BATTLEMAGE)
[04:25:52] [PASSED] 0xB080 (PANTHERLAKE)
[04:25:52] [PASSED] 0xB081 (PANTHERLAKE)
[04:25:52] [PASSED] 0xB082 (PANTHERLAKE)
[04:25:52] [PASSED] 0xB083 (PANTHERLAKE)
[04:25:52] [PASSED] 0xB084 (PANTHERLAKE)
[04:25:52] [PASSED] 0xB085 (PANTHERLAKE)
[04:25:52] [PASSED] 0xB086 (PANTHERLAKE)
[04:25:52] [PASSED] 0xB087 (PANTHERLAKE)
[04:25:52] [PASSED] 0xB08F (PANTHERLAKE)
[04:25:52] [PASSED] 0xB090 (PANTHERLAKE)
[04:25:52] [PASSED] 0xB0A0 (PANTHERLAKE)
[04:25:52] [PASSED] 0xB0A1 (PANTHERLAKE)
[04:25:52] [PASSED] 0xB0B0 (PANTHERLAKE)
[04:25:52] [PASSED] 0xFD80 (PANTHERLAKE)
[04:25:52] [PASSED] 0xFD81 (PANTHERLAKE)
[04:25:52] [PASSED] 0xD740 (NOVALAKE_S)
[04:25:52] [PASSED] 0xD741 (NOVALAKE_S)
[04:25:52] [PASSED] 0xD742 (NOVALAKE_S)
[04:25:52] [PASSED] 0xD743 (NOVALAKE_S)
[04:25:52] [PASSED] 0xD745 (NOVALAKE_S)
[04:25:52] [PASSED] 0xD74A (NOVALAKE_S)
[04:25:52] [PASSED] 0xD74B (NOVALAKE_S)
[04:25:52] [PASSED] 0x674C (CRESCENTISLAND)
[04:25:52] [PASSED] 0x674D (CRESCENTISLAND)
[04:25:52] [PASSED] 0x674E (CRESCENTISLAND)
[04:25:52] [PASSED] 0x674F (CRESCENTISLAND)
[04:25:52] [PASSED] 0x6750 (CRESCENTISLAND)
[04:25:52] [PASSED] 0x6751 (CRESCENTISLAND)
[04:25:52] [PASSED] 0xD750 (NOVALAKE_P)
[04:25:52] [PASSED] 0xD751 (NOVALAKE_P)
[04:25:52] [PASSED] 0xD752 (NOVALAKE_P)
[04:25:52] [PASSED] 0xD753 (NOVALAKE_P)
[04:25:52] [PASSED] 0xD754 (NOVALAKE_P)
[04:25:52] [PASSED] 0xD755 (NOVALAKE_P)
[04:25:52] [PASSED] 0xD756 (NOVALAKE_P)
[04:25:52] [PASSED] 0xD757 (NOVALAKE_P)
[04:25:52] [PASSED] 0xD75F (NOVALAKE_P)
[04:25:52] =============== [PASSED] check_platform_desc ===============
[04:25:52] ===================== [PASSED] xe_pci ======================
[04:25:52] ============= xe_rtp_tables_test (5 subtests) ==============
[04:25:52] ================== xe_rtp_table_gt_test ===================
[04:25:52] [PASSED] gt_was/14011060649
[04:25:52] [PASSED] gt_was/14011059788
[04:25:52] [PASSED] gt_was/14015795083
[04:25:52] [PASSED] gt_was/16021867713
[04:25:52] [PASSED] gt_was/14019449301
[04:25:52] [PASSED] gt_was/16028005424
[04:25:52] [PASSED] gt_was/14026578760
[04:25:52] [PASSED] gt_was/1409420604
[04:25:52] [PASSED] gt_was/1408615072
[04:25:52] [PASSED] gt_was/22010523718
[04:25:52] [PASSED] gt_was/14011006942
[04:25:52] [PASSED] gt_was/14014830051
[04:25:52] [PASSED] gt_was/18018781329
[04:25:52] [PASSED] gt_was/1509235366
[04:25:52] [PASSED] gt_was/18018781329
[04:25:52] [PASSED] gt_was/16016694945
[04:25:52] [PASSED] gt_was/14018575942
[04:25:52] [PASSED] gt_was/22016670082
[04:25:52] [PASSED] gt_was/22016670082
[04:25:52] [PASSED] gt_was/14017421178
[04:25:52] [PASSED] gt_was/16025250150
[04:25:52] [PASSED] gt_was/14021871409
[04:25:52] [PASSED] gt_was/16021865536
[04:25:52] [PASSED] gt_was/14021486841
[04:25:52] [PASSED] gt_was/14025160223
[04:25:52] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[04:25:52] [PASSED] gt_was/14025635424
[04:25:52] [PASSED] gt_was/16028005424
[04:25:52] ============== [PASSED] xe_rtp_table_gt_test ===============
[04:25:52] ================== xe_rtp_table_gt_test ===================
[04:25:52] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[04:25:52] [PASSED] gt_tunings/Tuning: 32B Access Enable
[04:25:52] [PASSED] gt_tunings/Tuning: L3 cache
[04:25:52] [PASSED] gt_tunings/Tuning: L3 cache - media
[04:25:52] [PASSED] gt_tunings/Tuning: Compression Overfetch
[04:25:52] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[04:25:52] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[04:25:52] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[04:25:52] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[04:25:52] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[04:25:52] [PASSED] gt_tunings/Tuning: Stateless compression control
[04:25:52] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[04:25:52] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[04:25:52] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[04:25:52] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[04:25:52] [PASSED] gt_tunings/Tuning: Force All Non-Compressible Memory Reads to be 256B Overfetches
[04:25:52] ============== [PASSED] xe_rtp_table_gt_test ===============
[04:25:52] ================== xe_rtp_table_oob_test ==================
[04:25:52] [PASSED] oob_was/1607983814
[04:25:52] [PASSED] oob_was/16010904313
[04:25:52] [PASSED] oob_was/18022495364
[04:25:52] [PASSED] oob_was/22012773006
[04:25:52] [PASSED] oob_was/14014475959
[04:25:52] [PASSED] oob_was/22011391025
[04:25:52] [PASSED] oob_was/22012727170
[04:25:52] [PASSED] oob_was/22012727685
[04:25:52] [PASSED] oob_was/22016596838
[04:25:52] [PASSED] oob_was/18020744125
[04:25:52] [PASSED] oob_was/1409600907
[04:25:52] [PASSED] oob_was/22014953428
[04:25:52] [PASSED] oob_was/16017236439
[04:25:52] [PASSED] oob_was/14019821291
[04:25:52] [PASSED] oob_was/14015076503
[04:25:52] [PASSED] oob_was/22016122933
[04:25:52] [PASSED] oob_was/14018913170
[04:25:52] [PASSED] oob_was/14018094691
[04:25:52] [PASSED] oob_was/18024947630
[04:25:52] [PASSED] oob_was/16022287689
[04:25:52] [PASSED] oob_was/13011645652
[04:25:52] [PASSED] oob_was/14022293748
[04:25:52] [PASSED] oob_was/22019794406
[04:25:52] [PASSED] oob_was/22019338487
[04:25:52] [PASSED] oob_was/16023588340
[04:25:52] [PASSED] oob_was/14019789679
[04:25:52] [PASSED] oob_was/14022866841
[04:25:52] [PASSED] oob_was/16021333562
[04:25:52] [PASSED] oob_was/14016712196
[04:25:52] [PASSED] oob_was/14015568240
[04:25:52] [PASSED] oob_was/18013179988
[04:25:52] [PASSED] oob_was/1508761755
[04:25:52] [PASSED] oob_was/16023105232
[04:25:52] [PASSED] oob_was/16026508708
[04:25:52] [PASSED] oob_was/14020001231
[04:25:52] [PASSED] oob_was/16023683509
[04:25:52] [PASSED] oob_was/14025515070
[04:25:52] [PASSED] oob_was/15015404425_disable
[04:25:52] [PASSED] oob_was/16026007364
[04:25:52] [PASSED] oob_was/14020316580
[04:25:52] [PASSED] oob_was/14025883347
[04:25:52] [PASSED] oob_was/16029380221
[04:25:52] [PASSED] oob_was/22022079272
[04:25:52] [PASSED] oob_was/16029897822
[04:25:52] [PASSED] oob_was/14027054324
[04:25:52] [PASSED] oob_was/14025941587
[04:25:52] [PASSED] oob_was/16030224309
[04:25:52] ============== [PASSED] xe_rtp_table_oob_test ==============
[04:25:52] ================ xe_rtp_table_dev_oob_test ================
[04:25:52] [PASSED] device_oob_was/22010954014
[04:25:52] [PASSED] device_oob_was/15015404425
[04:25:52] [PASSED] device_oob_was/22019338487_display
[04:25:52] [PASSED] device_oob_was/14022085890
[04:25:52] [PASSED] device_oob_was/14026539277
[04:25:52] [PASSED] device_oob_was/14026633728
[04:25:52] [PASSED] device_oob_was/14026746987
[04:25:52] [PASSED] device_oob_was/14026779378
[04:25:52] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[04:25:52] ========== xe_rtp_table_missing_upper_bound_test ==========
[04:25:52] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[04:25:52] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[04:25:52] [PASSED] register_whitelist/1806527549
[04:25:52] [PASSED] register_whitelist/allow_read_ctx_timestamp
[04:25:52] [PASSED] register_whitelist/allow_read_queue_timestamp
[04:25:52] [PASSED] register_whitelist/16014440446
[04:25:52] [PASSED] register_whitelist/16017236439
[04:25:52] [PASSED] register_whitelist/16020183090
[04:25:52] [PASSED] register_whitelist/14024997852
[04:25:52] [PASSED] register_whitelist/14024997852
[04:25:52] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[04:25:52] =============== [PASSED] xe_rtp_tables_test ================
[04:25:52] =================== xe_rtp (3 subtests) ====================
[04:25:52] =================== xe_rtp_rules_tests ====================
[04:25:52] [PASSED] no
[04:25:52] [PASSED] yes
[04:25:52] [PASSED] no-and-no
[04:25:52] [PASSED] no-and-yes
[04:25:52] [PASSED] yes-and-no
[04:25:52] [PASSED] yes-and-yes
[04:25:52] [PASSED] no-or-no
[04:25:52] [PASSED] no-or-yes
[04:25:52] [PASSED] yes-or-no
[04:25:52] [PASSED] yes-or-yes
[04:25:52] [PASSED] no-yes-or-yes-no
[04:25:52] [PASSED] no-yes-or-yes-yes
[04:25:52] [PASSED] yes-yes-or-no-yes
[04:25:52] [PASSED] yes-yes-or-yes-yes
[04:25:52] [PASSED] no-no-or-yes-or-no
[04:25:52] [PASSED] or
[04:25:52] [PASSED] or-yes
[04:25:52] [PASSED] or-no
[04:25:52] [PASSED] yes-or
[04:25:52] [PASSED] no-or
[04:25:52] [PASSED] no-or-or-yes
[04:25:52] [PASSED] yes-or-or-no
[04:25:52] [PASSED] no-or-or-no
[04:25:52] [PASSED] missing-context-engine-class
[04:25:52] [PASSED] missing-context-engine-class-or-yes
[04:25:52] [PASSED] missing-context-engine-class-or-or-yes
[04:25:52] =============== [PASSED] xe_rtp_rules_tests ================
[04:25:52] =============== xe_rtp_process_to_sr_tests ================
[04:25:52] [PASSED] coalesce-same-reg
[04:25:52] [PASSED] coalesce-same-reg-literal-and-func
[04:25:52] [PASSED] no-match-no-add
[04:25:52] [PASSED] two-regs-two-entries
[04:25:52] [PASSED] clr-one-set-other
[04:25:52] [PASSED] set-field
[04:25:52] [PASSED] conflict-duplicate
[04:25:52] [PASSED] conflict-not-disjoint
[04:25:52] [PASSED] conflict-not-disjoint-literal-and-func
[04:25:52] [PASSED] conflict-reg-type
[04:25:52] [PASSED] bad-mcr-reg-forced-to-regular
[04:25:52] [PASSED] bad-regular-reg-forced-to-mcr
[04:25:52] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[04:25:52] ================== xe_rtp_process_tests ===================
[04:25:52] [PASSED] active1
[04:25:52] [PASSED] active2
[04:25:52] [PASSED] active-inactive
[04:25:52] [PASSED] inactive-active
[04:25:52] [PASSED] inactive-active-inactive
[04:25:52] [PASSED] inactive-inactive-inactive
[04:25:52] ============== [PASSED] xe_rtp_process_tests ===============
[04:25:52] ===================== [PASSED] xe_rtp ======================
[04:25:52] ==================== xe_wa (1 subtest) =====================
[04:25:52] ======================== xe_wa_gt =========================
[04:25:52] [PASSED] TIGERLAKE B0
[04:25:52] [PASSED] DG1 A0
[04:25:52] [PASSED] DG1 B0
[04:25:52] [PASSED] ALDERLAKE_S A0
[04:25:52] [PASSED] ALDERLAKE_S B0
[04:25:52] [PASSED] ALDERLAKE_S C0
[04:25:52] [PASSED] ALDERLAKE_S D0
[04:25:52] [PASSED] ALDERLAKE_P A0
[04:25:52] [PASSED] ALDERLAKE_P B0
[04:25:52] [PASSED] ALDERLAKE_P C0
[04:25:52] [PASSED] ALDERLAKE_S RPLS D0
[04:25:52] [PASSED] ALDERLAKE_P RPLU E0
[04:25:52] [PASSED] DG2 G10 C0
[04:25:52] [PASSED] DG2 G11 B1
[04:25:52] [PASSED] DG2 G12 A1
[04:25:52] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[04:25:52] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[04:25:52] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[04:25:52] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[04:25:52] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[04:25:52] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[04:25:52] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[04:25:52] ==================== [PASSED] xe_wa_gt =====================
[04:25:52] ====================== [PASSED] xe_wa ======================
[04:25:52] ============================================================
[04:25:52] Testing complete. Ran 838 tests: passed: 809, skipped: 29
[04:25:52] Elapsed time: 41.370s total, 1.874s configuring, 38.730s building, 0.726s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[04:25:52] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:25:54] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:26:19] Starting KUnit Kernel (1/1)...
[04:26:19] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:26:19] ============ drm_test_pick_cmdline (2 subtests) ============
[04:26:19] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[04:26:19] =============== drm_test_pick_cmdline_named ===============
[04:26:19] [PASSED] NTSC
[04:26:19] [PASSED] NTSC-J
[04:26:19] [PASSED] PAL
[04:26:19] [PASSED] PAL-M
[04:26:19] =========== [PASSED] drm_test_pick_cmdline_named ===========
[04:26:19] ============== [PASSED] drm_test_pick_cmdline ==============
[04:26:19] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[04:26:19] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[04:26:19] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[04:26:19] =========== drm_validate_clone_mode (2 subtests) ===========
[04:26:19] ============== drm_test_check_in_clone_mode ===============
[04:26:19] [PASSED] in_clone_mode
[04:26:19] [PASSED] not_in_clone_mode
[04:26:19] ========== [PASSED] drm_test_check_in_clone_mode ===========
[04:26:19] =============== drm_test_check_valid_clones ===============
[04:26:19] [PASSED] not_in_clone_mode
[04:26:19] [PASSED] valid_clone
[04:26:19] [PASSED] invalid_clone
[04:26:19] =========== [PASSED] drm_test_check_valid_clones ===========
[04:26:19] ============= [PASSED] drm_validate_clone_mode =============
[04:26:19] ============= drm_validate_modeset (1 subtest) =============
[04:26:19] [PASSED] drm_test_check_connector_changed_modeset
[04:26:19] ============== [PASSED] drm_validate_modeset ===============
[04:26:19] ====== drm_test_bridge_get_current_state (1 subtest) =======
[04:26:19] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[04:26:19] ======== [PASSED] drm_test_bridge_get_current_state ========
[04:26:19] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[04:26:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[04:26:19] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[04:26:19] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[04:26:19] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[04:26:19] ============== drm_bridge_alloc (2 subtests) ===============
[04:26:19] [PASSED] drm_test_drm_bridge_alloc_basic
[04:26:19] [PASSED] drm_test_drm_bridge_alloc_get_put
[04:26:19] ================ [PASSED] drm_bridge_alloc =================
[04:26:19] ============= drm_bridge_bus_fmt (5 subtests) ==============
[04:26:19] [PASSED] drm_test_bridge_rgb_yuv_rgb
[04:26:19] [PASSED] drm_test_bridge_must_convert_to_yuv444
[04:26:19] [PASSED] drm_test_bridge_hdmi_auto_rgb
[04:26:19] [PASSED] drm_test_bridge_auto_first
[04:26:19] [PASSED] drm_test_bridge_rgb_yuv_no_path
[04:26:19] =============== [PASSED] drm_bridge_bus_fmt ================
[04:26:19] ============= drm_cmdline_parser (40 subtests) =============
[04:26:19] [PASSED] drm_test_cmdline_force_d_only
[04:26:19] [PASSED] drm_test_cmdline_force_D_only_dvi
[04:26:19] [PASSED] drm_test_cmdline_force_D_only_hdmi
[04:26:19] [PASSED] drm_test_cmdline_force_D_only_not_digital
[04:26:19] [PASSED] drm_test_cmdline_force_e_only
[04:26:19] [PASSED] drm_test_cmdline_res
[04:26:19] [PASSED] drm_test_cmdline_res_vesa
[04:26:19] [PASSED] drm_test_cmdline_res_vesa_rblank
[04:26:19] [PASSED] drm_test_cmdline_res_rblank
[04:26:19] [PASSED] drm_test_cmdline_res_bpp
[04:26:19] [PASSED] drm_test_cmdline_res_refresh
[04:26:19] [PASSED] drm_test_cmdline_res_bpp_refresh
[04:26:19] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[04:26:19] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[04:26:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[04:26:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[04:26:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[04:26:19] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[04:26:19] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[04:26:19] [PASSED] drm_test_cmdline_res_margins_force_on
[04:26:19] [PASSED] drm_test_cmdline_res_vesa_margins
[04:26:19] [PASSED] drm_test_cmdline_name
[04:26:19] [PASSED] drm_test_cmdline_name_bpp
[04:26:19] [PASSED] drm_test_cmdline_name_option
[04:26:19] [PASSED] drm_test_cmdline_name_bpp_option
[04:26:19] [PASSED] drm_test_cmdline_rotate_0
[04:26:19] [PASSED] drm_test_cmdline_rotate_90
[04:26:19] [PASSED] drm_test_cmdline_rotate_180
[04:26:19] [PASSED] drm_test_cmdline_rotate_270
[04:26:19] [PASSED] drm_test_cmdline_hmirror
[04:26:19] [PASSED] drm_test_cmdline_vmirror
[04:26:19] [PASSED] drm_test_cmdline_margin_options
[04:26:19] [PASSED] drm_test_cmdline_multiple_options
[04:26:19] [PASSED] drm_test_cmdline_bpp_extra_and_option
[04:26:19] [PASSED] drm_test_cmdline_extra_and_option
[04:26:19] [PASSED] drm_test_cmdline_freestanding_options
[04:26:19] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[04:26:19] [PASSED] drm_test_cmdline_panel_orientation
[04:26:19] ================ drm_test_cmdline_invalid =================
[04:26:19] [PASSED] margin_only
[04:26:19] [PASSED] interlace_only
[04:26:19] [PASSED] res_missing_x
[04:26:19] [PASSED] res_missing_y
[04:26:19] [PASSED] res_bad_y
[04:26:19] [PASSED] res_missing_y_bpp
[04:26:19] [PASSED] res_bad_bpp
[04:26:19] [PASSED] res_bad_refresh
[04:26:19] [PASSED] res_bpp_refresh_force_on_off
[04:26:19] [PASSED] res_invalid_mode
[04:26:19] [PASSED] res_bpp_wrong_place_mode
[04:26:19] [PASSED] name_bpp_refresh
[04:26:19] [PASSED] name_refresh
[04:26:19] [PASSED] name_refresh_wrong_mode
[04:26:19] [PASSED] name_refresh_invalid_mode
[04:26:19] [PASSED] rotate_multiple
[04:26:19] [PASSED] rotate_invalid_val
[04:26:19] [PASSED] rotate_truncated
[04:26:19] [PASSED] invalid_option
[04:26:19] [PASSED] invalid_tv_option
[04:26:19] [PASSED] truncated_tv_option
[04:26:19] ============ [PASSED] drm_test_cmdline_invalid =============
[04:26:19] =============== drm_test_cmdline_tv_options ===============
[04:26:19] [PASSED] NTSC
[04:26:19] [PASSED] NTSC_443
[04:26:19] [PASSED] NTSC_J
[04:26:19] [PASSED] PAL
[04:26:19] [PASSED] PAL_M
[04:26:19] [PASSED] PAL_N
[04:26:19] [PASSED] SECAM
[04:26:19] [PASSED] MONO_525
[04:26:19] [PASSED] MONO_625
[04:26:19] =========== [PASSED] drm_test_cmdline_tv_options ===========
[04:26:19] =============== [PASSED] drm_cmdline_parser ================
[04:26:19] ========== drmm_connector_hdmi_init (20 subtests) ==========
[04:26:19] [PASSED] drm_test_connector_hdmi_init_valid
[04:26:19] [PASSED] drm_test_connector_hdmi_init_bpc_8
[04:26:19] [PASSED] drm_test_connector_hdmi_init_bpc_10
[04:26:19] [PASSED] drm_test_connector_hdmi_init_bpc_12
[04:26:19] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[04:26:19] [PASSED] drm_test_connector_hdmi_init_bpc_null
[04:26:19] [PASSED] drm_test_connector_hdmi_init_formats_empty
[04:26:19] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[04:26:19] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[04:26:19] [PASSED] supported_formats=0x9 yuv420_allowed=1
[04:26:19] [PASSED] supported_formats=0x9 yuv420_allowed=0
[04:26:19] [PASSED] supported_formats=0x5 yuv420_allowed=1
[04:26:19] [PASSED] supported_formats=0x5 yuv420_allowed=0
[04:26:19] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[04:26:19] [PASSED] drm_test_connector_hdmi_init_null_ddc
[04:26:19] [PASSED] drm_test_connector_hdmi_init_null_product
[04:26:19] [PASSED] drm_test_connector_hdmi_init_null_vendor
[04:26:19] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[04:26:19] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[04:26:19] [PASSED] drm_test_connector_hdmi_init_product_valid
[04:26:19] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[04:26:19] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[04:26:19] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[04:26:19] ========= drm_test_connector_hdmi_init_type_valid =========
[04:26:19] [PASSED] HDMI-A
[04:26:19] [PASSED] HDMI-B
[04:26:19] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[04:26:19] ======== drm_test_connector_hdmi_init_type_invalid ========
[04:26:19] [PASSED] Unknown
[04:26:19] [PASSED] VGA
[04:26:19] [PASSED] DVI-I
[04:26:19] [PASSED] DVI-D
[04:26:19] [PASSED] DVI-A
[04:26:19] [PASSED] Composite
[04:26:19] [PASSED] SVIDEO
[04:26:19] [PASSED] LVDS
[04:26:19] [PASSED] Component
[04:26:19] [PASSED] DIN
[04:26:19] [PASSED] DP
[04:26:19] [PASSED] TV
[04:26:19] [PASSED] eDP
[04:26:19] [PASSED] Virtual
[04:26:19] [PASSED] DSI
[04:26:19] [PASSED] DPI
[04:26:19] [PASSED] Writeback
[04:26:19] [PASSED] SPI
[04:26:19] [PASSED] USB
[04:26:19] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[04:26:19] ============ [PASSED] drmm_connector_hdmi_init =============
[04:26:19] ============= drmm_connector_init (3 subtests) =============
[04:26:19] [PASSED] drm_test_drmm_connector_init
[04:26:19] [PASSED] drm_test_drmm_connector_init_null_ddc
[04:26:19] ========= drm_test_drmm_connector_init_type_valid =========
[04:26:19] [PASSED] Unknown
[04:26:19] [PASSED] VGA
[04:26:19] [PASSED] DVI-I
[04:26:19] [PASSED] DVI-D
[04:26:19] [PASSED] DVI-A
[04:26:19] [PASSED] Composite
[04:26:19] [PASSED] SVIDEO
[04:26:19] [PASSED] LVDS
[04:26:19] [PASSED] Component
[04:26:19] [PASSED] DIN
[04:26:19] [PASSED] DP
[04:26:19] [PASSED] HDMI-A
[04:26:19] [PASSED] HDMI-B
[04:26:19] [PASSED] TV
[04:26:19] [PASSED] eDP
[04:26:19] [PASSED] Virtual
[04:26:19] [PASSED] DSI
[04:26:19] [PASSED] DPI
[04:26:19] [PASSED] Writeback
[04:26:19] [PASSED] SPI
[04:26:19] [PASSED] USB
[04:26:19] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[04:26:19] =============== [PASSED] drmm_connector_init ===============
[04:26:19] ========= drm_connector_dynamic_init (6 subtests) ==========
[04:26:19] [PASSED] drm_test_drm_connector_dynamic_init
[04:26:19] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[04:26:19] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[04:26:19] [PASSED] drm_test_drm_connector_dynamic_init_properties
[04:26:19] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[04:26:19] [PASSED] Unknown
[04:26:19] [PASSED] VGA
[04:26:19] [PASSED] DVI-I
[04:26:19] [PASSED] DVI-D
[04:26:19] [PASSED] DVI-A
[04:26:19] [PASSED] Composite
[04:26:19] [PASSED] SVIDEO
[04:26:19] [PASSED] LVDS
[04:26:19] [PASSED] Component
[04:26:19] [PASSED] DIN
[04:26:19] [PASSED] DP
[04:26:19] [PASSED] HDMI-A
[04:26:19] [PASSED] HDMI-B
[04:26:19] [PASSED] TV
[04:26:19] [PASSED] eDP
[04:26:19] [PASSED] Virtual
[04:26:19] [PASSED] DSI
[04:26:19] [PASSED] DPI
[04:26:19] [PASSED] Writeback
[04:26:19] [PASSED] SPI
[04:26:19] [PASSED] USB
[04:26:19] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[04:26:19] ======== drm_test_drm_connector_dynamic_init_name =========
[04:26:19] [PASSED] Unknown
[04:26:19] [PASSED] VGA
[04:26:19] [PASSED] DVI-I
[04:26:19] [PASSED] DVI-D
[04:26:19] [PASSED] DVI-A
[04:26:19] [PASSED] Composite
[04:26:19] [PASSED] SVIDEO
[04:26:19] [PASSED] LVDS
[04:26:19] [PASSED] Component
[04:26:19] [PASSED] DIN
[04:26:19] [PASSED] DP
[04:26:19] [PASSED] HDMI-A
[04:26:19] [PASSED] HDMI-B
[04:26:19] [PASSED] TV
[04:26:19] [PASSED] eDP
[04:26:19] [PASSED] Virtual
[04:26:19] [PASSED] DSI
[04:26:19] [PASSED] DPI
[04:26:19] [PASSED] Writeback
[04:26:19] [PASSED] SPI
[04:26:19] [PASSED] USB
[04:26:19] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[04:26:19] =========== [PASSED] drm_connector_dynamic_init ============
[04:26:19] ==== drm_connector_dynamic_register_early (4 subtests) =====
[04:26:19] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[04:26:19] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[04:26:19] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[04:26:19] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[04:26:19] ====== [PASSED] drm_connector_dynamic_register_early =======
[04:26:19] ======= drm_connector_dynamic_register (7 subtests) ========
[04:26:19] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[04:26:19] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[04:26:19] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[04:26:19] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[04:26:19] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[04:26:19] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[04:26:19] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[04:26:19] ========= [PASSED] drm_connector_dynamic_register ==========
[04:26:19] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[04:26:19] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[04:26:19] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[04:26:19] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[04:26:19] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[04:26:19] ========== drm_test_get_tv_mode_from_name_valid ===========
[04:26:19] [PASSED] NTSC
[04:26:19] [PASSED] NTSC-443
[04:26:19] [PASSED] NTSC-J
[04:26:19] [PASSED] PAL
[04:26:19] [PASSED] PAL-M
[04:26:19] [PASSED] PAL-N
[04:26:19] [PASSED] SECAM
[04:26:19] [PASSED] Mono
[04:26:19] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[04:26:19] [PASSED] drm_test_get_tv_mode_from_name_truncated
[04:26:19] ============ [PASSED] drm_get_tv_mode_from_name ============
[04:26:19] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[04:26:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[04:26:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[04:26:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[04:26:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[04:26:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[04:26:19] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[04:26:19] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[04:26:19] [PASSED] VIC 96
[04:26:19] [PASSED] VIC 97
[04:26:19] [PASSED] VIC 101
[04:26:19] [PASSED] VIC 102
[04:26:19] [PASSED] VIC 106
[04:26:19] [PASSED] VIC 107
[04:26:19] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[04:26:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[04:26:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[04:26:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[04:26:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[04:26:19] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[04:26:19] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[04:26:19] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[04:26:19] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[04:26:19] [PASSED] Automatic
[04:26:19] [PASSED] Full
[04:26:19] [PASSED] Limited 16:235
[04:26:19] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[04:26:19] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[04:26:19] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[04:26:19] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[04:26:19] === drm_test_drm_hdmi_connector_get_output_format_name ====
[04:26:19] [PASSED] RGB
[04:26:19] [PASSED] YUV 4:2:0
[04:26:19] [PASSED] YUV 4:2:2
[04:26:19] [PASSED] YUV 4:4:4
[04:26:19] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[04:26:19] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[04:26:19] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[04:26:19] ============= drm_damage_helper (21 subtests) ==============
[04:26:19] [PASSED] drm_test_damage_iter_no_damage
[04:26:19] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[04:26:19] [PASSED] drm_test_damage_iter_no_damage_src_moved
[04:26:19] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[04:26:19] [PASSED] drm_test_damage_iter_no_damage_not_visible
[04:26:19] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[04:26:19] [PASSED] drm_test_damage_iter_no_damage_no_fb
[04:26:19] [PASSED] drm_test_damage_iter_simple_damage
[04:26:19] [PASSED] drm_test_damage_iter_single_damage
[04:26:19] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[04:26:19] [PASSED] drm_test_damage_iter_single_damage_outside_src
[04:26:19] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[04:26:19] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[04:26:19] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[04:26:19] [PASSED] drm_test_damage_iter_single_damage_src_moved
[04:26:19] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[04:26:19] [PASSED] drm_test_damage_iter_damage
[04:26:19] [PASSED] drm_test_damage_iter_damage_one_intersect
[04:26:19] [PASSED] drm_test_damage_iter_damage_one_outside
[04:26:19] [PASSED] drm_test_damage_iter_damage_src_moved
[04:26:19] [PASSED] drm_test_damage_iter_damage_not_visible
[04:26:19] ================ [PASSED] drm_damage_helper ================
[04:26:19] ============== drm_dp_mst_helper (3 subtests) ==============
[04:26:19] ============== drm_test_dp_mst_calc_pbn_mode ==============
[04:26:19] [PASSED] Clock 154000 BPP 30 DSC disabled
[04:26:19] [PASSED] Clock 234000 BPP 30 DSC disabled
[04:26:19] [PASSED] Clock 297000 BPP 24 DSC disabled
[04:26:19] [PASSED] Clock 332880 BPP 24 DSC enabled
[04:26:19] [PASSED] Clock 324540 BPP 24 DSC enabled
[04:26:19] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[04:26:19] ============== drm_test_dp_mst_calc_pbn_div ===============
[04:26:19] [PASSED] Link rate 2000000 lane count 4
[04:26:19] [PASSED] Link rate 2000000 lane count 2
[04:26:19] [PASSED] Link rate 2000000 lane count 1
[04:26:19] [PASSED] Link rate 1350000 lane count 4
[04:26:19] [PASSED] Link rate 1350000 lane count 2
[04:26:19] [PASSED] Link rate 1350000 lane count 1
[04:26:19] [PASSED] Link rate 1000000 lane count 4
[04:26:19] [PASSED] Link rate 1000000 lane count 2
[04:26:19] [PASSED] Link rate 1000000 lane count 1
[04:26:19] [PASSED] Link rate 810000 lane count 4
[04:26:19] [PASSED] Link rate 810000 lane count 2
[04:26:19] [PASSED] Link rate 810000 lane count 1
[04:26:19] [PASSED] Link rate 540000 lane count 4
[04:26:19] [PASSED] Link rate 540000 lane count 2
[04:26:19] [PASSED] Link rate 540000 lane count 1
[04:26:19] [PASSED] Link rate 270000 lane count 4
[04:26:19] [PASSED] Link rate 270000 lane count 2
[04:26:19] [PASSED] Link rate 270000 lane count 1
[04:26:19] [PASSED] Link rate 162000 lane count 4
[04:26:19] [PASSED] Link rate 162000 lane count 2
[04:26:19] [PASSED] Link rate 162000 lane count 1
[04:26:19] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[04:26:19] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[04:26:19] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[04:26:19] [PASSED] DP_POWER_UP_PHY with port number
[04:26:19] [PASSED] DP_POWER_DOWN_PHY with port number
[04:26:19] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[04:26:19] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[04:26:19] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[04:26:19] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[04:26:19] [PASSED] DP_QUERY_PAYLOAD with port number
[04:26:19] [PASSED] DP_QUERY_PAYLOAD with VCPI
[04:26:19] [PASSED] DP_REMOTE_DPCD_READ with port number
[04:26:19] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[04:26:19] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[04:26:19] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[04:26:19] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[04:26:19] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[04:26:19] [PASSED] DP_REMOTE_I2C_READ with port number
[04:26:19] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[04:26:19] [PASSED] DP_REMOTE_I2C_READ with transactions array
[04:26:19] [PASSED] DP_REMOTE_I2C_WRITE with port number
[04:26:19] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[04:26:19] [PASSED] DP_REMOTE_I2C_WRITE with data array
[04:26:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[04:26:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[04:26:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[04:26:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[04:26:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[04:26:19] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[04:26:19] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[04:26:19] ================ [PASSED] drm_dp_mst_helper ================
[04:26:19] ================== drm_exec (7 subtests) ===================
[04:26:19] [PASSED] sanitycheck
[04:26:19] [PASSED] test_lock
[04:26:19] [PASSED] test_lock_unlock
[04:26:19] [PASSED] test_duplicates
[04:26:19] [PASSED] test_prepare
[04:26:19] [PASSED] test_prepare_array
[04:26:19] [PASSED] test_multiple_loops
[04:26:19] ==================== [PASSED] drm_exec =====================
[04:26:19] =========== drm_format_helper_test (17 subtests) ===========
[04:26:19] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[04:26:19] [PASSED] single_pixel_source_buffer
[04:26:19] [PASSED] single_pixel_clip_rectangle
[04:26:19] [PASSED] well_known_colors
[04:26:19] [PASSED] destination_pitch
[04:26:19] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[04:26:19] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[04:26:19] [PASSED] single_pixel_source_buffer
[04:26:19] [PASSED] single_pixel_clip_rectangle
[04:26:19] [PASSED] well_known_colors
[04:26:19] [PASSED] destination_pitch
[04:26:19] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[04:26:19] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[04:26:19] [PASSED] single_pixel_source_buffer
[04:26:19] [PASSED] single_pixel_clip_rectangle
[04:26:19] [PASSED] well_known_colors
[04:26:19] [PASSED] destination_pitch
[04:26:19] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[04:26:19] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[04:26:19] [PASSED] single_pixel_source_buffer
[04:26:19] [PASSED] single_pixel_clip_rectangle
[04:26:19] [PASSED] well_known_colors
[04:26:19] [PASSED] destination_pitch
[04:26:19] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[04:26:19] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[04:26:19] [PASSED] single_pixel_source_buffer
[04:26:19] [PASSED] single_pixel_clip_rectangle
[04:26:19] [PASSED] well_known_colors
[04:26:19] [PASSED] destination_pitch
[04:26:19] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[04:26:19] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[04:26:19] [PASSED] single_pixel_source_buffer
[04:26:19] [PASSED] single_pixel_clip_rectangle
[04:26:19] [PASSED] well_known_colors
[04:26:19] [PASSED] destination_pitch
[04:26:19] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[04:26:19] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[04:26:19] [PASSED] single_pixel_source_buffer
[04:26:19] [PASSED] single_pixel_clip_rectangle
[04:26:19] [PASSED] well_known_colors
[04:26:19] [PASSED] destination_pitch
[04:26:19] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[04:26:19] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[04:26:19] [PASSED] single_pixel_source_buffer
[04:26:19] [PASSED] single_pixel_clip_rectangle
[04:26:19] [PASSED] well_known_colors
[04:26:19] [PASSED] destination_pitch
[04:26:19] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[04:26:19] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[04:26:19] [PASSED] single_pixel_source_buffer
[04:26:19] [PASSED] single_pixel_clip_rectangle
[04:26:19] [PASSED] well_known_colors
[04:26:19] [PASSED] destination_pitch
[04:26:19] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[04:26:19] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[04:26:19] [PASSED] single_pixel_source_buffer
[04:26:19] [PASSED] single_pixel_clip_rectangle
[04:26:19] [PASSED] well_known_colors
[04:26:19] [PASSED] destination_pitch
[04:26:19] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[04:26:19] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[04:26:19] [PASSED] single_pixel_source_buffer
[04:26:19] [PASSED] single_pixel_clip_rectangle
[04:26:19] [PASSED] well_known_colors
[04:26:19] [PASSED] destination_pitch
[04:26:19] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[04:26:19] ============== drm_test_fb_xrgb8888_to_mono ===============
[04:26:19] [PASSED] single_pixel_source_buffer
[04:26:19] [PASSED] single_pixel_clip_rectangle
[04:26:19] [PASSED] well_known_colors
[04:26:19] [PASSED] destination_pitch
[04:26:19] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[04:26:19] ==================== drm_test_fb_swab =====================
[04:26:19] [PASSED] single_pixel_source_buffer
[04:26:19] [PASSED] single_pixel_clip_rectangle
[04:26:19] [PASSED] well_known_colors
[04:26:19] [PASSED] destination_pitch
[04:26:19] ================ [PASSED] drm_test_fb_swab =================
[04:26:19] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[04:26:19] [PASSED] single_pixel_source_buffer
[04:26:19] [PASSED] single_pixel_clip_rectangle
[04:26:19] [PASSED] well_known_colors
[04:26:19] [PASSED] destination_pitch
[04:26:19] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[04:26:19] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[04:26:19] [PASSED] single_pixel_source_buffer
[04:26:19] [PASSED] single_pixel_clip_rectangle
[04:26:19] [PASSED] well_known_colors
[04:26:19] [PASSED] destination_pitch
[04:26:19] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[04:26:19] ================= drm_test_fb_clip_offset =================
[04:26:19] [PASSED] pass through
[04:26:19] [PASSED] horizontal offset
[04:26:19] [PASSED] vertical offset
[04:26:19] [PASSED] horizontal and vertical offset
[04:26:19] [PASSED] horizontal offset (custom pitch)
[04:26:19] [PASSED] vertical offset (custom pitch)
[04:26:19] [PASSED] horizontal and vertical offset (custom pitch)
[04:26:19] ============= [PASSED] drm_test_fb_clip_offset =============
[04:26:19] =================== drm_test_fb_memcpy ====================
[04:26:19] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[04:26:19] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[04:26:19] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[04:26:19] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[04:26:19] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[04:26:19] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[04:26:19] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[04:26:19] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[04:26:19] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[04:26:19] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[04:26:19] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[04:26:19] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[04:26:19] =============== [PASSED] drm_test_fb_memcpy ================
[04:26:19] ============= [PASSED] drm_format_helper_test ==============
[04:26:19] ================= drm_format (18 subtests) =================
[04:26:19] [PASSED] drm_test_format_block_width_invalid
[04:26:19] [PASSED] drm_test_format_block_width_one_plane
[04:26:19] [PASSED] drm_test_format_block_width_two_plane
[04:26:19] [PASSED] drm_test_format_block_width_three_plane
[04:26:19] [PASSED] drm_test_format_block_width_tiled
[04:26:19] [PASSED] drm_test_format_block_height_invalid
[04:26:19] [PASSED] drm_test_format_block_height_one_plane
[04:26:19] [PASSED] drm_test_format_block_height_two_plane
[04:26:19] [PASSED] drm_test_format_block_height_three_plane
[04:26:19] [PASSED] drm_test_format_block_height_tiled
[04:26:19] [PASSED] drm_test_format_min_pitch_invalid
[04:26:19] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[04:26:19] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[04:26:19] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[04:26:19] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[04:26:19] [PASSED] drm_test_format_min_pitch_two_plane
[04:26:19] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[04:26:19] [PASSED] drm_test_format_min_pitch_tiled
[04:26:19] =================== [PASSED] drm_format ====================
[04:26:19] ============== drm_framebuffer (10 subtests) ===============
[04:26:19] ========== drm_test_framebuffer_check_src_coords ==========
[04:26:19] [PASSED] Success: source fits into fb
[04:26:19] [PASSED] Fail: overflowing fb with x-axis coordinate
[04:26:19] [PASSED] Fail: overflowing fb with y-axis coordinate
[04:26:19] [PASSED] Fail: overflowing fb with source width
[04:26:19] [PASSED] Fail: overflowing fb with source height
[04:26:19] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[04:26:19] [PASSED] drm_test_framebuffer_cleanup
[04:26:19] =============== drm_test_framebuffer_create ===============
[04:26:19] [PASSED] ABGR8888 normal sizes
[04:26:19] [PASSED] ABGR8888 max sizes
[04:26:19] [PASSED] ABGR8888 pitch greater than min required
[04:26:19] [PASSED] ABGR8888 pitch less than min required
[04:26:19] [PASSED] ABGR8888 Invalid width
[04:26:19] [PASSED] ABGR8888 Invalid buffer handle
[04:26:19] [PASSED] No pixel format
[04:26:19] [PASSED] ABGR8888 Width 0
[04:26:19] [PASSED] ABGR8888 Height 0
[04:26:19] [PASSED] ABGR8888 Out of bound height * pitch combination
[04:26:19] [PASSED] ABGR8888 Large buffer offset
[04:26:19] [PASSED] ABGR8888 Buffer offset for inexistent plane
[04:26:19] [PASSED] ABGR8888 Invalid flag
[04:26:19] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[04:26:19] [PASSED] ABGR8888 Valid buffer modifier
[04:26:19] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[04:26:19] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[04:26:19] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[04:26:19] [PASSED] NV12 Normal sizes
[04:26:19] [PASSED] NV12 Max sizes
[04:26:19] [PASSED] NV12 Invalid pitch
[04:26:19] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[04:26:19] [PASSED] NV12 different modifier per-plane
[04:26:19] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[04:26:19] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[04:26:19] [PASSED] NV12 Modifier for inexistent plane
[04:26:19] [PASSED] NV12 Handle for inexistent plane
[04:26:19] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[04:26:19] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[04:26:19] [PASSED] YVU420 Normal sizes
[04:26:19] [PASSED] YVU420 Max sizes
[04:26:19] [PASSED] YVU420 Invalid pitch
[04:26:19] [PASSED] YVU420 Different pitches
[04:26:19] [PASSED] YVU420 Different buffer offsets/pitches
[04:26:19] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[04:26:19] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[04:26:19] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[04:26:19] [PASSED] YVU420 Valid modifier
[04:26:19] [PASSED] YVU420 Different modifiers per plane
[04:26:19] [PASSED] YVU420 Modifier for inexistent plane
[04:26:19] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[04:26:19] [PASSED] X0L2 Normal sizes
[04:26:19] [PASSED] X0L2 Max sizes
[04:26:19] [PASSED] X0L2 Invalid pitch
[04:26:19] [PASSED] X0L2 Pitch greater than minimum required
[04:26:19] [PASSED] X0L2 Handle for inexistent plane
[04:26:19] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[04:26:19] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[04:26:19] [PASSED] X0L2 Valid modifier
[04:26:19] [PASSED] X0L2 Modifier for inexistent plane
[04:26:19] =========== [PASSED] drm_test_framebuffer_create ===========
[04:26:19] [PASSED] drm_test_framebuffer_free
[04:26:19] [PASSED] drm_test_framebuffer_init
[04:26:19] [PASSED] drm_test_framebuffer_init_bad_format
[04:26:19] [PASSED] drm_test_framebuffer_init_dev_mismatch
[04:26:19] [PASSED] drm_test_framebuffer_lookup
[04:26:19] [PASSED] drm_test_framebuffer_lookup_inexistent
[04:26:19] [PASSED] drm_test_framebuffer_modifiers_not_supported
[04:26:19] ================= [PASSED] drm_framebuffer =================
[04:26:19] ================ drm_gem_shmem (8 subtests) ================
[04:26:19] [PASSED] drm_gem_shmem_test_obj_create
[04:26:19] [PASSED] drm_gem_shmem_test_obj_create_private
[04:26:19] [PASSED] drm_gem_shmem_test_pin_pages
[04:26:19] [PASSED] drm_gem_shmem_test_vmap
[04:26:19] [PASSED] drm_gem_shmem_test_get_sg_table
[04:26:19] [PASSED] drm_gem_shmem_test_get_pages_sgt
[04:26:19] [PASSED] drm_gem_shmem_test_madvise
[04:26:19] [PASSED] drm_gem_shmem_test_purge
[04:26:19] ================== [PASSED] drm_gem_shmem ==================
[04:26:19] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[04:26:19] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[04:26:19] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[04:26:19] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[04:26:19] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[04:26:19] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[04:26:19] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[04:26:19] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[04:26:19] [PASSED] Automatic
[04:26:19] [PASSED] Full
[04:26:19] [PASSED] Limited 16:235
[04:26:19] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[04:26:19] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[04:26:19] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[04:26:19] [PASSED] drm_test_check_disable_connector
[04:26:19] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[04:26:19] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[04:26:19] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[04:26:19] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[04:26:19] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[04:26:19] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[04:26:19] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[04:26:19] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[04:26:19] [PASSED] drm_test_check_output_bpc_dvi
[04:26:19] [PASSED] drm_test_check_output_bpc_format_vic_1
[04:26:19] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[04:26:19] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[04:26:19] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[04:26:19] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[04:26:19] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[04:26:19] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[04:26:19] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[04:26:19] ============ drm_test_check_hdmi_color_format =============
[04:26:19] [PASSED] AUTO -> RGB
[04:26:19] [PASSED] YCBCR422 -> YUV422
[04:26:19] [PASSED] YCBCR420 -> YUV420
[04:26:19] [PASSED] YCBCR444 -> YUV444
[04:26:19] [PASSED] RGB -> RGB
[04:26:19] ======== [PASSED] drm_test_check_hdmi_color_format =========
[04:26:19] ======== drm_test_check_hdmi_color_format_420_only ========
[04:26:19] [PASSED] RGB should fail
[04:26:19] [PASSED] YUV444 should fail
[04:26:19] [PASSED] YUV422 should fail
[04:26:19] [PASSED] YUV420 should work
[04:26:19] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[04:26:19] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[04:26:19] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[04:26:19] [PASSED] drm_test_check_broadcast_rgb_value
[04:26:19] [PASSED] drm_test_check_bpc_8_value
[04:26:19] [PASSED] drm_test_check_bpc_10_value
[04:26:19] [PASSED] drm_test_check_bpc_12_value
[04:26:19] [PASSED] drm_test_check_format_value
[04:26:19] [PASSED] drm_test_check_tmds_char_value
[04:26:19] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[04:26:19] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[04:26:19] [PASSED] drm_test_check_mode_valid
[04:26:19] [PASSED] drm_test_check_mode_valid_reject
[04:26:19] [PASSED] drm_test_check_mode_valid_reject_rate
[04:26:19] [PASSED] drm_test_check_mode_valid_reject_max_clock
[04:26:19] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[04:26:19] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[04:26:19] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[04:26:19] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[04:26:19] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[04:26:19] [PASSED] drm_test_check_infoframes
[04:26:19] [PASSED] drm_test_check_reject_avi_infoframe
[04:26:19] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[04:26:19] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[04:26:19] [PASSED] drm_test_check_reject_audio_infoframe
[04:26:19] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[04:26:19] ================= drm_managed (2 subtests) =================
[04:26:19] [PASSED] drm_test_managed_release_action
[04:26:19] [PASSED] drm_test_managed_run_action
[04:26:19] =================== [PASSED] drm_managed ===================
[04:26:19] =================== drm_mm (6 subtests) ====================
[04:26:19] [PASSED] drm_test_mm_init
[04:26:19] [PASSED] drm_test_mm_debug
[04:26:19] [PASSED] drm_test_mm_align32
[04:26:19] [PASSED] drm_test_mm_align64
[04:26:19] [PASSED] drm_test_mm_lowest
[04:26:19] [PASSED] drm_test_mm_highest
[04:26:19] ===================== [PASSED] drm_mm ======================
[04:26:19] ============= drm_modes_analog_tv (5 subtests) =============
[04:26:19] [PASSED] drm_test_modes_analog_tv_mono_576i
[04:26:19] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[04:26:19] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[04:26:19] [PASSED] drm_test_modes_analog_tv_pal_576i
[04:26:19] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[04:26:19] =============== [PASSED] drm_modes_analog_tv ===============
[04:26:19] ============== drm_panic_helper (3 subtests) ===============
[04:26:19] ============= drm_test_panic_screen_user_map ==============
[04:26:19] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[04:26:19] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[04:26:19] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[04:26:19] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[04:26:19] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[04:26:19] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[04:26:19] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[04:26:19] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[04:26:19] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[04:26:19] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[04:26:19] ========= [PASSED] drm_test_panic_screen_user_map ==========
[04:26:19] ============= drm_test_panic_screen_user_page =============
[04:26:19] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[04:26:19] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[04:26:19] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[04:26:19] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[04:26:19] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[04:26:19] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[04:26:19] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[04:26:19] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[04:26:19] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[04:26:19] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[04:26:19] ========= [PASSED] drm_test_panic_screen_user_page =========
[04:26:19] ========== drm_test_panic_screen_user_set_pixel ===========
[04:26:19] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[04:26:19] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[04:26:19] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[04:26:19] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[04:26:19] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[04:26:19] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[04:26:19] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[04:26:19] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[04:26:20] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[04:26:20] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[04:26:20] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[04:26:20] ================ [PASSED] drm_panic_helper =================
[04:26:20] ============== drm_plane_helper (2 subtests) ===============
[04:26:20] =============== drm_test_check_plane_state ================
[04:26:20] [PASSED] clipping_simple
[04:26:20] [PASSED] clipping_rotate_reflect
[04:26:20] [PASSED] positioning_simple
[04:26:20] [PASSED] upscaling
[04:26:20] [PASSED] downscaling
[04:26:20] [PASSED] rounding1
[04:26:20] [PASSED] rounding2
[04:26:20] [PASSED] rounding3
[04:26:20] [PASSED] rounding4
[04:26:20] =========== [PASSED] drm_test_check_plane_state ============
[04:26:20] =========== drm_test_check_invalid_plane_state ============
[04:26:20] [PASSED] positioning_invalid
[04:26:20] [PASSED] upscaling_invalid
[04:26:20] [PASSED] downscaling_invalid
[04:26:20] ======= [PASSED] drm_test_check_invalid_plane_state ========
[04:26:20] ================ [PASSED] drm_plane_helper =================
[04:26:20] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[04:26:20] ====== drm_test_connector_helper_tv_get_modes_check =======
[04:26:20] [PASSED] None
[04:26:20] [PASSED] PAL
[04:26:20] [PASSED] NTSC
[04:26:20] [PASSED] Both, NTSC Default
[04:26:20] [PASSED] Both, PAL Default
[04:26:20] [PASSED] Both, NTSC Default, with PAL on command-line
[04:26:20] [PASSED] Both, PAL Default, with NTSC on command-line
[04:26:20] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[04:26:20] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[04:26:20] ================== drm_rect (9 subtests) ===================
[04:26:20] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[04:26:20] [PASSED] drm_test_rect_clip_scaled_not_clipped
[04:26:20] [PASSED] drm_test_rect_clip_scaled_clipped
[04:26:20] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[04:26:20] ================= drm_test_rect_intersect =================
[04:26:20] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[04:26:20] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[04:26:20] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[04:26:20] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[04:26:20] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[04:26:20] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[04:26:20] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[04:26:20] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[04:26:20] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[04:26:20] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[04:26:20] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[04:26:20] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[04:26:20] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[04:26:20] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[04:26:20] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[04:26:20] ============= [PASSED] drm_test_rect_intersect =============
[04:26:20] ================ drm_test_rect_calc_hscale ================
[04:26:20] [PASSED] normal use
[04:26:20] [PASSED] out of max range
[04:26:20] [PASSED] out of min range
[04:26:20] [PASSED] zero dst
[04:26:20] [PASSED] negative src
[04:26:20] [PASSED] negative dst
[04:26:20] ============ [PASSED] drm_test_rect_calc_hscale ============
[04:26:20] ================ drm_test_rect_calc_vscale ================
[04:26:20] [PASSED] normal use
[04:26:20] [PASSED] out of max range
[04:26:20] [PASSED] out of min range
[04:26:20] [PASSED] zero dst
[04:26:20] [PASSED] negative src
[04:26:20] [PASSED] negative dst
[04:26:20] ============ [PASSED] drm_test_rect_calc_vscale ============
[04:26:20] ================== drm_test_rect_rotate ===================
[04:26:20] [PASSED] reflect-x
[04:26:20] [PASSED] reflect-y
[04:26:20] [PASSED] rotate-0
[04:26:20] [PASSED] rotate-90
[04:26:20] [PASSED] rotate-180
[04:26:20] [PASSED] rotate-270
[04:26:20] ============== [PASSED] drm_test_rect_rotate ===============
[04:26:20] ================ drm_test_rect_rotate_inv =================
[04:26:20] [PASSED] reflect-x
[04:26:20] [PASSED] reflect-y
[04:26:20] [PASSED] rotate-0
[04:26:20] [PASSED] rotate-90
[04:26:20] [PASSED] rotate-180
[04:26:20] [PASSED] rotate-270
[04:26:20] ============ [PASSED] drm_test_rect_rotate_inv =============
[04:26:20] ==================== [PASSED] drm_rect =====================
[04:26:20] ============ drm_sysfb_modeset_test (1 subtest) ============
[04:26:20] ============ drm_test_sysfb_build_fourcc_list =============
[04:26:20] [PASSED] no native formats
[04:26:20] [PASSED] XRGB8888 as native format
[04:26:20] [PASSED] remove duplicates
[04:26:20] [PASSED] convert alpha formats
[04:26:20] [PASSED] random formats
[04:26:20] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[04:26:20] ============= [PASSED] drm_sysfb_modeset_test ==============
[04:26:20] ================== drm_fixp (2 subtests) ===================
[04:26:20] [PASSED] drm_test_int2fixp
[04:26:20] [PASSED] drm_test_sm2fixp
[04:26:20] ==================== [PASSED] drm_fixp =====================
[04:26:20] ============================================================
[04:26:20] Testing complete. Ran 667 tests: passed: 667
[04:26:20] Elapsed time: 27.394s total, 1.854s configuring, 25.075s building, 0.412s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[04:26:20] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:26:22] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:26:32] Starting KUnit Kernel (1/1)...
[04:26:32] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:26:32] ================= ttm_device (5 subtests) ==================
[04:26:32] [PASSED] ttm_device_init_basic
[04:26:32] [PASSED] ttm_device_init_multiple
[04:26:32] [PASSED] ttm_device_fini_basic
[04:26:32] [PASSED] ttm_device_init_no_vma_man
[04:26:32] ================== ttm_device_init_pools ==================
[04:26:32] [PASSED] No DMA allocations, no DMA32 required
[04:26:32] [PASSED] DMA allocations, DMA32 required
[04:26:32] [PASSED] No DMA allocations, DMA32 required
[04:26:32] [PASSED] DMA allocations, no DMA32 required
[04:26:32] ============== [PASSED] ttm_device_init_pools ==============
[04:26:32] =================== [PASSED] ttm_device ====================
[04:26:32] ================== ttm_pool (8 subtests) ===================
[04:26:32] ================== ttm_pool_alloc_basic ===================
[04:26:32] [PASSED] One page
[04:26:32] [PASSED] More than one page
[04:26:32] [PASSED] Above the allocation limit
[04:26:32] [PASSED] One page, with coherent DMA mappings enabled
[04:26:32] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[04:26:32] ============== [PASSED] ttm_pool_alloc_basic ===============
[04:26:32] ============== ttm_pool_alloc_basic_dma_addr ==============
[04:26:32] [PASSED] One page
[04:26:32] [PASSED] More than one page
[04:26:32] [PASSED] Above the allocation limit
[04:26:32] [PASSED] One page, with coherent DMA mappings enabled
[04:26:32] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[04:26:32] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[04:26:32] [PASSED] ttm_pool_alloc_order_caching_match
[04:26:32] [PASSED] ttm_pool_alloc_caching_mismatch
[04:26:32] [PASSED] ttm_pool_alloc_order_mismatch
[04:26:32] [PASSED] ttm_pool_free_dma_alloc
[04:26:32] [PASSED] ttm_pool_free_no_dma_alloc
[04:26:32] [PASSED] ttm_pool_fini_basic
[04:26:32] ==================== [PASSED] ttm_pool =====================
[04:26:32] ================ ttm_resource (8 subtests) =================
[04:26:32] ================= ttm_resource_init_basic =================
[04:26:32] [PASSED] Init resource in TTM_PL_SYSTEM
[04:26:32] [PASSED] Init resource in TTM_PL_VRAM
[04:26:32] [PASSED] Init resource in a private placement
[04:26:32] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[04:26:32] ============= [PASSED] ttm_resource_init_basic =============
[04:26:32] [PASSED] ttm_resource_init_pinned
[04:26:32] [PASSED] ttm_resource_fini_basic
[04:26:32] [PASSED] ttm_resource_manager_init_basic
[04:26:32] [PASSED] ttm_resource_manager_usage_basic
[04:26:32] [PASSED] ttm_resource_manager_set_used_basic
[04:26:32] [PASSED] ttm_sys_man_alloc_basic
[04:26:32] [PASSED] ttm_sys_man_free_basic
[04:26:32] ================== [PASSED] ttm_resource ===================
[04:26:32] =================== ttm_tt (15 subtests) ===================
[04:26:32] ==================== ttm_tt_init_basic ====================
[04:26:32] [PASSED] Page-aligned size
[04:26:32] [PASSED] Extra pages requested
[04:26:32] ================ [PASSED] ttm_tt_init_basic ================
[04:26:32] [PASSED] ttm_tt_init_misaligned
[04:26:32] [PASSED] ttm_tt_fini_basic
[04:26:32] [PASSED] ttm_tt_fini_sg
[04:26:32] [PASSED] ttm_tt_fini_shmem
[04:26:32] [PASSED] ttm_tt_create_basic
[04:26:32] [PASSED] ttm_tt_create_invalid_bo_type
[04:26:32] [PASSED] ttm_tt_create_ttm_exists
[04:26:32] [PASSED] ttm_tt_create_failed
[04:26:32] [PASSED] ttm_tt_destroy_basic
[04:26:32] [PASSED] ttm_tt_populate_null_ttm
[04:26:32] [PASSED] ttm_tt_populate_populated_ttm
[04:26:32] [PASSED] ttm_tt_unpopulate_basic
[04:26:32] [PASSED] ttm_tt_unpopulate_empty_ttm
[04:26:32] [PASSED] ttm_tt_swapin_basic
[04:26:32] ===================== [PASSED] ttm_tt ======================
[04:26:32] =================== ttm_bo (14 subtests) ===================
[04:26:32] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[04:26:32] [PASSED] Cannot be interrupted and sleeps
[04:26:32] [PASSED] Cannot be interrupted, locks straight away
[04:26:32] [PASSED] Can be interrupted, sleeps
[04:26:32] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[04:26:32] [PASSED] ttm_bo_reserve_locked_no_sleep
[04:26:32] [PASSED] ttm_bo_reserve_no_wait_ticket
[04:26:32] [PASSED] ttm_bo_reserve_double_resv
[04:26:32] [PASSED] ttm_bo_reserve_interrupted
[04:26:32] [PASSED] ttm_bo_reserve_deadlock
[04:26:32] [PASSED] ttm_bo_unreserve_basic
[04:26:32] [PASSED] ttm_bo_unreserve_pinned
[04:26:32] [PASSED] ttm_bo_unreserve_bulk
[04:26:32] [PASSED] ttm_bo_fini_basic
[04:26:32] [PASSED] ttm_bo_fini_shared_resv
[04:26:32] [PASSED] ttm_bo_pin_basic
[04:26:32] [PASSED] ttm_bo_pin_unpin_resource
[04:26:32] [PASSED] ttm_bo_multiple_pin_one_unpin
[04:26:32] ===================== [PASSED] ttm_bo ======================
[04:26:32] ============== ttm_bo_validate (22 subtests) ===============
[04:26:32] ============== ttm_bo_init_reserved_sys_man ===============
[04:26:32] [PASSED] Buffer object for userspace
[04:26:32] [PASSED] Kernel buffer object
[04:26:32] [PASSED] Shared buffer object
[04:26:32] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[04:26:32] ============== ttm_bo_init_reserved_mock_man ==============
[04:26:32] [PASSED] Buffer object for userspace
[04:26:32] [PASSED] Kernel buffer object
[04:26:32] [PASSED] Shared buffer object
[04:26:32] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[04:26:32] [PASSED] ttm_bo_init_reserved_resv
[04:26:32] ================== ttm_bo_validate_basic ==================
[04:26:32] [PASSED] Buffer object for userspace
[04:26:32] [PASSED] Kernel buffer object
[04:26:32] [PASSED] Shared buffer object
[04:26:32] ============== [PASSED] ttm_bo_validate_basic ==============
[04:26:32] [PASSED] ttm_bo_validate_invalid_placement
[04:26:32] ============= ttm_bo_validate_same_placement ==============
[04:26:32] [PASSED] System manager
[04:26:32] [PASSED] VRAM manager
[04:26:32] ========= [PASSED] ttm_bo_validate_same_placement ==========
[04:26:32] [PASSED] ttm_bo_validate_failed_alloc
[04:26:32] [PASSED] ttm_bo_validate_pinned
[04:26:32] [PASSED] ttm_bo_validate_busy_placement
[04:26:32] ================ ttm_bo_validate_multihop =================
[04:26:32] [PASSED] Buffer object for userspace
[04:26:32] [PASSED] Kernel buffer object
[04:26:32] [PASSED] Shared buffer object
[04:26:32] ============ [PASSED] ttm_bo_validate_multihop =============
[04:26:32] ========== ttm_bo_validate_no_placement_signaled ==========
[04:26:32] [PASSED] Buffer object in system domain, no page vector
[04:26:32] [PASSED] Buffer object in system domain with an existing page vector
[04:26:32] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[04:26:32] ======== ttm_bo_validate_no_placement_not_signaled ========
[04:26:32] [PASSED] Buffer object for userspace
[04:26:32] [PASSED] Kernel buffer object
[04:26:32] [PASSED] Shared buffer object
[04:26:32] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[04:26:32] [PASSED] ttm_bo_validate_move_fence_signaled
[04:26:32] ========= ttm_bo_validate_move_fence_not_signaled =========
[04:26:32] [PASSED] Waits for GPU
[04:26:32] [PASSED] Tries to lock straight away
[04:26:32] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[04:26:32] [PASSED] ttm_bo_validate_swapout
[04:26:32] [PASSED] ttm_bo_validate_happy_evict
[04:26:32] [PASSED] ttm_bo_validate_all_pinned_evict
[04:26:32] [PASSED] ttm_bo_validate_allowed_only_evict
[04:26:32] [PASSED] ttm_bo_validate_deleted_evict
[04:26:32] [PASSED] ttm_bo_validate_busy_domain_evict
[04:26:32] [PASSED] ttm_bo_validate_evict_gutting
[04:26:32] [PASSED] ttm_bo_validate_recrusive_evict
[04:26:32] ================= [PASSED] ttm_bo_validate =================
[04:26:32] ============================================================
[04:26:32] Testing complete. Ran 102 tests: passed: 102
[04:26:32] Elapsed time: 12.240s total, 1.869s configuring, 10.156s building, 0.178s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[04:26:32] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:26:34] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:26:43] Starting KUnit Kernel (1/1)...
[04:26:43] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:26:43] =============== dma-buf-fence (12 subtests) ================
[04:26:43] [PASSED] test_sanitycheck
[04:26:43] [PASSED] test_signaling
[04:26:43] [PASSED] test_add_callback
[04:26:43] [PASSED] test_late_add_callback
[04:26:43] [PASSED] test_rm_callback
[04:26:43] [PASSED] test_late_rm_callback
[04:26:43] [PASSED] test_status
[04:26:43] [PASSED] test_error
[04:26:43] [PASSED] test_wait
[04:26:43] [PASSED] test_wait_timeout
[04:26:43] [PASSED] test_stub
[04:26:43] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[04:26:43] ================== [PASSED] dma-buf-fence ==================
[04:26:43] ============ dma-buf-fence-chain (11 subtests) =============
[04:26:43] [PASSED] test_sanitycheck
[04:26:43] [PASSED] test_find_seqno
[04:26:43] [PASSED] test_find_signaled
[04:26:43] [PASSED] test_find_out_of_order
[04:26:48] [PASSED] test_find_gap
[04:26:48] [PASSED] test_find_race
[04:26:48] [PASSED] test_signal_forward
[04:26:48] [PASSED] test_signal_backward
[04:26:48] [PASSED] test_wait_forward
[04:26:48] [PASSED] test_wait_backward
[04:26:48] [PASSED] test_wait_random
[04:26:48] =============== [PASSED] dma-buf-fence-chain ===============
[04:26:48] ============ dma-buf-fence-unwrap (11 subtests) ============
[04:26:48] [PASSED] test_sanitycheck
[04:26:48] [PASSED] test_unwrap_array
[04:26:48] [PASSED] test_unwrap_chain
[04:26:48] [PASSED] test_unwrap_chain_array
[04:26:48] [PASSED] test_unwrap_merge
[04:26:48] [PASSED] test_unwrap_merge_duplicate
[04:26:48] [PASSED] test_unwrap_merge_seqno
[04:26:48] [PASSED] test_unwrap_merge_order
[04:26:48] [PASSED] test_unwrap_merge_complex
[04:26:48] [PASSED] test_unwrap_merge_complex_seqno
[04:26:48] [PASSED] test_dedup_empty
[04:26:48] ============== [PASSED] dma-buf-fence-unwrap ===============
[04:26:48] ================ dma-buf-resv (5 subtests) =================
[04:26:48] [PASSED] test_sanitycheck
[04:26:48] ===================== test_signaling ======================
[04:26:48] [PASSED] kernel
[04:26:48] [PASSED] write
[04:26:48] [PASSED] read
[04:26:48] [PASSED] bookkeep
[04:26:48] ================= [PASSED] test_signaling ==================
[04:26:48] ====================== test_for_each ======================
[04:26:48] [PASSED] kernel
[04:26:48] [PASSED] write
[04:26:48] [PASSED] read
[04:26:48] [PASSED] bookkeep
[04:26:48] ================== [PASSED] test_for_each ==================
[04:26:48] ================= test_for_each_unlocked ==================
[04:26:48] [PASSED] kernel
[04:26:48] [PASSED] write
[04:26:48] [PASSED] read
[04:26:48] [PASSED] bookkeep
[04:26:48] ============= [PASSED] test_for_each_unlocked ==============
[04:26:48] ===================== test_get_fences =====================
[04:26:48] [PASSED] kernel
[04:26:48] [PASSED] write
[04:26:48] [PASSED] read
[04:26:48] [PASSED] bookkeep
[04:26:48] ================= [PASSED] test_get_fences =================
[04:26:48] ================== [PASSED] dma-buf-resv ===================
[04:26:48] ============================================================
[04:26:48] Testing complete. Ran 51 tests: passed: 50, skipped: 1
[04:26:48] Elapsed time: 15.842s total, 1.848s configuring, 8.723s building, 5.260s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v5 03/13] drm/xe/cper: Initialize Intel-specific section header
2026-10-23 4:34 ` [PATCH v5 03/13] drm/xe/cper: Initialize Intel-specific section header Badal Nilawar
@ 2026-10-23 4:30 ` sashiko-bot
2026-10-26 5:57 ` Raag Jadav
1 sibling, 0 replies; 37+ messages in thread
From: sashiko-bot @ 2026-10-23 4:30 UTC (permalink / raw)
To: Badal Nilawar, intel-xe
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/xe/cper: cper_init_intel_hdr() never sets unknown sig_id to U32_MAX
--
commit 1eb07867e667177c6634aadbe7bf46699728e40f
Author: Badal Nilawar <badal.nilawar@intel.com>
drm/xe/cper: Initialize Intel-specific section header
This commit defines struct xe_cper_intel_hdr for the Intel GPU error
section of a CPER record and adds helpers in drivers/gpu/drm/xe/xe_cper.c
to initialize it from a RAS error counter response.
> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> index a9044e708caca..3d7657517223a 100644
> --- a/drivers/gpu/drm/xe/xe_cper.c
> +++ b/drivers/gpu/drm/xe/xe_cper.c
[ ... ]
> +static bool is_valid_sigid(u32 sigid)
> +{
> + return sigid != U32_MAX;
> +}
> +
> static bool is_hw_sigid(enum xe_sigid sigid)
> {
> return in_range(sigid, INTEL_SIGID_GPU_XE_HARDWARE_START, INTEL_SIGID_BATCH);
> }
>
> +static void cper_init_intel_hdr(struct xe_device *xe,
> + const struct xe_ras_error_class *counter,
> + u64 first_timestamp, u32 sig_id, u32 error_count,
> + struct xe_cper_intel_hdr *ihdr)
> +{
> + ihdr->counter = *counter;
> + ihdr->validation_bits |= XE_CPER_VALID_LOCATION;
> +
> + if (first_timestamp) {
> + ihdr->first_timestamp = first_timestamp;
> + ihdr->validation_bits |= XE_CPER_VALID_FIRST_TIMESTAMP;
> + }
> +
> + if (is_valid_sigid(sig_id)) {
> + ihdr->sig_id = sig_id;
> + ihdr->validation_bits |= XE_CPER_VALID_SIG_ID;
> + }
[Severity: Medium]
In drivers/gpu/drm/xe/xe_cper_types.h, struct xe_cper_intel_hdr documents
sig_id as:
/** @sig_id: Aggregated error class SIG ID; set to U32_MAX if unknown */
u32 sig_id;
However, cper_emit_counter() zero-initializes struct xe_cper_intel_hdr ihdr
before calling cper_init_intel_hdr(). When sig_id is U32_MAX,
is_valid_sigid(sig_id) returns false and skips the assignment, leaving
ihdr->sig_id as 0 instead of U32_MAX.
Conversely, if INTEL_SIGID_INVALID (0) is passed, is_valid_sigid(sig_id)
returns true, leaving ihdr->sig_id as 0 while also setting
XE_CPER_VALID_SIG_ID in ihdr->validation_bits.
Should cper_init_intel_hdr() explicitly set ihdr->sig_id to U32_MAX when
sig_id is unknown, and should is_valid_sigid() also reject
INTEL_SIGID_INVALID?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261023043422.681260-15-badal.nilawar@intel.com?part=3
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v5 00/13] Add CPER logging support for CRI
@ 2026-10-23 4:34 Badal Nilawar
2026-10-23 4:24 ` ✗ CI.checkpatch: warning for Add CPER logging support for CRI (rev5) Patchwork
` (16 more replies)
0 siblings, 17 replies; 37+ messages in thread
From: Badal Nilawar @ 2026-10-23 4:34 UTC (permalink / raw)
To: intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
This patch series adds CPER (Common Platform Error Record) logging support
for RAS errors reported by Intel Xe GPUs. CPER records are emitted through
a trace event.
v2:
- Extended CPER logging to Uncorrectable errors and xe_ras_get_counter
request
- Log CPER records via xe_log SIGID infra
v3:
- Added the patches in incremental order (Raag)
- Fixed Sashiko warnings which are applicable
v4:
- Split the patches further for incremental review (Raag)
- Refactor info queue handling (Raag)
- Fix applicable Sashiko warnings
v5:
- Fixed v4 comments
- Covered default paths in error handling flow
- Moved info queue related patches at top
- Added example logs
Badal Nilawar (13):
drm/xe/cper: Add CPER reporting entry point for xe_log
drm/xe/cper: Retrieve the error counter record for CPER reporting
drm/xe/cper: Initialize Intel-specific section header
drm/xe/cper: Construct CPER record for hardware errors
drm/xe/cper: Log CPER records for aggregate counter retrieval
drm/xe/cper: Emit cper record to trace buf
drm/xe/xe_ras: Report device memory errors using SIGID
drm/xe/xe_ras: Report core compute errors using SIGID
drm/xe/xe_ras: Report soc internal errors using SIGID
drm/xe/xe_ras: Report correctable errors using SIGID
drm/xe/xe_ras: Report unknown errors using SIGID
drm/xe/xe_ras: Add support to retrieve info queue data
drm/xe/cper: Prepare Intel CPER info records
.../ABI/testing/sysfs-driver-intel-xe-cper | 18 +
drivers/gpu/drm/xe/Makefile | 3 +
drivers/gpu/drm/xe/xe_cper.c | 558 ++++++++++++++++++
drivers/gpu/drm/xe/xe_cper.h | 37 ++
drivers/gpu/drm/xe/xe_cper_types.h | 162 +++++
drivers/gpu/drm/xe/xe_device_types.h | 4 +
drivers/gpu/drm/xe/xe_log.c | 5 +-
drivers/gpu/drm/xe/xe_ras.c | 288 ++++++++-
drivers/gpu/drm/xe/xe_ras.h | 5 +
drivers/gpu/drm/xe/xe_ras_types.h | 116 +++-
drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 2 +
drivers/gpu/drm/xe/xe_trace_cper.c | 9 +
drivers/gpu/drm/xe/xe_trace_cper.h | 65 ++
13 files changed, 1241 insertions(+), 31 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-xe-cper
create mode 100644 drivers/gpu/drm/xe/xe_cper.c
create mode 100644 drivers/gpu/drm/xe/xe_cper.h
create mode 100644 drivers/gpu/drm/xe/xe_cper_types.h
create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.c
create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.h
--
2.54.0
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v5 01/13] drm/xe/cper: Add CPER reporting entry point for xe_log
2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
2026-10-23 4:24 ` ✗ CI.checkpatch: warning for Add CPER logging support for CRI (rev5) Patchwork
2026-10-23 4:26 ` ✓ CI.KUnit: success " Patchwork
@ 2026-10-23 4:34 ` Badal Nilawar
2026-10-24 11:38 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 02/13] drm/xe/cper: Retrieve the error counter record for CPER reporting Badal Nilawar
` (13 subsequent siblings)
16 siblings, 1 reply; 37+ messages in thread
From: Badal Nilawar @ 2026-10-23 4:34 UTC (permalink / raw)
To: intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
Introduce xe_cper_emit() as the single entry point for emitting
CPER records from xe_log. xe_log now forwards every SIGID log entry
with its full context (component, location, data/len and formatted
message), and xe_cper decides how to report it. Hardware SIGIDs are
routed to a hardware error helper, software SIGIDs are left as TODO.
Assisted-by: LLM
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
v5:
- Drop xe and len check (Raag)
- s/*error_class/*counter
- drop xe_ from static function to shorten function name
v4:
- s/CONFIG_UEFI_CPER_X86/CONFIG_UEFI_CPER/ (Raag)
- Use in_range() for hardware SIGID check in xe_cper (Raag)
- Drop unused response param and constify error_class
- Check data len against struct xe_ras_error_class before use (Michal)
---
drivers/gpu/drm/xe/Makefile | 2 ++
drivers/gpu/drm/xe/xe_cper.c | 48 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_cper.h | 26 +++++++++++++++++++
drivers/gpu/drm/xe/xe_log.c | 5 +++-
4 files changed, 80 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/xe/xe_cper.c
create mode 100644 drivers/gpu/drm/xe/xe_cper.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 6fb916f1699b..ec463018f77d 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -169,6 +169,8 @@ xe-$(CONFIG_HWMON) += xe_hwmon.o
xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
xe-$(CONFIG_CONFIGFS_FS) += xe_configfs.o
+xe-$(CONFIG_UEFI_CPER) += xe_cper.o
+
# graphics virtualization (SR-IOV) support
xe-y += \
xe_gt_sriov_vf.o \
diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
new file mode 100644
index 000000000000..8b52752c067f
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_cper.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <linux/err.h>
+#include <linux/minmax.h>
+
+#include "xe_cper.h"
+#include "xe_device.h"
+#include "xe_ras_types.h"
+
+static bool is_hw_sigid(enum xe_sigid sigid)
+{
+ return in_range(sigid, INTEL_SIGID_GPU_XE_HARDWARE_START, INTEL_SIGID_BATCH);
+}
+
+static void cper_emit_hw_err(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
+ const struct xe_ras_error_class *counter)
+{
+ /* TODO */
+}
+
+/**
+ * xe_cper_emit() - Emit a CPER record for a SIGID log entry
+ * @xe: The &xe_device
+ * @cper_sev: CPER severity
+ * @sigid: Error signature identifier
+ * @component: Component identifier
+ * @location: Location details of the @component
+ * @data: Pointer to the additional details, or ERR_PTR, or NULL if not applicable
+ * @len: Length of the @data in bytes, or 0 if not applicable
+ * @vaf: Formatted log message
+ *
+ * Emit a CPER record for a SIGID log entry
+ */
+void xe_cper_emit(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
+ u32 component, u32 location, const void *data, size_t len,
+ struct va_format *vaf)
+{
+ if (is_hw_sigid(sigid)) {
+ if (!IS_ERR_OR_NULL(data))
+ cper_emit_hw_err(xe, cper_sev, sigid, data);
+ return;
+ }
+
+ /* TODO software CPER */
+}
diff --git a/drivers/gpu/drm/xe/xe_cper.h b/drivers/gpu/drm/xe/xe_cper.h
new file mode 100644
index 000000000000..84676c7645a5
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_cper.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_CPER_H_
+#define _XE_CPER_H_
+
+#include <linux/types.h>
+
+#include "abi/xe_sigid_abi.h"
+
+struct va_format;
+struct xe_device;
+
+#if IS_ENABLED(CONFIG_UEFI_CPER)
+void xe_cper_emit(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
+ u32 component, u32 location, const void *data, size_t len,
+ struct va_format *vaf);
+#else
+static inline void xe_cper_emit(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
+ u32 component, u32 location, const void *data, size_t len,
+ struct va_format *vaf) {}
+#endif
+
+#endif /* _XE_CPER_H_ */
diff --git a/drivers/gpu/drm/xe/xe_log.c b/drivers/gpu/drm/xe/xe_log.c
index 29eb16db3320..80e2b1724ceb 100644
--- a/drivers/gpu/drm/xe/xe_log.c
+++ b/drivers/gpu/drm/xe/xe_log.c
@@ -8,6 +8,7 @@
#include "abi/xe_log_abi.h"
+#include "xe_cper.h"
#include "xe_device.h"
#include "xe_log.h"
#include "xe_pci_types.h"
@@ -19,7 +20,9 @@ static void log_emit_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigi
{
KUNIT_STATIC_STUB_REDIRECT(log_emit_cper, pdev, cper_sev, sigid,
component, location, data, len, vaf);
- /* TODO */
+
+ xe_cper_emit(xe_any_to_xe(pdev), cper_sev, sigid,
+ component, location, data, len, vaf);
}
static const char *log_unknown_component_prefix(u32 component)
--
2.54.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v5 02/13] drm/xe/cper: Retrieve the error counter record for CPER reporting
2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
` (2 preceding siblings ...)
2026-10-23 4:34 ` [PATCH v5 01/13] drm/xe/cper: Add CPER reporting entry point for xe_log Badal Nilawar
@ 2026-10-23 4:34 ` Badal Nilawar
2026-10-24 11:50 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 03/13] drm/xe/cper: Initialize Intel-specific section header Badal Nilawar
` (12 subsequent siblings)
16 siblings, 1 reply; 37+ messages in thread
From: Badal Nilawar @ 2026-10-23 4:34 UTC (permalink / raw)
To: intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
Retrieve error counter record required to build a CPER record.
Assisted-by: LLM
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
v5:
- Retain get_counter() (Raag)
v4:
- Drop redundant xe_ras_counter_is_valid() check (Raag)
- Add might_sleep() to assert that the caller is in a sleepable
context (sashiko)
- Add xe_device_assert_mem_access() to assert the outer runtime PM
wake reference requirement (sashiko)
---
drivers/gpu/drm/xe/xe_cper.c | 14 ++++++++++-
drivers/gpu/drm/xe/xe_ras.c | 47 +++++++++++++++++++++++++++---------
drivers/gpu/drm/xe/xe_ras.h | 2 ++
3 files changed, 51 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
index 8b52752c067f..a9044e708cac 100644
--- a/drivers/gpu/drm/xe/xe_cper.c
+++ b/drivers/gpu/drm/xe/xe_cper.c
@@ -4,10 +4,13 @@
*/
#include <linux/err.h>
+#include <linux/kernel.h>
#include <linux/minmax.h>
#include "xe_cper.h"
#include "xe_device.h"
+#include "xe_printk.h"
+#include "xe_ras.h"
#include "xe_ras_types.h"
static bool is_hw_sigid(enum xe_sigid sigid)
@@ -18,7 +21,16 @@ static bool is_hw_sigid(enum xe_sigid sigid)
static void cper_emit_hw_err(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
const struct xe_ras_error_class *counter)
{
- /* TODO */
+ struct xe_ras_get_counter_response response = {};
+
+ /* Fetching the counter sends a sysctrl command */
+ might_sleep();
+ xe_device_assert_mem_access(xe);
+
+ if (xe_ras_get_counter_response(xe, counter, &response)) {
+ xe_err(xe, "CPER: failed to get counter, skipping record\n");
+ return;
+ }
}
/**
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index db3cbc186a51..1da523c6e84c 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -528,8 +528,7 @@ static void ras_send_error_event(struct xe_device *xe, u8 severity, u8 component
{
struct xe_ras_error_class counter = {0};
u8 drm_severity, drm_component;
- u32 value;
- int ret;
+ u32 value; int ret;
counter.common.severity = severity;
counter.common.component = component;
@@ -676,19 +675,46 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe,
}
}
-static int get_counter(struct xe_device *xe, struct xe_ras_error_class *counter, u32 *value)
+static int get_counter(struct xe_device *xe,
+ struct xe_ras_error_class *counter,
+ u32 *value)
+{
+ struct xe_ras_get_counter_response response = {};
+ int ret;
+
+ ret = xe_ras_get_counter_response(xe, counter, &response);
+ if (ret)
+ return ret;
+
+ *value = response.value;
+
+ return 0;
+}
+
+/**
+ * xe_ras_get_counter_response() - Get error counter record
+ * @xe: Xe device instance
+ * @counter: RAS error class
+ * @out: Counter record retrieved
+ *
+ * Retrieve the counter record of a specific error class from firmware.
+ *
+ * Return: 0 on success, negative error code on failure.
+ */
+int xe_ras_get_counter_response(struct xe_device *xe, const struct xe_ras_error_class *counter,
+ struct xe_ras_get_counter_response *out)
{
- struct xe_ras_get_counter_response response = {0};
struct xe_ras_get_counter_request request = {0};
struct xe_sysctrl_mailbox_command command = {0};
struct xe_ras_error_common *common;
size_t rlen;
int ret;
+ memset(out, 0, sizeof(*out));
request.counter = *counter;
xe_sysctrl_create_command(&command, XE_SYSCTRL_GROUP_GFSP, XE_SYSCTRL_CMD_GET_COUNTER,
- &request, sizeof(request), &response, sizeof(response));
+ &request, sizeof(request), out, sizeof(*out));
ret = xe_sysctrl_send_command(&xe->sc, &command, &rlen);
if (ret) {
@@ -696,19 +722,18 @@ static int get_counter(struct xe_device *xe, struct xe_ras_error_class *counter,
return ret;
}
- if (rlen != sizeof(response)) {
+ if (rlen != sizeof(*out)) {
xe_err(xe, "sysctrl: unexpected get counter response length %zu (expected %zu)\n",
- rlen, sizeof(response));
+ rlen, sizeof(*out));
return -EIO;
}
- if (!ras_counter_is_valid(xe, &response.counter))
+ if (!ras_counter_is_valid(xe, &out->counter))
return -EBADMSG;
- common = &response.counter.common;
- *value = response.value;
+ common = &out->counter.common;
- xe_dbg(xe, "[RAS]: get counter %u for %s %s\n", *value, comp_to_str(common->component),
+ xe_dbg(xe, "[RAS]: get counter %u for %s %s\n", out->value, comp_to_str(common->component),
sev_to_str(common->severity));
return 0;
diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
index 1b358c7d040f..c736d5a01c47 100644
--- a/drivers/gpu/drm/xe/xe_ras.h
+++ b/drivers/gpu/drm/xe/xe_ras.h
@@ -23,5 +23,7 @@ int xe_ras_init(struct xe_device *xe);
enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe);
bool xe_ras_get_disable_vram_page_offline(struct xe_device *xe);
u32 xe_ras_get_max_pages(struct xe_device *xe);
+int xe_ras_get_counter_response(struct xe_device *xe, const struct xe_ras_error_class *counter,
+ struct xe_ras_get_counter_response *out);
#endif
--
2.54.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v5 03/13] drm/xe/cper: Initialize Intel-specific section header
2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
` (3 preceding siblings ...)
2026-10-23 4:34 ` [PATCH v5 02/13] drm/xe/cper: Retrieve the error counter record for CPER reporting Badal Nilawar
@ 2026-10-23 4:34 ` Badal Nilawar
2026-10-23 4:30 ` sashiko-bot
2026-10-26 5:57 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 04/13] drm/xe/cper: Construct CPER record for hardware errors Badal Nilawar
` (11 subsequent siblings)
16 siblings, 2 replies; 37+ messages in thread
From: Badal Nilawar @ 2026-10-23 4:34 UTC (permalink / raw)
To: intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
Define the Intel-specific CPER header and initialize it
from the error counter record for Intel GPU hardware errors.
Assisted-by: LLM
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
v5:
- Move xe_cper_emit_counter() from patch 7 of rev4 to this patch to
avoid code churn (Raag)
- Use __packed for individual structures instead of #pragma pack (Raag)
- Drop redundent 'err'/'error' references, shorten structure name (Raag)
v4:
- Split from "drm/xe/cper: Prepare CPER record" (Raag)
- Add dedicated struct xe_cper_error_class (Michal)
- Drop empty fill_fw_id() stub, leave a TODO instead
v2:
- Guard against NULL THIS_MODULE->srcversion (sashiko)
---
drivers/gpu/drm/xe/xe_cper.c | 52 ++++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_cper_types.h | 51 +++++++++++++++++++++++++++++
2 files changed, 103 insertions(+)
create mode 100644 drivers/gpu/drm/xe/xe_cper_types.h
diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
index a9044e708cac..3d7657517223 100644
--- a/drivers/gpu/drm/xe/xe_cper.c
+++ b/drivers/gpu/drm/xe/xe_cper.c
@@ -6,18 +6,68 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/minmax.h>
+#include <linux/pci.h>
#include "xe_cper.h"
+#include "xe_cper_types.h"
#include "xe_device.h"
#include "xe_printk.h"
#include "xe_ras.h"
#include "xe_ras_types.h"
+static bool is_valid_sigid(u32 sigid)
+{
+ return sigid != U32_MAX;
+}
+
static bool is_hw_sigid(enum xe_sigid sigid)
{
return in_range(sigid, INTEL_SIGID_GPU_XE_HARDWARE_START, INTEL_SIGID_BATCH);
}
+static void cper_init_intel_hdr(struct xe_device *xe,
+ const struct xe_ras_error_class *counter,
+ u64 first_timestamp, u32 sig_id, u32 error_count,
+ struct xe_cper_intel_hdr *ihdr)
+{
+ ihdr->counter = *counter;
+ ihdr->validation_bits |= XE_CPER_VALID_LOCATION;
+
+ if (first_timestamp) {
+ ihdr->first_timestamp = first_timestamp;
+ ihdr->validation_bits |= XE_CPER_VALID_FIRST_TIMESTAMP;
+ }
+
+ if (is_valid_sigid(sig_id)) {
+ ihdr->sig_id = sig_id;
+ ihdr->validation_bits |= XE_CPER_VALID_SIG_ID;
+ }
+
+ ihdr->error_count = error_count;
+
+ strscpy(ihdr->pci_bdf, pci_name(to_pci_dev(xe->drm.dev)), sizeof(ihdr->pci_bdf));
+ ihdr->validation_bits |= XE_CPER_VALID_PCI_BDF;
+
+#ifdef MODULE
+ if (THIS_MODULE->srcversion) {
+ strscpy(ihdr->drv_version, THIS_MODULE->srcversion, sizeof(ihdr->drv_version));
+ ihdr->validation_bits |= XE_CPER_VALID_DRV_VERSION;
+ }
+#endif
+
+ /* TODO: fill fw_id and set XE_CPER_VALID_FW_ID */
+}
+
+static void cper_emit_counter(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
+ const struct xe_ras_error_class *counter,
+ const struct xe_ras_get_counter_response *response)
+{
+ struct xe_cper_intel_hdr ihdr = {};
+
+ cper_init_intel_hdr(xe, counter, response->timestamp,
+ sigid, response->value, &ihdr);
+}
+
static void cper_emit_hw_err(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
const struct xe_ras_error_class *counter)
{
@@ -31,6 +81,8 @@ static void cper_emit_hw_err(struct xe_device *xe, int cper_sev, enum xe_sigid s
xe_err(xe, "CPER: failed to get counter, skipping record\n");
return;
}
+
+ cper_emit_counter(xe, cper_sev, sigid, counter, &response);
}
/**
diff --git a/drivers/gpu/drm/xe/xe_cper_types.h b/drivers/gpu/drm/xe/xe_cper_types.h
new file mode 100644
index 000000000000..a8730ff62b69
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_cper_types.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_CPER_TYPES_H_
+#define _XE_CPER_TYPES_H_
+
+#include <linux/types.h>
+
+#include "xe_ras_types.h"
+
+/*
+ * Validation bits definition for validation_bits in struct
+ * xe_cper_intel_hdr. When set, corresponding fields in header
+ * contains valid data
+ */
+#define XE_CPER_VALID_LOCATION 0x0001
+#define XE_CPER_VALID_FIRST_TIMESTAMP 0x0002
+#define XE_CPER_VALID_SIG_ID 0x0004
+#define XE_CPER_VALID_PCI_BDF 0x0008
+#define XE_CPER_VALID_DRV_VERSION 0x0010
+
+/**
+ * struct xe_cper_intel_hdr - Intel-specific CPER header
+ *
+ * Fixed-size header for the Intel GPU error section of a CPER record.
+ * All multi-byte fields are little-endian.
+ */
+struct xe_cper_intel_hdr {
+ /** @counter: Error class (severity, component, location, cause) */
+ struct xe_ras_error_class counter;
+ /** @first_timestamp: First occurrence of this error class, in ticks */
+ u64 first_timestamp;
+ /** @sig_id: Aggregated error class SIG ID; set to U32_MAX if unknown */
+ u32 sig_id;
+ /** @error_count: Number of times this error has been observed */
+ u32 error_count;
+ /** @validation_bits: Raw u16 view of all valid bits */
+ u16 validation_bits;
+ /** @pci_bdf: PCI location string, format "DDDD:bb:dd.f" */
+ char pci_bdf[16];
+ /** @drv_version: Driver source version string (THIS_MODULE->srcversion) */
+ char drv_version[25];
+ /** @fw_id: Firmware version string (GFSP+PCODE+CSC+GUC or MNG+NUC+RAS+GUC) */
+ char fw_id[256];
+ /** @reserved: Reserved for future use, must be zero */
+ u8 reserved[5];
+} __packed;
+
+#endif
--
2.54.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v5 04/13] drm/xe/cper: Construct CPER record for hardware errors
2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
` (4 preceding siblings ...)
2026-10-23 4:34 ` [PATCH v5 03/13] drm/xe/cper: Initialize Intel-specific section header Badal Nilawar
@ 2026-10-23 4:34 ` Badal Nilawar
2026-10-26 9:54 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 05/13] drm/xe/cper: Log CPER records for aggregate counter retrieval Badal Nilawar
` (10 subsequent siblings)
16 siblings, 1 reply; 37+ messages in thread
From: Badal Nilawar @ 2026-10-23 4:34 UTC (permalink / raw)
To: intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
Assemble the CPER record header, section descriptor and the Intel
error section for Intel GPU hardware errors.
Assisted-by: LLM
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
v5:
- Rebased
- Add helpers to initialize CPER headers (Raag)
v4:
- Split from "drm/xe/cper: Prepare CPER record" (Raag)
- Use xe->device_uid for FRU ID
- Add platform IDs for all CRI PCI device IDs
v2:
- Encode cper_record_header timestamp in BCD format (sashiko)
---
drivers/gpu/drm/xe/xe_cper.c | 139 +++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_cper_types.h | 53 +++++++++++
2 files changed, 192 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
index 3d7657517223..012693fe48c4 100644
--- a/drivers/gpu/drm/xe/xe_cper.c
+++ b/drivers/gpu/drm/xe/xe_cper.c
@@ -3,10 +3,14 @@
* Copyright © 2026 Intel Corporation
*/
+#include <linux/bcd.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/minmax.h>
#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/time.h>
+#include <linux/timekeeping.h>
#include "xe_cper.h"
#include "xe_cper_types.h"
@@ -25,6 +29,60 @@ static bool is_hw_sigid(enum xe_sigid sigid)
return in_range(sigid, INTEL_SIGID_GPU_XE_HARDWARE_START, INTEL_SIGID_BATCH);
}
+static const struct xe_platform_id_entry xe_platform_ids[] = {
+ /* 0x674C platform/8086:674c */
+ { 0x674C, GUID_INIT(0x9046afe5, 0x9041, 0x5124,
+ 0x86, 0x14, 0x92, 0x55, 0x0d, 0x9e, 0x9d, 0xa6) },
+ /* 0x674D platform/8086:674d */
+ { 0x674D, GUID_INIT(0xf95911b8, 0x6564, 0x5905,
+ 0xa6, 0xa7, 0xb9, 0xbf, 0x54, 0xab, 0x6c, 0x27) },
+ /* 0x674E platform/8086:674e */
+ { 0x674E, GUID_INIT(0xb8d24106, 0x0108, 0x59f1,
+ 0x8f, 0xfc, 0x9f, 0xc4, 0xa9, 0xc9, 0xb7, 0xb0) },
+ /* 0x674F platform/8086:674f */
+ { 0x674F, GUID_INIT(0xdd8dd88e, 0xef2f, 0x59b1,
+ 0x99, 0x15, 0xdb, 0x6f, 0x1d, 0xc9, 0xb4, 0x5d) },
+ /* 0x6750 platform/8086:6750 */
+ { 0x6750, GUID_INIT(0x1dd66c44, 0x87d5, 0x524a,
+ 0xad, 0x6e, 0xfc, 0x18, 0x9d, 0x42, 0x6f, 0x1a) },
+ /* 0x6751 platform/8086:6751 */
+ { 0x6751, GUID_INIT(0x17d0dd04, 0x2fad, 0x5400,
+ 0x99, 0xc8, 0x9b, 0x45, 0x51, 0x3b, 0x67, 0xe3) },
+};
+
+static const guid_t *lookup_platform_id(const struct pci_dev *pdev)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(xe_platform_ids); i++)
+ if (xe_platform_ids[i].device_id == pdev->device)
+ return &xe_platform_ids[i].platform_id;
+ return NULL;
+}
+
+static u64 cper_timestamp_now(void)
+{
+ struct tm tm;
+ u64 ts = 0;
+ u8 *p = (u8 *)&ts;
+ int year;
+
+ time64_to_tm(ktime_get_real_seconds(), 0, &tm);
+
+ year = tm.tm_year + 1900;
+
+ p[0] = bin2bcd(tm.tm_sec);
+ p[1] = bin2bcd(tm.tm_min);
+ p[2] = bin2bcd(tm.tm_hour);
+ p[3] = 0x1; /* precise time */
+ p[4] = bin2bcd(tm.tm_mday);
+ p[5] = bin2bcd(tm.tm_mon + 1);
+ p[6] = bin2bcd(year % 100);
+ p[7] = bin2bcd(year / 100);
+
+ return ts;
+}
+
static void cper_init_intel_hdr(struct xe_device *xe,
const struct xe_ras_error_class *counter,
u64 first_timestamp, u32 sig_id, u32 error_count,
@@ -58,6 +116,86 @@ static void cper_init_intel_hdr(struct xe_device *xe,
/* TODO: fill fw_id and set XE_CPER_VALID_FW_ID */
}
+static void cper_init_record_hdr(struct xe_device *xe, u8 severity,
+ const guid_t *notification_type,
+ struct cper_record_header *rhdr,
+ u32 total_len)
+{
+ const guid_t *platform_id;
+ struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+
+ /* Assemble the CPER record header (UEFI Appendix N.2.1) */
+ memcpy(rhdr->signature, CPER_SIG_RECORD, CPER_SIG_SIZE);
+ rhdr->revision = CPER_RECORD_REV;
+ rhdr->signature_end = CPER_SIG_END;
+ rhdr->section_count = 1;
+ rhdr->error_severity = severity;
+ rhdr->validation_bits = CPER_VALID_TIMESTAMP;
+ rhdr->record_length = total_len;
+ rhdr->timestamp = cper_timestamp_now();
+ rhdr->creator_id = INTEL_CPER_CREATOR_XEKMD;
+ rhdr->notification_type = *notification_type;
+ rhdr->record_id = cper_next_record_id();
+ platform_id = lookup_platform_id(pdev);
+ if (platform_id) {
+ rhdr->platform_id = *platform_id;
+ rhdr->validation_bits |= CPER_VALID_PLATFORM_ID;
+ }
+}
+
+static void cper_init_section_desc(struct xe_device *xe, u8 severity,
+ struct cper_section_descriptor *sdesc,
+ u32 einfo_len)
+{
+ sdesc->section_offset = sizeof(struct cper_record_header) +
+ sizeof(struct cper_section_descriptor);
+ sdesc->section_length = sizeof(struct xe_cper_intel_hdr) + einfo_len;
+ sdesc->revision = CPER_SEC_REV;
+ sdesc->validation_bits = 0;
+ sdesc->section_type = INTEL_CPER_SECTION_ACCEL_GENERIC;
+ sdesc->section_severity = severity;
+ if (xe->info.has_device_uid) {
+ memcpy(&sdesc->fru_id, &xe->device_uid, sizeof(xe->device_uid));
+ sdesc->validation_bits |= CPER_SEC_VALID_FRU_ID;
+ }
+}
+
+static void cper_record_emit(struct xe_device *xe, u8 severity,
+ const guid_t *notification_type,
+ const struct xe_cper_intel_hdr *ihdr,
+ const void *einfo, u32 einfo_len)
+{
+ struct cper_section_descriptor *sdesc;
+ struct cper_record_header *rhdr;
+ struct xe_cper_nonstd_record *rec;
+ u32 total_len;
+
+ total_len = sizeof(struct xe_cper_nonstd_record) + einfo_len;
+ rec = kzalloc(total_len, GFP_KERNEL);
+ if (!rec)
+ return;
+
+ rhdr = &rec->record_hdr;
+ sdesc = &rec->section_desc;
+
+ /* Assemble the CPER record header (UEFI Appendix N.2.1) */
+ cper_init_record_hdr(xe, severity, notification_type, rhdr, total_len);
+
+ /* Assemble the section descriptor (UEFI Appendix N.2.2) */
+ cper_init_section_desc(xe, severity, sdesc, einfo_len);
+
+ /* Copy the Intel-specific section header */
+ rec->intel_hdr = *ihdr;
+
+ /* Append optional variable-length error info */
+ if (einfo && einfo_len)
+ memcpy((u8 *)rec + sizeof(*rec), einfo, einfo_len);
+
+ /* TODO: Emit trace event */
+
+ kfree(rec);
+}
+
static void cper_emit_counter(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
const struct xe_ras_error_class *counter,
const struct xe_ras_get_counter_response *response)
@@ -66,6 +204,7 @@ static void cper_emit_counter(struct xe_device *xe, int cper_sev, enum xe_sigid
cper_init_intel_hdr(xe, counter, response->timestamp,
sigid, response->value, &ihdr);
+ cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR, &ihdr, NULL, 0);
}
static void cper_emit_hw_err(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
diff --git a/drivers/gpu/drm/xe/xe_cper_types.h b/drivers/gpu/drm/xe/xe_cper_types.h
index a8730ff62b69..e32c7d539257 100644
--- a/drivers/gpu/drm/xe/xe_cper_types.h
+++ b/drivers/gpu/drm/xe/xe_cper_types.h
@@ -6,7 +6,9 @@
#ifndef _XE_CPER_TYPES_H_
#define _XE_CPER_TYPES_H_
+#include <linux/cper.h>
#include <linux/types.h>
+#include <linux/uuid.h>
#include "xe_ras_types.h"
@@ -21,6 +23,28 @@
#define XE_CPER_VALID_PCI_BDF 0x0008
#define XE_CPER_VALID_DRV_VERSION 0x0010
+/*
+ * Intel CPER GUID Namespace — RFC 9562 UUIDv5 (SHA-1 name-based)
+ *
+ * All values below are generated deterministically by uuid generator.
+ * Do not hand-edit the byte values.
+ */
+
+/* Creator IDs */
+#define INTEL_CPER_CREATOR_XEKMD \
+ GUID_INIT(0x9a42070f, 0xdf9d, 0x555e, \
+ 0xba, 0x02, 0x7c, 0xbc, 0x86, 0x3d, 0x37, 0x1c)
+
+/* Notification Types */
+#define INTEL_CPER_NOTIFY_GPU_ERROR \
+ GUID_INIT(0x4ae12aef, 0x8745, 0x5fc7, \
+ 0xb9, 0x96, 0x71, 0xee, 0xbb, 0x51, 0xf2, 0x23)
+
+/* Section Types */
+#define INTEL_CPER_SECTION_ACCEL_GENERIC \
+ GUID_INIT(0xea9d8f84, 0x4258, 0x5227, \
+ 0x80, 0x28, 0xb9, 0xb1, 0x3e, 0x6d, 0x58, 0xb0)
+
/**
* struct xe_cper_intel_hdr - Intel-specific CPER header
*
@@ -48,4 +72,33 @@ struct xe_cper_intel_hdr {
u8 reserved[5];
} __packed;
+/**
+ * struct xe_cper_nonstd_record - Intel GPU CPER record
+ *
+ * Contains the standard CPER record header, section descriptor, and the
+ * Intel error section header.
+ */
+struct xe_cper_nonstd_record {
+ /** @record_hdr: Standard CPER record header (UEFI Appendix N.2.1) */
+ struct cper_record_header record_hdr;
+ /** @section_desc: CPER section descriptor */
+ struct cper_section_descriptor section_desc;
+ /** @intel_hdr: Intel-specific CPER header */
+ struct xe_cper_intel_hdr intel_hdr;
+} __packed;
+
+/**
+ * struct xe_platform_id_entry - Mapping from PCI device ID to CPER platform GUID
+ *
+ * Used to resolve the platform_id field in a CPER section descriptor.
+ * GUIDs are UUIDv5 (RFC 9562, SHA-1) derived from the Intel CPER namespace
+ * with name string "platform/8086:<dev_id_hex_lower>".
+ */
+struct xe_platform_id_entry {
+ /** @device_id: PCI device ID */
+ u16 device_id;
+ /** @platform_id: Corresponding UUIDv5 platform GUID */
+ guid_t platform_id;
+};
+
#endif
--
2.54.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v5 05/13] drm/xe/cper: Log CPER records for aggregate counter retrieval
2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
` (5 preceding siblings ...)
2026-10-23 4:34 ` [PATCH v5 04/13] drm/xe/cper: Construct CPER record for hardware errors Badal Nilawar
@ 2026-10-23 4:34 ` Badal Nilawar
2026-10-26 11:31 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 06/13] drm/xe/cper: Emit cper record to trace buf Badal Nilawar
` (9 subsequent siblings)
16 siblings, 1 reply; 37+ messages in thread
From: Badal Nilawar @ 2026-10-23 4:34 UTC (permalink / raw)
To: intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
Log CPER records for aggregate counter retrieval from userspace when
cper_on_query sysfs is enabled.
Assisted-by: LLM
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
v5:
- Refactor get_counter() to conditionally emit cper (Raag)
v4:
- Add xe_cper_emit_counter() to emit records from the counter response
already fetched for userspace, instead of fetching it again
- Move cper_on_query to struct xe_cper and xe_cper.c (Raag)
- Document cper_on_query sysfs in ABI
- Fix sysfs attribute cper_on_query permissions (sashiko)
---
.../ABI/testing/sysfs-driver-intel-xe-cper | 18 +++++
drivers/gpu/drm/xe/xe_cper.c | 67 +++++++++++++++++--
drivers/gpu/drm/xe/xe_cper.h | 11 +++
drivers/gpu/drm/xe/xe_cper_types.h | 8 +++
drivers/gpu/drm/xe/xe_device_types.h | 4 ++
drivers/gpu/drm/xe/xe_ras.c | 51 ++++++++++++--
6 files changed, 150 insertions(+), 9 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-xe-cper
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-cper b/Documentation/ABI/testing/sysfs-driver-intel-xe-cper
new file mode 100644
index 000000000000..19f56d2c0ab3
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-cper
@@ -0,0 +1,18 @@
+What: /sys/bus/pci/drivers/xe/.../cper_on_query
+Date: October 2026
+KernelVersion: 7.4
+Contact: intel-xe@lists.freedesktop.org
+Description:
+ This file controls whether a CPER (Common Platform Error Record)
+ is emitted each time a RAS error counter is queried.
+
+ This sysfs file is present only on Intel Xe platforms that support
+ the RAS error counter interface and when the kernel is built with
+ CPER support. Reading the current setting is available to all
+ users, while updating it is restricted to administrative users
+ only.
+
+ The value is a boolean. When set to 1, every counter query emits
+ a CPER record built from the counter and its associated info
+ queue data. When set to 0 (default), no record is emitted on
+ query.
diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
index 012693fe48c4..0ead6237bbb4 100644
--- a/drivers/gpu/drm/xe/xe_cper.c
+++ b/drivers/gpu/drm/xe/xe_cper.c
@@ -4,11 +4,13 @@
*/
#include <linux/bcd.h>
+#include <linux/device.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/minmax.h>
#include <linux/pci.h>
#include <linux/slab.h>
+#include <linux/sysfs.h>
#include <linux/time.h>
#include <linux/timekeeping.h>
@@ -196,12 +198,24 @@ static void cper_record_emit(struct xe_device *xe, u8 severity,
kfree(rec);
}
-static void cper_emit_counter(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
- const struct xe_ras_error_class *counter,
- const struct xe_ras_get_counter_response *response)
+/**
+ * xe_cper_emit_counter() - Emit CPER records for an already fetched error counter
+ * @xe: The &xe_device
+ * @cper_sev: CPER severity
+ * @sigid: Error signature identifier
+ * @counter: RAS error class
+ * @response: Counter response returned by firmware for @counter
+ *
+ * Build and emit a CPER record from @response.
+ */
+void xe_cper_emit_counter(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
+ const struct xe_ras_error_class *counter,
+ const struct xe_ras_get_counter_response *response)
{
struct xe_cper_intel_hdr ihdr = {};
+ xe_assert(xe, is_hw_sigid(sigid));
+
cper_init_intel_hdr(xe, counter, response->timestamp,
sigid, response->value, &ihdr);
cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR, &ihdr, NULL, 0);
@@ -221,7 +235,7 @@ static void cper_emit_hw_err(struct xe_device *xe, int cper_sev, enum xe_sigid s
return;
}
- cper_emit_counter(xe, cper_sev, sigid, counter, &response);
+ xe_cper_emit_counter(xe, cper_sev, sigid, counter, &response);
}
/**
@@ -249,3 +263,48 @@ void xe_cper_emit(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
/* TODO software CPER */
}
+
+static ssize_t cper_on_query_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct xe_device *xe = kdev_to_xe_device(dev);
+
+ return sysfs_emit(buf, "%u\n", READ_ONCE(xe->cper.on_query));
+}
+
+static ssize_t cper_on_query_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct xe_device *xe = kdev_to_xe_device(dev);
+ bool enable;
+ int ret;
+
+ ret = kstrtobool(buf, &enable);
+ if (ret)
+ return ret;
+
+ WRITE_ONCE(xe->cper.on_query, enable);
+
+ return count;
+}
+static DEVICE_ATTR_RW(cper_on_query);
+
+static struct attribute *cper_attrs[] = {
+ &dev_attr_cper_on_query.attr,
+ NULL
+};
+
+/* See Documentation/ABI/testing/sysfs-driver-intel-xe-cper */
+static const struct attribute_group cper_group = {
+ .attrs = cper_attrs,
+};
+
+/**
+ * xe_cper_sysfs_init() - Create the CPER sysfs attributes
+ * @xe: The &xe_device
+ *
+ * Return: 0 on success, negative error code on failure.
+ */
+int xe_cper_sysfs_init(struct xe_device *xe)
+{
+ return devm_device_add_group(xe->drm.dev, &cper_group);
+}
diff --git a/drivers/gpu/drm/xe/xe_cper.h b/drivers/gpu/drm/xe/xe_cper.h
index 84676c7645a5..ad50349c0a6f 100644
--- a/drivers/gpu/drm/xe/xe_cper.h
+++ b/drivers/gpu/drm/xe/xe_cper.h
@@ -12,15 +12,26 @@
struct va_format;
struct xe_device;
+struct xe_ras_error_class;
+struct xe_ras_get_counter_response;
#if IS_ENABLED(CONFIG_UEFI_CPER)
void xe_cper_emit(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
u32 component, u32 location, const void *data, size_t len,
struct va_format *vaf);
+void xe_cper_emit_counter(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
+ const struct xe_ras_error_class *error_class,
+ const struct xe_ras_get_counter_response *resp);
+int xe_cper_sysfs_init(struct xe_device *xe);
#else
static inline void xe_cper_emit(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
u32 component, u32 location, const void *data, size_t len,
struct va_format *vaf) {}
+static inline void xe_cper_emit_counter(struct xe_device *xe, int cper_sev,
+ enum xe_sigid sigid,
+ const struct xe_ras_error_class *error_class,
+ const struct xe_ras_get_counter_response *resp) {}
+static inline int xe_cper_sysfs_init(struct xe_device *xe) { return 0; }
#endif
#endif /* _XE_CPER_H_ */
diff --git a/drivers/gpu/drm/xe/xe_cper_types.h b/drivers/gpu/drm/xe/xe_cper_types.h
index e32c7d539257..107688b17d17 100644
--- a/drivers/gpu/drm/xe/xe_cper_types.h
+++ b/drivers/gpu/drm/xe/xe_cper_types.h
@@ -101,4 +101,12 @@ struct xe_platform_id_entry {
guid_t platform_id;
};
+/**
+ * struct xe_cper - Xe CPER state
+ */
+struct xe_cper {
+ /** @on_query: Emit a CPER record on each RAS counter query */
+ bool on_query;
+};
+
#endif
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 6a6f9a24365c..b98418795d5e 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -12,6 +12,7 @@
#include <drm/drm_file.h>
#include <drm/ttm/ttm_device.h>
+#include "xe_cper_types.h"
#include "xe_devcoredump_types.h"
#include "xe_drm_ras_types.h"
#include "xe_heci_gsc.h"
@@ -566,6 +567,9 @@ struct xe_device {
struct xe_ras_state state;
} ras;
+ /** @cper: CPER state */
+ struct xe_cper cper;
+
/** @i2c: I2C host controller */
struct xe_i2c *i2c;
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 1da523c6e84c..95e87c635b04 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -6,6 +6,7 @@
#include "xe_assert.h"
#include "xe_bo.h"
#include "xe_configfs.h"
+#include "xe_cper.h"
#include "xe_debugfs.h"
#include "xe_device.h"
#include "xe_drm_ras.h"
@@ -110,7 +111,8 @@ static const char * const gpu_health_states[] = {
};
static_assert(ARRAY_SIZE(gpu_health_states) == XE_RAS_HEALTH_MAX);
-static int get_counter(struct xe_device *xe, struct xe_ras_error_class *counter, u32 *value);
+static int get_counter(struct xe_device *xe, struct xe_ras_error_class *counter,
+ u32 *value, bool emit_cper);
static u8 drm_to_xe_ras_severity(u8 severity)
{
@@ -192,6 +194,38 @@ static int ras_status_to_errno(u32 status)
}
}
+static enum xe_sigid ras_comp_to_hw_sigid(u8 component)
+{
+ switch (component) {
+ case XE_RAS_COMP_DEVICE_MEMORY:
+ return XE_SIGID_DEVICE_MEMORY;
+ case XE_RAS_COMP_CORE_COMPUTE:
+ return XE_SIGID_CORE_COMPUTE;
+ case XE_RAS_COMP_PCIE:
+ return XE_SIGID_PCIE;
+ case XE_RAS_COMP_FABRIC:
+ return XE_SIGID_FABRIC;
+ case XE_RAS_COMP_SOC_INTERNAL:
+ return XE_SIGID_SOC_INTERNAL;
+ default:
+ return XE_SIGID_HW;
+ }
+}
+
+static u8 ras_sev_to_cper_sev(u8 ras_sev)
+{
+ switch (ras_sev) {
+ case XE_RAS_SEV_CORRECTABLE:
+ return CPER_SEV_CORRECTED;
+ case XE_RAS_SEV_UNCORRECTABLE:
+ return CPER_SEV_RECOVERABLE;
+ case XE_RAS_SEV_INFORMATIONAL:
+ return CPER_SEV_INFORMATIONAL;
+ default:
+ return CPER_SEV_RECOVERABLE;
+ }
+}
+
static inline const char *sev_to_str(u8 severity)
{
if (severity >= XE_RAS_SEV_MAX)
@@ -533,7 +567,7 @@ static void ras_send_error_event(struct xe_device *xe, u8 severity, u8 component
counter.common.severity = severity;
counter.common.component = component;
- ret = get_counter(xe, &counter, &value);
+ ret = get_counter(xe, &counter, &value, false);
if (ret)
return;
@@ -677,7 +711,7 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe,
static int get_counter(struct xe_device *xe,
struct xe_ras_error_class *counter,
- u32 *value)
+ u32 *value, bool emit_cper)
{
struct xe_ras_get_counter_response response = {};
int ret;
@@ -687,7 +721,10 @@ static int get_counter(struct xe_device *xe,
return ret;
*value = response.value;
-
+ if (emit_cper)
+ xe_cper_emit_counter(xe, ras_sev_to_cper_sev(counter->common.severity),
+ ras_comp_to_hw_sigid(counter->common.component),
+ counter, &response);
return 0;
}
@@ -869,7 +906,7 @@ int xe_ras_get_counter(struct xe_device *xe, u8 severity, u8 component, u32 *val
counter.common.component = drm_to_xe_ras_component(component);
guard(xe_pm_runtime)(xe);
- return get_counter(xe, &counter, value);
+ return get_counter(xe, &counter, value, READ_ONCE(xe->cper.on_query));
}
/**
@@ -1248,5 +1285,9 @@ int xe_ras_init(struct xe_device *xe)
if (ret)
xe_err(xe, "Failed to create GPU health sysfs, err=%d\n", ret);
+ ret = xe_cper_sysfs_init(xe);
+ if (ret)
+ xe_err(xe, "Failed to create cper_on_query sysfs, err=%d\n", ret);
+
return devm_add_action_or_reset(xe->drm.dev, ras_fini, xe);
}
--
2.54.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v5 06/13] drm/xe/cper: Emit cper record to trace buf
2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
` (6 preceding siblings ...)
2026-10-23 4:34 ` [PATCH v5 05/13] drm/xe/cper: Log CPER records for aggregate counter retrieval Badal Nilawar
@ 2026-10-23 4:34 ` Badal Nilawar
2026-10-26 12:29 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 07/13] drm/xe/xe_ras: Report device memory errors using SIGID Badal Nilawar
` (8 subsequent siblings)
16 siblings, 1 reply; 37+ messages in thread
From: Badal Nilawar @ 2026-10-23 4:34 UTC (permalink / raw)
To: intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
Add the xe_error_cper tracepoint and emit each assembled CPER record
through it. Besides the raw record, the event carries the device name,
platform ID, FRU ID, severity and the Intel error section header, so
tools can pick up the records from the trace buffer.
Assisted-by: LLM
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
v5:
- Add example CPER trace
- Use %pUl for platform and FRU GUIDs (Sashiko)
v4:
- Build xe_trace_cper.o with CONFIG_UEFI_CPER instead of
CONFIG_UEFI_CPER_X86
---
drivers/gpu/drm/xe/Makefile | 3 +-
drivers/gpu/drm/xe/xe_cper.c | 15 ++++++-
drivers/gpu/drm/xe/xe_trace_cper.c | 9 +++++
drivers/gpu/drm/xe/xe_trace_cper.h | 65 ++++++++++++++++++++++++++++++
4 files changed, 90 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.c
create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index ec463018f77d..4377f60f5dab 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -169,7 +169,8 @@ xe-$(CONFIG_HWMON) += xe_hwmon.o
xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
xe-$(CONFIG_CONFIGFS_FS) += xe_configfs.o
-xe-$(CONFIG_UEFI_CPER) += xe_cper.o
+xe-$(CONFIG_UEFI_CPER) += xe_cper.o \
+ xe_trace_cper.o
# graphics virtualization (SR-IOV) support
xe-y += \
diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
index 0ead6237bbb4..cb4a15a036ac 100644
--- a/drivers/gpu/drm/xe/xe_cper.c
+++ b/drivers/gpu/drm/xe/xe_cper.c
@@ -20,6 +20,7 @@
#include "xe_printk.h"
#include "xe_ras.h"
#include "xe_ras_types.h"
+#include "xe_trace_cper.h"
static bool is_valid_sigid(u32 sigid)
{
@@ -193,7 +194,8 @@ static void cper_record_emit(struct xe_device *xe, u8 severity,
if (einfo && einfo_len)
memcpy((u8 *)rec + sizeof(*rec), einfo, einfo_len);
- /* TODO: Emit trace event */
+ trace_xe_error_cper(xe, &rhdr->platform_id, &sdesc->fru_id, severity,
+ &rec->intel_hdr, total_len, (u8 *)rec);
kfree(rec);
}
@@ -250,6 +252,17 @@ static void cper_emit_hw_err(struct xe_device *xe, int cper_sev, enum xe_sigid s
* @vaf: Formatted log message
*
* Emit a CPER record for a SIGID log entry
+ *
+ * Example trace output::
+ *
+ * xe_error_cper: dev=0000:03:00.0 severity=2
+ * platform_id=9046afe5-9041-5124-8614-92550d9e9da6
+ * fru_id=91befe38-2f61-3d7b-0000-000000000000
+ * intel_err_hdr_raw=
+ * 01 02 00 18 00 00 00 01 00 00 00 00 64 77 51 14 ...
+ * cper_len=1772
+ * cper_raw=
+ * 43 50 45 52 00 01 ff ff ff ff 01 00 02 00 00 00 ...
*/
void xe_cper_emit(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
u32 component, u32 location, const void *data, size_t len,
diff --git a/drivers/gpu/drm/xe/xe_trace_cper.c b/drivers/gpu/drm/xe/xe_trace_cper.c
new file mode 100644
index 000000000000..caea8783ab7c
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_trace_cper.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef __CHECKER__
+#define CREATE_TRACE_POINTS
+#include "xe_trace_cper.h"
+#endif
diff --git a/drivers/gpu/drm/xe/xe_trace_cper.h b/drivers/gpu/drm/xe/xe_trace_cper.h
new file mode 100644
index 000000000000..01c0a057aa60
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_trace_cper.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM xe
+
+#if !defined(_XE_TRACE_CPER_H_) || defined(TRACE_HEADER_MULTI_READ)
+#define _XE_TRACE_CPER_H_
+
+#include <linux/tracepoint.h>
+#include <linux/types.h>
+
+#include "xe_cper_types.h"
+#include "xe_device_types.h"
+
+#define __dev_name_xe(xe) dev_name((xe)->drm.dev)
+
+TRACE_EVENT(xe_error_cper,
+ TP_PROTO(struct xe_device *xe,
+ const guid_t *platform_id, const guid_t *fru_id,
+ const u8 severity,
+ const struct xe_cper_intel_hdr *ihdr,
+ u32 cper_len, const u8 *cper),
+ TP_ARGS(xe, platform_id, fru_id, severity, ihdr, cper_len, cper),
+
+ TP_STRUCT__entry(
+ __string(dev, __dev_name_xe(xe))
+ __array(char, platform_id, UUID_SIZE)
+ __array(char, fru_id, UUID_SIZE)
+ __field(u8, sev)
+ __array(u8, ihdr_raw, sizeof(struct xe_cper_intel_hdr))
+ __field(u32, cper_len)
+ __dynamic_array(u8, cper, cper_len)
+ ),
+
+ TP_fast_assign(
+ __assign_str(dev);
+ __entry->sev = severity;
+ memcpy(__entry->platform_id, platform_id, UUID_SIZE);
+ memcpy(__entry->fru_id, fru_id, UUID_SIZE);
+ memcpy(__entry->ihdr_raw, ihdr, sizeof(struct xe_cper_intel_hdr));
+ __entry->cper_len = cper_len;
+ memcpy(__get_dynamic_array(cper), cper, cper_len);
+ ),
+
+ TP_printk("dev=%s severity=%d platform_id=%pUl fru_id=%pUl intel_err_hdr_raw=%s cper_len=%u cper_raw=%s",
+ __get_str(dev), __entry->sev,
+ __entry->platform_id, __entry->fru_id,
+ __print_hex(__entry->ihdr_raw,
+ sizeof(struct xe_cper_intel_hdr)),
+ __entry->cper_len,
+ __print_hex(__get_dynamic_array(cper),
+ __entry->cper_len))
+);
+
+#endif
+
+/* This part must be outside protection */
+#undef TRACE_INCLUDE_PATH
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
+#define TRACE_INCLUDE_FILE xe_trace_cper
+#include <trace/define_trace.h>
--
2.54.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v5 07/13] drm/xe/xe_ras: Report device memory errors using SIGID
2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
` (7 preceding siblings ...)
2026-10-23 4:34 ` [PATCH v5 06/13] drm/xe/cper: Emit cper record to trace buf Badal Nilawar
@ 2026-10-23 4:34 ` Badal Nilawar
2026-10-26 12:47 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 08/13] drm/xe/xe_ras: Report core compute " Badal Nilawar
` (7 subsequent siblings)
16 siblings, 1 reply; 37+ messages in thread
From: Badal Nilawar @ 2026-10-23 4:34 UTC (permalink / raw)
To: intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
Use xe_log_comp_info helper to report device memory errors using the
corresponding SIGID.
Example:
xe 0000:03:00.0: [drm] SIGID=202 (020100020008002000300000)
DEVICE_MEMORY: Double-bit ECC error detected at sw address 0x63000
Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Cc: Riana Tauro <riana.tauro@intel.com>
---
v5:
- Log unknown memory errors
- Add example log in commit message (Raag)
---
drivers/gpu/drm/xe/xe_ras.c | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 95e87c635b04..5ebfc6e8dfc7 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -643,6 +643,7 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_array *arr)
{
struct xe_ras_memory_error *info = (void *)arr->details;
+ u8 cper_sev = ras_sev_to_cper_sev(arr->counter.common.severity);
int ret;
/*
@@ -654,17 +655,30 @@ static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_
*/
switch (info->category) {
case XE_RAS_MEMORY_POISON:
- xe_info(xe, "[RAS]: Poison error detected\n");
+ xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
+ "Poison error detected\n");
break;
case XE_RAS_MEMORY_DATA_PARITY:
- xe_info(xe, "[RAS]: Data parity error detected\n");
+ xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
+ "Data parity error detected\n");
break;
case XE_RAS_MEMORY_DB_ECC:
ret = handle_page_offline(xe, info->sw_address, true);
- if (ret)
+ if (ret) {
+ xe_log_comp(xe, cper_sev, DEVICE_MEMORY,
+ &arr->counter, sizeof(arr->counter),
+ "Failed to recover double-bit ECC error at sw address 0x%llx\n",
+ info->sw_address);
return XE_RAS_RECOVERY_ACTION_RESET;
+ }
+
+ xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
+ "Double-bit ECC error at sw address 0x%llx\n",
+ info->sw_address);
break;
default:
+ xe_log_comp(xe, cper_sev, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
+ "Unknown error detected\n");
return XE_RAS_RECOVERY_ACTION_RESET;
}
--
2.54.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v5 08/13] drm/xe/xe_ras: Report core compute errors using SIGID
2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
` (8 preceding siblings ...)
2026-10-23 4:34 ` [PATCH v5 07/13] drm/xe/xe_ras: Report device memory errors using SIGID Badal Nilawar
@ 2026-10-23 4:34 ` Badal Nilawar
2026-10-23 6:24 ` Mallesh, Koujalagi
2026-10-27 12:43 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 09/13] drm/xe/xe_ras: Report soc internal " Badal Nilawar
` (6 subsequent siblings)
16 siblings, 2 replies; 37+ messages in thread
From: Badal Nilawar @ 2026-10-23 4:34 UTC (permalink / raw)
To: intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
Use xe_log_* helpers to report core compute errors.
Example:
xe 0000:03:00.0: [drm] *ERROR* SIGID=203 (02020012000a000200000800)
[Hardware Error]: CORE_COMPUTE: Uncorrectable error detected, type 2
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Cc: Riana Tauro <riana.tauro@intel.com>
---
v5:
- Print uncorr error type in sig id log (Riana)
v2:
- Pass RAS firmware reported severity to xe_log
---
drivers/gpu/drm/xe/xe_ras.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 5ebfc6e8dfc7..1f94dd1fb91b 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -577,13 +577,17 @@ static void ras_send_error_event(struct xe_device *xe, u8 severity, u8 component
xe_drm_ras_event(xe, drm_component, drm_severity, value);
}
-static u8 handle_core_compute_errors(struct xe_ras_error_array *arr)
+static u8 handle_core_compute_errors(struct xe_device *xe, struct xe_ras_error_array *arr)
{
struct xe_ras_compute_error *error_info = (void *)arr->details;
+ u8 cper_sev = ras_sev_to_cper_sev(arr->counter.common.severity);
u8 uncorr_type;
uncorr_type = FIELD_GET(CORE_COMPUTE_UNCORR_TYPE, error_info->log_header);
+ xe_log_comp(xe, cper_sev, CORE_COMPUTE, &arr->counter, sizeof(arr->counter),
+ "Uncorrectable error detected, type %u\n", uncorr_type);
+
/* Request a reset if error is global */
if (uncorr_type == GLOBAL_UNCORR_ERROR)
return XE_RAS_RECOVERY_ACTION_RESET;
@@ -867,7 +871,7 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
switch (component) {
case XE_RAS_COMP_CORE_COMPUTE:
- action = handle_core_compute_errors(arr);
+ action = handle_core_compute_errors(xe, arr);
break;
case XE_RAS_COMP_SOC_INTERNAL:
action = handle_soc_internal_errors(xe, arr);
--
2.54.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v5 09/13] drm/xe/xe_ras: Report soc internal errors using SIGID
2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
` (9 preceding siblings ...)
2026-10-23 4:34 ` [PATCH v5 08/13] drm/xe/xe_ras: Report core compute " Badal Nilawar
@ 2026-10-23 4:34 ` Badal Nilawar
2026-10-23 6:16 ` Mallesh, Koujalagi
2026-10-26 12:57 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 10/13] drm/xe/xe_ras: Report correctable " Badal Nilawar
` (5 subsequent siblings)
16 siblings, 2 replies; 37+ messages in thread
From: Badal Nilawar @ 2026-10-23 4:34 UTC (permalink / raw)
To: intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
Use xe_log_* helpers to report soc internal errors.
Example:
xe 0000:03:00.0: [drm] *ERROR* SIGID=205 FATAL
(020600700000000000000000) [Hardware Error]: SOC_INTERNAL:
PUNIT error detected: 0x00000002
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Cc: Riana Tauro <riana.tauro@intel.com>
---
v5:
- Log unknown soc internal errors
---
drivers/gpu/drm/xe/xe_ras.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 1f94dd1fb91b..4408fc530900 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -608,7 +608,6 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
{
struct xe_ras_soc_error *info = (void *)arr->details;
struct xe_ras_soc_error_source *source = &info->source;
- struct xe_ras_error_class *counter = &arr->counter;
if (source->csc) {
struct xe_ras_csc_error *csc_error = (void *)info->details;
@@ -622,9 +621,8 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
* is required.
*/
if (csc_error->hec_fw_error) {
- xe_err(xe, "[RAS]: CSC %s detected: 0x%x\n",
- sev_to_str(counter->common.severity),
- csc_error->hec_fw_error);
+ xe_log_comp_fatal(xe, SOC_INTERNAL, &arr->counter, sizeof(arr->counter),
+ "CSC error detected: 0x%08x\n", csc_error->hec_fw_error);
xe_survivability_mode_runtime_enable(xe);
return XE_RAS_RECOVERY_ACTION_DISCONNECT;
}
@@ -632,15 +630,19 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
struct xe_ras_ieh_error *ieh_error = (void *)info->details;
if (ieh_error->global_error_status & XE_RAS_SOC_IEH_PUNIT) {
- xe_err(xe, "[RAS]: PUNIT %s detected: 0x%x\n",
- sev_to_str(counter->common.severity),
- ieh_error->global_error_status);
+ xe_log_comp_fatal(xe, SOC_INTERNAL, &arr->counter, sizeof(arr->counter),
+ "PUNIT error detected: 0x%08x\n",
+ ieh_error->global_error_status);
punit_error_handler(xe);
return XE_RAS_RECOVERY_ACTION_DISCONNECT;
}
}
/* For other SoC internal errors, request a reset as recovery mechanism */
+ xe_log_comp(xe, ras_sev_to_cper_sev(arr->counter.common.severity), SOC_INTERNAL,
+ &arr->counter, sizeof(arr->counter),
+ "Unknown error detected (csc=%u ieh=%u)\n",
+ source->csc, source->ieh);
return XE_RAS_RECOVERY_ACTION_RESET;
}
--
2.54.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v5 10/13] drm/xe/xe_ras: Report correctable errors using SIGID
2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
` (10 preceding siblings ...)
2026-10-23 4:34 ` [PATCH v5 09/13] drm/xe/xe_ras: Report soc internal " Badal Nilawar
@ 2026-10-23 4:34 ` Badal Nilawar
2026-10-26 15:17 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 11/13] drm/xe/xe_ras: Report unknown " Badal Nilawar
` (4 subsequent siblings)
16 siblings, 1 reply; 37+ messages in thread
From: Badal Nilawar @ 2026-10-23 4:34 UTC (permalink / raw)
To: intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
Use xe_log_* helper to report correctable errors.
Example:
xe 0000:03:00.0: [drm] *ERROR* SIGID=203 CORRECTED
(010200180000000100000000) [Hardware Error]: CORE_COMPUTE: error detected
Assisted-by: LLM
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Cc: Raag Jadav <raag.jadav@intel.com>
---
v4:
- Pass structured log component to xe_log_from() (sashiko)
---
drivers/gpu/drm/xe/xe_ras.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 4408fc530900..cd64baddd8de 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -3,6 +3,8 @@
* Copyright © 2026 Intel Corporation
*/
+#include <linux/bitfield.h>
+
#include "xe_assert.h"
#include "xe_bo.h"
#include "xe_configfs.h"
@@ -226,6 +228,12 @@ static u8 ras_sev_to_cper_sev(u8 ras_sev)
}
}
+static u16 ras_comp_to_log_comp(u8 component)
+{
+ return FIELD_PREP(XE_LOG_COMPONENT_CLASS_MASK, XE_LOG_COMPONENT_CLASS_HARDWARE) |
+ FIELD_PREP(XE_LOG_COMPONENT_TYPE_MASK, component);
+}
+
static inline const char *sev_to_str(u8 severity)
{
if (severity >= XE_RAS_SEV_MAX)
@@ -717,8 +725,11 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe,
if (!ras_counter_is_valid(xe, &errors[id]))
continue;
- xe_warn(xe, "[RAS]: %s %s detected\n",
- comp_to_str(component), sev_to_str(severity));
+ xe_log_from(xe, ras_sev_to_cper_sev(severity),
+ ras_comp_to_hw_sigid(component),
+ ras_comp_to_log_comp(component),
+ &errors[id], sizeof(errors[id]),
+ "error detected\n");
/* Send event once per component */
if (sent & BIT(component))
--
2.54.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v5 11/13] drm/xe/xe_ras: Report unknown errors using SIGID
2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
` (11 preceding siblings ...)
2026-10-23 4:34 ` [PATCH v5 10/13] drm/xe/xe_ras: Report correctable " Badal Nilawar
@ 2026-10-23 4:34 ` Badal Nilawar
2026-10-23 4:34 ` [PATCH v5 12/13] drm/xe/xe_ras: Add support to retrieve info queue data Badal Nilawar
` (3 subsequent siblings)
16 siblings, 0 replies; 37+ messages in thread
From: Badal Nilawar @ 2026-10-23 4:34 UTC (permalink / raw)
To: intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
Use xe_log_* helper to report unknown errors.
Assisted-by: LLM
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
drivers/gpu/drm/xe/xe_ras.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index cd64baddd8de..b3dc4d8ad190 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -893,6 +893,11 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
action = handle_device_memory_errors(xe, arr);
break;
default:
+ xe_log_from(xe, ras_sev_to_cper_sev(severity),
+ ras_comp_to_hw_sigid(component),
+ ras_comp_to_log_comp(component),
+ &arr->counter, sizeof(arr->counter),
+ "Unknown error detected, reset required\n");
/* For any other component, reset */
action = XE_RAS_RECOVERY_ACTION_RESET;
break;
--
2.54.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v5 12/13] drm/xe/xe_ras: Add support to retrieve info queue data
2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
` (12 preceding siblings ...)
2026-10-23 4:34 ` [PATCH v5 11/13] drm/xe/xe_ras: Report unknown " Badal Nilawar
@ 2026-10-23 4:34 ` Badal Nilawar
2026-10-23 4:34 ` [PATCH v5 13/13] drm/xe/cper: Prepare Intel CPER info records Badal Nilawar
` (2 subsequent siblings)
16 siblings, 0 replies; 37+ messages in thread
From: Badal Nilawar @ 2026-10-23 4:34 UTC (permalink / raw)
To: intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
Retrieve the RAS info queue data, in multiple chunks, and assemble it into
a flat buffer.
Assisted-by: LLM
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
v5:
- Marked unused fields reserved
- Handle response.status
v4:
- Simplify info queue handling and validation (Raag)
- Clean up info queue naming and definitions (Raag)
- Validate each chunk against the requested offset
---
drivers/gpu/drm/xe/xe_ras.c | 130 ++++++++++++++++++
drivers/gpu/drm/xe/xe_ras.h | 3 +
drivers/gpu/drm/xe/xe_ras_types.h | 91 +++++++++++-
drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 2 +
4 files changed, 224 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index b3dc4d8ad190..12ac9a29555a 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -1114,6 +1114,136 @@ int xe_ras_set_threshold(struct xe_device *xe, u8 severity, u8 component, u32 th
return 0;
}
+static int get_info_queue_data(struct xe_device *xe,
+ struct xe_ras_get_info_queue_request *req,
+ struct xe_ras_get_info_queue_response *out)
+{
+ struct xe_ras_get_info_queue_response response = {0};
+ struct xe_sysctrl_mailbox_command command = {0};
+ const struct xe_ras_info_queue_header *hdr;
+ size_t rlen;
+ int ret;
+
+ xe_sysctrl_create_command(&command, XE_SYSCTRL_GROUP_GFSP, XE_SYSCTRL_CMD_GET_INFO_QUEUE,
+ req, sizeof(*req), &response, sizeof(response));
+
+ ret = xe_sysctrl_send_command(&xe->sc, &command, &rlen);
+ if (ret) {
+ xe_err(xe, "sysctrl: failed to get info queue data %d\n", ret);
+ return ret;
+ }
+
+ if (rlen != sizeof(response)) {
+ xe_err(xe, "sysctrl: unexpected get info queue data response length %zu (expected %zu)\n",
+ rlen, sizeof(response));
+ return -EIO;
+ }
+
+ ret = ras_status_to_errno(response.status);
+ if (ret) {
+ xe_err(xe, "sysctrl: get info queue command failed with status %#x\n",
+ response.status);
+ return ret;
+ }
+
+ hdr = &response.queue_response.header;
+ xe_dbg(xe, "[RAS] info queue: total_size=%u chunk_offset=%u chunk_size=%u flags=0x%x num_headers=%u\n",
+ hdr->total_size, hdr->chunk_offset, hdr->chunk_size,
+ hdr->flags, hdr->num_headers);
+
+ *out = response;
+ return 0;
+}
+
+static bool chunk_is_valid(const struct xe_ras_info_queue_header *hdr,
+ u32 expected_offset, u32 dest_size)
+{
+ u32 end;
+
+ return hdr->chunk_offset == expected_offset &&
+ hdr->chunk_size && hdr->chunk_size <= XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE &&
+ !check_add_overflow(hdr->chunk_offset, hdr->chunk_size, &end) &&
+ end <= XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE && end <= dest_size;
+}
+
+/**
+ * xe_ras_drain_info_queue_raw() - Drain the full RAS info queue into a flat buffer
+ * @xe: xe device
+ * @counter_resp: counter response carrying the first embedded chunk and the
+ * counter identifier used as the source context for subsequent
+ * GET_INFO_QUEUE fetches
+ * @dest_buf: destination buffer supplied by the caller
+ * @dest_size: size of @dest_buf in bytes; also caps the total amount of data
+ * assembled from the info queue
+ *
+ * Copies the first chunk already embedded in @counter_resp, then loops
+ * issuing GET_INFO_QUEUE to fetch any remaining chunks until the queue
+ * signals no more data or a transport/bounds error is encountered. On
+ * transport or bounds errors the function stops and returns whatever has
+ * been assembled so far.
+ *
+ * Returns: Number of valid bytes written into @dest_buf. Zero if @dest_buf is
+ * NULL or @dest_size is 0.
+ */
+u32 xe_ras_drain_info_queue_raw(struct xe_device *xe,
+ const struct xe_ras_get_counter_response *counter_resp,
+ u8 *dest_buf, u32 dest_size)
+{
+ const struct xe_ras_info_queue_header *first_hdr;
+ u32 flags, offset = 0;
+ int ret;
+
+ xe_assert(xe, counter_resp->has_info_queue);
+
+ if (!dest_buf || !dest_size)
+ return 0;
+
+ first_hdr = &counter_resp->first.header;
+
+ if (!chunk_is_valid(first_hdr, offset, dest_size)) {
+ xe_warn(xe, "[RAS]: invalid first info queue chunk (offset=%u size=%u, expected offset=%u)\n",
+ first_hdr->chunk_offset, first_hdr->chunk_size, offset);
+ return 0;
+ }
+
+ /* Copy first chunk already embedded in the counter response */
+ memcpy(dest_buf, counter_resp->first.data, first_hdr->chunk_size);
+ offset = first_hdr->chunk_size;
+ flags = first_hdr->flags;
+
+ /* Fetch any remaining chunks */
+ while ((flags & XE_RAS_INFO_QUEUE_FLAG_MORE_DATA) && offset < dest_size) {
+ struct xe_ras_get_info_queue_request req = {};
+ struct xe_ras_get_info_queue_response resp = {};
+ struct xe_ras_info_queue_header *hdr;
+
+ req.queue_request.offset = offset;
+ req.queue_request.size = min(XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE, dest_size - offset);
+ req.queue_request.session_id = counter_resp->counter;
+
+ ret = get_info_queue_data(xe, &req, &resp);
+ if (ret) {
+ xe_err(xe, "[RAS]: info queue drain aborted: fetch at offset=%u, ret = %d\n",
+ offset, ret);
+ return offset;
+ }
+
+ hdr = &resp.queue_response.header;
+
+ if (!chunk_is_valid(hdr, offset, dest_size)) {
+ xe_warn(xe, "[RAS]: invalid info queue chunk (offset=%u size=%u, expected offset=%u)\n",
+ hdr->chunk_offset, hdr->chunk_size, offset);
+ return offset;
+ }
+
+ memcpy(dest_buf + offset, resp.queue_response.data, hdr->chunk_size);
+ offset += hdr->chunk_size;
+ flags = hdr->flags;
+ }
+
+ return min(offset, first_hdr->total_size);
+}
+
static ssize_t gpu_health_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct xe_ras_get_health_response response = {0};
diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
index c736d5a01c47..ccb79f2c2844 100644
--- a/drivers/gpu/drm/xe/xe_ras.h
+++ b/drivers/gpu/drm/xe/xe_ras.h
@@ -25,5 +25,8 @@ bool xe_ras_get_disable_vram_page_offline(struct xe_device *xe);
u32 xe_ras_get_max_pages(struct xe_device *xe);
int xe_ras_get_counter_response(struct xe_device *xe, const struct xe_ras_error_class *counter,
struct xe_ras_get_counter_response *out);
+u32 xe_ras_drain_info_queue_raw(struct xe_device *xe,
+ const struct xe_ras_get_counter_response *counter_resp,
+ u8 *dest_buf, u32 dest_size);
#endif
diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
index a86f9d2b8c92..67d57182aac9 100644
--- a/drivers/gpu/drm/xe/xe_ras_types.h
+++ b/drivers/gpu/drm/xe/xe_ras_types.h
@@ -19,6 +19,10 @@
#define XE_RAS_MEMORY_POISON BIT(2)
#define XE_RAS_MEMORY_DATA_PARITY BIT(5)
+#define XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE 200
+#define XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE 5120
+#define XE_RAS_INFO_QUEUE_FLAG_MORE_DATA 0x02
+
/**
* enum xe_ras_page_action - Page offline actions for page offline request
*
@@ -110,6 +114,83 @@ struct xe_ras_threshold_crossed {
struct xe_ras_error_class counters[XE_RAS_NUM_COUNTERS];
} __packed;
+/**
+ * struct xe_ras_info_queue_header - Metadata for large info queue data transfers
+ *
+ * Provides chunk metadata for commands that support extended info queue
+ * functionality. Used when the total data exceeds a single mailbox response.
+ */
+struct xe_ras_info_queue_header {
+ /** @total_size: Total size of the complete info queue data in bytes */
+ u32 total_size;
+ /** @chunk_offset: Offset of this chunk within the total data in bytes */
+ u32 chunk_offset;
+ /** @chunk_size: Size of the data in this chunk in bytes */
+ u32 chunk_size;
+ /** @reserved0: Reserved for future use */
+ u32 reserved0;
+ /** @flags: Info queue control flags (XE_RAS_INFO_QUEUE_FLAG_*) */
+ u32 flags:8;
+ /** @reserved1: Reserved for future use */
+ u32 reserved1:4;
+ /** @num_headers: Number of detailed counter headers at start of the data */
+ u32 num_headers:5;
+ /** @reserved2: Reserved for future use */
+ u32 reserved2:15;
+ /** @reserved3: Reserved for future use */
+ u32 reserved3;
+} __packed;
+
+/**
+ * struct xe_ras_info_queue_data_request - Request for a specific chunk of info queue data
+ *
+ * Allows the driver to request continuation of large info queue transfers
+ * by specifying an offset and size within the full data set.
+ */
+struct xe_ras_info_queue_data_request {
+ /** @offset: Byte offset of the requested data chunk */
+ u32 offset;
+ /** @size: Maximum size of the requested chunk in bytes */
+ u32 size;
+ /** @session_id: Session ID to correlate multi-chunk transfers */
+ struct xe_ras_error_class session_id;
+ /** @reserved: Reserved for future use */
+ u32 reserved;
+} __packed;
+
+/**
+ * struct xe_ras_info_queue_data_response - Generic response for commands with info queues
+ *
+ * Standard response format for any command that returns an info queue
+ * payload. May be embedded in a command-specific response structure.
+ */
+struct xe_ras_info_queue_data_response {
+ /** @header: Info queue metadata for this chunk */
+ struct xe_ras_info_queue_header header;
+ /** @data: Info queue data for this chunk */
+ u8 data[XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE];
+} __packed;
+
+/**
+ * struct xe_ras_get_info_queue_request - Request for XE_SYSCTRL_CMD_GET_INFO_QUEUE
+ */
+struct xe_ras_get_info_queue_request {
+ /** @queue_request: Info queue request parameters */
+ struct xe_ras_info_queue_data_request queue_request;
+ /** @reserved: Reserved for future use */
+ u32 reserved[16];
+} __packed;
+
+/**
+ * struct xe_ras_get_info_queue_response - Response for XE_SYSCTRL_CMD_GET_INFO_QUEUE
+ */
+struct xe_ras_get_info_queue_response {
+ /** @status: Status of the retrieval operation */
+ u32 status;
+ /** @queue_response: Info queue data chunk */
+ struct xe_ras_info_queue_data_response queue_response;
+} __packed;
+
/**
* struct xe_ras_get_counter_request - Request structure for get counter
*/
@@ -132,8 +213,14 @@ struct xe_ras_get_counter_response {
u64 timestamp;
/** @threshold: Threshold value for the counter */
u32 threshold;
- /** @reserved: Reserved */
- u32 reserved[57];
+ /** @reserved: Reserved for future use */
+ u32 reserved:9;
+ /** @has_info_queue: Set if info queue is available */
+ u32 has_info_queue:1;
+ /** @reserved1: Reserved for future use */
+ u32 reserved1:22;
+ /** @first: First info queue chunk, if @has_info_queue is set */
+ struct xe_ras_info_queue_data_response first;
} __packed;
/**
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
index 1f3f782d770e..9188457ef7ae 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
@@ -37,6 +37,7 @@ enum xe_sysctrl_group {
* @XE_SYSCTRL_CMD_GET_OFFLINE_QUEUE: Retrieve list of offlined queued pages from firmware
* @XE_SYSCTRL_CMD_GET_HEALTH: Retrieve gpu health
* @XE_SYSCTRL_CMD_SET_HEALTH: Set gpu health
+ * @XE_SYSCTRL_CMD_GET_INFO_QUEUE: Retrieve a chunk of info queue data
*/
enum xe_sysctrl_gfsp_cmd {
XE_SYSCTRL_CMD_GET_SOC_ERROR = 0x01,
@@ -50,6 +51,7 @@ enum xe_sysctrl_gfsp_cmd {
XE_SYSCTRL_CMD_GET_OFFLINE_QUEUE = 0x0A,
XE_SYSCTRL_CMD_GET_HEALTH = 0x0B,
XE_SYSCTRL_CMD_SET_HEALTH = 0x0C,
+ XE_SYSCTRL_CMD_GET_INFO_QUEUE = 0x0D,
};
/**
--
2.54.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v5 13/13] drm/xe/cper: Prepare Intel CPER info records
2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
` (13 preceding siblings ...)
2026-10-23 4:34 ` [PATCH v5 12/13] drm/xe/xe_ras: Add support to retrieve info queue data Badal Nilawar
@ 2026-10-23 4:34 ` Badal Nilawar
2026-10-23 6:34 ` ✓ Xe.CI.FULL: success for Add CPER logging support for CRI (rev5) Patchwork
2026-10-23 6:35 ` ✓ Xe.CI.BAT: " Patchwork
16 siblings, 0 replies; 37+ messages in thread
From: Badal Nilawar @ 2026-10-23 4:34 UTC (permalink / raw)
To: intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
Prepare xe_cper_intel_info records from RAS info queue data. Depending
on the error class type, detail or aggregate, one or more info records
may be generated and embedded in the CPER record.
Assisted-by: LLM
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
v5:
- Simplify CPER info and event queue naming, and use size consistently
for byte-size fields (Raag)
- Add and handle info_log_size in cper intel header
v4:
- Move struct xe_cper_einfo_entry to xe_cper_types.h (Raag)
- Use kzalloc_flex()/kzalloc_objs() (Raag)
- Allocate info queue buffer from reported total size (Raag)
---
drivers/gpu/drm/xe/xe_cper.c | 247 ++++++++++++++++++++++++++++-
drivers/gpu/drm/xe/xe_cper_types.h | 54 ++++++-
drivers/gpu/drm/xe/xe_ras_types.h | 25 +++
3 files changed, 318 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
index cb4a15a036ac..0d04a85cb1af 100644
--- a/drivers/gpu/drm/xe/xe_cper.c
+++ b/drivers/gpu/drm/xe/xe_cper.c
@@ -89,7 +89,7 @@ static u64 cper_timestamp_now(void)
static void cper_init_intel_hdr(struct xe_device *xe,
const struct xe_ras_error_class *counter,
u64 first_timestamp, u32 sig_id, u32 error_count,
- struct xe_cper_intel_hdr *ihdr)
+ u32 einfo_size, struct xe_cper_intel_hdr *ihdr)
{
ihdr->counter = *counter;
ihdr->validation_bits |= XE_CPER_VALID_LOCATION;
@@ -105,6 +105,7 @@ static void cper_init_intel_hdr(struct xe_device *xe,
}
ihdr->error_count = error_count;
+ ihdr->info_log_size = einfo_size;
strscpy(ihdr->pci_bdf, pci_name(to_pci_dev(xe->drm.dev)), sizeof(ihdr->pci_bdf));
ihdr->validation_bits |= XE_CPER_VALID_PCI_BDF;
@@ -200,6 +201,212 @@ static void cper_record_emit(struct xe_device *xe, u8 severity,
kfree(rec);
}
+/* Entries built from RAS error logs carry fixed-size error_details */
+#define XE_CPER_RAS_LOG_ENTRY_SIZE \
+ (offsetof(struct xe_cper_intel_priv_event, metadata) + \
+ sizeof_field(struct xe_ras_error_log, error_details))
+
+static struct xe_cper_intel_info *
+build_einfo(const struct xe_ras_error_log *logs, u32 num_logs,
+ const struct xe_ras_error_class *ec, u32 error_count)
+{
+ struct xe_cper_intel_priv_event *entry;
+ struct xe_cper_intel_info *einfo;
+ u32 queue_size, i;
+
+ queue_size = num_logs * XE_CPER_RAS_LOG_ENTRY_SIZE;
+ einfo = kzalloc_flex(*einfo, queue, queue_size);
+ if (!einfo)
+ return NULL;
+
+ einfo->error_count = error_count;
+ einfo->queue_size = queue_size;
+ einfo->queue_count = num_logs;
+ einfo->counter = *ec;
+
+ entry = (struct xe_cper_intel_priv_event *)einfo->queue;
+ for (i = 0; i < num_logs; i++) {
+ entry->size = sizeof_field(struct xe_ras_error_log, error_details);
+ entry->timestamp = logs[i].timestamp;
+ memcpy(entry->metadata, logs[i].error_details, sizeof(logs[i].error_details));
+ entry = (void *)entry + XE_CPER_RAS_LOG_ENTRY_SIZE;
+ }
+
+ return einfo;
+}
+
+static void free_einfo_arr(struct xe_cper_einfo_entry *einfo_arr, u32 count)
+{
+ u32 i;
+
+ for (i = 0; i < count; i++)
+ kfree(einfo_arr[i].einfo);
+ kfree(einfo_arr);
+}
+
+static bool fill_einfo_entry(struct xe_cper_einfo_entry *entry,
+ const struct xe_ras_error_class *counter, u32 count,
+ const struct xe_ras_error_log *logs, u32 num_logs)
+{
+ entry->einfo = build_einfo(logs, num_logs, counter, count);
+ if (!entry->einfo)
+ return false;
+
+ entry->einfo_size = struct_size(entry->einfo, queue,
+ entry->einfo->queue_size);
+ /* The first log is the first occurrence of the error */
+ entry->timestamp = logs[0].timestamp;
+ entry->hdr.counter = *counter;
+ entry->hdr.count = count;
+ return true;
+}
+
+static u32 build_detail_einfo(const struct xe_ras_error_class *counter, u32 count,
+ const struct xe_ras_error_log *logs, u32 num_logs,
+ struct xe_cper_einfo_entry *einfo_arr)
+{
+ /* All logs belong to the queried class; the error count may exceed the logs kept */
+ if (!num_logs)
+ return 0;
+
+ num_logs = min_t(u32, num_logs, XE_RAS_NUM_COUNTERS);
+
+ return fill_einfo_entry(&einfo_arr[0], counter, count, logs, num_logs) ? 1 : 0;
+}
+
+static u32 build_aggregate_einfo(struct xe_device *xe,
+ const struct xe_ras_info_queue_dynamic_counter_hdr *hdrs,
+ u32 num_hdrs, const struct xe_ras_error_log *logs,
+ u32 avail_logs, struct xe_cper_einfo_entry *einfo_arr)
+{
+ u32 log_offset = 0, count = 0, i;
+
+ for (i = 0; i < num_hdrs; i++) {
+ /* @count is the error count; firmware logs at most XE_RAS_NUM_COUNTERS */
+ u32 num_logs = min_t(u32, hdrs[i].count, XE_RAS_NUM_COUNTERS);
+
+ if (num_logs > avail_logs - log_offset) {
+ xe_warn(xe, "CPER: header[%u] claims %u logs but only %u remain\n",
+ i, num_logs, avail_logs - log_offset);
+ break;
+ }
+
+ if (!num_logs)
+ continue;
+
+ if (!fill_einfo_entry(&einfo_arr[count], &hdrs[i].counter, hdrs[i].count,
+ &logs[log_offset], num_logs))
+ break;
+
+ log_offset += num_logs;
+ count++;
+ }
+
+ return count;
+}
+
+/**
+ * cper_prepare_einfo() - Build the CPER error info records from RAS info queue data
+ * @xe: xe device instance
+ * @counter_resp: counter response containing the first embedded chunk
+ * @counter: RAS error class used to populate the einfo error_class fields
+ * @count_out: output number of entries in the returned array
+ *
+ * Assembles the complete raw info queue data from the first chunk already
+ * embedded in @counter_resp and any additional chunks fetched via
+ * GET_INFO_QUEUE. Two use cases are supported based on num_headers in
+ * the info queue header:
+ *
+ * Detail error counter (num_headers == 0)::
+ *
+ * [xe_ras_error_log * N]
+ *
+ * Returns one xe_cper_einfo_entry covering up to XE_RAS_NUM_COUNTERS logs.
+ *
+ * Aggregate error counter (num_headers > 0)::
+ *
+ * [xe_ras_info_queue_dynamic_counter_hdr * num_headers]
+ * [xe_ras_error_log * N]
+ *
+ * Returns one xe_cper_einfo_entry per header. Each header's @counter
+ * identifies its error class, and @count gives its error count. Up to
+ * XE_RAS_NUM_COUNTERS xe_ras_error_log entries are associated with each
+ * header, and @counter populates the entry's einfo->error_class.
+ *
+ * Returns: allocated xe_cper_einfo_entry array on success (caller must free it
+ * with free_einfo_arr()), NULL if no info queue is available or no
+ * error info could be built. @count_out is set to the number of
+ * entries in the array, or zero when returning NULL.
+ */
+static struct xe_cper_einfo_entry *
+cper_prepare_einfo(struct xe_device *xe,
+ const struct xe_ras_get_counter_response *counter_resp,
+ const struct xe_ras_error_class *counter, u32 *count_out)
+{
+ const struct xe_ras_info_queue_header *first_qhdr = &counter_resp->first.header;
+ struct xe_cper_einfo_entry *einfo_arr = NULL;
+ const struct xe_ras_error_log *logs;
+ u32 buf_size, raw_total, num_headers, headers_size;
+ u32 avail_logs, count = 0;
+ u8 *raw_buf = NULL;
+
+ *count_out = 0;
+ if (!counter_resp->has_info_queue)
+ return NULL;
+
+ if (!first_qhdr->total_size) {
+ xe_warn(xe, "CPER: info queue reports zero total size\n");
+ goto out;
+ }
+
+ if (first_qhdr->total_size > XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE)
+ xe_warn(xe, "CPER: info queue size %u exceeds max %u, truncating\n",
+ first_qhdr->total_size, XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE);
+
+ buf_size = min(first_qhdr->total_size, XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE);
+ raw_buf = kzalloc_objs(*raw_buf, buf_size);
+ if (!raw_buf)
+ goto out;
+
+ raw_total = xe_ras_drain_info_queue_raw(xe, counter_resp, raw_buf, buf_size);
+ if (!raw_total)
+ goto out;
+
+ num_headers = first_qhdr->num_headers;
+ headers_size = num_headers * sizeof(struct xe_ras_info_queue_dynamic_counter_hdr);
+ if (headers_size > raw_total) {
+ xe_warn(xe, "CPER: aggregate headers size (%u) exceeds raw total (%u)\n",
+ headers_size, raw_total);
+ goto out;
+ }
+
+ logs = (const struct xe_ras_error_log *)(raw_buf + headers_size);
+ avail_logs = (raw_total - headers_size) / sizeof(*logs);
+
+ einfo_arr = kzalloc_objs(*einfo_arr, num_headers ?: 1);
+ if (!einfo_arr)
+ goto out;
+
+ if (num_headers)
+ count = build_aggregate_einfo(xe, (const void *)raw_buf, num_headers,
+ logs, avail_logs, einfo_arr);
+ else
+ count = build_detail_einfo(counter, counter_resp->value,
+ logs, avail_logs, einfo_arr);
+
+ if (!count) {
+ kfree(einfo_arr);
+ einfo_arr = NULL;
+ }
+out:
+ kfree(raw_buf);
+ *count_out = count;
+ if (!einfo_arr)
+ xe_warn(xe, "CPER: failed to build error info from info queue, emitting record without it\n");
+
+ return einfo_arr;
+}
+
/**
* xe_cper_emit_counter() - Emit CPER records for an already fetched error counter
* @xe: The &xe_device
@@ -208,19 +415,47 @@ static void cper_record_emit(struct xe_device *xe, u8 severity,
* @counter: RAS error class
* @response: Counter response returned by firmware for @counter
*
- * Build and emit a CPER record from @response.
+ * Build and emit CPER records from @resp, including any info queue data.
+ * Must be called from a sleepable context with a runtime PM reference held.
*/
void xe_cper_emit_counter(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
const struct xe_ras_error_class *counter,
const struct xe_ras_get_counter_response *response)
{
- struct xe_cper_intel_hdr ihdr = {};
+ struct xe_cper_einfo_entry *einfo_arr = NULL, *entries;
+ struct xe_cper_einfo_entry single = {};
+ u32 einfo_count = 0, count, i;
xe_assert(xe, is_hw_sigid(sigid));
- cper_init_intel_hdr(xe, counter, response->timestamp,
- sigid, response->value, &ihdr);
- cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR, &ihdr, NULL, 0);
+ /* Draining the info queue sends sysctrl commands */
+ might_sleep();
+ xe_device_assert_mem_access(xe);
+
+ /* Without info queue data, emit a single record from the counter itself */
+ single.hdr.counter = *counter;
+ single.hdr.count = response->value;
+ single.timestamp = response->timestamp;
+ entries = &single;
+ count = 1;
+
+ einfo_arr = cper_prepare_einfo(xe, response, counter, &einfo_count);
+ if (einfo_arr) {
+ entries = einfo_arr;
+ count = einfo_count;
+ }
+
+ for (i = 0; i < count; i++) {
+ struct xe_cper_intel_hdr ihdr = {};
+
+ cper_init_intel_hdr(xe, &entries[i].hdr.counter, entries[i].timestamp,
+ sigid, entries[i].hdr.count, entries[i].einfo_size, &ihdr);
+
+ cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR, &ihdr,
+ entries[i].einfo, entries[i].einfo_size);
+ }
+
+ free_einfo_arr(einfo_arr, einfo_count);
}
static void cper_emit_hw_err(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
diff --git a/drivers/gpu/drm/xe/xe_cper_types.h b/drivers/gpu/drm/xe/xe_cper_types.h
index 107688b17d17..3252e89f64cd 100644
--- a/drivers/gpu/drm/xe/xe_cper_types.h
+++ b/drivers/gpu/drm/xe/xe_cper_types.h
@@ -69,14 +69,50 @@ struct xe_cper_intel_hdr {
/** @fw_id: Firmware version string (GFSP+PCODE+CSC+GUC or MNG+NUC+RAS+GUC) */
char fw_id[256];
/** @reserved: Reserved for future use, must be zero */
- u8 reserved[5];
+ u8 reserved[2];
+ /** @info_log_size: Size of xe_cper_intel_info */
+ u16 info_log_size;
+ /** @reserved1: Reserved for future use, must be zero */
+ u8 reserved1;
+} __packed;
+
+/**
+ * struct xe_cper_intel_info - Variable-length Intel GPU error payload
+ *
+ * Appended after &xe_cper_intel_hdr when detailed error information
+ * is available.
+ */
+struct xe_cper_intel_info {
+ /** @counter: Error class (severity, component, location, cause) */
+ struct xe_ras_error_class counter;
+ /** @error_count: Total number of errors recorded */
+ u32 error_count;
+ /** @queue_size: Total byte size of the @queue array */
+ u32 queue_size;
+ /** @queue_count: Number of entries in @queue */
+ u32 queue_count;
+ /** @queue: Packed array of &xe_cper_intel_priv_event records */
+ u8 queue[];
+} __packed;
+
+/**
+ * struct xe_cper_intel_priv_event - Single event in the event queue
+ */
+struct xe_cper_intel_priv_event {
+ /** @size: Byte size of the @metadata payload */
+ u32 size;
+ /** @timestamp: Timestamp of this event, in firmware ticks */
+ u64 timestamp;
+ /** @metadata: Event-specific payload bytes */
+ u8 metadata[];
} __packed;
/**
* struct xe_cper_nonstd_record - Intel GPU CPER record
*
* Contains the standard CPER record header, section descriptor, and the
- * Intel error section header.
+ * Intel section header. A &xe_cper_intel_info payload may be
+ * appended dynamically.
*/
struct xe_cper_nonstd_record {
/** @record_hdr: Standard CPER record header (UEFI Appendix N.2.1) */
@@ -101,6 +137,20 @@ struct xe_platform_id_entry {
guid_t platform_id;
};
+/**
+ * struct xe_cper_einfo_entry - One CPER error info payload and its source counter
+ */
+struct xe_cper_einfo_entry {
+ /** @hdr: Error class and counter value used for the CPER section header */
+ struct xe_ras_info_queue_dynamic_counter_hdr hdr;
+ /** @einfo: Allocated info payload, NULL if none */
+ struct xe_cper_intel_info *einfo;
+ /** @einfo_size: Byte size of @einfo including the event queue */
+ u32 einfo_size;
+ /** @timestamp: Timestamp of the first occurrence of this error class */
+ u64 timestamp;
+};
+
/**
* struct xe_cper - Xe CPER state
*/
diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
index 67d57182aac9..903a122e468e 100644
--- a/drivers/gpu/drm/xe/xe_ras_types.h
+++ b/drivers/gpu/drm/xe/xe_ras_types.h
@@ -171,6 +171,31 @@ struct xe_ras_info_queue_data_response {
u8 data[XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE];
} __packed;
+/**
+ * struct xe_ras_info_queue_dynamic_counter_hdr - Aggregate counter header entry
+ *
+ * When a session requests aggregate counter data, one header per matching
+ * dynamic counter class is prepended to the queue data. The @counter field
+ * identifies the error class, and @count is its error count; at most
+ * XE_RAS_NUM_COUNTERS error log entries follow for it.
+ */
+struct xe_ras_info_queue_dynamic_counter_hdr {
+ /** @counter: Error class associated with this counter group */
+ struct xe_ras_error_class counter;
+ /** @count: Error count of this class */
+ u32 count;
+} __packed;
+
+/**
+ * struct xe_ras_error_log - Single error log entry following dynamic counter headers
+ */
+struct xe_ras_error_log {
+ /** @timestamp: Timestamp when the error was recorded */
+ u64 timestamp;
+ /** @error_details: Error-specific details */
+ u32 error_details[16];
+} __packed;
+
/**
* struct xe_ras_get_info_queue_request - Request for XE_SYSCTRL_CMD_GET_INFO_QUEUE
*/
--
2.54.0
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH v5 09/13] drm/xe/xe_ras: Report soc internal errors using SIGID
2026-10-23 4:34 ` [PATCH v5 09/13] drm/xe/xe_ras: Report soc internal " Badal Nilawar
@ 2026-10-23 6:16 ` Mallesh, Koujalagi
2026-10-26 12:57 ` Raag Jadav
1 sibling, 0 replies; 37+ messages in thread
From: Mallesh, Koujalagi @ 2026-10-23 6:16 UTC (permalink / raw)
To: Badal Nilawar, intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, aravind.iddamsetty, himal.prasad.ghimiray,
arvind.yadav, syed.abdul.muqthyar.ahmed, nitin.r.gote
On 23-10-2026 10:04 am, Badal Nilawar wrote:
> Use xe_log_* helpers to report soc internal errors.
>
> Example:
> xe 0000:03:00.0: [drm] *ERROR* SIGID=205 FATAL
> (020600700000000000000000) [Hardware Error]: SOC_INTERNAL:
> PUNIT error detected: 0x00000002
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
LGTM,
Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> Cc: Riana Tauro <riana.tauro@intel.com>
> ---
> v5:
> - Log unknown soc internal errors
> ---
> drivers/gpu/drm/xe/xe_ras.c | 16 +++++++++-------
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 1f94dd1fb91b..4408fc530900 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -608,7 +608,6 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
> {
> struct xe_ras_soc_error *info = (void *)arr->details;
> struct xe_ras_soc_error_source *source = &info->source;
> - struct xe_ras_error_class *counter = &arr->counter;
>
> if (source->csc) {
> struct xe_ras_csc_error *csc_error = (void *)info->details;
> @@ -622,9 +621,8 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
> * is required.
> */
> if (csc_error->hec_fw_error) {
> - xe_err(xe, "[RAS]: CSC %s detected: 0x%x\n",
> - sev_to_str(counter->common.severity),
> - csc_error->hec_fw_error);
> + xe_log_comp_fatal(xe, SOC_INTERNAL, &arr->counter, sizeof(arr->counter),
> + "CSC error detected: 0x%08x\n", csc_error->hec_fw_error);
> xe_survivability_mode_runtime_enable(xe);
> return XE_RAS_RECOVERY_ACTION_DISCONNECT;
> }
> @@ -632,15 +630,19 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
> struct xe_ras_ieh_error *ieh_error = (void *)info->details;
>
> if (ieh_error->global_error_status & XE_RAS_SOC_IEH_PUNIT) {
> - xe_err(xe, "[RAS]: PUNIT %s detected: 0x%x\n",
> - sev_to_str(counter->common.severity),
> - ieh_error->global_error_status);
> + xe_log_comp_fatal(xe, SOC_INTERNAL, &arr->counter, sizeof(arr->counter),
> + "PUNIT error detected: 0x%08x\n",
> + ieh_error->global_error_status);
> punit_error_handler(xe);
> return XE_RAS_RECOVERY_ACTION_DISCONNECT;
> }
> }
>
> /* For other SoC internal errors, request a reset as recovery mechanism */
> + xe_log_comp(xe, ras_sev_to_cper_sev(arr->counter.common.severity), SOC_INTERNAL,
> + &arr->counter, sizeof(arr->counter),
> + "Unknown error detected (csc=%u ieh=%u)\n",
> + source->csc, source->ieh);
> return XE_RAS_RECOVERY_ACTION_RESET;
> }
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v5 08/13] drm/xe/xe_ras: Report core compute errors using SIGID
2026-10-23 4:34 ` [PATCH v5 08/13] drm/xe/xe_ras: Report core compute " Badal Nilawar
@ 2026-10-23 6:24 ` Mallesh, Koujalagi
2026-10-27 12:43 ` Raag Jadav
1 sibling, 0 replies; 37+ messages in thread
From: Mallesh, Koujalagi @ 2026-10-23 6:24 UTC (permalink / raw)
To: Badal Nilawar, intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, aravind.iddamsetty, himal.prasad.ghimiray,
arvind.yadav, syed.abdul.muqthyar.ahmed, nitin.r.gote
On 23-10-2026 10:04 am, Badal Nilawar wrote:
> Use xe_log_* helpers to report core compute errors.
>
> Example:
> xe 0000:03:00.0: [drm] *ERROR* SIGID=203 (02020012000a000200000800)
> [Hardware Error]: CORE_COMPUTE: Uncorrectable error detected, type 2
>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
LGTM,
Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> Cc: Riana Tauro <riana.tauro@intel.com>
> ---
> v5:
> - Print uncorr error type in sig id log (Riana)
> v2:
> - Pass RAS firmware reported severity to xe_log
> ---
> drivers/gpu/drm/xe/xe_ras.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 5ebfc6e8dfc7..1f94dd1fb91b 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -577,13 +577,17 @@ static void ras_send_error_event(struct xe_device *xe, u8 severity, u8 component
> xe_drm_ras_event(xe, drm_component, drm_severity, value);
> }
>
> -static u8 handle_core_compute_errors(struct xe_ras_error_array *arr)
> +static u8 handle_core_compute_errors(struct xe_device *xe, struct xe_ras_error_array *arr)
> {
> struct xe_ras_compute_error *error_info = (void *)arr->details;
> + u8 cper_sev = ras_sev_to_cper_sev(arr->counter.common.severity);
> u8 uncorr_type;
>
> uncorr_type = FIELD_GET(CORE_COMPUTE_UNCORR_TYPE, error_info->log_header);
>
> + xe_log_comp(xe, cper_sev, CORE_COMPUTE, &arr->counter, sizeof(arr->counter),
> + "Uncorrectable error detected, type %u\n", uncorr_type);
> +
> /* Request a reset if error is global */
> if (uncorr_type == GLOBAL_UNCORR_ERROR)
> return XE_RAS_RECOVERY_ACTION_RESET;
> @@ -867,7 +871,7 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
>
> switch (component) {
> case XE_RAS_COMP_CORE_COMPUTE:
> - action = handle_core_compute_errors(arr);
> + action = handle_core_compute_errors(xe, arr);
> break;
> case XE_RAS_COMP_SOC_INTERNAL:
> action = handle_soc_internal_errors(xe, arr);
^ permalink raw reply [flat|nested] 37+ messages in thread
* ✓ Xe.CI.FULL: success for Add CPER logging support for CRI (rev5)
2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
` (14 preceding siblings ...)
2026-10-23 4:34 ` [PATCH v5 13/13] drm/xe/cper: Prepare Intel CPER info records Badal Nilawar
@ 2026-10-23 6:34 ` Patchwork
2026-10-23 6:35 ` ✓ Xe.CI.BAT: " Patchwork
16 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2026-10-23 6:34 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 41953 bytes --]
== Series Details ==
Series: Add CPER logging support for CRI (rev5)
URL : https://patchwork.freedesktop.org/series/169692/
State : success
== Summary ==
CI Bug Log - changes from xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f_FULL -> xe-pw-169692v5_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (3 -> 3)
------------------------------
No changes in participating hosts
New tests
---------
New tests have been introduced between xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f_FULL and xe-pw-169692v5_FULL:
### New IGT tests (2) ###
* igt@xe_oa@tail-address-wrap@oam-2-256k:
- Statuses : 1 pass(s)
- Exec time: [0.07] s
* igt@xe_oa@tail-address-wrap@sag-1-256k:
- Statuses : 1 pass(s)
- Exec time: [0.07] s
Known issues
------------
Here are the changes found in xe-pw-169692v5_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@intel_hwmon@hwmon-read:
- shard-ptl: NOTRUN -> [SKIP][1] ([Intel XE#7225])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-5/igt@intel_hwmon@hwmon-read.html
* igt@intel_hwmon@hwmon-write:
- shard-bmg: [PASS][2] -> [FAIL][3] ([Intel XE#8583])
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-5/igt@intel_hwmon@hwmon-write.html
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-1/igt@intel_hwmon@hwmon-write.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-270:
- shard-bmg: NOTRUN -> [SKIP][4] ([Intel XE#2327])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-5/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-ptl: NOTRUN -> [SKIP][5] ([Intel XE#6925])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@linear-16bpp-rotate-90:
- shard-ptl: NOTRUN -> [SKIP][6] ([Intel XE#5901]) +1 other test skip
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-8/igt@kms_big_fb@linear-16bpp-rotate-90.html
* igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip:
- shard-bmg: NOTRUN -> [SKIP][7] ([Intel XE#7059] / [Intel XE#7085])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-8/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html
- shard-ptl: NOTRUN -> [SKIP][8] ([Intel XE#7085])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-6/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-bmg: NOTRUN -> [SKIP][9] ([Intel XE#607] / [Intel XE#7361])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-8/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
- shard-ptl: NOTRUN -> [SKIP][10] ([Intel XE#5851])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-6/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-ptl: NOTRUN -> [SKIP][11] ([Intel XE#5855])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-5/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][12] ([Intel XE#1124]) +1 other test skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-4/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-ptl: NOTRUN -> [SKIP][13] ([Intel XE#5808]) +9 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_bw@connected-linear-tiling-2-displays-target-2560x1440p:
- shard-ptl: NOTRUN -> [SKIP][14] ([Intel XE#7679])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-6/igt@kms_bw@connected-linear-tiling-2-displays-target-2560x1440p.html
* igt@kms_bw@linear-tiling-1-displays-target-1920x1080p:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#367])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-2/igt@kms_bw@linear-tiling-1-displays-target-1920x1080p.html
* igt@kms_bw@linear-tiling-4-displays-target-3840x2160p:
- shard-ptl: NOTRUN -> [SKIP][16] ([Intel XE#367])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-2/igt@kms_bw@linear-tiling-4-displays-target-3840x2160p.html
* igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc:
- shard-ptl: NOTRUN -> [SKIP][17] ([Intel XE#5822]) +12 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-4/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#2652]) +7 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-2/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1:
- shard-ptl: NOTRUN -> [SKIP][19] ([Intel XE#5823] / [Intel XE#6918]) +4 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs:
- shard-bmg: NOTRUN -> [SKIP][20] ([Intel XE#3432]) +1 other test skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs:
- shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#2887]) +5 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-6/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs.html
* igt@kms_chamelium_color@ctm-negative:
- shard-ptl: NOTRUN -> [SKIP][22] ([Intel XE#5824]) +1 other test skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-3/igt@kms_chamelium_color@ctm-negative.html
- shard-bmg: NOTRUN -> [SKIP][23] ([Intel XE#2325] / [Intel XE#7358])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-10/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_chamelium_edid@dp-edid-change-during-hibernate:
- shard-ptl: NOTRUN -> [SKIP][24] ([Intel XE#2252]) +5 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-7/igt@kms_chamelium_edid@dp-edid-change-during-hibernate.html
* igt@kms_chamelium_edid@dp-edid-resolution-list:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#2252]) +1 other test skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-10/igt@kms_chamelium_edid@dp-edid-resolution-list.html
* igt@kms_chamelium_sharpness_filter@filter-basic:
- shard-ptl: NOTRUN -> [SKIP][26] ([Intel XE#6507])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-6/igt@kms_chamelium_sharpness_filter@filter-basic.html
* igt@kms_content_protection@atomic@pipe-a-dp-1:
- shard-bmg: NOTRUN -> [FAIL][27] ([Intel XE#3304])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-7/igt@kms_content_protection@atomic@pipe-a-dp-1.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-ptl: NOTRUN -> [SKIP][28] ([Intel XE#5832] / [Intel XE#6974])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-2/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@legacy:
- shard-ptl: NOTRUN -> [SKIP][29] ([Intel XE#7642]) +2 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-2/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@legacy-hdcp14@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][30] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-10/igt@kms_content_protection@legacy-hdcp14@pipe-a-dp-2.html
* igt@kms_content_protection@lic-type-0@pipe-a-dp-1:
- shard-bmg: NOTRUN -> [FAIL][31] ([Intel XE#3304] / [Intel XE#7374])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-7/igt@kms_content_protection@lic-type-0@pipe-a-dp-1.html
* igt@kms_content_protection@uevent@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][32] ([Intel XE#6707] / [Intel XE#7439])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-10/igt@kms_content_protection@uevent@pipe-a-dp-2.html
* igt@kms_cursor_crc@cursor-offscreen-256x85:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#2320])
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-2/igt@kms_cursor_crc@cursor-offscreen-256x85.html
* igt@kms_cursor_crc@cursor-random-128x42:
- shard-ptl: NOTRUN -> [SKIP][34] ([Intel XE#5900]) +1 other test skip
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-5/igt@kms_cursor_crc@cursor-random-128x42.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
- shard-ptl: NOTRUN -> [SKIP][35] ([Intel XE#5962]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-7/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_display_modes@extended-mode-basic:
- shard-ptl: NOTRUN -> [SKIP][36] ([Intel XE#4302])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-1/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_dsc@dsc-with-bpc-bigjoiner:
- shard-bmg: NOTRUN -> [SKIP][37] ([Intel XE#8265]) +2 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-4/igt@kms_dsc@dsc-with-bpc-bigjoiner.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-ptl: NOTRUN -> [SKIP][38] ([Intel XE#5907]) +3 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-4/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
- shard-ptl: NOTRUN -> [SKIP][39] ([Intel XE#2316]) +2 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-8/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
* igt@kms_flip@plain-flip-ts-check:
- shard-bmg: [PASS][40] -> [FAIL][41] ([Intel XE#5408] / [Intel XE#6266]) +1 other test fail
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-9/igt@kms_flip@plain-flip-ts-check.html
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-9/igt@kms_flip@plain-flip-ts-check.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
- shard-ptl: NOTRUN -> [SKIP][42] ([Intel XE#7178]) +2 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html
- shard-bmg: NOTRUN -> [SKIP][43] ([Intel XE#7178] / [Intel XE#7351])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-4/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling:
- shard-ptl: NOTRUN -> [SKIP][44] ([Intel XE#5828]) +3 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-6/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling.html
* igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x:
- shard-bmg: NOTRUN -> [SKIP][45] ([Intel XE#7179])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-7/igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x.html
- shard-ptl: NOTRUN -> [SKIP][46] ([Intel XE#7179])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-8/igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x.html
* igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc:
- shard-ptl: NOTRUN -> [SKIP][47] ([Intel XE#5800] / [Intel XE#6312]) +8 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-5/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][48] ([Intel XE#4141]) +3 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-10/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-ptl: NOTRUN -> [SKIP][49] ([Intel XE#5812]) +53 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-blt:
- shard-ptl: NOTRUN -> [SKIP][50] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-2/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-render:
- shard-bmg: NOTRUN -> [SKIP][51] ([Intel XE#7061] / [Intel XE#7356])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-offscreen-pri-indfb-draw-blt:
- shard-ptl: NOTRUN -> [SKIP][52] ([Intel XE#6312]) +10 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-3/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-offscreen-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-pri-shrfb-draw-render:
- shard-bmg: NOTRUN -> [SKIP][53] ([Intel XE#2311]) +17 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-10/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][54] ([Intel XE#2313]) +19 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsrhdr-abgr161616f-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][55] ([Intel XE#7061]) +1 other test skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsrhdr-abgr161616f-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsrhdr-rgb565-draw-blt:
- shard-ptl: NOTRUN -> [SKIP][56] ([Intel XE#7865]) +11 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-4/igt@kms_frontbuffer_tracking@fbcpsrhdr-rgb565-draw-blt.html
* igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-render:
- shard-ptl: NOTRUN -> [SKIP][57] ([Intel XE#7061]) +3 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-2/igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-render.html
* igt@kms_hdmi_audio_bw@audio-bw-hblank80:
- shard-bmg: [PASS][58] -> [FAIL][59] ([Intel XE#9313])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-6/igt@kms_hdmi_audio_bw@audio-bw-hblank80.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-3/igt@kms_hdmi_audio_bw@audio-bw-hblank80.html
* igt@kms_hdmi_audio_bw@dpms-audio-recovery:
- shard-ptl: NOTRUN -> [SKIP][60] ([Intel XE#9312])
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-7/igt@kms_hdmi_audio_bw@dpms-audio-recovery.html
* igt@kms_joiner@basic-big-joiner:
- shard-ptl: NOTRUN -> [SKIP][61] ([Intel XE#6901]) +1 other test skip
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-6/igt@kms_joiner@basic-big-joiner.html
* igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier:
- shard-bmg: NOTRUN -> [SKIP][62] ([Intel XE#7283])
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-2/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier.html
- shard-ptl: NOTRUN -> [SKIP][63] ([Intel XE#7283]) +2 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-7/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier.html
* igt@kms_plane_lowres@tiling-yf:
- shard-bmg: NOTRUN -> [SKIP][64] ([Intel XE#2393])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-6/igt@kms_plane_lowres@tiling-yf.html
- shard-ptl: NOTRUN -> [SKIP][65] ([Intel XE#5946])
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-7/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-b:
- shard-ptl: NOTRUN -> [SKIP][66] ([Intel XE#6886]) +9 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-6/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-b.html
* igt@kms_pm_dc@dc5-psr-suspend-resume:
- shard-lnl: [PASS][67] -> [FAIL][68] ([Intel XE#8399])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-lnl-5/igt@kms_pm_dc@dc5-psr-suspend-resume.html
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-lnl-2/igt@kms_pm_dc@dc5-psr-suspend-resume.html
* igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-bmg: NOTRUN -> [SKIP][69] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383] / [Intel XE#836])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-9/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area:
- shard-ptl: NOTRUN -> [SKIP][70] ([Intel XE#7304]) +1 other test skip
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-2/igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
- shard-bmg: NOTRUN -> [SKIP][71] ([Intel XE#1489]) +1 other test skip
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf:
- shard-ptl: NOTRUN -> [SKIP][72] ([Intel XE#5858] / [Intel XE#7304]) +3 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-7/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-a-edp-1:
- shard-ptl: NOTRUN -> [SKIP][73] ([Intel XE#5858]) +1 other test skip
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-7/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-a-edp-1.html
* igt@kms_psr@fbc-psr-basic:
- shard-bmg: NOTRUN -> [SKIP][74] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-4/igt@kms_psr@fbc-psr-basic.html
* igt@kms_psr@fbc-psr2-dpms:
- shard-ptl: NOTRUN -> [SKIP][75] ([Intel XE#1406] / [Intel XE#5835]) +1 other test skip
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-7/igt@kms_psr@fbc-psr2-dpms.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-bmg: NOTRUN -> [SKIP][76] ([Intel XE#3904] / [Intel XE#7342]) +2 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-10/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- shard-ptl: NOTRUN -> [SKIP][77] ([Intel XE#5821]) +2 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
* igt@kms_vrr@flipline@pipe-a-edp-1:
- shard-ptl: [PASS][78] -> [FAIL][79] ([Intel XE#4227] / [Intel XE#7397]) +1 other test fail
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-ptl-2/igt@kms_vrr@flipline@pipe-a-edp-1.html
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-4/igt@kms_vrr@flipline@pipe-a-edp-1.html
* igt@xe_ccs@vm-bind-fault-mode-decompress:
- shard-ptl: NOTRUN -> [SKIP][80] ([Intel XE#7644])
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-5/igt@xe_ccs@vm-bind-fault-mode-decompress.html
* igt@xe_evict@evict-beng-threads-large-multi-vm:
- shard-ptl: NOTRUN -> [SKIP][81] ([Intel XE#5764]) +4 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-6/igt@xe_evict@evict-beng-threads-large-multi-vm.html
* igt@xe_evict@evict-mixed-many-threads-small:
- shard-bmg: NOTRUN -> [INCOMPLETE][82] ([Intel XE#6321] / [Intel XE#8355])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-4/igt@xe_evict@evict-mixed-many-threads-small.html
* igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-samefd:
- shard-ptl: NOTRUN -> [SKIP][83] ([Intel XE#6144]) +1 other test skip
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-2/igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-samefd.html
* igt@xe_exec_balancer@once-virtual-rebind:
- shard-ptl: NOTRUN -> [SKIP][84] ([Intel XE#7482]) +13 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-2/igt@xe_exec_balancer@once-virtual-rebind.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind:
- shard-ptl: NOTRUN -> [SKIP][85] ([Intel XE#5575] / [Intel XE#7484]) +5 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-4/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind.html
- shard-bmg: NOTRUN -> [SKIP][86] ([Intel XE#2322] / [Intel XE#7372])
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-6/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind.html
* igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr:
- shard-bmg: NOTRUN -> [SKIP][87] ([Intel XE#8374]) +4 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-5/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr.html
* igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind:
- shard-ptl: NOTRUN -> [SKIP][88] ([Intel XE#8374]) +7 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-7/igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind.html
* igt@xe_exec_multi_queue@max-queues-basic:
- shard-bmg: NOTRUN -> [SKIP][89] ([Intel XE#8364]) +12 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-10/igt@xe_exec_multi_queue@max-queues-basic.html
* igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-close-fd-smem:
- shard-ptl: NOTRUN -> [SKIP][90] ([Intel XE#8364]) +19 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-8/igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-close-fd-smem.html
* igt@xe_exec_reset@multi-queue-cancel:
- shard-ptl: NOTRUN -> [SKIP][91] ([Intel XE#8369])
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-1/igt@xe_exec_reset@multi-queue-cancel.html
- shard-bmg: NOTRUN -> [SKIP][92] ([Intel XE#8369])
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-5/igt@xe_exec_reset@multi-queue-cancel.html
* igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-basic:
- shard-bmg: NOTRUN -> [SKIP][93] ([Intel XE#8378]) +2 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-6/igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-basic.html
* igt@xe_exec_threads@threads-multi-queue-shared-vm-basic:
- shard-ptl: NOTRUN -> [SKIP][94] ([Intel XE#8378]) +4 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-5/igt@xe_exec_threads@threads-multi-queue-shared-vm-basic.html
* igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit:
- shard-ptl: NOTRUN -> [SKIP][95] ([Intel XE#5775])
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-6/igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit.html
* igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
- shard-bmg: NOTRUN -> [SKIP][96] ([Intel XE#2229])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-8/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html
* igt@xe_media_fill@media-fill:
- shard-bmg: NOTRUN -> [SKIP][97] ([Intel XE#2459] / [Intel XE#2596] / [Intel XE#7321] / [Intel XE#7453])
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-5/igt@xe_media_fill@media-fill.html
- shard-ptl: NOTRUN -> [SKIP][98] ([Intel XE#5830] / [Intel XE#7453])
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-1/igt@xe_media_fill@media-fill.html
* igt@xe_multigpu_svm@mgpu-coherency-conflict:
- shard-ptl: NOTRUN -> [SKIP][99] ([Intel XE#6964]) +1 other test skip
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-2/igt@xe_multigpu_svm@mgpu-coherency-conflict.html
* igt@xe_multigpu_svm@mgpu-coherency-fail-basic:
- shard-bmg: NOTRUN -> [SKIP][100] ([Intel XE#6964])
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-2/igt@xe_multigpu_svm@mgpu-coherency-fail-basic.html
* igt@xe_page_reclaim@binds-full-pd:
- shard-bmg: NOTRUN -> [SKIP][101] ([Intel XE#7793])
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-10/igt@xe_page_reclaim@binds-full-pd.html
- shard-ptl: NOTRUN -> [SKIP][102] ([Intel XE#7793])
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-5/igt@xe_page_reclaim@binds-full-pd.html
* igt@xe_peer2peer@read:
- shard-ptl: NOTRUN -> [SKIP][103] ([Intel XE#6588])
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-6/igt@xe_peer2peer@read.html
* igt@xe_pm@d3cold-multiple-execs:
- shard-bmg: NOTRUN -> [SKIP][104] ([Intel XE#2284] / [Intel XE#7370])
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-1/igt@xe_pm@d3cold-multiple-execs.html
- shard-ptl: NOTRUN -> [SKIP][105] ([Intel XE#5741])
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-4/igt@xe_pm@d3cold-multiple-execs.html
* igt@xe_pm@s4-vm-bind-prefetch:
- shard-ptl: [PASS][106] -> [ABORT][107] ([Intel XE#9362])
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-ptl-3/igt@xe_pm@s4-vm-bind-prefetch.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-7/igt@xe_pm@s4-vm-bind-prefetch.html
* igt@xe_pm@s4-vm-bind-userptr:
- shard-lnl: [PASS][108] -> [ABORT][109] ([Intel XE#9362])
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-lnl-2/igt@xe_pm@s4-vm-bind-userptr.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-lnl-4/igt@xe_pm@s4-vm-bind-userptr.html
* igt@xe_pm_residency@aspm_link_residency:
- shard-ptl: NOTRUN -> [SKIP][110] ([Intel XE#7271])
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-7/igt@xe_pm_residency@aspm_link_residency.html
* igt@xe_pm_residency@gt-c6-freeze@gt1:
- shard-bmg: [PASS][111] -> [FAIL][112] ([Intel XE#9254])
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-5/igt@xe_pm_residency@gt-c6-freeze@gt1.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-8/igt@xe_pm_residency@gt-c6-freeze@gt1.html
* igt@xe_query@multigpu-query-invalid-query:
- shard-bmg: NOTRUN -> [SKIP][113] ([Intel XE#944]) +1 other test skip
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-1/igt@xe_query@multigpu-query-invalid-query.html
* igt@xe_query@multigpu-query-oa-units:
- shard-ptl: NOTRUN -> [SKIP][114] ([Intel XE#6019]) +2 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-7/igt@xe_query@multigpu-query-oa-units.html
* igt@xe_sriov_flr@flr-vfs-parallel:
- shard-bmg: [PASS][115] -> [FAIL][116] ([Intel XE#6569])
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-3/igt@xe_sriov_flr@flr-vfs-parallel.html
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-5/igt@xe_sriov_flr@flr-vfs-parallel.html
#### Possible fixes ####
* igt@kms_hdmi_audio_bw@audio-bw-hblank160:
- shard-bmg: [FAIL][117] ([Intel XE#9313]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-5/igt@kms_hdmi_audio_bw@audio-bw-hblank160.html
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-7/igt@kms_hdmi_audio_bw@audio-bw-hblank160.html
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [SKIP][119] ([Intel XE#1503]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-5/igt@kms_hdr@invalid-hdr.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-2/igt@kms_hdr@invalid-hdr.html
* igt@kms_vrr@flip-dpms@pipe-a-edp-1:
- shard-ptl: [FAIL][121] ([Intel XE#4227] / [Intel XE#7397]) -> [PASS][122] +1 other test pass
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-ptl-8/igt@kms_vrr@flip-dpms@pipe-a-edp-1.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-ptl-3/igt@kms_vrr@flip-dpms@pipe-a-edp-1.html
* igt@xe_exec_threads@threads-hang-userptr-invalidate-race:
- shard-lnl: [FAIL][123] ([Intel XE#9096]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-lnl-6/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-lnl-8/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html
* igt@xe_pm_residency@gt-c6-freeze@gt0:
- shard-bmg: [FAIL][125] ([Intel XE#9254]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-5/igt@xe_pm_residency@gt-c6-freeze@gt0.html
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-8/igt@xe_pm_residency@gt-c6-freeze@gt0.html
* igt@xe_survivability@runtime-survivability:
- shard-bmg: [DMESG-WARN][127] ([Intel XE#9365]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f/shard-bmg-9/igt@xe_survivability@runtime-survivability.html
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/shard-bmg-6/igt@xe_survivability@runtime-survivability.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
[Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
[Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
[Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
[Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
[Intel XE#5408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5408
[Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
[Intel XE#5741]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5741
[Intel XE#5764]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5764
[Intel XE#5775]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5775
[Intel XE#5800]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5800
[Intel XE#5808]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5808
[Intel XE#5812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5812
[Intel XE#5821]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5821
[Intel XE#5822]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5822
[Intel XE#5823]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5823
[Intel XE#5824]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5824
[Intel XE#5828]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5828
[Intel XE#5830]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5830
[Intel XE#5832]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5832
[Intel XE#5835]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5835
[Intel XE#5851]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5851
[Intel XE#5855]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5855
[Intel XE#5858]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5858
[Intel XE#5900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5900
[Intel XE#5901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5901
[Intel XE#5907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5907
[Intel XE#5946]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5946
[Intel XE#5962]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5962
[Intel XE#6019]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6019
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#6144]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6144
[Intel XE#6266]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6266
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6507
[Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
[Intel XE#6588]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6588
[Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
[Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
[Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
[Intel XE#6918]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6918
[Intel XE#6925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6925
[Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
[Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
[Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
[Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
[Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
[Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
[Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
[Intel XE#7225]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7225
[Intel XE#7271]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7271
[Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
[Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
[Intel XE#7321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7321
[Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
[Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
[Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
[Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
[Intel XE#7361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7361
[Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
[Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
[Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
[Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
[Intel XE#7397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7397
[Intel XE#7439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7439
[Intel XE#7453]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7453
[Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
[Intel XE#7484]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7484
[Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
[Intel XE#7644]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7644
[Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
[Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
[Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
[Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
[Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
[Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
[Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
[Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
[Intel XE#8399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8399
[Intel XE#8583]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8583
[Intel XE#9096]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9096
[Intel XE#9254]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9254
[Intel XE#9312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9312
[Intel XE#9313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9313
[Intel XE#9362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9362
[Intel XE#9365]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9365
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* IGT: IGT_9159 -> IGT_9160
* Linux: xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f -> xe-pw-169692v5
IGT_9159: 9159
IGT_9160: 9160
xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f: 55c6bb0b4d006ee415abe9f048014f7bcc90ae6f
xe-pw-169692v5: 169692v5
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/index.html
[-- Attachment #2: Type: text/html, Size: 46648 bytes --]
^ permalink raw reply [flat|nested] 37+ messages in thread
* ✓ Xe.CI.BAT: success for Add CPER logging support for CRI (rev5)
2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
` (15 preceding siblings ...)
2026-10-23 6:34 ` ✓ Xe.CI.FULL: success for Add CPER logging support for CRI (rev5) Patchwork
@ 2026-10-23 6:35 ` Patchwork
16 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2026-10-23 6:35 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 909 bytes --]
== Series Details ==
Series: Add CPER logging support for CRI (rev5)
URL : https://patchwork.freedesktop.org/series/169692/
State : success
== Summary ==
CI Bug Log - changes from xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f_BAT -> xe-pw-169692v5_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (15 -> 15)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* IGT: IGT_9159 -> IGT_9160
* Linux: xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f -> xe-pw-169692v5
IGT_9159: 9159
IGT_9160: 9160
xe-6001-55c6bb0b4d006ee415abe9f048014f7bcc90ae6f: 55c6bb0b4d006ee415abe9f048014f7bcc90ae6f
xe-pw-169692v5: 169692v5
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v5/index.html
[-- Attachment #2: Type: text/html, Size: 1471 bytes --]
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v5 01/13] drm/xe/cper: Add CPER reporting entry point for xe_log
2026-10-23 4:34 ` [PATCH v5 01/13] drm/xe/cper: Add CPER reporting entry point for xe_log Badal Nilawar
@ 2026-10-24 11:38 ` Raag Jadav
0 siblings, 0 replies; 37+ messages in thread
From: Raag Jadav @ 2026-10-24 11:38 UTC (permalink / raw)
To: Badal Nilawar
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
On Fri, Oct 23, 2026 at 10:04:23AM +0530, Badal Nilawar wrote:
> Introduce xe_cper_emit() as the single entry point for emitting
> CPER records from xe_log. xe_log now forwards every SIGID log entry
> with its full context (component, location, data/len and formatted
> message), and xe_cper decides how to report it. Hardware SIGIDs are
> routed to a hardware error helper, software SIGIDs are left as TODO.
>
> Assisted-by: LLM
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> v5:
> - Drop xe and len check (Raag)
> - s/*error_class/*counter
> - drop xe_ from static function to shorten function name
> v4:
> - s/CONFIG_UEFI_CPER_X86/CONFIG_UEFI_CPER/ (Raag)
> - Use in_range() for hardware SIGID check in xe_cper (Raag)
> - Drop unused response param and constify error_class
> - Check data len against struct xe_ras_error_class before use (Michal)
> ---
> drivers/gpu/drm/xe/Makefile | 2 ++
> drivers/gpu/drm/xe/xe_cper.c | 48 ++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_cper.h | 26 +++++++++++++++++++
> drivers/gpu/drm/xe/xe_log.c | 5 +++-
> 4 files changed, 80 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/xe/xe_cper.c
> create mode 100644 drivers/gpu/drm/xe/xe_cper.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 6fb916f1699b..ec463018f77d 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -169,6 +169,8 @@ xe-$(CONFIG_HWMON) += xe_hwmon.o
> xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
> xe-$(CONFIG_CONFIGFS_FS) += xe_configfs.o
>
> +xe-$(CONFIG_UEFI_CPER) += xe_cper.o
> +
> # graphics virtualization (SR-IOV) support
> xe-y += \
> xe_gt_sriov_vf.o \
> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> new file mode 100644
> index 000000000000..8b52752c067f
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_cper.c
> @@ -0,0 +1,48 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include <linux/err.h>
> +#include <linux/minmax.h>
> +
> +#include "xe_cper.h"
> +#include "xe_device.h"
> +#include "xe_ras_types.h"
> +
> +static bool is_hw_sigid(enum xe_sigid sigid)
> +{
> + return in_range(sigid, INTEL_SIGID_GPU_XE_HARDWARE_START, INTEL_SIGID_BATCH);
> +}
> +
> +static void cper_emit_hw_err(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
> + const struct xe_ras_error_class *counter)
> +{
> + /* TODO */
> +}
> +
> +/**
> + * xe_cper_emit() - Emit a CPER record for a SIGID log entry
> + * @xe: The &xe_device
> + * @cper_sev: CPER severity
> + * @sigid: Error signature identifier
> + * @component: Component identifier
> + * @location: Location details of the @component
> + * @data: Pointer to the additional details, or ERR_PTR, or NULL if not applicable
> + * @len: Length of the @data in bytes, or 0 if not applicable
> + * @vaf: Formatted log message
> + *
> + * Emit a CPER record for a SIGID log entry
> + */
> +void xe_cper_emit(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
> + u32 component, u32 location, const void *data, size_t len,
> + struct va_format *vaf)
> +{
> + if (is_hw_sigid(sigid)) {
> + if (!IS_ERR_OR_NULL(data))
What is data expectation for sw cper? If it's same as hw cper, you can
early return from this function using IS_ERR_OR_NULL() check. Otherwise
this can be a simple if (is_hw_sigid() && !IS_ERR_OR_NULL()) for hw cper
case.
Raag
> + cper_emit_hw_err(xe, cper_sev, sigid, data);
> + return;
> + }
> +
> + /* TODO software CPER */
> +}
> diff --git a/drivers/gpu/drm/xe/xe_cper.h b/drivers/gpu/drm/xe/xe_cper.h
> new file mode 100644
> index 000000000000..84676c7645a5
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_cper.h
> @@ -0,0 +1,26 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_CPER_H_
> +#define _XE_CPER_H_
> +
> +#include <linux/types.h>
> +
> +#include "abi/xe_sigid_abi.h"
> +
> +struct va_format;
> +struct xe_device;
> +
> +#if IS_ENABLED(CONFIG_UEFI_CPER)
> +void xe_cper_emit(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
> + u32 component, u32 location, const void *data, size_t len,
> + struct va_format *vaf);
> +#else
> +static inline void xe_cper_emit(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
> + u32 component, u32 location, const void *data, size_t len,
> + struct va_format *vaf) {}
> +#endif
> +
> +#endif /* _XE_CPER_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_log.c b/drivers/gpu/drm/xe/xe_log.c
> index 29eb16db3320..80e2b1724ceb 100644
> --- a/drivers/gpu/drm/xe/xe_log.c
> +++ b/drivers/gpu/drm/xe/xe_log.c
> @@ -8,6 +8,7 @@
>
> #include "abi/xe_log_abi.h"
>
> +#include "xe_cper.h"
> #include "xe_device.h"
> #include "xe_log.h"
> #include "xe_pci_types.h"
> @@ -19,7 +20,9 @@ static void log_emit_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigi
> {
> KUNIT_STATIC_STUB_REDIRECT(log_emit_cper, pdev, cper_sev, sigid,
> component, location, data, len, vaf);
> - /* TODO */
> +
> + xe_cper_emit(xe_any_to_xe(pdev), cper_sev, sigid,
> + component, location, data, len, vaf);
> }
>
> static const char *log_unknown_component_prefix(u32 component)
> --
> 2.54.0
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v5 02/13] drm/xe/cper: Retrieve the error counter record for CPER reporting
2026-10-23 4:34 ` [PATCH v5 02/13] drm/xe/cper: Retrieve the error counter record for CPER reporting Badal Nilawar
@ 2026-10-24 11:50 ` Raag Jadav
0 siblings, 0 replies; 37+ messages in thread
From: Raag Jadav @ 2026-10-24 11:50 UTC (permalink / raw)
To: Badal Nilawar
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
On Fri, Oct 23, 2026 at 10:04:24AM +0530, Badal Nilawar wrote:
> Retrieve error counter record required to build a CPER record.
>
> Assisted-by: LLM
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> v5:
> - Retain get_counter() (Raag)
> v4:
> - Drop redundant xe_ras_counter_is_valid() check (Raag)
> - Add might_sleep() to assert that the caller is in a sleepable
> context (sashiko)
> - Add xe_device_assert_mem_access() to assert the outer runtime PM
> wake reference requirement (sashiko)
> ---
> drivers/gpu/drm/xe/xe_cper.c | 14 ++++++++++-
> drivers/gpu/drm/xe/xe_ras.c | 47 +++++++++++++++++++++++++++---------
> drivers/gpu/drm/xe/xe_ras.h | 2 ++
> 3 files changed, 51 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> index 8b52752c067f..a9044e708cac 100644
> --- a/drivers/gpu/drm/xe/xe_cper.c
> +++ b/drivers/gpu/drm/xe/xe_cper.c
> @@ -4,10 +4,13 @@
> */
>
> #include <linux/err.h>
> +#include <linux/kernel.h>
> #include <linux/minmax.h>
>
> #include "xe_cper.h"
> #include "xe_device.h"
> +#include "xe_printk.h"
> +#include "xe_ras.h"
> #include "xe_ras_types.h"
>
> static bool is_hw_sigid(enum xe_sigid sigid)
> @@ -18,7 +21,16 @@ static bool is_hw_sigid(enum xe_sigid sigid)
> static void cper_emit_hw_err(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
> const struct xe_ras_error_class *counter)
> {
> - /* TODO */
> + struct xe_ras_get_counter_response response = {};
> +
> + /* Fetching the counter sends a sysctrl command */
> + might_sleep();
> + xe_device_assert_mem_access(xe);
> +
> + if (xe_ras_get_counter_response(xe, counter, &response)) {
> + xe_err(xe, "CPER: failed to get counter, skipping record\n");
> + return;
> + }
> }
>
> /**
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index db3cbc186a51..1da523c6e84c 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -528,8 +528,7 @@ static void ras_send_error_event(struct xe_device *xe, u8 severity, u8 component
> {
> struct xe_ras_error_class counter = {0};
> u8 drm_severity, drm_component;
> - u32 value;
> - int ret;
> + u32 value; int ret;
Redundant churn, shouldn't be in this patch.
> counter.common.severity = severity;
> counter.common.component = component;
> @@ -676,19 +675,46 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe,
> }
> }
>
> -static int get_counter(struct xe_device *xe, struct xe_ras_error_class *counter, u32 *value)
> +static int get_counter(struct xe_device *xe,
> + struct xe_ras_error_class *counter,
> + u32 *value)
Why the wrapping? What changed?
> +{
> + struct xe_ras_get_counter_response response = {};
> + int ret;
> +
> + ret = xe_ras_get_counter_response(xe, counter, &response);
> + if (ret)
> + return ret;
> +
> + *value = response.value;
> +
> + return 0;
> +}
> +
> +/**
> + * xe_ras_get_counter_response() - Get error counter record
> + * @xe: Xe device instance
> + * @counter: RAS error class
> + * @out: Counter record retrieved
> + *
> + * Retrieve the counter record of a specific error class from firmware.
> + *
> + * Return: 0 on success, negative error code on failure.
> + */
> +int xe_ras_get_counter_response(struct xe_device *xe, const struct xe_ras_error_class *counter,
> + struct xe_ras_get_counter_response *out)
'response'
> {
> - struct xe_ras_get_counter_response response = {0};
> struct xe_ras_get_counter_request request = {0};
> struct xe_sysctrl_mailbox_command command = {0};
> struct xe_ras_error_common *common;
> size_t rlen;
> int ret;
>
> + memset(out, 0, sizeof(*out));
I think I've already mentioned to drop this in the previous rev[1].
[1] https://lore.kernel.org/intel-xe/asyjSMUDo0XMX-U4@black.igk.intel.com/
Raag
> request.counter = *counter;
>
> xe_sysctrl_create_command(&command, XE_SYSCTRL_GROUP_GFSP, XE_SYSCTRL_CMD_GET_COUNTER,
> - &request, sizeof(request), &response, sizeof(response));
> + &request, sizeof(request), out, sizeof(*out));
>
> ret = xe_sysctrl_send_command(&xe->sc, &command, &rlen);
> if (ret) {
> @@ -696,19 +722,18 @@ static int get_counter(struct xe_device *xe, struct xe_ras_error_class *counter,
> return ret;
> }
>
> - if (rlen != sizeof(response)) {
> + if (rlen != sizeof(*out)) {
> xe_err(xe, "sysctrl: unexpected get counter response length %zu (expected %zu)\n",
> - rlen, sizeof(response));
> + rlen, sizeof(*out));
> return -EIO;
> }
>
> - if (!ras_counter_is_valid(xe, &response.counter))
> + if (!ras_counter_is_valid(xe, &out->counter))
> return -EBADMSG;
>
> - common = &response.counter.common;
> - *value = response.value;
> + common = &out->counter.common;
>
> - xe_dbg(xe, "[RAS]: get counter %u for %s %s\n", *value, comp_to_str(common->component),
> + xe_dbg(xe, "[RAS]: get counter %u for %s %s\n", out->value, comp_to_str(common->component),
> sev_to_str(common->severity));
>
> return 0;
> diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
> index 1b358c7d040f..c736d5a01c47 100644
> --- a/drivers/gpu/drm/xe/xe_ras.h
> +++ b/drivers/gpu/drm/xe/xe_ras.h
> @@ -23,5 +23,7 @@ int xe_ras_init(struct xe_device *xe);
> enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe);
> bool xe_ras_get_disable_vram_page_offline(struct xe_device *xe);
> u32 xe_ras_get_max_pages(struct xe_device *xe);
> +int xe_ras_get_counter_response(struct xe_device *xe, const struct xe_ras_error_class *counter,
> + struct xe_ras_get_counter_response *out);
>
> #endif
> --
> 2.54.0
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v5 03/13] drm/xe/cper: Initialize Intel-specific section header
2026-10-23 4:34 ` [PATCH v5 03/13] drm/xe/cper: Initialize Intel-specific section header Badal Nilawar
2026-10-23 4:30 ` sashiko-bot
@ 2026-10-26 5:57 ` Raag Jadav
1 sibling, 0 replies; 37+ messages in thread
From: Raag Jadav @ 2026-10-26 5:57 UTC (permalink / raw)
To: Badal Nilawar
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
On Fri, Oct 23, 2026 at 10:04:25AM +0530, Badal Nilawar wrote:
> Define the Intel-specific CPER header and initialize it
Please also use the same terminology in subject.
> from the error counter record for Intel GPU hardware errors.
>
> Assisted-by: LLM
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> v5:
> - Move xe_cper_emit_counter() from patch 7 of rev4 to this patch to
> avoid code churn (Raag)
> - Use __packed for individual structures instead of #pragma pack (Raag)
> - Drop redundent 'err'/'error' references, shorten structure name (Raag)
> v4:
> - Split from "drm/xe/cper: Prepare CPER record" (Raag)
> - Add dedicated struct xe_cper_error_class (Michal)
> - Drop empty fill_fw_id() stub, leave a TODO instead
> v2:
> - Guard against NULL THIS_MODULE->srcversion (sashiko)
> ---
> drivers/gpu/drm/xe/xe_cper.c | 52 ++++++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_cper_types.h | 51 +++++++++++++++++++++++++++++
> 2 files changed, 103 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/xe_cper_types.h
>
> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> index a9044e708cac..3d7657517223 100644
> --- a/drivers/gpu/drm/xe/xe_cper.c
> +++ b/drivers/gpu/drm/xe/xe_cper.c
> @@ -6,18 +6,68 @@
> #include <linux/err.h>
> #include <linux/kernel.h>
> #include <linux/minmax.h>
> +#include <linux/pci.h>
>
> #include "xe_cper.h"
> +#include "xe_cper_types.h"
> #include "xe_device.h"
> #include "xe_printk.h"
> #include "xe_ras.h"
> #include "xe_ras_types.h"
>
> +static bool is_valid_sigid(u32 sigid)
Can simply be is_sigid().
> +{
> + return sigid != U32_MAX;
> +}
> +
> static bool is_hw_sigid(enum xe_sigid sigid)
> {
> return in_range(sigid, INTEL_SIGID_GPU_XE_HARDWARE_START, INTEL_SIGID_BATCH);
> }
>
> +static void cper_init_intel_hdr(struct xe_device *xe,
> + const struct xe_ras_error_class *counter,
This looks like can be less lines.
> + u64 first_timestamp, u32 sig_id, u32 error_count,
> + struct xe_cper_intel_hdr *ihdr)
> +{
> + ihdr->counter = *counter;
> + ihdr->validation_bits |= XE_CPER_VALID_LOCATION;
> +
> + if (first_timestamp) {
> + ihdr->first_timestamp = first_timestamp;
> + ihdr->validation_bits |= XE_CPER_VALID_FIRST_TIMESTAMP;
> + }
> +
> + if (is_valid_sigid(sig_id)) {
> + ihdr->sig_id = sig_id;
> + ihdr->validation_bits |= XE_CPER_VALID_SIG_ID;
> + }
> +
> + ihdr->error_count = error_count;
> +
> + strscpy(ihdr->pci_bdf, pci_name(to_pci_dev(xe->drm.dev)), sizeof(ihdr->pci_bdf));
> + ihdr->validation_bits |= XE_CPER_VALID_PCI_BDF;
> +
> +#ifdef MODULE
> + if (THIS_MODULE->srcversion) {
> + strscpy(ihdr->drv_version, THIS_MODULE->srcversion, sizeof(ihdr->drv_version));
> + ihdr->validation_bits |= XE_CPER_VALID_DRV_VERSION;
> + }
> +#endif
> +
> + /* TODO: fill fw_id and set XE_CPER_VALID_FW_ID */
Hm, see below.
> +}
> +
> +static void cper_emit_counter(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
> + const struct xe_ras_error_class *counter,
> + const struct xe_ras_get_counter_response *response)
> +{
> + struct xe_cper_intel_hdr ihdr = {};
> +
> + cper_init_intel_hdr(xe, counter, response->timestamp,
> + sigid, response->value, &ihdr);
> +}
> +
> static void cper_emit_hw_err(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
> const struct xe_ras_error_class *counter)
> {
> @@ -31,6 +81,8 @@ static void cper_emit_hw_err(struct xe_device *xe, int cper_sev, enum xe_sigid s
> xe_err(xe, "CPER: failed to get counter, skipping record\n");
> return;
> }
> +
> + cper_emit_counter(xe, cper_sev, sigid, counter, &response);
> }
>
> /**
> diff --git a/drivers/gpu/drm/xe/xe_cper_types.h b/drivers/gpu/drm/xe/xe_cper_types.h
> new file mode 100644
> index 000000000000..a8730ff62b69
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_cper_types.h
> @@ -0,0 +1,51 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_CPER_TYPES_H_
> +#define _XE_CPER_TYPES_H_
> +
> +#include <linux/types.h>
> +
> +#include "xe_ras_types.h"
> +
> +/*
> + * Validation bits definition for validation_bits in struct
> + * xe_cper_intel_hdr. When set, corresponding fields in header
> + * contains valid data
> + */
> +#define XE_CPER_VALID_LOCATION 0x0001
> +#define XE_CPER_VALID_FIRST_TIMESTAMP 0x0002
> +#define XE_CPER_VALID_SIG_ID 0x0004
> +#define XE_CPER_VALID_PCI_BDF 0x0008
> +#define XE_CPER_VALID_DRV_VERSION 0x0010
> +
> +/**
> + * struct xe_cper_intel_hdr - Intel-specific CPER header
> + *
> + * Fixed-size header for the Intel GPU error section of a CPER record.
> + * All multi-byte fields are little-endian.
> + */
> +struct xe_cper_intel_hdr {
> + /** @counter: Error class (severity, component, location, cause) */
> + struct xe_ras_error_class counter;
> + /** @first_timestamp: First occurrence of this error class, in ticks */
> + u64 first_timestamp;
> + /** @sig_id: Aggregated error class SIG ID; set to U32_MAX if unknown */
> + u32 sig_id;
> + /** @error_count: Number of times this error has been observed */
> + u32 error_count;
> + /** @validation_bits: Raw u16 view of all valid bits */
> + u16 validation_bits;
> + /** @pci_bdf: PCI location string, format "DDDD:bb:dd.f" */
> + char pci_bdf[16];
> + /** @drv_version: Driver source version string (THIS_MODULE->srcversion) */
> + char drv_version[25];
> + /** @fw_id: Firmware version string (GFSP+PCODE+CSC+GUC or MNG+NUC+RAS+GUC) */
> + char fw_id[256];
Please introduce this member in the patch you actually use it.
Raag
> + /** @reserved: Reserved for future use, must be zero */
> + u8 reserved[5];
> +} __packed;
> +
> +#endif
> --
> 2.54.0
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v5 04/13] drm/xe/cper: Construct CPER record for hardware errors
2026-10-23 4:34 ` [PATCH v5 04/13] drm/xe/cper: Construct CPER record for hardware errors Badal Nilawar
@ 2026-10-26 9:54 ` Raag Jadav
2026-10-27 3:34 ` Nilawar, Badal
0 siblings, 1 reply; 37+ messages in thread
From: Raag Jadav @ 2026-10-26 9:54 UTC (permalink / raw)
To: Badal Nilawar
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
On Fri, Oct 23, 2026 at 10:04:26AM +0530, Badal Nilawar wrote:
> Assemble the CPER record header, section descriptor and the Intel
> error section for Intel GPU hardware errors.
>
> Assisted-by: LLM
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> v5:
> - Rebased
> - Add helpers to initialize CPER headers (Raag)
> v4:
> - Split from "drm/xe/cper: Prepare CPER record" (Raag)
> - Use xe->device_uid for FRU ID
> - Add platform IDs for all CRI PCI device IDs
> v2:
> - Encode cper_record_header timestamp in BCD format (sashiko)
> ---
> drivers/gpu/drm/xe/xe_cper.c | 139 +++++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_cper_types.h | 53 +++++++++++
> 2 files changed, 192 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> index 3d7657517223..012693fe48c4 100644
> --- a/drivers/gpu/drm/xe/xe_cper.c
> +++ b/drivers/gpu/drm/xe/xe_cper.c
> @@ -3,10 +3,14 @@
> * Copyright © 2026 Intel Corporation
> */
>
> +#include <linux/bcd.h>
> #include <linux/err.h>
> #include <linux/kernel.h>
> #include <linux/minmax.h>
> #include <linux/pci.h>
> +#include <linux/slab.h>
> +#include <linux/time.h>
> +#include <linux/timekeeping.h>
>
> #include "xe_cper.h"
> #include "xe_cper_types.h"
> @@ -25,6 +29,60 @@ static bool is_hw_sigid(enum xe_sigid sigid)
> return in_range(sigid, INTEL_SIGID_GPU_XE_HARDWARE_START, INTEL_SIGID_BATCH);
> }
>
> +static const struct xe_platform_id_entry xe_platform_ids[] = {
In xe terminology platform signifies the name, which is different from device
id (which looks like the mapping is for). So this can be xe_device_guid_entry
or something like that.
> + /* 0x674C platform/8086:674c */
> + { 0x674C, GUID_INIT(0x9046afe5, 0x9041, 0x5124,
> + 0x86, 0x14, 0x92, 0x55, 0x0d, 0x9e, 0x9d, 0xa6) },
> + /* 0x674D platform/8086:674d */
> + { 0x674D, GUID_INIT(0xf95911b8, 0x6564, 0x5905,
> + 0xa6, 0xa7, 0xb9, 0xbf, 0x54, 0xab, 0x6c, 0x27) },
> + /* 0x674E platform/8086:674e */
> + { 0x674E, GUID_INIT(0xb8d24106, 0x0108, 0x59f1,
> + 0x8f, 0xfc, 0x9f, 0xc4, 0xa9, 0xc9, 0xb7, 0xb0) },
> + /* 0x674F platform/8086:674f */
> + { 0x674F, GUID_INIT(0xdd8dd88e, 0xef2f, 0x59b1,
> + 0x99, 0x15, 0xdb, 0x6f, 0x1d, 0xc9, 0xb4, 0x5d) },
> + /* 0x6750 platform/8086:6750 */
> + { 0x6750, GUID_INIT(0x1dd66c44, 0x87d5, 0x524a,
> + 0xad, 0x6e, 0xfc, 0x18, 0x9d, 0x42, 0x6f, 0x1a) },
> + /* 0x6751 platform/8086:6751 */
> + { 0x6751, GUID_INIT(0x17d0dd04, 0x2fad, 0x5400,
> + 0x99, 0xc8, 0x9b, 0x45, 0x51, 0x3b, 0x67, 0xe3) },
I'd try to reuse INTEL_CRI_IDS() here instead of playing catch up on each update.
> +};
> +
> +static const guid_t *lookup_platform_id(const struct pci_dev *pdev)
> +{
> + unsigned int i;
> +
> + for (i = 0; i < ARRAY_SIZE(xe_platform_ids); i++)
> + if (xe_platform_ids[i].device_id == pdev->device)
> + return &xe_platform_ids[i].platform_id;
> + return NULL;
> +}
> +
> +static u64 cper_timestamp_now(void)
> +{
> + struct tm tm;
> + u64 ts = 0;
> + u8 *p = (u8 *)&ts;
> + int year;
> +
> + time64_to_tm(ktime_get_real_seconds(), 0, &tm);
> +
> + year = tm.tm_year + 1900;
> +
> + p[0] = bin2bcd(tm.tm_sec);
> + p[1] = bin2bcd(tm.tm_min);
> + p[2] = bin2bcd(tm.tm_hour);
> + p[3] = 0x1; /* precise time */
From what I understand a precise timestamp is the time of the error event
which needs to come from sysctrl firmware and not kernel, but please correct
me if I'm wrong.
> + p[4] = bin2bcd(tm.tm_mday);
> + p[5] = bin2bcd(tm.tm_mon + 1);
> + p[6] = bin2bcd(year % 100);
> + p[7] = bin2bcd(year / 100);
> +
> + return ts;
> +}
> +
> static void cper_init_intel_hdr(struct xe_device *xe,
> const struct xe_ras_error_class *counter,
> u64 first_timestamp, u32 sig_id, u32 error_count,
> @@ -58,6 +116,86 @@ static void cper_init_intel_hdr(struct xe_device *xe,
> /* TODO: fill fw_id and set XE_CPER_VALID_FW_ID */
> }
>
> +static void cper_init_record_hdr(struct xe_device *xe, u8 severity,
> + const guid_t *notification_type,
> + struct cper_record_header *rhdr,
> + u32 total_len)
> +{
> + const guid_t *platform_id;
> + struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> +
> + /* Assemble the CPER record header (UEFI Appendix N.2.1) */
> + memcpy(rhdr->signature, CPER_SIG_RECORD, CPER_SIG_SIZE);
> + rhdr->revision = CPER_RECORD_REV;
> + rhdr->signature_end = CPER_SIG_END;
> + rhdr->section_count = 1;
> + rhdr->error_severity = severity;
> + rhdr->validation_bits = CPER_VALID_TIMESTAMP;
> + rhdr->record_length = total_len;
> + rhdr->timestamp = cper_timestamp_now();
> + rhdr->creator_id = INTEL_CPER_CREATOR_XEKMD;
> + rhdr->notification_type = *notification_type;
> + rhdr->record_id = cper_next_record_id();
> + platform_id = lookup_platform_id(pdev);
> + if (platform_id) {
> + rhdr->platform_id = *platform_id;
> + rhdr->validation_bits |= CPER_VALID_PLATFORM_ID;
> + }
> +}
> +
> +static void cper_init_section_desc(struct xe_device *xe, u8 severity,
> + struct cper_section_descriptor *sdesc,
> + u32 einfo_len)
> +{
> + sdesc->section_offset = sizeof(struct cper_record_header) +
> + sizeof(struct cper_section_descriptor);
> + sdesc->section_length = sizeof(struct xe_cper_intel_hdr) + einfo_len;
> + sdesc->revision = CPER_SEC_REV;
> + sdesc->validation_bits = 0;
> + sdesc->section_type = INTEL_CPER_SECTION_ACCEL_GENERIC;
> + sdesc->section_severity = severity;
> + if (xe->info.has_device_uid) {
> + memcpy(&sdesc->fru_id, &xe->device_uid, sizeof(xe->device_uid));
> + sdesc->validation_bits |= CPER_SEC_VALID_FRU_ID;
> + }
> +}
> +
> +static void cper_record_emit(struct xe_device *xe, u8 severity,
> + const guid_t *notification_type,
> + const struct xe_cper_intel_hdr *ihdr,
> + const void *einfo, u32 einfo_len)
> +{
> + struct cper_section_descriptor *sdesc;
> + struct cper_record_header *rhdr;
> + struct xe_cper_nonstd_record *rec;
> + u32 total_len;
> +
> + total_len = sizeof(struct xe_cper_nonstd_record) + einfo_len;
> + rec = kzalloc(total_len, GFP_KERNEL);
> + if (!rec)
> + return;
> +
> + rhdr = &rec->record_hdr;
> + sdesc = &rec->section_desc;
> +
> + /* Assemble the CPER record header (UEFI Appendix N.2.1) */
> + cper_init_record_hdr(xe, severity, notification_type, rhdr, total_len);
> +
> + /* Assemble the section descriptor (UEFI Appendix N.2.2) */
> + cper_init_section_desc(xe, severity, sdesc, einfo_len);
> +
> + /* Copy the Intel-specific section header */
> + rec->intel_hdr = *ihdr;
> +
> + /* Append optional variable-length error info */
> + if (einfo && einfo_len)
> + memcpy((u8 *)rec + sizeof(*rec), einfo, einfo_len);
> +
> + /* TODO: Emit trace event */
> +
> + kfree(rec);
> +}
> +
> static void cper_emit_counter(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
> const struct xe_ras_error_class *counter,
> const struct xe_ras_get_counter_response *response)
> @@ -66,6 +204,7 @@ static void cper_emit_counter(struct xe_device *xe, int cper_sev, enum xe_sigid
>
> cper_init_intel_hdr(xe, counter, response->timestamp,
> sigid, response->value, &ihdr);
> + cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR, &ihdr, NULL, 0);
> }
>
> static void cper_emit_hw_err(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
> diff --git a/drivers/gpu/drm/xe/xe_cper_types.h b/drivers/gpu/drm/xe/xe_cper_types.h
> index a8730ff62b69..e32c7d539257 100644
> --- a/drivers/gpu/drm/xe/xe_cper_types.h
> +++ b/drivers/gpu/drm/xe/xe_cper_types.h
> @@ -6,7 +6,9 @@
> #ifndef _XE_CPER_TYPES_H_
> #define _XE_CPER_TYPES_H_
>
> +#include <linux/cper.h>
> #include <linux/types.h>
> +#include <linux/uuid.h>
>
> #include "xe_ras_types.h"
>
> @@ -21,6 +23,28 @@
> #define XE_CPER_VALID_PCI_BDF 0x0008
> #define XE_CPER_VALID_DRV_VERSION 0x0010
>
> +/*
> + * Intel CPER GUID Namespace — RFC 9562 UUIDv5 (SHA-1 name-based)
> + *
> + * All values below are generated deterministically by uuid generator.
> + * Do not hand-edit the byte values.
> + */
> +
> +/* Creator IDs */
> +#define INTEL_CPER_CREATOR_XEKMD \
> + GUID_INIT(0x9a42070f, 0xdf9d, 0x555e, \
> + 0xba, 0x02, 0x7c, 0xbc, 0x86, 0x3d, 0x37, 0x1c)
> +
> +/* Notification Types */
> +#define INTEL_CPER_NOTIFY_GPU_ERROR \
> + GUID_INIT(0x4ae12aef, 0x8745, 0x5fc7, \
> + 0xb9, 0x96, 0x71, 0xee, 0xbb, 0x51, 0xf2, 0x23)
> +
> +/* Section Types */
> +#define INTEL_CPER_SECTION_ACCEL_GENERIC \
> + GUID_INIT(0xea9d8f84, 0x4258, 0x5227, \
> + 0x80, 0x28, 0xb9, 0xb1, 0x3e, 0x6d, 0x58, 0xb0)
> +
> /**
> * struct xe_cper_intel_hdr - Intel-specific CPER header
> *
> @@ -48,4 +72,33 @@ struct xe_cper_intel_hdr {
> u8 reserved[5];
> } __packed;
>
> +/**
> + * struct xe_cper_nonstd_record - Intel GPU CPER record
> + *
> + * Contains the standard CPER record header, section descriptor, and the
> + * Intel error section header.
> + */
> +struct xe_cper_nonstd_record {
> + /** @record_hdr: Standard CPER record header (UEFI Appendix N.2.1) */
> + struct cper_record_header record_hdr;
> + /** @section_desc: CPER section descriptor */
> + struct cper_section_descriptor section_desc;
> + /** @intel_hdr: Intel-specific CPER header */
> + struct xe_cper_intel_hdr intel_hdr;
> +} __packed;
> +
> +/**
> + * struct xe_platform_id_entry - Mapping from PCI device ID to CPER platform GUID
'xe_device_guid_entry'
> + *
> + * Used to resolve the platform_id field in a CPER section descriptor.
> + * GUIDs are UUIDv5 (RFC 9562, SHA-1) derived from the Intel CPER namespace
> + * with name string "platform/8086:<dev_id_hex_lower>".
> + */
> +struct xe_platform_id_entry {
> + /** @device_id: PCI device ID */
> + u16 device_id;
> + /** @platform_id: Corresponding UUIDv5 platform GUID */
> + guid_t platform_id;
'guid'
Raag
> +};
> +
> #endif
> --
> 2.54.0
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v5 05/13] drm/xe/cper: Log CPER records for aggregate counter retrieval
2026-10-23 4:34 ` [PATCH v5 05/13] drm/xe/cper: Log CPER records for aggregate counter retrieval Badal Nilawar
@ 2026-10-26 11:31 ` Raag Jadav
0 siblings, 0 replies; 37+ messages in thread
From: Raag Jadav @ 2026-10-26 11:31 UTC (permalink / raw)
To: Badal Nilawar
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
On Fri, Oct 23, 2026 at 10:04:27AM +0530, Badal Nilawar wrote:
> Log CPER records for aggregate counter retrieval from userspace when
> cper_on_query sysfs is enabled.
...
> +static enum xe_sigid ras_comp_to_hw_sigid(u8 component)
Group these with other 'component' switcheroos, preferably above
ras_status_to_errno().
> +{
> + switch (component) {
> + case XE_RAS_COMP_DEVICE_MEMORY:
> + return XE_SIGID_DEVICE_MEMORY;
> + case XE_RAS_COMP_CORE_COMPUTE:
> + return XE_SIGID_CORE_COMPUTE;
> + case XE_RAS_COMP_PCIE:
> + return XE_SIGID_PCIE;
> + case XE_RAS_COMP_FABRIC:
> + return XE_SIGID_FABRIC;
> + case XE_RAS_COMP_SOC_INTERNAL:
> + return XE_SIGID_SOC_INTERNAL;
> + default:
> + return XE_SIGID_HW;
> + }
> +}
> +
> +static u8 ras_sev_to_cper_sev(u8 ras_sev)
Ditto, move this above drm_to_xe_ras_component() with other 'severity'
switcheroos. Also use 'severity' as parameter name.
> +{
> + switch (ras_sev) {
> + case XE_RAS_SEV_CORRECTABLE:
> + return CPER_SEV_CORRECTED;
> + case XE_RAS_SEV_UNCORRECTABLE:
> + return CPER_SEV_RECOVERABLE;
> + case XE_RAS_SEV_INFORMATIONAL:
> + return CPER_SEV_INFORMATIONAL;
> + default:
> + return CPER_SEV_RECOVERABLE;
> + }
> +}
...
> @@ -1248,5 +1285,9 @@ int xe_ras_init(struct xe_device *xe)
> if (ret)
> xe_err(xe, "Failed to create GPU health sysfs, err=%d\n", ret);
>
> + ret = xe_cper_sysfs_init(xe);
> + if (ret)
> + xe_err(xe, "Failed to create cper_on_query sysfs, err=%d\n", ret);
This function is int now, so let's not hide bugs and return the error.
Raag
> +
> return devm_add_action_or_reset(xe->drm.dev, ras_fini, xe);
> }
> --
> 2.54.0
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v5 06/13] drm/xe/cper: Emit cper record to trace buf
2026-10-23 4:34 ` [PATCH v5 06/13] drm/xe/cper: Emit cper record to trace buf Badal Nilawar
@ 2026-10-26 12:29 ` Raag Jadav
2026-10-27 4:21 ` Nilawar, Badal
0 siblings, 1 reply; 37+ messages in thread
From: Raag Jadav @ 2026-10-26 12:29 UTC (permalink / raw)
To: Badal Nilawar
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
On Fri, Oct 23, 2026 at 10:04:28AM +0530, Badal Nilawar wrote:
> Add the xe_error_cper tracepoint and emit each assembled CPER record
> through it. Besides the raw record, the event carries the device name,
> platform ID, FRU ID, severity and the Intel error section header, so
> tools can pick up the records from the trace buffer.
...
> + * Example trace output::
> + *
> + * xe_error_cper: dev=0000:03:00.0 severity=2
> + * platform_id=9046afe5-9041-5124-8614-92550d9e9da6
> + * fru_id=91befe38-2f61-3d7b-0000-000000000000
> + * intel_err_hdr_raw=
'intel_hdr_raw'
> + * 01 02 00 18 00 00 00 01 00 00 00 00 64 77 51 14 ...
> + * cper_len=1772
> + * cper_raw=
> + * 43 50 45 52 00 01 ff ff ff ff 01 00 02 00 00 00 ...
...
> + TP_printk("dev=%s severity=%d platform_id=%pUl fru_id=%pUl intel_err_hdr_raw=%s cper_len=%u cper_raw=%s",
Ditto.
Raag
> + __get_str(dev), __entry->sev,
> + __entry->platform_id, __entry->fru_id,
> + __print_hex(__entry->ihdr_raw,
> + sizeof(struct xe_cper_intel_hdr)),
> + __entry->cper_len,
> + __print_hex(__get_dynamic_array(cper),
> + __entry->cper_len))
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v5 07/13] drm/xe/xe_ras: Report device memory errors using SIGID
2026-10-23 4:34 ` [PATCH v5 07/13] drm/xe/xe_ras: Report device memory errors using SIGID Badal Nilawar
@ 2026-10-26 12:47 ` Raag Jadav
2026-10-26 18:31 ` Nilawar, Badal
0 siblings, 1 reply; 37+ messages in thread
From: Raag Jadav @ 2026-10-26 12:47 UTC (permalink / raw)
To: Badal Nilawar
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
On Fri, Oct 23, 2026 at 10:04:29AM +0530, Badal Nilawar wrote:
> Use xe_log_comp_info helper to report device memory errors using the
> corresponding SIGID.
>
> Example:
> xe 0000:03:00.0: [drm] SIGID=202 (020100020008002000300000)
> DEVICE_MEMORY: Double-bit ECC error detected at sw address 0x63000
>
> Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> Cc: Riana Tauro <riana.tauro@intel.com>
> ---
> v5:
> - Log unknown memory errors
> - Add example log in commit message (Raag)
> ---
> drivers/gpu/drm/xe/xe_ras.c | 20 +++++++++++++++++---
> 1 file changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 95e87c635b04..5ebfc6e8dfc7 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -643,6 +643,7 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
> static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_array *arr)
> {
> struct xe_ras_memory_error *info = (void *)arr->details;
> + u8 cper_sev = ras_sev_to_cper_sev(arr->counter.common.severity);
> int ret;
>
> /*
> @@ -654,17 +655,30 @@ static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_
> */
> switch (info->category) {
> case XE_RAS_MEMORY_POISON:
> - xe_info(xe, "[RAS]: Poison error detected\n");
> + xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
> + "Poison error detected\n");
> break;
> case XE_RAS_MEMORY_DATA_PARITY:
> - xe_info(xe, "[RAS]: Data parity error detected\n");
> + xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
> + "Data parity error detected\n");
> break;
> case XE_RAS_MEMORY_DB_ECC:
> ret = handle_page_offline(xe, info->sw_address, true);
> - if (ret)
> + if (ret) {
> + xe_log_comp(xe, cper_sev, DEVICE_MEMORY,
> + &arr->counter, sizeof(arr->counter),
> + "Failed to recover double-bit ECC error at sw address 0x%llx\n",
> + info->sw_address);
Isn't handle_page_offline() already logging this? If no, shouldn't we
try to consolidate?
> return XE_RAS_RECOVERY_ACTION_RESET;
> + }
> +
> + xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
> + "Double-bit ECC error at sw address 0x%llx\n",
> + info->sw_address);
Ditto.
Raag
> break;
> default:
> + xe_log_comp(xe, cper_sev, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
> + "Unknown error detected\n");
> return XE_RAS_RECOVERY_ACTION_RESET;
> }
>
> --
> 2.54.0
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v5 09/13] drm/xe/xe_ras: Report soc internal errors using SIGID
2026-10-23 4:34 ` [PATCH v5 09/13] drm/xe/xe_ras: Report soc internal " Badal Nilawar
2026-10-23 6:16 ` Mallesh, Koujalagi
@ 2026-10-26 12:57 ` Raag Jadav
1 sibling, 0 replies; 37+ messages in thread
From: Raag Jadav @ 2026-10-26 12:57 UTC (permalink / raw)
To: Badal Nilawar
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
On Fri, Oct 23, 2026 at 10:04:31AM +0530, Badal Nilawar wrote:
> Use xe_log_* helpers to report soc internal errors.
>
> Example:
> xe 0000:03:00.0: [drm] *ERROR* SIGID=205 FATAL
> (020600700000000000000000) [Hardware Error]: SOC_INTERNAL:
> PUNIT error detected: 0x00000002
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> Cc: Riana Tauro <riana.tauro@intel.com>
> ---
> v5:
> - Log unknown soc internal errors
> ---
> drivers/gpu/drm/xe/xe_ras.c | 16 +++++++++-------
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 1f94dd1fb91b..4408fc530900 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -608,7 +608,6 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
> {
> struct xe_ras_soc_error *info = (void *)arr->details;
> struct xe_ras_soc_error_source *source = &info->source;
> - struct xe_ras_error_class *counter = &arr->counter;
>
> if (source->csc) {
> struct xe_ras_csc_error *csc_error = (void *)info->details;
> @@ -622,9 +621,8 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
> * is required.
> */
> if (csc_error->hec_fw_error) {
> - xe_err(xe, "[RAS]: CSC %s detected: 0x%x\n",
> - sev_to_str(counter->common.severity),
> - csc_error->hec_fw_error);
> + xe_log_comp_fatal(xe, SOC_INTERNAL, &arr->counter, sizeof(arr->counter),
> + "CSC error detected: 0x%08x\n", csc_error->hec_fw_error);
> xe_survivability_mode_runtime_enable(xe);
> return XE_RAS_RECOVERY_ACTION_DISCONNECT;
> }
> @@ -632,15 +630,19 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
> struct xe_ras_ieh_error *ieh_error = (void *)info->details;
>
> if (ieh_error->global_error_status & XE_RAS_SOC_IEH_PUNIT) {
> - xe_err(xe, "[RAS]: PUNIT %s detected: 0x%x\n",
> - sev_to_str(counter->common.severity),
> - ieh_error->global_error_status);
> + xe_log_comp_fatal(xe, SOC_INTERNAL, &arr->counter, sizeof(arr->counter),
> + "PUNIT error detected: 0x%08x\n",
> + ieh_error->global_error_status);
> punit_error_handler(xe);
> return XE_RAS_RECOVERY_ACTION_DISCONNECT;
> }
> }
>
> /* For other SoC internal errors, request a reset as recovery mechanism */
> + xe_log_comp(xe, ras_sev_to_cper_sev(arr->counter.common.severity), SOC_INTERNAL,
> + &arr->counter, sizeof(arr->counter),
> + "Unknown error detected (csc=%u ieh=%u)\n",
If the error is unknown, we may want to print the entire source using 0x%08x.
Raag
> + source->csc, source->ieh);
> return XE_RAS_RECOVERY_ACTION_RESET;
> }
>
> --
> 2.54.0
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v5 10/13] drm/xe/xe_ras: Report correctable errors using SIGID
2026-10-23 4:34 ` [PATCH v5 10/13] drm/xe/xe_ras: Report correctable " Badal Nilawar
@ 2026-10-26 15:17 ` Raag Jadav
2026-10-27 4:13 ` Raag Jadav
0 siblings, 1 reply; 37+ messages in thread
From: Raag Jadav @ 2026-10-26 15:17 UTC (permalink / raw)
To: Badal Nilawar
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
On Fri, Oct 23, 2026 at 10:04:32AM +0530, Badal Nilawar wrote:
> Use xe_log_* helper to report correctable errors.
>
> Example:
> xe 0000:03:00.0: [drm] *ERROR* SIGID=203 CORRECTED
> (010200180000000100000000) [Hardware Error]: CORE_COMPUTE: error detected
>
> Assisted-by: LLM
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> Cc: Raag Jadav <raag.jadav@intel.com>
> ---
> v4:
> - Pass structured log component to xe_log_from() (sashiko)
> ---
> drivers/gpu/drm/xe/xe_ras.c | 15 +++++++++++++--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 4408fc530900..cd64baddd8de 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -3,6 +3,8 @@
> * Copyright © 2026 Intel Corporation
> */
>
> +#include <linux/bitfield.h>
> +
> #include "xe_assert.h"
> #include "xe_bo.h"
> #include "xe_configfs.h"
> @@ -226,6 +228,12 @@ static u8 ras_sev_to_cper_sev(u8 ras_sev)
> }
> }
>
> +static u16 ras_comp_to_log_comp(u8 component)
I know xe_log_component_bits is u16 but I'd use u32 here to make this consistent
with __xe_log_emit(), which is ultimately how I think it's going to be consumed.
Raag
> +{
> + return FIELD_PREP(XE_LOG_COMPONENT_CLASS_MASK, XE_LOG_COMPONENT_CLASS_HARDWARE) |
> + FIELD_PREP(XE_LOG_COMPONENT_TYPE_MASK, component);
> +}
> +
> static inline const char *sev_to_str(u8 severity)
> {
> if (severity >= XE_RAS_SEV_MAX)
> @@ -717,8 +725,11 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe,
> if (!ras_counter_is_valid(xe, &errors[id]))
> continue;
>
> - xe_warn(xe, "[RAS]: %s %s detected\n",
> - comp_to_str(component), sev_to_str(severity));
> + xe_log_from(xe, ras_sev_to_cper_sev(severity),
> + ras_comp_to_hw_sigid(component),
> + ras_comp_to_log_comp(component),
> + &errors[id], sizeof(errors[id]),
> + "error detected\n");
>
> /* Send event once per component */
> if (sent & BIT(component))
> --
> 2.54.0
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v5 07/13] drm/xe/xe_ras: Report device memory errors using SIGID
2026-10-26 12:47 ` Raag Jadav
@ 2026-10-26 18:31 ` Nilawar, Badal
2026-10-27 1:29 ` Raag Jadav
0 siblings, 1 reply; 37+ messages in thread
From: Nilawar, Badal @ 2026-10-26 18:31 UTC (permalink / raw)
To: Raag Jadav
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
On 26-10-2026 18:17, Raag Jadav wrote:
> On Fri, Oct 23, 2026 at 10:04:29AM +0530, Badal Nilawar wrote:
>> Use xe_log_comp_info helper to report device memory errors using the
>> corresponding SIGID.
>>
>> Example:
>> xe 0000:03:00.0: [drm] SIGID=202 (020100020008002000300000)
>> DEVICE_MEMORY: Double-bit ECC error detected at sw address 0x63000
>>
>> Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
>> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
>> Cc: Riana Tauro <riana.tauro@intel.com>
>> ---
>> v5:
>> - Log unknown memory errors
>> - Add example log in commit message (Raag)
>> ---
>> drivers/gpu/drm/xe/xe_ras.c | 20 +++++++++++++++++---
>> 1 file changed, 17 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
>> index 95e87c635b04..5ebfc6e8dfc7 100644
>> --- a/drivers/gpu/drm/xe/xe_ras.c
>> +++ b/drivers/gpu/drm/xe/xe_ras.c
>> @@ -643,6 +643,7 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
>> static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_array *arr)
>> {
>> struct xe_ras_memory_error *info = (void *)arr->details;
>> + u8 cper_sev = ras_sev_to_cper_sev(arr->counter.common.severity);
>> int ret;
>>
>> /*
>> @@ -654,17 +655,30 @@ static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_
>> */
>> switch (info->category) {
>> case XE_RAS_MEMORY_POISON:
>> - xe_info(xe, "[RAS]: Poison error detected\n");
>> + xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
>> + "Poison error detected\n");
>> break;
>> case XE_RAS_MEMORY_DATA_PARITY:
>> - xe_info(xe, "[RAS]: Data parity error detected\n");
>> + xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
>> + "Data parity error detected\n");
>> break;
>> case XE_RAS_MEMORY_DB_ECC:
>> ret = handle_page_offline(xe, info->sw_address, true);
>> - if (ret)
>> + if (ret) {
>> + xe_log_comp(xe, cper_sev, DEVICE_MEMORY,
>> + &arr->counter, sizeof(arr->counter),
>> + "Failed to recover double-bit ECC error at sw address 0x%llx\n",
>> + info->sw_address);
> Isn't handle_page_offline() already logging this? If no, shouldn't we
> try to consolidate?
It doesn't emit CPER. I will consolidate this to
xe_log_comp(xe, ret ? cper_sev : CPER_SEV_INFORMATIONAL,
DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
"Double-bit ECC error at sw
address 0x%llx\n", info->sw_address);
if (ret)
return XE_RAS_RECOVERY_ACTION_RESET;
Thanks,
Badal
>
>> return XE_RAS_RECOVERY_ACTION_RESET;
>> + }
>> +
>> + xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
>> + "Double-bit ECC error at sw address 0x%llx\n",
>> + info->sw_address);
> Ditto.
>
> Raag
>
>> break;
>> default:
>> + xe_log_comp(xe, cper_sev, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
>> + "Unknown error detected\n");
>> return XE_RAS_RECOVERY_ACTION_RESET;
>> }
>>
>> --
>> 2.54.0
>>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v5 07/13] drm/xe/xe_ras: Report device memory errors using SIGID
2026-10-26 18:31 ` Nilawar, Badal
@ 2026-10-27 1:29 ` Raag Jadav
2026-10-27 6:03 ` Nilawar, Badal
0 siblings, 1 reply; 37+ messages in thread
From: Raag Jadav @ 2026-10-27 1:29 UTC (permalink / raw)
To: Nilawar, Badal
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
On Tue, Oct 27, 2026 at 12:01:42AM +0530, Nilawar, Badal wrote:
> On 26-10-2026 18:17, Raag Jadav wrote:
> > On Fri, Oct 23, 2026 at 10:04:29AM +0530, Badal Nilawar wrote:
> > > Use xe_log_comp_info helper to report device memory errors using the
> > > corresponding SIGID.
> > >
> > > Example:
> > > xe 0000:03:00.0: [drm] SIGID=202 (020100020008002000300000)
> > > DEVICE_MEMORY: Double-bit ECC error detected at sw address 0x63000
> > >
> > > Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> > > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> > > Cc: Riana Tauro <riana.tauro@intel.com>
> > > ---
> > > v5:
> > > - Log unknown memory errors
> > > - Add example log in commit message (Raag)
> > > ---
> > > drivers/gpu/drm/xe/xe_ras.c | 20 +++++++++++++++++---
> > > 1 file changed, 17 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> > > index 95e87c635b04..5ebfc6e8dfc7 100644
> > > --- a/drivers/gpu/drm/xe/xe_ras.c
> > > +++ b/drivers/gpu/drm/xe/xe_ras.c
> > > @@ -643,6 +643,7 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
> > > static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_array *arr)
> > > {
> > > struct xe_ras_memory_error *info = (void *)arr->details;
> > > + u8 cper_sev = ras_sev_to_cper_sev(arr->counter.common.severity);
> > > int ret;
> > > /*
> > > @@ -654,17 +655,30 @@ static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_
> > > */
> > > switch (info->category) {
> > > case XE_RAS_MEMORY_POISON:
> > > - xe_info(xe, "[RAS]: Poison error detected\n");
> > > + xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
> > > + "Poison error detected\n");
> > > break;
> > > case XE_RAS_MEMORY_DATA_PARITY:
> > > - xe_info(xe, "[RAS]: Data parity error detected\n");
> > > + xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
> > > + "Data parity error detected\n");
> > > break;
> > > case XE_RAS_MEMORY_DB_ECC:
> > > ret = handle_page_offline(xe, info->sw_address, true);
> > > - if (ret)
> > > + if (ret) {
> > > + xe_log_comp(xe, cper_sev, DEVICE_MEMORY,
> > > + &arr->counter, sizeof(arr->counter),
> > > + "Failed to recover double-bit ECC error at sw address 0x%llx\n",
> > > + info->sw_address);
> > Isn't handle_page_offline() already logging this? If no, shouldn't we
> > try to consolidate?
>
> It doesn't emit CPER.
So perhaps convert them into cper instead of duplicating logs?
Raag
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v5 04/13] drm/xe/cper: Construct CPER record for hardware errors
2026-10-26 9:54 ` Raag Jadav
@ 2026-10-27 3:34 ` Nilawar, Badal
0 siblings, 0 replies; 37+ messages in thread
From: Nilawar, Badal @ 2026-10-27 3:34 UTC (permalink / raw)
To: Raag Jadav
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
On 26-10-2026 15:24, Raag Jadav wrote:
> On Fri, Oct 23, 2026 at 10:04:26AM +0530, Badal Nilawar wrote:
>> Assemble the CPER record header, section descriptor and the Intel
>> error section for Intel GPU hardware errors.
>>
>> Assisted-by: LLM
>> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
>> ---
>> v5:
>> - Rebased
>> - Add helpers to initialize CPER headers (Raag)
>> v4:
>> - Split from "drm/xe/cper: Prepare CPER record" (Raag)
>> - Use xe->device_uid for FRU ID
>> - Add platform IDs for all CRI PCI device IDs
>> v2:
>> - Encode cper_record_header timestamp in BCD format (sashiko)
>> ---
>> drivers/gpu/drm/xe/xe_cper.c | 139 +++++++++++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_cper_types.h | 53 +++++++++++
>> 2 files changed, 192 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
>> index 3d7657517223..012693fe48c4 100644
>> --- a/drivers/gpu/drm/xe/xe_cper.c
>> +++ b/drivers/gpu/drm/xe/xe_cper.c
>> @@ -3,10 +3,14 @@
>> * Copyright © 2026 Intel Corporation
>> */
>>
>> +#include <linux/bcd.h>
>> #include <linux/err.h>
>> #include <linux/kernel.h>
>> #include <linux/minmax.h>
>> #include <linux/pci.h>
>> +#include <linux/slab.h>
>> +#include <linux/time.h>
>> +#include <linux/timekeeping.h>
>>
>> #include "xe_cper.h"
>> #include "xe_cper_types.h"
>> @@ -25,6 +29,60 @@ static bool is_hw_sigid(enum xe_sigid sigid)
>> return in_range(sigid, INTEL_SIGID_GPU_XE_HARDWARE_START, INTEL_SIGID_BATCH);
>> }
>>
>> +static const struct xe_platform_id_entry xe_platform_ids[] = {
> In xe terminology platform signifies the name, which is different from device
> id (which looks like the mapping is for). So this can be xe_device_guid_entry
> or something like that.
ok
>
>> + /* 0x674C platform/8086:674c */
>> + { 0x674C, GUID_INIT(0x9046afe5, 0x9041, 0x5124,
>> + 0x86, 0x14, 0x92, 0x55, 0x0d, 0x9e, 0x9d, 0xa6) },
>> + /* 0x674D platform/8086:674d */
>> + { 0x674D, GUID_INIT(0xf95911b8, 0x6564, 0x5905,
>> + 0xa6, 0xa7, 0xb9, 0xbf, 0x54, 0xab, 0x6c, 0x27) },
>> + /* 0x674E platform/8086:674e */
>> + { 0x674E, GUID_INIT(0xb8d24106, 0x0108, 0x59f1,
>> + 0x8f, 0xfc, 0x9f, 0xc4, 0xa9, 0xc9, 0xb7, 0xb0) },
>> + /* 0x674F platform/8086:674f */
>> + { 0x674F, GUID_INIT(0xdd8dd88e, 0xef2f, 0x59b1,
>> + 0x99, 0x15, 0xdb, 0x6f, 0x1d, 0xc9, 0xb4, 0x5d) },
>> + /* 0x6750 platform/8086:6750 */
>> + { 0x6750, GUID_INIT(0x1dd66c44, 0x87d5, 0x524a,
>> + 0xad, 0x6e, 0xfc, 0x18, 0x9d, 0x42, 0x6f, 0x1a) },
>> + /* 0x6751 platform/8086:6751 */
>> + { 0x6751, GUID_INIT(0x17d0dd04, 0x2fad, 0x5400,
>> + 0x99, 0xc8, 0x9b, 0x45, 0x51, 0x3b, 0x67, 0xe3) },
> I'd try to reuse INTEL_CRI_IDS() here instead of playing catch up on each update.
How?
>
>> +};
>> +
>> +static const guid_t *lookup_platform_id(const struct pci_dev *pdev)
>> +{
>> + unsigned int i;
>> +
>> + for (i = 0; i < ARRAY_SIZE(xe_platform_ids); i++)
>> + if (xe_platform_ids[i].device_id == pdev->device)
>> + return &xe_platform_ids[i].platform_id;
>> + return NULL;
>> +}
>> +
>> +static u64 cper_timestamp_now(void)
>> +{
>> + struct tm tm;
>> + u64 ts = 0;
>> + u8 *p = (u8 *)&ts;
>> + int year;
>> +
>> + time64_to_tm(ktime_get_real_seconds(), 0, &tm);
>> +
>> + year = tm.tm_year + 1900;
>> +
>> + p[0] = bin2bcd(tm.tm_sec);
>> + p[1] = bin2bcd(tm.tm_min);
>> + p[2] = bin2bcd(tm.tm_hour);
>> + p[3] = 0x1; /* precise time */
> From what I understand a precise timestamp is the time of the error event
> which needs to come from sysctrl firmware and not kernel, but please correct
> me if I'm wrong.
True, I will drop precise. This is timestamp when error info collected
to generate CPER log.
>
>> + p[4] = bin2bcd(tm.tm_mday);
>> + p[5] = bin2bcd(tm.tm_mon + 1);
>> + p[6] = bin2bcd(year % 100);
>> + p[7] = bin2bcd(year / 100);
>> +
>> + return ts;
>> +}
>> +
>> static void cper_init_intel_hdr(struct xe_device *xe,
>> const struct xe_ras_error_class *counter,
>> u64 first_timestamp, u32 sig_id, u32 error_count,
>> @@ -58,6 +116,86 @@ static void cper_init_intel_hdr(struct xe_device *xe,
>> /* TODO: fill fw_id and set XE_CPER_VALID_FW_ID */
>> }
>>
>> +static void cper_init_record_hdr(struct xe_device *xe, u8 severity,
>> + const guid_t *notification_type,
>> + struct cper_record_header *rhdr,
>> + u32 total_len)
>> +{
>> + const guid_t *platform_id;
>> + struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
>> +
>> + /* Assemble the CPER record header (UEFI Appendix N.2.1) */
>> + memcpy(rhdr->signature, CPER_SIG_RECORD, CPER_SIG_SIZE);
>> + rhdr->revision = CPER_RECORD_REV;
>> + rhdr->signature_end = CPER_SIG_END;
>> + rhdr->section_count = 1;
>> + rhdr->error_severity = severity;
>> + rhdr->validation_bits = CPER_VALID_TIMESTAMP;
>> + rhdr->record_length = total_len;
>> + rhdr->timestamp = cper_timestamp_now();
>> + rhdr->creator_id = INTEL_CPER_CREATOR_XEKMD;
>> + rhdr->notification_type = *notification_type;
>> + rhdr->record_id = cper_next_record_id();
>> + platform_id = lookup_platform_id(pdev);
>> + if (platform_id) {
>> + rhdr->platform_id = *platform_id;
>> + rhdr->validation_bits |= CPER_VALID_PLATFORM_ID;
>> + }
>> +}
>> +
>> +static void cper_init_section_desc(struct xe_device *xe, u8 severity,
>> + struct cper_section_descriptor *sdesc,
>> + u32 einfo_len)
>> +{
>> + sdesc->section_offset = sizeof(struct cper_record_header) +
>> + sizeof(struct cper_section_descriptor);
>> + sdesc->section_length = sizeof(struct xe_cper_intel_hdr) + einfo_len;
>> + sdesc->revision = CPER_SEC_REV;
>> + sdesc->validation_bits = 0;
>> + sdesc->section_type = INTEL_CPER_SECTION_ACCEL_GENERIC;
>> + sdesc->section_severity = severity;
>> + if (xe->info.has_device_uid) {
>> + memcpy(&sdesc->fru_id, &xe->device_uid, sizeof(xe->device_uid));
>> + sdesc->validation_bits |= CPER_SEC_VALID_FRU_ID;
>> + }
>> +}
>> +
>> +static void cper_record_emit(struct xe_device *xe, u8 severity,
>> + const guid_t *notification_type,
>> + const struct xe_cper_intel_hdr *ihdr,
>> + const void *einfo, u32 einfo_len)
>> +{
>> + struct cper_section_descriptor *sdesc;
>> + struct cper_record_header *rhdr;
>> + struct xe_cper_nonstd_record *rec;
>> + u32 total_len;
>> +
>> + total_len = sizeof(struct xe_cper_nonstd_record) + einfo_len;
>> + rec = kzalloc(total_len, GFP_KERNEL);
>> + if (!rec)
>> + return;
>> +
>> + rhdr = &rec->record_hdr;
>> + sdesc = &rec->section_desc;
>> +
>> + /* Assemble the CPER record header (UEFI Appendix N.2.1) */
>> + cper_init_record_hdr(xe, severity, notification_type, rhdr, total_len);
>> +
>> + /* Assemble the section descriptor (UEFI Appendix N.2.2) */
>> + cper_init_section_desc(xe, severity, sdesc, einfo_len);
>> +
>> + /* Copy the Intel-specific section header */
>> + rec->intel_hdr = *ihdr;
>> +
>> + /* Append optional variable-length error info */
>> + if (einfo && einfo_len)
>> + memcpy((u8 *)rec + sizeof(*rec), einfo, einfo_len);
>> +
>> + /* TODO: Emit trace event */
>> +
>> + kfree(rec);
>> +}
>> +
>> static void cper_emit_counter(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
>> const struct xe_ras_error_class *counter,
>> const struct xe_ras_get_counter_response *response)
>> @@ -66,6 +204,7 @@ static void cper_emit_counter(struct xe_device *xe, int cper_sev, enum xe_sigid
>>
>> cper_init_intel_hdr(xe, counter, response->timestamp,
>> sigid, response->value, &ihdr);
>> + cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR, &ihdr, NULL, 0);
>> }
>>
>> static void cper_emit_hw_err(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
>> diff --git a/drivers/gpu/drm/xe/xe_cper_types.h b/drivers/gpu/drm/xe/xe_cper_types.h
>> index a8730ff62b69..e32c7d539257 100644
>> --- a/drivers/gpu/drm/xe/xe_cper_types.h
>> +++ b/drivers/gpu/drm/xe/xe_cper_types.h
>> @@ -6,7 +6,9 @@
>> #ifndef _XE_CPER_TYPES_H_
>> #define _XE_CPER_TYPES_H_
>>
>> +#include <linux/cper.h>
>> #include <linux/types.h>
>> +#include <linux/uuid.h>
>>
>> #include "xe_ras_types.h"
>>
>> @@ -21,6 +23,28 @@
>> #define XE_CPER_VALID_PCI_BDF 0x0008
>> #define XE_CPER_VALID_DRV_VERSION 0x0010
>>
>> +/*
>> + * Intel CPER GUID Namespace — RFC 9562 UUIDv5 (SHA-1 name-based)
>> + *
>> + * All values below are generated deterministically by uuid generator.
>> + * Do not hand-edit the byte values.
>> + */
>> +
>> +/* Creator IDs */
>> +#define INTEL_CPER_CREATOR_XEKMD \
>> + GUID_INIT(0x9a42070f, 0xdf9d, 0x555e, \
>> + 0xba, 0x02, 0x7c, 0xbc, 0x86, 0x3d, 0x37, 0x1c)
>> +
>> +/* Notification Types */
>> +#define INTEL_CPER_NOTIFY_GPU_ERROR \
>> + GUID_INIT(0x4ae12aef, 0x8745, 0x5fc7, \
>> + 0xb9, 0x96, 0x71, 0xee, 0xbb, 0x51, 0xf2, 0x23)
>> +
>> +/* Section Types */
>> +#define INTEL_CPER_SECTION_ACCEL_GENERIC \
>> + GUID_INIT(0xea9d8f84, 0x4258, 0x5227, \
>> + 0x80, 0x28, 0xb9, 0xb1, 0x3e, 0x6d, 0x58, 0xb0)
>> +
>> /**
>> * struct xe_cper_intel_hdr - Intel-specific CPER header
>> *
>> @@ -48,4 +72,33 @@ struct xe_cper_intel_hdr {
>> u8 reserved[5];
>> } __packed;
>>
>> +/**
>> + * struct xe_cper_nonstd_record - Intel GPU CPER record
>> + *
>> + * Contains the standard CPER record header, section descriptor, and the
>> + * Intel error section header.
>> + */
>> +struct xe_cper_nonstd_record {
>> + /** @record_hdr: Standard CPER record header (UEFI Appendix N.2.1) */
>> + struct cper_record_header record_hdr;
>> + /** @section_desc: CPER section descriptor */
>> + struct cper_section_descriptor section_desc;
>> + /** @intel_hdr: Intel-specific CPER header */
>> + struct xe_cper_intel_hdr intel_hdr;
>> +} __packed;
>> +
>> +/**
>> + * struct xe_platform_id_entry - Mapping from PCI device ID to CPER platform GUID
> 'xe_device_guid_entry'
Ok.
>
>> + *
>> + * Used to resolve the platform_id field in a CPER section descriptor.
>> + * GUIDs are UUIDv5 (RFC 9562, SHA-1) derived from the Intel CPER namespace
>> + * with name string "platform/8086:<dev_id_hex_lower>".
>> + */
>> +struct xe_platform_id_entry {
>> + /** @device_id: PCI device ID */
>> + u16 device_id;
>> + /** @platform_id: Corresponding UUIDv5 platform GUID */
>> + guid_t platform_id;
> 'guid'
Ok
Thanks,
Badal
>
> Raag
>
>> +};
>> +
>> #endif
>> --
>> 2.54.0
>>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v5 10/13] drm/xe/xe_ras: Report correctable errors using SIGID
2026-10-26 15:17 ` Raag Jadav
@ 2026-10-27 4:13 ` Raag Jadav
0 siblings, 0 replies; 37+ messages in thread
From: Raag Jadav @ 2026-10-27 4:13 UTC (permalink / raw)
To: Badal Nilawar
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
On Mon, Oct 26, 2026 at 04:17:50PM +0100, Raag Jadav wrote:
> On Fri, Oct 23, 2026 at 10:04:32AM +0530, Badal Nilawar wrote:
> > Use xe_log_* helper to report correctable errors.
> >
> > Example:
> > xe 0000:03:00.0: [drm] *ERROR* SIGID=203 CORRECTED
> > (010200180000000100000000) [Hardware Error]: CORE_COMPUTE: error detected
> >
> > Assisted-by: LLM
> > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> > Cc: Raag Jadav <raag.jadav@intel.com>
> > ---
> > v4:
> > - Pass structured log component to xe_log_from() (sashiko)
> > ---
> > drivers/gpu/drm/xe/xe_ras.c | 15 +++++++++++++--
> > 1 file changed, 13 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> > index 4408fc530900..cd64baddd8de 100644
> > --- a/drivers/gpu/drm/xe/xe_ras.c
> > +++ b/drivers/gpu/drm/xe/xe_ras.c
> > @@ -3,6 +3,8 @@
> > * Copyright © 2026 Intel Corporation
> > */
> >
> > +#include <linux/bitfield.h>
> > +
> > #include "xe_assert.h"
> > #include "xe_bo.h"
> > #include "xe_configfs.h"
> > @@ -226,6 +228,12 @@ static u8 ras_sev_to_cper_sev(u8 ras_sev)
> > }
> > }
> >
> > +static u16 ras_comp_to_log_comp(u8 component)
>
> I know xe_log_component_bits is u16 but I'd use u32 here to make this consistent
> with __xe_log_emit(), which is ultimately how I think it's going to be consumed.
On second thought, you can keep it as u16.
Reviewed-by: Raag Jadav <raag.jadav@intel.com>
> > +{
> > + return FIELD_PREP(XE_LOG_COMPONENT_CLASS_MASK, XE_LOG_COMPONENT_CLASS_HARDWARE) |
> > + FIELD_PREP(XE_LOG_COMPONENT_TYPE_MASK, component);
> > +}
> > +
> > static inline const char *sev_to_str(u8 severity)
> > {
> > if (severity >= XE_RAS_SEV_MAX)
> > @@ -717,8 +725,11 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe,
> > if (!ras_counter_is_valid(xe, &errors[id]))
> > continue;
> >
> > - xe_warn(xe, "[RAS]: %s %s detected\n",
> > - comp_to_str(component), sev_to_str(severity));
> > + xe_log_from(xe, ras_sev_to_cper_sev(severity),
> > + ras_comp_to_hw_sigid(component),
> > + ras_comp_to_log_comp(component),
> > + &errors[id], sizeof(errors[id]),
> > + "error detected\n");
> >
> > /* Send event once per component */
> > if (sent & BIT(component))
> > --
> > 2.54.0
> >
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v5 06/13] drm/xe/cper: Emit cper record to trace buf
2026-10-26 12:29 ` Raag Jadav
@ 2026-10-27 4:21 ` Nilawar, Badal
0 siblings, 0 replies; 37+ messages in thread
From: Nilawar, Badal @ 2026-10-27 4:21 UTC (permalink / raw)
To: Raag Jadav
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
[-- Attachment #1: Type: text/plain, Size: 1381 bytes --]
On 26-10-2026 17:59, Raag Jadav wrote:
> On Fri, Oct 23, 2026 at 10:04:28AM +0530, Badal Nilawar wrote:
>> Add the xe_error_cper tracepoint and emit each assembled CPER record
>> through it. Besides the raw record, the event carries the device name,
>> platform ID, FRU ID, severity and the Intel error section header, so
>> tools can pick up the records from the trace buffer.
> ...
>
>> + * Example trace output::
>> + *
>> + * xe_error_cper: dev=0000:03:00.0 severity=2
>> + * platform_id=9046afe5-9041-5124-8614-92550d9e9da6
>> + * fru_id=91befe38-2f61-3d7b-0000-000000000000
>> + * intel_err_hdr_raw=
> 'intel_hdr_raw'
The specs uses intel_err_hdr_raw in the example trace output, so I kept
the same naming here for consistency.
Thanks,
Badal
>
>> + * 01 02 00 18 00 00 00 01 00 00 00 00 64 77 51 14 ...
>> + * cper_len=1772
>> + * cper_raw=
>> + * 43 50 45 52 00 01 ff ff ff ff 01 00 02 00 00 00 ...
> ...
>
>> + TP_printk("dev=%s severity=%d platform_id=%pUl fru_id=%pUl intel_err_hdr_raw=%s cper_len=%u cper_raw=%s",
> Ditto.
>
> Raag
>
>> + __get_str(dev), __entry->sev,
>> + __entry->platform_id, __entry->fru_id,
>> + __print_hex(__entry->ihdr_raw,
>> + sizeof(struct xe_cper_intel_hdr)),
>> + __entry->cper_len,
>> + __print_hex(__get_dynamic_array(cper),
>> + __entry->cper_len))
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^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v5 07/13] drm/xe/xe_ras: Report device memory errors using SIGID
2026-10-27 1:29 ` Raag Jadav
@ 2026-10-27 6:03 ` Nilawar, Badal
0 siblings, 0 replies; 37+ messages in thread
From: Nilawar, Badal @ 2026-10-27 6:03 UTC (permalink / raw)
To: Raag Jadav
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
[-- Attachment #1: Type: text/plain, Size: 3197 bytes --]
On 27-10-2026 06:59, Raag Jadav wrote:
> On Tue, Oct 27, 2026 at 12:01:42AM +0530, Nilawar, Badal wrote:
>> On 26-10-2026 18:17, Raag Jadav wrote:
>>> On Fri, Oct 23, 2026 at 10:04:29AM +0530, Badal Nilawar wrote:
>>>> Use xe_log_comp_info helper to report device memory errors using the
>>>> corresponding SIGID.
>>>>
>>>> Example:
>>>> xe 0000:03:00.0: [drm] SIGID=202 (020100020008002000300000)
>>>> DEVICE_MEMORY: Double-bit ECC error detected at sw address 0x63000
>>>>
>>>> Reviewed-by: Mallesh Koujalagi<mallesh.koujalagi@intel.com>
>>>> Signed-off-by: Badal Nilawar<badal.nilawar@intel.com>
>>>> Cc: Riana Tauro<riana.tauro@intel.com>
>>>> ---
>>>> v5:
>>>> - Log unknown memory errors
>>>> - Add example log in commit message (Raag)
>>>> ---
>>>> drivers/gpu/drm/xe/xe_ras.c | 20 +++++++++++++++++---
>>>> 1 file changed, 17 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
>>>> index 95e87c635b04..5ebfc6e8dfc7 100644
>>>> --- a/drivers/gpu/drm/xe/xe_ras.c
>>>> +++ b/drivers/gpu/drm/xe/xe_ras.c
>>>> @@ -643,6 +643,7 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
>>>> static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_array *arr)
>>>> {
>>>> struct xe_ras_memory_error *info = (void *)arr->details;
>>>> + u8 cper_sev = ras_sev_to_cper_sev(arr->counter.common.severity);
>>>> int ret;
>>>> /*
>>>> @@ -654,17 +655,30 @@ static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_
>>>> */
>>>> switch (info->category) {
>>>> case XE_RAS_MEMORY_POISON:
>>>> - xe_info(xe, "[RAS]: Poison error detected\n");
>>>> + xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
>>>> + "Poison error detected\n");
>>>> break;
>>>> case XE_RAS_MEMORY_DATA_PARITY:
>>>> - xe_info(xe, "[RAS]: Data parity error detected\n");
>>>> + xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
>>>> + "Data parity error detected\n");
>>>> break;
>>>> case XE_RAS_MEMORY_DB_ECC:
>>>> ret = handle_page_offline(xe, info->sw_address, true);
>>>> - if (ret)
>>>> + if (ret) {
>>>> + xe_log_comp(xe, cper_sev, DEVICE_MEMORY,
>>>> + &arr->counter, sizeof(arr->counter),
>>>> + "Failed to recover double-bit ECC error at sw address 0x%llx\n",
>>>> + info->sw_address);
>>> Isn't handle_page_offline() already logging this? If no, shouldn't we
>>> try to consolidate?
>> It doesn't emit CPER.
> So perhaps convert them into cper instead of duplicating logs?
I'd prefer to keep the CPER emission in handle_device_memory_errors(),
which is called from xe_ras_process_error().
handle_page_offline() and its sub-functions invoke SIGID at multiple
places, not all of which require CPER emission. These functions are also
called outside the error-handling path.
Moving CPER emission into these helpers could therefore result in
multiple hardware CPER records being emitted for a single error event.
My suggestion to authors of this feature is to clean up SIGID logging in
handle_page_offline().
Thanks,
Badal
>
> Raag
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^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v5 08/13] drm/xe/xe_ras: Report core compute errors using SIGID
2026-10-23 4:34 ` [PATCH v5 08/13] drm/xe/xe_ras: Report core compute " Badal Nilawar
2026-10-23 6:24 ` Mallesh, Koujalagi
@ 2026-10-27 12:43 ` Raag Jadav
1 sibling, 0 replies; 37+ messages in thread
From: Raag Jadav @ 2026-10-27 12:43 UTC (permalink / raw)
To: Badal Nilawar
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote
On Fri, Oct 23, 2026 at 10:04:30AM +0530, Badal Nilawar wrote:
> Use xe_log_* helpers to report core compute errors.
>
> Example:
> xe 0000:03:00.0: [drm] *ERROR* SIGID=203 (02020012000a000200000800)
> [Hardware Error]: CORE_COMPUTE: Uncorrectable error detected, type 2
>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> Cc: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Raag Jadav <raag.jadav@intel.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
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2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
2026-10-23 4:24 ` ✗ CI.checkpatch: warning for Add CPER logging support for CRI (rev5) Patchwork
2026-10-23 4:26 ` ✓ CI.KUnit: success " Patchwork
2026-10-23 4:34 ` [PATCH v5 01/13] drm/xe/cper: Add CPER reporting entry point for xe_log Badal Nilawar
2026-10-24 11:38 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 02/13] drm/xe/cper: Retrieve the error counter record for CPER reporting Badal Nilawar
2026-10-24 11:50 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 03/13] drm/xe/cper: Initialize Intel-specific section header Badal Nilawar
2026-10-23 4:30 ` sashiko-bot
2026-10-26 5:57 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 04/13] drm/xe/cper: Construct CPER record for hardware errors Badal Nilawar
2026-10-26 9:54 ` Raag Jadav
2026-10-27 3:34 ` Nilawar, Badal
2026-10-23 4:34 ` [PATCH v5 05/13] drm/xe/cper: Log CPER records for aggregate counter retrieval Badal Nilawar
2026-10-26 11:31 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 06/13] drm/xe/cper: Emit cper record to trace buf Badal Nilawar
2026-10-26 12:29 ` Raag Jadav
2026-10-27 4:21 ` Nilawar, Badal
2026-10-23 4:34 ` [PATCH v5 07/13] drm/xe/xe_ras: Report device memory errors using SIGID Badal Nilawar
2026-10-26 12:47 ` Raag Jadav
2026-10-26 18:31 ` Nilawar, Badal
2026-10-27 1:29 ` Raag Jadav
2026-10-27 6:03 ` Nilawar, Badal
2026-10-23 4:34 ` [PATCH v5 08/13] drm/xe/xe_ras: Report core compute " Badal Nilawar
2026-10-23 6:24 ` Mallesh, Koujalagi
2026-10-27 12:43 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 09/13] drm/xe/xe_ras: Report soc internal " Badal Nilawar
2026-10-23 6:16 ` Mallesh, Koujalagi
2026-10-26 12:57 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 10/13] drm/xe/xe_ras: Report correctable " Badal Nilawar
2026-10-26 15:17 ` Raag Jadav
2026-10-27 4:13 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 11/13] drm/xe/xe_ras: Report unknown " Badal Nilawar
2026-10-23 4:34 ` [PATCH v5 12/13] drm/xe/xe_ras: Add support to retrieve info queue data Badal Nilawar
2026-10-23 4:34 ` [PATCH v5 13/13] drm/xe/cper: Prepare Intel CPER info records Badal Nilawar
2026-10-23 6:34 ` ✓ Xe.CI.FULL: success for Add CPER logging support for CRI (rev5) Patchwork
2026-10-23 6:35 ` ✓ Xe.CI.BAT: " Patchwork
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