[PATCH 00/12] Add support for Common SDP Transmission Line

[PATCH 00/12] Add support for Common SDP Transmission Line

[Ankit Nautiyal]

Xe3p_lpd introduces new register bits to program a common SDP
Transmission line that will be used by the Hardware to position the
SDPs. Along with this, another new register is also added to stagger
the different SDPs.

This series adds support for programming the Common SDP Transmission Line
(CMN_SDP_TL) and its stagger control registers.

Rev2:
 - Add tracking for AS SDP Transmission line first. Instead of directly
   programming it in the register, compute the state during
   compute_config_late() and write the value from crtc_state.
   Readout from the register through a vrr helper, since the register is
   defined in context of VRR and will be used for both DP and HDMI VRR
   packets.
 - Add support to track other SDP transmission lines, instead of stagger
   values.
 - Compute the transmission lines in compute_config_late path and add
   readout.
 - Always write the Common SDP Transmission line and other stagger
   values, whether the packets are sent or not.
 - Dump SDP transmission lines in crtc_state.

Ankit Nautiyal (11):
  drm/i915/vrr: Add HAS_EMP_AS_SDP_TL macro
  drm/i915/vrr: Add helper to readback EMP_AS_SDP_TL
  drm/i915/vrr: Separate out helper to write EMP_AS_SDP_TL
  drm/i915/dp: Add helper to get AS SDP Transmission Line
  drm/i915/dp: Add crtc state for AS SDP transmission line
  drm/i915/dp: Store and use AS SDP transmission line from crtc state
  drm/i915/display: Add HAS_CMN_SDP_TL macro
  drm/i915/dp: Store SDP transmission lines in crtc_state
  drm/i915/dp: Introduce helpers to enable/disable CMN SDP Transmission
    line
  drm/i915/dp: Enable Common SDP Transmission line
  drm/i915/display: Dump SDP Transmission lines

Arun R Murthy (1):
  drm/i915/nvl: Add register definitions for common SDP Transmission
    Line

 .../drm/i915/display/intel_crtc_state_dump.c  |   8 +
 drivers/gpu/drm/i915/display/intel_ddi.c      |   4 +
 drivers/gpu/drm/i915/display/intel_display.c  |   7 +
 .../drm/i915/display/intel_display_device.h   |   2 +
 .../gpu/drm/i915/display/intel_display_regs.h |  19 ++
 .../drm/i915/display/intel_display_types.h    |  14 ++
 drivers/gpu/drm/i915/display/intel_dp.c       | 177 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h       |   5 +
 drivers/gpu/drm/i915/display/intel_vrr.c      |  48 +++--
 drivers/gpu/drm/i915/display/intel_vrr.h      |   1 +
 10 files changed, 274 insertions(+), 11 deletions(-)

-- 
2.45.2

[PATCH 01/12] drm/i915/vrr: Add HAS_EMP_AS_SDP_TL macro

[Ankit Nautiyal]

For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
double buffering point and transmission line for VRR packets for
HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.

Add a macro for this and use it in intel_vrr.c

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 drivers/gpu/drm/i915/display/intel_vrr.c            | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 1170ac346615..9338ea087e92 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -173,6 +173,7 @@ struct intel_display_platforms {
 #define HAS_DSC(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_dsc)
 #define HAS_DSC_3ENGINES(__display)	(DISPLAY_VERx100(__display) == 1401 && HAS_DSC(__display))
 #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
+#define HAS_EMP_AS_SDP_TL(__display)	(DISPLAY_VERx100(__display) == 1401 || DISPLAY_VER(__display) >= 20)
 #define HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
 #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >= 30)
 #define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index fae1186a90b2..1fed597439b0 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -656,7 +656,7 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 	 * Since currently we support VRR only for DP/eDP, so this is programmed
 	 * to for Adaptive Sync SDP to Vsync start.
 	 */
-	if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
+	if (HAS_EMP_AS_SDP_TL(display))
 		intel_de_write(display,
 			       EMP_AS_SDP_TL(display, cpu_transcoder),
 			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
-- 
2.45.2

[PATCH 02/12] drm/i915/vrr: Add helper to readback EMP_AS_SDP_TL

[Ankit Nautiyal]

EMP_AS_SDP_TL is used to program both DP Adaptive Sync SDP and HDMI
Video Timing EMP for VRR operation. Add a helper to read back the
programmed transmission line from hardware so VRR code can populate
the corresponding CRTC state fields during get_config.

This provides a common read-back path for VRR packet transmission
line state.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h |  1 +
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 1fed597439b0..abdae7f1f8a8 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -1218,3 +1218,16 @@ int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_st
 
 	return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
 }
+
+u16 intel_vrr_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 val;
+
+	if (!HAS_EMP_AS_SDP_TL(display))
+		return 0;
+
+	val = intel_de_read(display, EMP_AS_SDP_TL(display, cpu_transcoder));
+	return REG_FIELD_GET(EMP_AS_SDP_DB_TL_MASK, val);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 4f16ca4af91f..6659a8a53432 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -53,5 +53,6 @@ int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_sta
 int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state);
 int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
 int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
+u16 intel_vrr_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_VRR_H__ */
-- 
2.45.2

[PATCH 03/12] drm/i915/vrr: Separate out helper to write EMP_AS_SDP_TL

[Ankit Nautiyal]

Move EMP_AS_SDP_TL programming into a separate helper.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 35 ++++++++++++++++--------
 1 file changed, 24 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index abdae7f1f8a8..5164d8c354e0 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -591,6 +591,29 @@ static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
 			VRR_CTL_PIPELINE_FULL_OVERRIDE;
 }
 
+static
+void intel_vrr_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	/*
+	 * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
+	 * double buffering point and transmission line for VRR packets for
+	 * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
+	 */
+	if (!HAS_EMP_AS_SDP_TL(display))
+		return;
+
+	/*
+	 * Since currently we support VRR only for DP/eDP, so this is programmed
+	 * only for Adaptive Sync SDP to Vsync start.
+	 */
+	intel_de_write(display,
+		       EMP_AS_SDP_TL(display, cpu_transcoder),
+		       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
+}
+
 void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -649,17 +672,7 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 			       VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
 			       VRR_VSYNC_START(crtc_state->vrr.vsync_start));
 
-	/*
-	 * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
-	 * double buffering point and transmission line for VRR packets for
-	 * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
-	 * Since currently we support VRR only for DP/eDP, so this is programmed
-	 * to for Adaptive Sync SDP to Vsync start.
-	 */
-	if (HAS_EMP_AS_SDP_TL(display))
-		intel_de_write(display,
-			       EMP_AS_SDP_TL(display, cpu_transcoder),
-			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
+	intel_vrr_write_emp_as_sdp_tl(crtc_state);
 }
 
 void
-- 
2.45.2

[PATCH 04/12] drm/i915/dp: Add helper to get AS SDP Transmission Line

[Ankit Nautiyal]

Introduce a DP helper to compute the Adaptive Sync SDP transmission line
and use it when programming the EMP_AS_SDP_TL register.

Currently the AS SDP transmission line is programmed to the T1 position.
This can be extended in the future to support programming the T2 position
as well.

While at it, improve the documentation: the AS SDP transmission line
corresponds to the T1 position, which maps to the start of the VSYNC
pulse.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c  | 12 ++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h  |  2 ++
 drivers/gpu/drm/i915/display/intel_vrr.c |  4 ++--
 3 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4955bd8b11d7..fd668babd641 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7415,3 +7415,15 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 
 	return true;
 }
+
+int intel_dp_sdp_as_tl(const struct intel_crtc_state *crtc_state)
+{
+	/*
+	 * EMP_AS_SDP_TL defines the T1 position as the default AS SDP
+	 * Transmission Line, which corresponds to the start of the
+	 * VSYNC pulse.
+	 *
+	 * Use the T1 position for now.
+	 */
+	return crtc_state->vrr.vsync_start;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 2849b9ecdc71..7024fd0ace0a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -238,4 +238,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
 		for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
 
+int intel_dp_sdp_as_tl(const struct intel_crtc_state *crtc_state);
+
 #endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5164d8c354e0..b700da4e9256 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -607,11 +607,11 @@ void intel_vrr_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
 
 	/*
 	 * Since currently we support VRR only for DP/eDP, so this is programmed
-	 * only for Adaptive Sync SDP to Vsync start.
+	 * only for Adaptive Sync SDP.
 	 */
 	intel_de_write(display,
 		       EMP_AS_SDP_TL(display, cpu_transcoder),
-		       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
+		       EMP_AS_SDP_DB_TL(intel_dp_sdp_as_tl(crtc_state)));
 }
 
 void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
-- 
2.45.2

[PATCH 05/12] drm/i915/dp: Add crtc state for AS SDP transmission line

[Ankit Nautiyal]

The Adaptive Sync SDP is currently the only DisplayPort SDP with a
programmable transmission line. Store the AS SDP transmission line
in the crtc state and include it in the pipe configuration comparison.

This provides a common place for SDP transmission lines and paves the way
for supporting additional SDP TL programming, including the common base
SDP transmission line introduced with Xe3p_lpd.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c       | 2 ++
 drivers/gpu/drm/i915/display/intel_display_types.h | 8 ++++++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 10b6c6fcb03f..c66541f26a09 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5434,6 +5434,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	}
 	PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
 
+	PIPE_CONF_CHECK_I(dp_sdp_tl.as);
+
 	PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
 	PIPE_CONF_CHECK_I(master_transcoder);
 	PIPE_CONF_CHECK_X(joiner_pipes);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e2496db1642a..f58454c23859 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1298,6 +1298,14 @@ struct intel_crtc_state {
 		struct drm_dp_as_sdp as_sdp;
 	} infoframes;
 
+	struct {
+		/*
+		 * SDP Transmission line, relative to the Vtotal.
+		 * The programmed transmit line is (Vtotal - value)
+		 */
+		u16 as;
+	} dp_sdp_tl;
+
 	u8 eld[MAX_ELD_BYTES];
 
 	/* HDMI scrambling status */
-- 
2.45.2

[PATCH 06/12] drm/i915/dp: Store and use AS SDP transmission line from crtc state

[Ankit Nautiyal]

The driver currently computes the Adaptive Sync SDP transmission line
directly at programming time. Instead, compute and store the
AS SDP transmission line in the crtc state and use it when programming the
EMP_AS_SDP_TL register.

We get the clear picture about the SDPs and guardband only in
intel_dp_sdp_compute_config_late() therefore we must configure the
AS SDP transmission line at this point when AS SDP is enabled in
crtc_state.

This prepares the ground for supporting programmable transmission lines
for additional DP SDPs.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c  | 44 +++++++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_dp.h  |  1 +
 3 files changed, 38 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ebefa889bc8c..344eef812e6b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4217,6 +4217,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
 	intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
 	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
 	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
+	intel_dp_sdp_transmission_line_get_config(pipe_config);
 
 	intel_audio_codec_get_config(encoder, pipe_config);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fd668babd641..0644fa8a7800 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7317,6 +7317,34 @@ void intel_dp_mst_resume(struct intel_display *display)
 	}
 }
 
+static
+int intel_dp_sdp_compute_as_tl(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!HAS_EMP_AS_SDP_TL(display))
+		return 0;
+
+	if (!(crtc_state->infoframes.enable &
+	      intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)))
+		return 0;
+
+	/*
+	 * EMP_AS_SDP_TL defines the T1 position as the default AS SDP
+	 * Transmission Line, which corresponds to the start of the
+	 * VSYNC pulse.
+	 *
+	 * Use the T1 position for now.
+	 */
+	return crtc_state->vrr.vsync_start;
+}
+
+static
+void intel_dp_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state)
+{
+	crtc_state->dp_sdp_tl.as = intel_dp_sdp_compute_as_tl(crtc_state);
+}
+
 static
 int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
 {
@@ -7330,6 +7358,8 @@ int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
 		return -EINVAL;
 	}
 
+	intel_dp_sdp_tl_compute_config_late(crtc_state);
+
 	return 0;
 }
 
@@ -7418,12 +7448,10 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 
 int intel_dp_sdp_as_tl(const struct intel_crtc_state *crtc_state)
 {
-	/*
-	 * EMP_AS_SDP_TL defines the T1 position as the default AS SDP
-	 * Transmission Line, which corresponds to the start of the
-	 * VSYNC pulse.
-	 *
-	 * Use the T1 position for now.
-	 */
-	return crtc_state->vrr.vsync_start;
+	return crtc_state->dp_sdp_tl.as;
+}
+
+void intel_dp_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state)
+{
+	crtc_state->dp_sdp_tl.as = intel_vrr_read_emp_as_sdp_tl(crtc_state);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 7024fd0ace0a..614b3f1fb72d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -239,5 +239,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 		for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
 
 int intel_dp_sdp_as_tl(const struct intel_crtc_state *crtc_state);
+void intel_dp_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_DP_H__ */
-- 
2.45.2

[PATCH 07/12] drm/i915/nvl: Add register definitions for common SDP Transmission Line

[Ankit Nautiyal]

From: Arun R Murthy <arun.r.murthy@intel.com>

Add registers definitions for common SDP transmission line CMN_SDP_TL
and CMN_SDP_TL_STGR_CTL.

Bspec: 74384
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../gpu/drm/i915/display/intel_display_regs.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index dada8dc27ea4..a02ced1b3052 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2122,6 +2122,25 @@
 							 _VLV_VIDEO_DIP_DATA_B, \
 							 _CHV_VIDEO_DIP_DATA_C)
 
+/* COMMON SDP TRANSMISSION LINE */
+#define _CMN_SDP_TL_A			0x6020c
+#define CMN_SDP_TL(display, trans)	_MMIO_TRANS2(display, (trans), _CMN_SDP_TL_A)
+#define  TRANSMISSION_LINE_ENABLE	REG_BIT(31)
+#define  BASE_TRANSMISSION_LINE_MASK	REG_GENMASK(12, 0)
+#define  BASE_TRANSMISSION_LINE(x)	REG_FIELD_PREP(BASE_TRANSMISSION_LINE_MASK, x)
+
+#define _CMN_SDP_TL_STGR_CTL_A			0x60214
+#define CMN_SDP_TL_STGR_CTL(display, trans)	_MMIO_TRANS2(display, (trans), _CMN_SDP_TL_STGR_CTL_A)
+#define  VSC_EXT_STAGGER_MASK			REG_GENMASK(11, 8)
+#define  VSC_EXT_STAGGER(x)			REG_FIELD_PREP(VSC_EXT_STAGGER_MASK, x)
+#define  VSC_EXT_STAGGER_DEFAULT		0x2
+#define  PPS_STAGGER_MASK			REG_GENMASK(7, 4)
+#define  PPS_STAGGER(x)				REG_FIELD_PREP(PPS_STAGGER_MASK, x)
+#define  PPS_STAGGER_DEFAULT			0x1
+#define  GMP_STAGGER_MASK			REG_GENMASK(3, 0)
+#define  GMP_STAGGER(x)				REG_FIELD_PREP(GMP_STAGGER_MASK, x)
+#define  GMP_STAGGER_DEFAULT			0x0
+
 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A	0x60210
 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B	0x61178
 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C	0x611f8
-- 
2.45.2

[PATCH 08/12] drm/i915/display: Add HAS_CMN_SDP_TL macro

[Ankit Nautiyal]

Add a helper macro to detect CMN SDP TL support on platforms with display
version 35 and above.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 9338ea087e92..36a8a956f54a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -154,6 +154,7 @@ struct intel_display_platforms {
 #define HAS_CASF(__display)		(DISPLAY_VER(__display) >= 20)
 #define HAS_CDCLK_CRAWL(__display)	(DISPLAY_INFO(__display)->has_cdclk_crawl)
 #define HAS_CDCLK_SQUASH(__display)	(DISPLAY_INFO(__display)->has_cdclk_squash)
+#define HAS_CMN_SDP_TL(__display)	(DISPLAY_VER(__display) >= 35)
 #define HAS_CMRR(__display)		(DISPLAY_VER(__display) >= 20)
 #define HAS_CMTG(__display)		(!(__display)->platform.dg2 && DISPLAY_VER(__display) >= 13)
 #define HAS_CUR_FBC(__display)		(!HAS_GMCH(__display) && IS_DISPLAY_VER(__display, 7, 13))
-- 
2.45.2

[PATCH 09/12] drm/i915/dp: Store SDP transmission lines in crtc_state

[Ankit Nautiyal]

Currently the driver only programs the transmission line for the
Adaptive-Sync SDP, while the hardware controls the transmission lines for
other SDPs.

Starting with Xe3p_lpd, the hardware allows the driver to program
transmission lines for additional DP SDPs. Prepare for this by adding
fields to struct intel_crtc_state to store SDP transmission lines, and
include them in pipe config comparison.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c       | 5 +++++
 drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c66541f26a09..5f17ea2b6170 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5435,6 +5435,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
 
 	PIPE_CONF_CHECK_I(dp_sdp_tl.as);
+	PIPE_CONF_CHECK_I(dp_sdp_tl.gmp);
+	PIPE_CONF_CHECK_I(dp_sdp_tl.pps);
+	PIPE_CONF_CHECK_I(dp_sdp_tl.vsc);
+	PIPE_CONF_CHECK_I(dp_sdp_tl.vsc_ext);
+	PIPE_CONF_CHECK_I(dp_sdp_tl.cmn);
 
 	PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
 	PIPE_CONF_CHECK_I(master_transcoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f58454c23859..3256d537d15e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1304,6 +1304,12 @@ struct intel_crtc_state {
 		 * The programmed transmit line is (Vtotal - value)
 		 */
 		u16 as;
+		u16 gmp;
+		u16 pps;
+		u16 vsc;
+		u16 vsc_ext;
+		/* CMN SDP Base transmission line (Xe3p_lpd+) */
+		u16 cmn;
 	} dp_sdp_tl;
 
 	u8 eld[MAX_ELD_BYTES];
-- 
2.45.2

[PATCH 10/12] drm/i915/dp: Introduce helpers to enable/disable CMN SDP Transmission line

[Ankit Nautiyal]

Introduce helpers to program or disable CMN_SDP_TL and stagger registers
using the state stored in crtc_state.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 49 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h |  2 +
 2 files changed, 51 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0644fa8a7800..b1168c147bc7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7451,7 +7451,56 @@ int intel_dp_sdp_as_tl(const struct intel_crtc_state *crtc_state)
 	return crtc_state->dp_sdp_tl.as;
 }
 
+static int intel_dp_sdp_tl_to_stagger(const struct intel_crtc_state *crtc_state,
+				      u16 sdp_tl)
+{
+	return sdp_tl - crtc_state->dp_sdp_tl.cmn;
+}
+
 void intel_dp_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state)
 {
 	crtc_state->dp_sdp_tl.as = intel_vrr_read_emp_as_sdp_tl(crtc_state);
 }
+
+void intel_dp_cmn_sdp_transmission_line_enable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	int gmp_stagger;
+	int pps_stagger;
+	int vsc_ext_stagger;
+
+	if (!crtc_state->dp_sdp_tl.cmn)
+		return;
+
+	gmp_stagger = intel_dp_sdp_tl_to_stagger(crtc_state, crtc_state->dp_sdp_tl.gmp);
+	pps_stagger = intel_dp_sdp_tl_to_stagger(crtc_state, crtc_state->dp_sdp_tl.pps);
+	vsc_ext_stagger = intel_dp_sdp_tl_to_stagger(crtc_state, crtc_state->dp_sdp_tl.vsc_ext);
+
+	if (drm_WARN_ON(display->drm, gmp_stagger < 0))
+		return;
+	if (drm_WARN_ON(display->drm, pps_stagger < 0))
+		return;
+	if (drm_WARN_ON(display->drm, vsc_ext_stagger < 0))
+		return;
+
+	intel_de_write(display, CMN_SDP_TL_STGR_CTL(display, cpu_transcoder),
+		       GMP_STAGGER(gmp_stagger) |
+		       PPS_STAGGER(pps_stagger) |
+		       VSC_EXT_STAGGER(vsc_ext_stagger));
+
+	intel_de_write(display, CMN_SDP_TL(display, cpu_transcoder),
+		       TRANSMISSION_LINE_ENABLE |
+		       BASE_TRANSMISSION_LINE(crtc_state->dp_sdp_tl.cmn));
+}
+
+void intel_dp_cmn_sdp_transmission_line_disable(const struct intel_crtc_state *old_crtc_state)
+{
+	struct intel_display *display = to_intel_display(old_crtc_state);
+	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+
+	if (!old_crtc_state->dp_sdp_tl.cmn)
+		return;
+
+	intel_de_write(display, CMN_SDP_TL(display, cpu_transcoder), 0);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 614b3f1fb72d..efaa18cfb41c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -240,5 +240,7 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 
 int intel_dp_sdp_as_tl(const struct intel_crtc_state *crtc_state);
 void intel_dp_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state);
+void intel_dp_cmn_sdp_transmission_line_enable(const struct intel_crtc_state *crtc_state);
+void intel_dp_cmn_sdp_transmission_line_disable(const struct intel_crtc_state *old_crtc_state);
 
 #endif /* __INTEL_DP_H__ */
-- 
2.45.2

[PATCH 11/12] drm/i915/dp: Enable Common SDP Transmission line

[Ankit Nautiyal]

Enable programming of the common SDP transmission line on platforms that
support it. Compute and program the common base transmission line and
per-SDP stagger values from the crtc state during modeset, and disable the
feature on pipe disable.

Currently, the stagger values are set as per the default policy of the
Hardware. This can be optimized later if we come up with a specific driver
policy to sequence the SDPs better.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  3 +
 drivers/gpu/drm/i915/display/intel_dp.c  | 88 ++++++++++++++++++++++++
 2 files changed, 91 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 344eef812e6b..b47a85932fc1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2726,6 +2726,8 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	/* 6.o Configure and enable FEC if needed */
 	intel_ddi_enable_fec(encoder, crtc_state);
 
+	intel_dp_cmn_sdp_transmission_line_enable(crtc_state);
+
 	/* 7.a 128b/132b SST. */
 	if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
 		/* VCPID 1, start slot 0 for 128b/132b, tu slots */
@@ -3113,6 +3115,7 @@ static void intel_ddi_buf_disable(struct intel_encoder *encoder,
 			     DP_TP_CTL_ENABLE, 0);
 	}
 
+	intel_dp_cmn_sdp_transmission_line_disable(crtc_state);
 	intel_ddi_disable_fec(encoder, crtc_state);
 
 	if (DISPLAY_VER(display) < 14)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b1168c147bc7..830e2a439deb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7317,6 +7317,57 @@ void intel_dp_mst_resume(struct intel_display *display)
 	}
 }
 
+static int intel_dp_sdp_stagger_to_tl(struct intel_crtc_state *crtc_state,
+				      int stagger)
+{
+	return crtc_state->dp_sdp_tl.cmn + stagger;
+}
+
+static
+void intel_dp_cmn_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	bool as_sdp;
+
+	if (!HAS_CMN_SDP_TL(display))
+		return;
+
+	as_sdp = crtc_state->infoframes.enable &
+		 intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
+	/*
+	 * When AS SDP is enabled :
+	 *  - The common SDP Transmission Line matches the EMP SDP Transmission Line.
+	 *
+	 * When AS SDP is disabled:
+	 *  - Bspec mentions the positions as lines of delayed vblank.
+	 *  - Guardband = 1st line of delayed vblank
+	 *  - Common SDP Transmission line is set to 2nd line of delayed vblank.
+	 */
+
+	if (as_sdp)
+		crtc_state->dp_sdp_tl.cmn = crtc_state->dp_sdp_tl.as;
+	else
+		crtc_state->dp_sdp_tl.cmn = crtc_state->vrr.guardband - 1;
+
+	/*
+	 * Currently we are programming the default stagger values, but these
+	 * can be optimized if required, based on number of SDPs enabled.
+	 *
+	 * Default values of the Transmission lines for SDPs other than AS SDP:
+	 * VSC : CMN SDP Transmission line
+	 * GMP : CMN SDP Transmission line
+	 * PPS : CMN SDP Transmission line + 1
+	 * VSC_EXT: CMN SDP Transmission line + 2
+	 */
+	crtc_state->dp_sdp_tl.vsc = crtc_state->dp_sdp_tl.cmn;
+	crtc_state->dp_sdp_tl.gmp =
+		intel_dp_sdp_stagger_to_tl(crtc_state, GMP_STAGGER_DEFAULT);
+	crtc_state->dp_sdp_tl.pps =
+		intel_dp_sdp_stagger_to_tl(crtc_state, PPS_STAGGER_DEFAULT);
+	crtc_state->dp_sdp_tl.vsc_ext =
+		intel_dp_sdp_stagger_to_tl(crtc_state, VSC_EXT_STAGGER_DEFAULT);
+}
+
 static
 int intel_dp_sdp_compute_as_tl(const struct intel_crtc_state *crtc_state)
 {
@@ -7343,6 +7394,7 @@ static
 void intel_dp_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state)
 {
 	crtc_state->dp_sdp_tl.as = intel_dp_sdp_compute_as_tl(crtc_state);
+	intel_dp_cmn_sdp_tl_compute_config_late(crtc_state);
 }
 
 static
@@ -7457,9 +7509,45 @@ static int intel_dp_sdp_tl_to_stagger(const struct intel_crtc_state *crtc_state,
 	return sdp_tl - crtc_state->dp_sdp_tl.cmn;
 }
 
+static
+void intel_dp_cmn_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u16 vsc_ext_stagger, pps_stagger, gmp_stagger;
+	u32 val;
+
+	if (!HAS_CMN_SDP_TL(display))
+		return;
+
+	val = intel_de_read(display, CMN_SDP_TL(display, cpu_transcoder));
+
+	if (!(val & TRANSMISSION_LINE_ENABLE))
+		return;
+
+	crtc_state->dp_sdp_tl.cmn = REG_FIELD_GET(BASE_TRANSMISSION_LINE_MASK, val);
+
+	/* SDP VSC uses same transmission line as CMN base transmission line */
+	crtc_state->dp_sdp_tl.vsc = crtc_state->dp_sdp_tl.cmn;
+
+	val = intel_de_read(display, CMN_SDP_TL_STGR_CTL(display, cpu_transcoder));
+
+	vsc_ext_stagger = REG_FIELD_GET(VSC_EXT_STAGGER_MASK, val);
+	pps_stagger = REG_FIELD_GET(PPS_STAGGER_MASK, val);
+	gmp_stagger = REG_FIELD_GET(GMP_STAGGER_MASK, val);
+
+	crtc_state->dp_sdp_tl.vsc_ext =
+		intel_dp_sdp_stagger_to_tl(crtc_state, vsc_ext_stagger);
+	crtc_state->dp_sdp_tl.pps =
+		intel_dp_sdp_stagger_to_tl(crtc_state, pps_stagger);
+	crtc_state->dp_sdp_tl.gmp =
+		intel_dp_sdp_stagger_to_tl(crtc_state, gmp_stagger);
+}
+
 void intel_dp_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state)
 {
 	crtc_state->dp_sdp_tl.as = intel_vrr_read_emp_as_sdp_tl(crtc_state);
+	intel_dp_cmn_sdp_transmission_line_get_config(crtc_state);
 }
 
 void intel_dp_cmn_sdp_transmission_line_enable(const struct intel_crtc_state *crtc_state)
-- 
2.45.2

[PATCH 12/12] drm/i915/display: Dump SDP Transmission lines

[Ankit Nautiyal]

Add SDP transmission lines to the CRTC state dump.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index c85ba9a95322..def696967706 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -251,6 +251,14 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 			   str_enabled_disabled(pipe_config->has_panel_replay),
 			   str_enabled_disabled(pipe_config->enable_psr2_sel_fetch));
 		drm_printf(&p, "minimum hblank: %d\n", pipe_config->min_hblank);
+
+		drm_printf(&p, "DP SDP TL: AS: %u, CMN: %u, GMP: %u, PPS: %u, VSC: %u, VSC_EXT: %u\n",
+			   pipe_config->dp_sdp_tl.as,
+			   pipe_config->dp_sdp_tl.cmn,
+			   pipe_config->dp_sdp_tl.gmp,
+			   pipe_config->dp_sdp_tl.pps,
+			   pipe_config->dp_sdp_tl.vsc,
+			   pipe_config->dp_sdp_tl.vsc_ext);
 	}
 
 	drm_printf(&p, "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
-- 
2.45.2

✗ CI.checkpatch: warning for Add support for Common SDP Transmission Line (rev2)

[Patchwork]

== Series Details ==

Series: Add support for Common SDP Transmission Line (rev2)
URL   : https://patchwork.freedesktop.org/series/162623/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit c38a955388dcc23ade695af7cea3c0ca8e2fd9a3
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Date:   Mon Apr 13 09:23:49 2026 +0530

    drm/i915/display: Dump SDP Transmission lines
    
    Add SDP transmission lines to the CRTC state dump.
    
    Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
+ /mt/dim checkpatch b6fce504bb100219c9b8bb7f719d67c660382f51 drm-intel
e1f37cf3952e drm/i915/vrr: Add HAS_EMP_AS_SDP_TL macro
-:22: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#22: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:176:
+#define HAS_EMP_AS_SDP_TL(__display)	(DISPLAY_VERx100(__display) == 1401 || DISPLAY_VER(__display) >= 20)

-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__display' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:176:
+#define HAS_EMP_AS_SDP_TL(__display)	(DISPLAY_VERx100(__display) == 1401 || DISPLAY_VER(__display) >= 20)

total: 0 errors, 1 warnings, 1 checks, 15 lines checked
c10fbe38850a drm/i915/vrr: Add helper to readback EMP_AS_SDP_TL
c7811bff82dc drm/i915/vrr: Separate out helper to write EMP_AS_SDP_TL
03da546b2eac drm/i915/dp: Add helper to get AS SDP Transmission Line
6a6d1a58521b drm/i915/dp: Add crtc state for AS SDP transmission line
f01e204e50b5 drm/i915/dp: Store and use AS SDP transmission line from crtc state
f7ca8bc5ceef drm/i915/nvl: Add register definitions for common SDP Transmission Line
-:30: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#30: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2133:
+#define CMN_SDP_TL_STGR_CTL(display, trans)	_MMIO_TRANS2(display, (trans), _CMN_SDP_TL_STGR_CTL_A)

total: 0 errors, 1 warnings, 0 checks, 25 lines checked
4373a1ef907f drm/i915/display: Add HAS_CMN_SDP_TL macro
dfbc826bdffb drm/i915/dp: Store SDP transmission lines in crtc_state
e445e67c8996 drm/i915/dp: Introduce helpers to enable/disable CMN SDP Transmission line
37f3d8e1ba38 drm/i915/dp: Enable Common SDP Transmission line
c38a955388dc drm/i915/display: Dump SDP Transmission lines

✓ CI.KUnit: success for Add support for Common SDP Transmission Line (rev2)

[Patchwork]

== Series Details ==

Series: Add support for Common SDP Transmission Line (rev2)
URL   : https://patchwork.freedesktop.org/series/162623/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[04:18:24] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:18:28] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:19:00] Starting KUnit Kernel (1/1)...
[04:19:00] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:19:00] ================== guc_buf (11 subtests) ===================
[04:19:00] [PASSED] test_smallest
[04:19:00] [PASSED] test_largest
[04:19:00] [PASSED] test_granular
[04:19:00] [PASSED] test_unique
[04:19:00] [PASSED] test_overlap
[04:19:00] [PASSED] test_reusable
[04:19:00] [PASSED] test_too_big
[04:19:00] [PASSED] test_flush
[04:19:00] [PASSED] test_lookup
[04:19:00] [PASSED] test_data
[04:19:00] [PASSED] test_class
[04:19:00] ===================== [PASSED] guc_buf =====================
[04:19:00] =================== guc_dbm (7 subtests) ===================
[04:19:00] [PASSED] test_empty
[04:19:00] [PASSED] test_default
[04:19:00] ======================== test_size  ========================
[04:19:00] [PASSED] 4
[04:19:00] [PASSED] 8
[04:19:00] [PASSED] 32
[04:19:00] [PASSED] 256
[04:19:00] ==================== [PASSED] test_size ====================
[04:19:00] ======================= test_reuse  ========================
[04:19:00] [PASSED] 4
[04:19:00] [PASSED] 8
[04:19:00] [PASSED] 32
[04:19:00] [PASSED] 256
[04:19:00] =================== [PASSED] test_reuse ====================
[04:19:00] =================== test_range_overlap  ====================
[04:19:00] [PASSED] 4
[04:19:00] [PASSED] 8
[04:19:00] [PASSED] 32
[04:19:00] [PASSED] 256
[04:19:00] =============== [PASSED] test_range_overlap ================
[04:19:00] =================== test_range_compact  ====================
[04:19:00] [PASSED] 4
[04:19:00] [PASSED] 8
[04:19:00] [PASSED] 32
[04:19:00] [PASSED] 256
[04:19:00] =============== [PASSED] test_range_compact ================
[04:19:00] ==================== test_range_spare  =====================
[04:19:00] [PASSED] 4
[04:19:00] [PASSED] 8
[04:19:00] [PASSED] 32
[04:19:00] [PASSED] 256
[04:19:00] ================ [PASSED] test_range_spare =================
[04:19:00] ===================== [PASSED] guc_dbm =====================
[04:19:00] =================== guc_idm (6 subtests) ===================
[04:19:00] [PASSED] bad_init
[04:19:00] [PASSED] no_init
[04:19:00] [PASSED] init_fini
[04:19:00] [PASSED] check_used
[04:19:00] [PASSED] check_quota
[04:19:00] [PASSED] check_all
[04:19:00] ===================== [PASSED] guc_idm =====================
[04:19:00] ================== no_relay (3 subtests) ===================
[04:19:00] [PASSED] xe_drops_guc2pf_if_not_ready
[04:19:00] [PASSED] xe_drops_guc2vf_if_not_ready
[04:19:00] [PASSED] xe_rejects_send_if_not_ready
[04:19:00] ==================== [PASSED] no_relay =====================
[04:19:00] ================== pf_relay (14 subtests) ==================
[04:19:00] [PASSED] pf_rejects_guc2pf_too_short
[04:19:00] [PASSED] pf_rejects_guc2pf_too_long
[04:19:00] [PASSED] pf_rejects_guc2pf_no_payload
[04:19:00] [PASSED] pf_fails_no_payload
[04:19:00] [PASSED] pf_fails_bad_origin
[04:19:00] [PASSED] pf_fails_bad_type
[04:19:00] [PASSED] pf_txn_reports_error
[04:19:00] [PASSED] pf_txn_sends_pf2guc
[04:19:00] [PASSED] pf_sends_pf2guc
[04:19:00] [SKIPPED] pf_loopback_nop
[04:19:00] [SKIPPED] pf_loopback_echo
[04:19:00] [SKIPPED] pf_loopback_fail
[04:19:00] [SKIPPED] pf_loopback_busy
[04:19:00] [SKIPPED] pf_loopback_retry
[04:19:00] ==================== [PASSED] pf_relay =====================
[04:19:00] ================== vf_relay (3 subtests) ===================
[04:19:00] [PASSED] vf_rejects_guc2vf_too_short
[04:19:00] [PASSED] vf_rejects_guc2vf_too_long
[04:19:00] [PASSED] vf_rejects_guc2vf_no_payload
[04:19:00] ==================== [PASSED] vf_relay =====================
[04:19:00] ================ pf_gt_config (9 subtests) =================
[04:19:00] [PASSED] fair_contexts_1vf
[04:19:00] [PASSED] fair_doorbells_1vf
[04:19:00] [PASSED] fair_ggtt_1vf
[04:19:00] ====================== fair_vram_1vf  ======================
[04:19:00] [PASSED] 3.50 GiB
[04:19:00] [PASSED] 11.5 GiB
[04:19:00] [PASSED] 15.5 GiB
[04:19:00] [PASSED] 31.5 GiB
[04:19:00] [PASSED] 63.5 GiB
[04:19:00] [PASSED] 1.91 GiB
[04:19:00] ================== [PASSED] fair_vram_1vf ==================
[04:19:00] ================ fair_vram_1vf_admin_only  =================
[04:19:00] [PASSED] 3.50 GiB
[04:19:00] [PASSED] 11.5 GiB
[04:19:00] [PASSED] 15.5 GiB
[04:19:00] [PASSED] 31.5 GiB
[04:19:00] [PASSED] 63.5 GiB
[04:19:00] [PASSED] 1.91 GiB
[04:19:00] ============ [PASSED] fair_vram_1vf_admin_only =============
[04:19:00] ====================== fair_contexts  ======================
[04:19:00] [PASSED] 1 VF
[04:19:00] [PASSED] 2 VFs
[04:19:00] [PASSED] 3 VFs
[04:19:00] [PASSED] 4 VFs
[04:19:00] [PASSED] 5 VFs
[04:19:00] [PASSED] 6 VFs
[04:19:00] [PASSED] 7 VFs
[04:19:00] [PASSED] 8 VFs
[04:19:00] [PASSED] 9 VFs
[04:19:00] [PASSED] 10 VFs
[04:19:00] [PASSED] 11 VFs
[04:19:00] [PASSED] 12 VFs
[04:19:00] [PASSED] 13 VFs
[04:19:00] [PASSED] 14 VFs
[04:19:00] [PASSED] 15 VFs
[04:19:00] [PASSED] 16 VFs
[04:19:00] [PASSED] 17 VFs
[04:19:00] [PASSED] 18 VFs
[04:19:00] [PASSED] 19 VFs
[04:19:00] [PASSED] 20 VFs
[04:19:00] [PASSED] 21 VFs
[04:19:00] [PASSED] 22 VFs
[04:19:00] [PASSED] 23 VFs
[04:19:00] [PASSED] 24 VFs
[04:19:00] [PASSED] 25 VFs
[04:19:00] [PASSED] 26 VFs
[04:19:00] [PASSED] 27 VFs
[04:19:00] [PASSED] 28 VFs
[04:19:00] [PASSED] 29 VFs
[04:19:00] [PASSED] 30 VFs
[04:19:00] [PASSED] 31 VFs
[04:19:00] [PASSED] 32 VFs
[04:19:00] [PASSED] 33 VFs
[04:19:00] [PASSED] 34 VFs
[04:19:00] [PASSED] 35 VFs
[04:19:00] [PASSED] 36 VFs
[04:19:00] [PASSED] 37 VFs
[04:19:00] [PASSED] 38 VFs
[04:19:00] [PASSED] 39 VFs
[04:19:00] [PASSED] 40 VFs
[04:19:00] [PASSED] 41 VFs
[04:19:00] [PASSED] 42 VFs
[04:19:00] [PASSED] 43 VFs
[04:19:00] [PASSED] 44 VFs
[04:19:00] [PASSED] 45 VFs
[04:19:00] [PASSED] 46 VFs
[04:19:00] [PASSED] 47 VFs
[04:19:00] [PASSED] 48 VFs
[04:19:00] [PASSED] 49 VFs
[04:19:00] [PASSED] 50 VFs
[04:19:00] [PASSED] 51 VFs
[04:19:00] [PASSED] 52 VFs
[04:19:00] [PASSED] 53 VFs
[04:19:00] [PASSED] 54 VFs
[04:19:00] [PASSED] 55 VFs
[04:19:00] [PASSED] 56 VFs
[04:19:00] [PASSED] 57 VFs
[04:19:00] [PASSED] 58 VFs
[04:19:00] [PASSED] 59 VFs
[04:19:00] [PASSED] 60 VFs
[04:19:00] [PASSED] 61 VFs
[04:19:00] [PASSED] 62 VFs
[04:19:00] [PASSED] 63 VFs
[04:19:00] ================== [PASSED] fair_contexts ==================
[04:19:00] ===================== fair_doorbells  ======================
[04:19:00] [PASSED] 1 VF
[04:19:00] [PASSED] 2 VFs
[04:19:00] [PASSED] 3 VFs
[04:19:00] [PASSED] 4 VFs
[04:19:00] [PASSED] 5 VFs
[04:19:00] [PASSED] 6 VFs
[04:19:00] [PASSED] 7 VFs
[04:19:00] [PASSED] 8 VFs
[04:19:00] [PASSED] 9 VFs
[04:19:00] [PASSED] 10 VFs
[04:19:00] [PASSED] 11 VFs
[04:19:00] [PASSED] 12 VFs
[04:19:00] [PASSED] 13 VFs
[04:19:00] [PASSED] 14 VFs
[04:19:00] [PASSED] 15 VFs
[04:19:00] [PASSED] 16 VFs
[04:19:00] [PASSED] 17 VFs
[04:19:00] [PASSED] 18 VFs
[04:19:00] [PASSED] 19 VFs
[04:19:00] [PASSED] 20 VFs
[04:19:00] [PASSED] 21 VFs
[04:19:00] [PASSED] 22 VFs
[04:19:00] [PASSED] 23 VFs
[04:19:00] [PASSED] 24 VFs
[04:19:00] [PASSED] 25 VFs
[04:19:00] [PASSED] 26 VFs
[04:19:00] [PASSED] 27 VFs
[04:19:00] [PASSED] 28 VFs
[04:19:00] [PASSED] 29 VFs
[04:19:00] [PASSED] 30 VFs
[04:19:00] [PASSED] 31 VFs
[04:19:00] [PASSED] 32 VFs
[04:19:00] [PASSED] 33 VFs
[04:19:00] [PASSED] 34 VFs
[04:19:00] [PASSED] 35 VFs
[04:19:00] [PASSED] 36 VFs
[04:19:00] [PASSED] 37 VFs
[04:19:00] [PASSED] 38 VFs
[04:19:00] [PASSED] 39 VFs
[04:19:00] [PASSED] 40 VFs
[04:19:00] [PASSED] 41 VFs
[04:19:00] [PASSED] 42 VFs
[04:19:00] [PASSED] 43 VFs
[04:19:00] [PASSED] 44 VFs
[04:19:00] [PASSED] 45 VFs
[04:19:00] [PASSED] 46 VFs
[04:19:00] [PASSED] 47 VFs
[04:19:00] [PASSED] 48 VFs
[04:19:00] [PASSED] 49 VFs
[04:19:00] [PASSED] 50 VFs
[04:19:00] [PASSED] 51 VFs
[04:19:00] [PASSED] 52 VFs
[04:19:00] [PASSED] 53 VFs
[04:19:00] [PASSED] 54 VFs
[04:19:00] [PASSED] 55 VFs
[04:19:00] [PASSED] 56 VFs
[04:19:00] [PASSED] 57 VFs
[04:19:00] [PASSED] 58 VFs
[04:19:00] [PASSED] 59 VFs
[04:19:00] [PASSED] 60 VFs
[04:19:00] [PASSED] 61 VFs
[04:19:00] [PASSED] 62 VFs
[04:19:00] [PASSED] 63 VFs
[04:19:00] ================= [PASSED] fair_doorbells ==================
[04:19:00] ======================== fair_ggtt  ========================
[04:19:00] [PASSED] 1 VF
[04:19:00] [PASSED] 2 VFs
[04:19:00] [PASSED] 3 VFs
[04:19:00] [PASSED] 4 VFs
[04:19:00] [PASSED] 5 VFs
[04:19:00] [PASSED] 6 VFs
[04:19:00] [PASSED] 7 VFs
[04:19:00] [PASSED] 8 VFs
[04:19:00] [PASSED] 9 VFs
[04:19:00] [PASSED] 10 VFs
[04:19:00] [PASSED] 11 VFs
[04:19:00] [PASSED] 12 VFs
[04:19:00] [PASSED] 13 VFs
[04:19:00] [PASSED] 14 VFs
[04:19:00] [PASSED] 15 VFs
[04:19:00] [PASSED] 16 VFs
[04:19:00] [PASSED] 17 VFs
[04:19:00] [PASSED] 18 VFs
[04:19:00] [PASSED] 19 VFs
[04:19:00] [PASSED] 20 VFs
[04:19:00] [PASSED] 21 VFs
[04:19:00] [PASSED] 22 VFs
[04:19:00] [PASSED] 23 VFs
[04:19:00] [PASSED] 24 VFs
[04:19:00] [PASSED] 25 VFs
[04:19:00] [PASSED] 26 VFs
[04:19:00] [PASSED] 27 VFs
[04:19:00] [PASSED] 28 VFs
[04:19:00] [PASSED] 29 VFs
[04:19:00] [PASSED] 30 VFs
[04:19:00] [PASSED] 31 VFs
[04:19:00] [PASSED] 32 VFs
[04:19:00] [PASSED] 33 VFs
[04:19:00] [PASSED] 34 VFs
[04:19:00] [PASSED] 35 VFs
[04:19:00] [PASSED] 36 VFs
[04:19:00] [PASSED] 37 VFs
[04:19:00] [PASSED] 38 VFs
[04:19:00] [PASSED] 39 VFs
[04:19:00] [PASSED] 40 VFs
[04:19:00] [PASSED] 41 VFs
[04:19:00] [PASSED] 42 VFs
[04:19:00] [PASSED] 43 VFs
[04:19:00] [PASSED] 44 VFs
[04:19:00] [PASSED] 45 VFs
[04:19:00] [PASSED] 46 VFs
[04:19:00] [PASSED] 47 VFs
[04:19:00] [PASSED] 48 VFs
[04:19:00] [PASSED] 49 VFs
[04:19:00] [PASSED] 50 VFs
[04:19:00] [PASSED] 51 VFs
[04:19:00] [PASSED] 52 VFs
[04:19:00] [PASSED] 53 VFs
[04:19:00] [PASSED] 54 VFs
[04:19:00] [PASSED] 55 VFs
[04:19:00] [PASSED] 56 VFs
[04:19:00] [PASSED] 57 VFs
[04:19:00] [PASSED] 58 VFs
[04:19:00] [PASSED] 59 VFs
[04:19:00] [PASSED] 60 VFs
[04:19:00] [PASSED] 61 VFs
[04:19:00] [PASSED] 62 VFs
[04:19:00] [PASSED] 63 VFs
[04:19:00] ==================== [PASSED] fair_ggtt ====================
[04:19:00] ======================== fair_vram  ========================
[04:19:00] [PASSED] 1 VF
[04:19:00] [PASSED] 2 VFs
[04:19:00] [PASSED] 3 VFs
[04:19:00] [PASSED] 4 VFs
[04:19:00] [PASSED] 5 VFs
[04:19:00] [PASSED] 6 VFs
[04:19:00] [PASSED] 7 VFs
[04:19:00] [PASSED] 8 VFs
[04:19:00] [PASSED] 9 VFs
[04:19:00] [PASSED] 10 VFs
[04:19:00] [PASSED] 11 VFs
[04:19:00] [PASSED] 12 VFs
[04:19:00] [PASSED] 13 VFs
[04:19:00] [PASSED] 14 VFs
[04:19:00] [PASSED] 15 VFs
[04:19:00] [PASSED] 16 VFs
[04:19:00] [PASSED] 17 VFs
[04:19:00] [PASSED] 18 VFs
[04:19:00] [PASSED] 19 VFs
[04:19:00] [PASSED] 20 VFs
[04:19:00] [PASSED] 21 VFs
[04:19:00] [PASSED] 22 VFs
[04:19:00] [PASSED] 23 VFs
[04:19:00] [PASSED] 24 VFs
[04:19:00] [PASSED] 25 VFs
[04:19:00] [PASSED] 26 VFs
[04:19:00] [PASSED] 27 VFs
[04:19:00] [PASSED] 28 VFs
[04:19:00] [PASSED] 29 VFs
[04:19:00] [PASSED] 30 VFs
[04:19:00] [PASSED] 31 VFs
[04:19:00] [PASSED] 32 VFs
[04:19:00] [PASSED] 33 VFs
[04:19:00] [PASSED] 34 VFs
[04:19:00] [PASSED] 35 VFs
[04:19:00] [PASSED] 36 VFs
[04:19:00] [PASSED] 37 VFs
[04:19:00] [PASSED] 38 VFs
[04:19:00] [PASSED] 39 VFs
[04:19:00] [PASSED] 40 VFs
[04:19:00] [PASSED] 41 VFs
[04:19:00] [PASSED] 42 VFs
[04:19:00] [PASSED] 43 VFs
[04:19:00] [PASSED] 44 VFs
[04:19:00] [PASSED] 45 VFs
[04:19:00] [PASSED] 46 VFs
[04:19:00] [PASSED] 47 VFs
[04:19:00] [PASSED] 48 VFs
[04:19:00] [PASSED] 49 VFs
[04:19:00] [PASSED] 50 VFs
[04:19:00] [PASSED] 51 VFs
[04:19:00] [PASSED] 52 VFs
[04:19:00] [PASSED] 53 VFs
[04:19:00] [PASSED] 54 VFs
[04:19:00] [PASSED] 55 VFs
[04:19:00] [PASSED] 56 VFs
[04:19:00] [PASSED] 57 VFs
[04:19:00] [PASSED] 58 VFs
[04:19:00] [PASSED] 59 VFs
[04:19:00] [PASSED] 60 VFs
[04:19:00] [PASSED] 61 VFs
[04:19:00] [PASSED] 62 VFs
[04:19:00] [PASSED] 63 VFs
[04:19:00] ==================== [PASSED] fair_vram ====================
[04:19:00] ================== [PASSED] pf_gt_config ===================
[04:19:00] ===================== lmtt (1 subtest) =====================
[04:19:00] ======================== test_ops  =========================
[04:19:00] [PASSED] 2-level
[04:19:00] [PASSED] multi-level
[04:19:00] ==================== [PASSED] test_ops =====================
[04:19:00] ====================== [PASSED] lmtt =======================
[04:19:00] ================= pf_service (11 subtests) =================
[04:19:00] [PASSED] pf_negotiate_any
[04:19:00] [PASSED] pf_negotiate_base_match
[04:19:00] [PASSED] pf_negotiate_base_newer
[04:19:00] [PASSED] pf_negotiate_base_next
[04:19:00] [SKIPPED] pf_negotiate_base_older
[04:19:00] [PASSED] pf_negotiate_base_prev
[04:19:00] [PASSED] pf_negotiate_latest_match
[04:19:00] [PASSED] pf_negotiate_latest_newer
[04:19:00] [PASSED] pf_negotiate_latest_next
[04:19:00] [SKIPPED] pf_negotiate_latest_older
[04:19:00] [SKIPPED] pf_negotiate_latest_prev
[04:19:00] =================== [PASSED] pf_service ====================
[04:19:00] ================= xe_guc_g2g (2 subtests) ==================
[04:19:00] ============== xe_live_guc_g2g_kunit_default  ==============
[04:19:00] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[04:19:00] ============== xe_live_guc_g2g_kunit_allmem  ===============
[04:19:00] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[04:19:00] =================== [SKIPPED] xe_guc_g2g ===================
[04:19:00] =================== xe_mocs (2 subtests) ===================
[04:19:00] ================ xe_live_mocs_kernel_kunit  ================
[04:19:00] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[04:19:00] ================ xe_live_mocs_reset_kunit  =================
[04:19:00] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[04:19:00] ==================== [SKIPPED] xe_mocs =====================
[04:19:00] ================= xe_migrate (2 subtests) ==================
[04:19:00] ================= xe_migrate_sanity_kunit  =================
[04:19:00] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[04:19:00] ================== xe_validate_ccs_kunit  ==================
[04:19:00] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[04:19:00] =================== [SKIPPED] xe_migrate ===================
[04:19:00] ================== xe_dma_buf (1 subtest) ==================
[04:19:00] ==================== xe_dma_buf_kunit  =====================
[04:19:00] ================ [SKIPPED] xe_dma_buf_kunit ================
[04:19:00] =================== [SKIPPED] xe_dma_buf ===================
[04:19:00] ================= xe_bo_shrink (1 subtest) =================
[04:19:00] =================== xe_bo_shrink_kunit  ====================
[04:19:00] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[04:19:00] ================== [SKIPPED] xe_bo_shrink ==================
[04:19:00] ==================== xe_bo (2 subtests) ====================
[04:19:00] ================== xe_ccs_migrate_kunit  ===================
[04:19:00] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[04:19:00] ==================== xe_bo_evict_kunit  ====================
[04:19:00] =============== [SKIPPED] xe_bo_evict_kunit ================
[04:19:00] ===================== [SKIPPED] xe_bo ======================
[04:19:00] ==================== args (13 subtests) ====================
[04:19:00] [PASSED] count_args_test
[04:19:00] [PASSED] call_args_example
[04:19:00] [PASSED] call_args_test
[04:19:00] [PASSED] drop_first_arg_example
[04:19:00] [PASSED] drop_first_arg_test
[04:19:00] [PASSED] first_arg_example
[04:19:00] [PASSED] first_arg_test
[04:19:00] [PASSED] last_arg_example
[04:19:00] [PASSED] last_arg_test
[04:19:00] [PASSED] pick_arg_example
[04:19:00] [PASSED] if_args_example
[04:19:00] [PASSED] if_args_test
[04:19:00] [PASSED] sep_comma_example
[04:19:00] ====================== [PASSED] args =======================
[04:19:00] =================== xe_pci (3 subtests) ====================
[04:19:00] ==================== check_graphics_ip  ====================
[04:19:00] [PASSED] 12.00 Xe_LP
[04:19:00] [PASSED] 12.10 Xe_LP+
[04:19:00] [PASSED] 12.55 Xe_HPG
[04:19:00] [PASSED] 12.60 Xe_HPC
[04:19:00] [PASSED] 12.70 Xe_LPG
[04:19:00] [PASSED] 12.71 Xe_LPG
[04:19:00] [PASSED] 12.74 Xe_LPG+
[04:19:00] [PASSED] 20.01 Xe2_HPG
[04:19:00] [PASSED] 20.02 Xe2_HPG
[04:19:00] [PASSED] 20.04 Xe2_LPG
[04:19:00] [PASSED] 30.00 Xe3_LPG
[04:19:00] [PASSED] 30.01 Xe3_LPG
[04:19:00] [PASSED] 30.03 Xe3_LPG
[04:19:00] [PASSED] 30.04 Xe3_LPG
[04:19:00] [PASSED] 30.05 Xe3_LPG
[04:19:00] [PASSED] 35.10 Xe3p_LPG
[04:19:00] [PASSED] 35.11 Xe3p_XPC
[04:19:00] ================ [PASSED] check_graphics_ip ================
[04:19:00] ===================== check_media_ip  ======================
[04:19:00] [PASSED] 12.00 Xe_M
[04:19:00] [PASSED] 12.55 Xe_HPM
[04:19:00] [PASSED] 13.00 Xe_LPM+
[04:19:00] [PASSED] 13.01 Xe2_HPM
[04:19:00] [PASSED] 20.00 Xe2_LPM
[04:19:00] [PASSED] 30.00 Xe3_LPM
[04:19:00] [PASSED] 30.02 Xe3_LPM
[04:19:00] [PASSED] 35.00 Xe3p_LPM
[04:19:00] [PASSED] 35.03 Xe3p_HPM
[04:19:00] ================= [PASSED] check_media_ip ==================
[04:19:00] =================== check_platform_desc  ===================
[04:19:00] [PASSED] 0x9A60 (TIGERLAKE)
[04:19:00] [PASSED] 0x9A68 (TIGERLAKE)
[04:19:00] [PASSED] 0x9A70 (TIGERLAKE)
[04:19:00] [PASSED] 0x9A40 (TIGERLAKE)
[04:19:00] [PASSED] 0x9A49 (TIGERLAKE)
[04:19:00] [PASSED] 0x9A59 (TIGERLAKE)
[04:19:00] [PASSED] 0x9A78 (TIGERLAKE)
[04:19:00] [PASSED] 0x9AC0 (TIGERLAKE)
[04:19:00] [PASSED] 0x9AC9 (TIGERLAKE)
[04:19:00] [PASSED] 0x9AD9 (TIGERLAKE)
[04:19:00] [PASSED] 0x9AF8 (TIGERLAKE)
[04:19:00] [PASSED] 0x4C80 (ROCKETLAKE)
[04:19:00] [PASSED] 0x4C8A (ROCKETLAKE)
[04:19:00] [PASSED] 0x4C8B (ROCKETLAKE)
[04:19:00] [PASSED] 0x4C8C (ROCKETLAKE)
[04:19:00] [PASSED] 0x4C90 (ROCKETLAKE)
[04:19:00] [PASSED] 0x4C9A (ROCKETLAKE)
[04:19:00] [PASSED] 0x4680 (ALDERLAKE_S)
[04:19:00] [PASSED] 0x4682 (ALDERLAKE_S)
[04:19:00] [PASSED] 0x4688 (ALDERLAKE_S)
[04:19:00] [PASSED] 0x468A (ALDERLAKE_S)
[04:19:00] [PASSED] 0x468B (ALDERLAKE_S)
[04:19:00] [PASSED] 0x4690 (ALDERLAKE_S)
[04:19:00] [PASSED] 0x4692 (ALDERLAKE_S)
[04:19:00] [PASSED] 0x4693 (ALDERLAKE_S)
[04:19:00] [PASSED] 0x46A0 (ALDERLAKE_P)
[04:19:00] [PASSED] 0x46A1 (ALDERLAKE_P)
[04:19:00] [PASSED] 0x46A2 (ALDERLAKE_P)
[04:19:00] [PASSED] 0x46A3 (ALDERLAKE_P)
[04:19:00] [PASSED] 0x46A6 (ALDERLAKE_P)
[04:19:00] [PASSED] 0x46A8 (ALDERLAKE_P)
[04:19:00] [PASSED] 0x46AA (ALDERLAKE_P)
[04:19:00] [PASSED] 0x462A (ALDERLAKE_P)
[04:19:00] [PASSED] 0x4626 (ALDERLAKE_P)
[04:19:00] [PASSED] 0x4628 (ALDERLAKE_P)
[04:19:00] [PASSED] 0x46B0 (ALDERLAKE_P)
[04:19:00] [PASSED] 0x46B1 (ALDERLAKE_P)
[04:19:00] [PASSED] 0x46B2 (ALDERLAKE_P)
[04:19:00] [PASSED] 0x46B3 (ALDERLAKE_P)
[04:19:00] [PASSED] 0x46C0 (ALDERLAKE_P)
[04:19:00] [PASSED] 0x46C1 (ALDERLAKE_P)
[04:19:00] [PASSED] 0x46C2 (ALDERLAKE_P)
[04:19:00] [PASSED] 0x46C3 (ALDERLAKE_P)
[04:19:00] [PASSED] 0x46D0 (ALDERLAKE_N)
[04:19:00] [PASSED] 0x46D1 (ALDERLAKE_N)
[04:19:00] [PASSED] 0x46D2 (ALDERLAKE_N)
[04:19:00] [PASSED] 0x46D3 (ALDERLAKE_N)
[04:19:00] [PASSED] 0x46D4 (ALDERLAKE_N)
[04:19:00] [PASSED] 0xA721 (ALDERLAKE_P)
[04:19:00] [PASSED] 0xA7A1 (ALDERLAKE_P)
[04:19:00] [PASSED] 0xA7A9 (ALDERLAKE_P)
[04:19:00] [PASSED] 0xA7AC (ALDERLAKE_P)
[04:19:00] [PASSED] 0xA7AD (ALDERLAKE_P)
[04:19:00] [PASSED] 0xA720 (ALDERLAKE_P)
[04:19:00] [PASSED] 0xA7A0 (ALDERLAKE_P)
[04:19:00] [PASSED] 0xA7A8 (ALDERLAKE_P)
[04:19:00] [PASSED] 0xA7AA (ALDERLAKE_P)
[04:19:00] [PASSED] 0xA7AB (ALDERLAKE_P)
[04:19:00] [PASSED] 0xA780 (ALDERLAKE_S)
[04:19:00] [PASSED] 0xA781 (ALDERLAKE_S)
[04:19:00] [PASSED] 0xA782 (ALDERLAKE_S)
[04:19:00] [PASSED] 0xA783 (ALDERLAKE_S)
[04:19:00] [PASSED] 0xA788 (ALDERLAKE_S)
[04:19:00] [PASSED] 0xA789 (ALDERLAKE_S)
[04:19:00] [PASSED] 0xA78A (ALDERLAKE_S)
[04:19:00] [PASSED] 0xA78B (ALDERLAKE_S)
[04:19:00] [PASSED] 0x4905 (DG1)
[04:19:00] [PASSED] 0x4906 (DG1)
[04:19:00] [PASSED] 0x4907 (DG1)
[04:19:00] [PASSED] 0x4908 (DG1)
[04:19:00] [PASSED] 0x4909 (DG1)
[04:19:00] [PASSED] 0x56C0 (DG2)
[04:19:00] [PASSED] 0x56C2 (DG2)
[04:19:00] [PASSED] 0x56C1 (DG2)
[04:19:00] [PASSED] 0x7D51 (METEORLAKE)
[04:19:00] [PASSED] 0x7DD1 (METEORLAKE)
[04:19:00] [PASSED] 0x7D41 (METEORLAKE)
[04:19:00] [PASSED] 0x7D67 (METEORLAKE)
[04:19:00] [PASSED] 0xB640 (METEORLAKE)
[04:19:00] [PASSED] 0x56A0 (DG2)
[04:19:00] [PASSED] 0x56A1 (DG2)
[04:19:00] [PASSED] 0x56A2 (DG2)
[04:19:00] [PASSED] 0x56BE (DG2)
[04:19:00] [PASSED] 0x56BF (DG2)
[04:19:00] [PASSED] 0x5690 (DG2)
[04:19:00] [PASSED] 0x5691 (DG2)
[04:19:00] [PASSED] 0x5692 (DG2)
[04:19:00] [PASSED] 0x56A5 (DG2)
[04:19:00] [PASSED] 0x56A6 (DG2)
[04:19:00] [PASSED] 0x56B0 (DG2)
[04:19:00] [PASSED] 0x56B1 (DG2)
[04:19:00] [PASSED] 0x56BA (DG2)
[04:19:00] [PASSED] 0x56BB (DG2)
[04:19:00] [PASSED] 0x56BC (DG2)
[04:19:00] [PASSED] 0x56BD (DG2)
[04:19:00] [PASSED] 0x5693 (DG2)
[04:19:00] [PASSED] 0x5694 (DG2)
[04:19:00] [PASSED] 0x5695 (DG2)
[04:19:00] [PASSED] 0x56A3 (DG2)
[04:19:00] [PASSED] 0x56A4 (DG2)
[04:19:00] [PASSED] 0x56B2 (DG2)
[04:19:00] [PASSED] 0x56B3 (DG2)
[04:19:00] [PASSED] 0x5696 (DG2)
[04:19:00] [PASSED] 0x5697 (DG2)
[04:19:00] [PASSED] 0xB69 (PVC)
[04:19:00] [PASSED] 0xB6E (PVC)
[04:19:00] [PASSED] 0xBD4 (PVC)
[04:19:00] [PASSED] 0xBD5 (PVC)
[04:19:00] [PASSED] 0xBD6 (PVC)
[04:19:00] [PASSED] 0xBD7 (PVC)
[04:19:00] [PASSED] 0xBD8 (PVC)
[04:19:00] [PASSED] 0xBD9 (PVC)
[04:19:00] [PASSED] 0xBDA (PVC)
[04:19:00] [PASSED] 0xBDB (PVC)
[04:19:00] [PASSED] 0xBE0 (PVC)
[04:19:00] [PASSED] 0xBE1 (PVC)
[04:19:00] [PASSED] 0xBE5 (PVC)
[04:19:00] [PASSED] 0x7D40 (METEORLAKE)
[04:19:00] [PASSED] 0x7D45 (METEORLAKE)
[04:19:00] [PASSED] 0x7D55 (METEORLAKE)
[04:19:00] [PASSED] 0x7D60 (METEORLAKE)
[04:19:00] [PASSED] 0x7DD5 (METEORLAKE)
[04:19:00] [PASSED] 0x6420 (LUNARLAKE)
[04:19:00] [PASSED] 0x64A0 (LUNARLAKE)
[04:19:00] [PASSED] 0x64B0 (LUNARLAKE)
[04:19:00] [PASSED] 0xE202 (BATTLEMAGE)
[04:19:00] [PASSED] 0xE209 (BATTLEMAGE)
[04:19:00] [PASSED] 0xE20B (BATTLEMAGE)
[04:19:00] [PASSED] 0xE20C (BATTLEMAGE)
[04:19:00] [PASSED] 0xE20D (BATTLEMAGE)
[04:19:00] [PASSED] 0xE210 (BATTLEMAGE)
[04:19:00] [PASSED] 0xE211 (BATTLEMAGE)
[04:19:00] [PASSED] 0xE212 (BATTLEMAGE)
[04:19:00] [PASSED] 0xE216 (BATTLEMAGE)
[04:19:00] [PASSED] 0xE220 (BATTLEMAGE)
[04:19:00] [PASSED] 0xE221 (BATTLEMAGE)
[04:19:00] [PASSED] 0xE222 (BATTLEMAGE)
[04:19:00] [PASSED] 0xE223 (BATTLEMAGE)
[04:19:00] [PASSED] 0xB080 (PANTHERLAKE)
[04:19:00] [PASSED] 0xB081 (PANTHERLAKE)
[04:19:00] [PASSED] 0xB082 (PANTHERLAKE)
[04:19:00] [PASSED] 0xB083 (PANTHERLAKE)
[04:19:00] [PASSED] 0xB084 (PANTHERLAKE)
[04:19:00] [PASSED] 0xB085 (PANTHERLAKE)
[04:19:00] [PASSED] 0xB086 (PANTHERLAKE)
[04:19:00] [PASSED] 0xB087 (PANTHERLAKE)
[04:19:00] [PASSED] 0xB08F (PANTHERLAKE)
[04:19:00] [PASSED] 0xB090 (PANTHERLAKE)
[04:19:00] [PASSED] 0xB0A0 (PANTHERLAKE)
[04:19:00] [PASSED] 0xB0B0 (PANTHERLAKE)
[04:19:00] [PASSED] 0xFD80 (PANTHERLAKE)
[04:19:00] [PASSED] 0xFD81 (PANTHERLAKE)
[04:19:00] [PASSED] 0xD740 (NOVALAKE_S)
[04:19:00] [PASSED] 0xD741 (NOVALAKE_S)
[04:19:00] [PASSED] 0xD742 (NOVALAKE_S)
[04:19:00] [PASSED] 0xD743 (NOVALAKE_S)
[04:19:00] [PASSED] 0xD744 (NOVALAKE_S)
[04:19:00] [PASSED] 0xD745 (NOVALAKE_S)
[04:19:00] [PASSED] 0x674C (CRESCENTISLAND)
[04:19:00] [PASSED] 0xD750 (NOVALAKE_P)
[04:19:00] [PASSED] 0xD751 (NOVALAKE_P)
[04:19:00] [PASSED] 0xD752 (NOVALAKE_P)
[04:19:00] [PASSED] 0xD753 (NOVALAKE_P)
[04:19:00] [PASSED] 0xD754 (NOVALAKE_P)
[04:19:00] [PASSED] 0xD755 (NOVALAKE_P)
[04:19:00] [PASSED] 0xD756 (NOVALAKE_P)
[04:19:00] [PASSED] 0xD757 (NOVALAKE_P)
[04:19:00] [PASSED] 0xD75F (NOVALAKE_P)
[04:19:00] =============== [PASSED] check_platform_desc ===============
[04:19:00] ===================== [PASSED] xe_pci ======================
[04:19:00] =================== xe_rtp (2 subtests) ====================
[04:19:00] =============== xe_rtp_process_to_sr_tests  ================
[04:19:00] [PASSED] coalesce-same-reg
[04:19:00] [PASSED] no-match-no-add
[04:19:00] [PASSED] match-or
[04:19:00] [PASSED] match-or-xfail
[04:19:00] [PASSED] no-match-no-add-multiple-rules
[04:19:00] [PASSED] two-regs-two-entries
[04:19:00] [PASSED] clr-one-set-other
[04:19:00] [PASSED] set-field
[04:19:00] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[04:19:00] [PASSED] conflict-not-disjoint
[04:19:00] [PASSED] conflict-reg-type
[04:19:00] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[04:19:00] ================== xe_rtp_process_tests  ===================
[04:19:00] [PASSED] active1
[04:19:00] [PASSED] active2
[04:19:00] [PASSED] active-inactive
[04:19:00] [PASSED] inactive-active
[04:19:00] [PASSED] inactive-1st_or_active-inactive
[04:19:00] [PASSED] inactive-2nd_or_active-inactive
[04:19:00] [PASSED] inactive-last_or_active-inactive
[04:19:00] [PASSED] inactive-no_or_active-inactive
[04:19:00] ============== [PASSED] xe_rtp_process_tests ===============
[04:19:00] ===================== [PASSED] xe_rtp ======================
[04:19:00] ==================== xe_wa (1 subtest) =====================
[04:19:00] ======================== xe_wa_gt  =========================
[04:19:00] [PASSED] TIGERLAKE B0
[04:19:00] [PASSED] DG1 A0
[04:19:00] [PASSED] DG1 B0
[04:19:00] [PASSED] ALDERLAKE_S A0
[04:19:00] [PASSED] ALDERLAKE_S B0
[04:19:00] [PASSED] ALDERLAKE_S C0
[04:19:00] [PASSED] ALDERLAKE_S D0
[04:19:00] [PASSED] ALDERLAKE_P A0
[04:19:00] [PASSED] ALDERLAKE_P B0
[04:19:00] [PASSED] ALDERLAKE_P C0
[04:19:00] [PASSED] ALDERLAKE_S RPLS D0
[04:19:00] [PASSED] ALDERLAKE_P RPLU E0
[04:19:00] [PASSED] DG2 G10 C0
[04:19:00] [PASSED] DG2 G11 B1
[04:19:00] [PASSED] DG2 G12 A1
[04:19:00] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[04:19:00] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[04:19:00] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[04:19:00] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[04:19:00] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[04:19:00] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[04:19:00] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[04:19:00] ==================== [PASSED] xe_wa_gt =====================
[04:19:00] ====================== [PASSED] xe_wa ======================
[04:19:00] ============================================================
[04:19:00] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[04:19:01] Elapsed time: 36.402s total, 4.326s configuring, 31.409s building, 0.610s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[04:19:01] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:19:02] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:19:27] Starting KUnit Kernel (1/1)...
[04:19:27] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:19:27] ============ drm_test_pick_cmdline (2 subtests) ============
[04:19:27] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[04:19:27] =============== drm_test_pick_cmdline_named  ===============
[04:19:27] [PASSED] NTSC
[04:19:27] [PASSED] NTSC-J
[04:19:27] [PASSED] PAL
[04:19:27] [PASSED] PAL-M
[04:19:27] =========== [PASSED] drm_test_pick_cmdline_named ===========
[04:19:27] ============== [PASSED] drm_test_pick_cmdline ==============
[04:19:27] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[04:19:27] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[04:19:27] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[04:19:27] =========== drm_validate_clone_mode (2 subtests) ===========
[04:19:27] ============== drm_test_check_in_clone_mode  ===============
[04:19:27] [PASSED] in_clone_mode
[04:19:27] [PASSED] not_in_clone_mode
[04:19:27] ========== [PASSED] drm_test_check_in_clone_mode ===========
[04:19:27] =============== drm_test_check_valid_clones  ===============
[04:19:27] [PASSED] not_in_clone_mode
[04:19:27] [PASSED] valid_clone
[04:19:27] [PASSED] invalid_clone
[04:19:27] =========== [PASSED] drm_test_check_valid_clones ===========
[04:19:27] ============= [PASSED] drm_validate_clone_mode =============
[04:19:27] ============= drm_validate_modeset (1 subtest) =============
[04:19:27] [PASSED] drm_test_check_connector_changed_modeset
[04:19:27] ============== [PASSED] drm_validate_modeset ===============
[04:19:27] ====== drm_test_bridge_get_current_state (2 subtests) ======
[04:19:27] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[04:19:27] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[04:19:27] ======== [PASSED] drm_test_bridge_get_current_state ========
[04:19:27] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[04:19:27] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[04:19:27] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[04:19:27] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[04:19:27] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[04:19:27] ============== drm_bridge_alloc (2 subtests) ===============
[04:19:27] [PASSED] drm_test_drm_bridge_alloc_basic
[04:19:27] [PASSED] drm_test_drm_bridge_alloc_get_put
[04:19:27] ================ [PASSED] drm_bridge_alloc =================
[04:19:27] ============= drm_cmdline_parser (40 subtests) =============
[04:19:27] [PASSED] drm_test_cmdline_force_d_only
[04:19:27] [PASSED] drm_test_cmdline_force_D_only_dvi
[04:19:27] [PASSED] drm_test_cmdline_force_D_only_hdmi
[04:19:27] [PASSED] drm_test_cmdline_force_D_only_not_digital
[04:19:27] [PASSED] drm_test_cmdline_force_e_only
[04:19:27] [PASSED] drm_test_cmdline_res
[04:19:27] [PASSED] drm_test_cmdline_res_vesa
[04:19:27] [PASSED] drm_test_cmdline_res_vesa_rblank
[04:19:27] [PASSED] drm_test_cmdline_res_rblank
[04:19:27] [PASSED] drm_test_cmdline_res_bpp
[04:19:27] [PASSED] drm_test_cmdline_res_refresh
[04:19:27] [PASSED] drm_test_cmdline_res_bpp_refresh
[04:19:27] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[04:19:27] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[04:19:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[04:19:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[04:19:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[04:19:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[04:19:27] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[04:19:27] [PASSED] drm_test_cmdline_res_margins_force_on
[04:19:27] [PASSED] drm_test_cmdline_res_vesa_margins
[04:19:27] [PASSED] drm_test_cmdline_name
[04:19:27] [PASSED] drm_test_cmdline_name_bpp
[04:19:27] [PASSED] drm_test_cmdline_name_option
[04:19:27] [PASSED] drm_test_cmdline_name_bpp_option
[04:19:27] [PASSED] drm_test_cmdline_rotate_0
[04:19:27] [PASSED] drm_test_cmdline_rotate_90
[04:19:27] [PASSED] drm_test_cmdline_rotate_180
[04:19:27] [PASSED] drm_test_cmdline_rotate_270
[04:19:27] [PASSED] drm_test_cmdline_hmirror
[04:19:27] [PASSED] drm_test_cmdline_vmirror
[04:19:27] [PASSED] drm_test_cmdline_margin_options
[04:19:27] [PASSED] drm_test_cmdline_multiple_options
[04:19:27] [PASSED] drm_test_cmdline_bpp_extra_and_option
[04:19:27] [PASSED] drm_test_cmdline_extra_and_option
[04:19:27] [PASSED] drm_test_cmdline_freestanding_options
[04:19:27] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[04:19:27] [PASSED] drm_test_cmdline_panel_orientation
[04:19:27] ================ drm_test_cmdline_invalid  =================
[04:19:27] [PASSED] margin_only
[04:19:27] [PASSED] interlace_only
[04:19:27] [PASSED] res_missing_x
[04:19:27] [PASSED] res_missing_y
[04:19:27] [PASSED] res_bad_y
[04:19:27] [PASSED] res_missing_y_bpp
[04:19:27] [PASSED] res_bad_bpp
[04:19:27] [PASSED] res_bad_refresh
[04:19:27] [PASSED] res_bpp_refresh_force_on_off
[04:19:27] [PASSED] res_invalid_mode
[04:19:27] [PASSED] res_bpp_wrong_place_mode
[04:19:27] [PASSED] name_bpp_refresh
[04:19:27] [PASSED] name_refresh
[04:19:27] [PASSED] name_refresh_wrong_mode
[04:19:27] [PASSED] name_refresh_invalid_mode
[04:19:27] [PASSED] rotate_multiple
[04:19:27] [PASSED] rotate_invalid_val
[04:19:27] [PASSED] rotate_truncated
[04:19:27] [PASSED] invalid_option
[04:19:27] [PASSED] invalid_tv_option
[04:19:27] [PASSED] truncated_tv_option
[04:19:27] ============ [PASSED] drm_test_cmdline_invalid =============
[04:19:27] =============== drm_test_cmdline_tv_options  ===============
[04:19:27] [PASSED] NTSC
[04:19:27] [PASSED] NTSC_443
[04:19:27] [PASSED] NTSC_J
[04:19:27] [PASSED] PAL
[04:19:27] [PASSED] PAL_M
[04:19:27] [PASSED] PAL_N
[04:19:27] [PASSED] SECAM
[04:19:27] [PASSED] MONO_525
[04:19:27] [PASSED] MONO_625
[04:19:27] =========== [PASSED] drm_test_cmdline_tv_options ===========
[04:19:27] =============== [PASSED] drm_cmdline_parser ================
[04:19:27] ========== drmm_connector_hdmi_init (20 subtests) ==========
[04:19:27] [PASSED] drm_test_connector_hdmi_init_valid
[04:19:27] [PASSED] drm_test_connector_hdmi_init_bpc_8
[04:19:27] [PASSED] drm_test_connector_hdmi_init_bpc_10
[04:19:27] [PASSED] drm_test_connector_hdmi_init_bpc_12
[04:19:27] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[04:19:27] [PASSED] drm_test_connector_hdmi_init_bpc_null
[04:19:27] [PASSED] drm_test_connector_hdmi_init_formats_empty
[04:19:27] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[04:19:27] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[04:19:27] [PASSED] supported_formats=0x9 yuv420_allowed=1
[04:19:27] [PASSED] supported_formats=0x9 yuv420_allowed=0
[04:19:27] [PASSED] supported_formats=0x5 yuv420_allowed=1
[04:19:27] [PASSED] supported_formats=0x5 yuv420_allowed=0
[04:19:27] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[04:19:27] [PASSED] drm_test_connector_hdmi_init_null_ddc
[04:19:27] [PASSED] drm_test_connector_hdmi_init_null_product
[04:19:27] [PASSED] drm_test_connector_hdmi_init_null_vendor
[04:19:27] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[04:19:27] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[04:19:27] [PASSED] drm_test_connector_hdmi_init_product_valid
[04:19:27] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[04:19:27] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[04:19:27] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[04:19:27] ========= drm_test_connector_hdmi_init_type_valid  =========
[04:19:27] [PASSED] HDMI-A
[04:19:27] [PASSED] HDMI-B
[04:19:27] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[04:19:27] ======== drm_test_connector_hdmi_init_type_invalid  ========
[04:19:27] [PASSED] Unknown
[04:19:27] [PASSED] VGA
[04:19:27] [PASSED] DVI-I
[04:19:27] [PASSED] DVI-D
[04:19:27] [PASSED] DVI-A
[04:19:27] [PASSED] Composite
[04:19:27] [PASSED] SVIDEO
[04:19:27] [PASSED] LVDS
[04:19:27] [PASSED] Component
[04:19:27] [PASSED] DIN
[04:19:27] [PASSED] DP
[04:19:27] [PASSED] TV
[04:19:27] [PASSED] eDP
[04:19:27] [PASSED] Virtual
[04:19:27] [PASSED] DSI
[04:19:27] [PASSED] DPI
[04:19:27] [PASSED] Writeback
[04:19:27] [PASSED] SPI
[04:19:27] [PASSED] USB
[04:19:27] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[04:19:27] ============ [PASSED] drmm_connector_hdmi_init =============
[04:19:27] ============= drmm_connector_init (3 subtests) =============
[04:19:27] [PASSED] drm_test_drmm_connector_init
[04:19:27] [PASSED] drm_test_drmm_connector_init_null_ddc
[04:19:27] ========= drm_test_drmm_connector_init_type_valid  =========
[04:19:27] [PASSED] Unknown
[04:19:27] [PASSED] VGA
[04:19:27] [PASSED] DVI-I
[04:19:27] [PASSED] DVI-D
[04:19:27] [PASSED] DVI-A
[04:19:27] [PASSED] Composite
[04:19:27] [PASSED] SVIDEO
[04:19:27] [PASSED] LVDS
[04:19:27] [PASSED] Component
[04:19:27] [PASSED] DIN
[04:19:27] [PASSED] DP
[04:19:27] [PASSED] HDMI-A
[04:19:27] [PASSED] HDMI-B
[04:19:27] [PASSED] TV
[04:19:27] [PASSED] eDP
[04:19:27] [PASSED] Virtual
[04:19:27] [PASSED] DSI
[04:19:27] [PASSED] DPI
[04:19:27] [PASSED] Writeback
[04:19:27] [PASSED] SPI
[04:19:27] [PASSED] USB
[04:19:27] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[04:19:27] =============== [PASSED] drmm_connector_init ===============
[04:19:27] ========= drm_connector_dynamic_init (6 subtests) ==========
[04:19:27] [PASSED] drm_test_drm_connector_dynamic_init
[04:19:27] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[04:19:27] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[04:19:27] [PASSED] drm_test_drm_connector_dynamic_init_properties
[04:19:27] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[04:19:27] [PASSED] Unknown
[04:19:27] [PASSED] VGA
[04:19:27] [PASSED] DVI-I
[04:19:27] [PASSED] DVI-D
[04:19:27] [PASSED] DVI-A
[04:19:27] [PASSED] Composite
[04:19:27] [PASSED] SVIDEO
[04:19:27] [PASSED] LVDS
[04:19:27] [PASSED] Component
[04:19:27] [PASSED] DIN
[04:19:27] [PASSED] DP
[04:19:27] [PASSED] HDMI-A
[04:19:27] [PASSED] HDMI-B
[04:19:27] [PASSED] TV
[04:19:27] [PASSED] eDP
[04:19:27] [PASSED] Virtual
[04:19:27] [PASSED] DSI
[04:19:27] [PASSED] DPI
[04:19:27] [PASSED] Writeback
[04:19:27] [PASSED] SPI
[04:19:27] [PASSED] USB
[04:19:27] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[04:19:27] ======== drm_test_drm_connector_dynamic_init_name  =========
[04:19:27] [PASSED] Unknown
[04:19:27] [PASSED] VGA
[04:19:27] [PASSED] DVI-I
[04:19:27] [PASSED] DVI-D
[04:19:27] [PASSED] DVI-A
[04:19:27] [PASSED] Composite
[04:19:27] [PASSED] SVIDEO
[04:19:27] [PASSED] LVDS
[04:19:27] [PASSED] Component
[04:19:27] [PASSED] DIN
[04:19:27] [PASSED] DP
[04:19:27] [PASSED] HDMI-A
[04:19:27] [PASSED] HDMI-B
[04:19:27] [PASSED] TV
[04:19:27] [PASSED] eDP
[04:19:27] [PASSED] Virtual
[04:19:27] [PASSED] DSI
[04:19:27] [PASSED] DPI
[04:19:27] [PASSED] Writeback
[04:19:27] [PASSED] SPI
[04:19:27] [PASSED] USB
[04:19:27] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[04:19:27] =========== [PASSED] drm_connector_dynamic_init ============
[04:19:27] ==== drm_connector_dynamic_register_early (4 subtests) =====
[04:19:27] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[04:19:27] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[04:19:27] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[04:19:27] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[04:19:27] ====== [PASSED] drm_connector_dynamic_register_early =======
[04:19:27] ======= drm_connector_dynamic_register (7 subtests) ========
[04:19:27] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[04:19:27] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[04:19:27] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[04:19:27] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[04:19:27] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[04:19:27] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[04:19:27] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[04:19:27] ========= [PASSED] drm_connector_dynamic_register ==========
[04:19:27] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[04:19:27] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[04:19:27] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[04:19:27] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[04:19:27] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[04:19:27] ========== drm_test_get_tv_mode_from_name_valid  ===========
[04:19:27] [PASSED] NTSC
[04:19:27] [PASSED] NTSC-443
[04:19:27] [PASSED] NTSC-J
[04:19:27] [PASSED] PAL
[04:19:27] [PASSED] PAL-M
[04:19:27] [PASSED] PAL-N
[04:19:27] [PASSED] SECAM
[04:19:27] [PASSED] Mono
[04:19:27] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[04:19:27] [PASSED] drm_test_get_tv_mode_from_name_truncated
[04:19:27] ============ [PASSED] drm_get_tv_mode_from_name ============
[04:19:27] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[04:19:27] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[04:19:27] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[04:19:27] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[04:19:27] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[04:19:27] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[04:19:27] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[04:19:27] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[04:19:27] [PASSED] VIC 96
[04:19:27] [PASSED] VIC 97
[04:19:27] [PASSED] VIC 101
[04:19:27] [PASSED] VIC 102
[04:19:27] [PASSED] VIC 106
[04:19:27] [PASSED] VIC 107
[04:19:27] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[04:19:27] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[04:19:27] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[04:19:27] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[04:19:27] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[04:19:27] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[04:19:27] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[04:19:27] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[04:19:27] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[04:19:27] [PASSED] Automatic
[04:19:27] [PASSED] Full
[04:19:27] [PASSED] Limited 16:235
[04:19:27] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[04:19:27] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[04:19:27] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[04:19:27] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[04:19:27] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[04:19:27] [PASSED] RGB
[04:19:27] [PASSED] YUV 4:2:0
[04:19:27] [PASSED] YUV 4:2:2
[04:19:27] [PASSED] YUV 4:4:4
[04:19:27] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[04:19:27] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[04:19:27] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[04:19:27] ============= drm_damage_helper (21 subtests) ==============
[04:19:27] [PASSED] drm_test_damage_iter_no_damage
[04:19:27] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[04:19:27] [PASSED] drm_test_damage_iter_no_damage_src_moved
[04:19:27] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[04:19:27] [PASSED] drm_test_damage_iter_no_damage_not_visible
[04:19:27] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[04:19:27] [PASSED] drm_test_damage_iter_no_damage_no_fb
[04:19:27] [PASSED] drm_test_damage_iter_simple_damage
[04:19:27] [PASSED] drm_test_damage_iter_single_damage
[04:19:27] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[04:19:27] [PASSED] drm_test_damage_iter_single_damage_outside_src
[04:19:27] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[04:19:27] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[04:19:27] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[04:19:27] [PASSED] drm_test_damage_iter_single_damage_src_moved
[04:19:27] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[04:19:27] [PASSED] drm_test_damage_iter_damage
[04:19:27] [PASSED] drm_test_damage_iter_damage_one_intersect
[04:19:27] [PASSED] drm_test_damage_iter_damage_one_outside
[04:19:27] [PASSED] drm_test_damage_iter_damage_src_moved
[04:19:27] [PASSED] drm_test_damage_iter_damage_not_visible
[04:19:27] ================ [PASSED] drm_damage_helper ================
[04:19:27] ============== drm_dp_mst_helper (3 subtests) ==============
[04:19:27] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[04:19:27] [PASSED] Clock 154000 BPP 30 DSC disabled
[04:19:27] [PASSED] Clock 234000 BPP 30 DSC disabled
[04:19:27] [PASSED] Clock 297000 BPP 24 DSC disabled
[04:19:27] [PASSED] Clock 332880 BPP 24 DSC enabled
[04:19:27] [PASSED] Clock 324540 BPP 24 DSC enabled
[04:19:27] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[04:19:27] ============== drm_test_dp_mst_calc_pbn_div  ===============
[04:19:27] [PASSED] Link rate 2000000 lane count 4
[04:19:27] [PASSED] Link rate 2000000 lane count 2
[04:19:27] [PASSED] Link rate 2000000 lane count 1
[04:19:27] [PASSED] Link rate 1350000 lane count 4
[04:19:27] [PASSED] Link rate 1350000 lane count 2
[04:19:27] [PASSED] Link rate 1350000 lane count 1
[04:19:27] [PASSED] Link rate 1000000 lane count 4
[04:19:27] [PASSED] Link rate 1000000 lane count 2
[04:19:27] [PASSED] Link rate 1000000 lane count 1
[04:19:27] [PASSED] Link rate 810000 lane count 4
[04:19:27] [PASSED] Link rate 810000 lane count 2
[04:19:27] [PASSED] Link rate 810000 lane count 1
[04:19:27] [PASSED] Link rate 540000 lane count 4
[04:19:27] [PASSED] Link rate 540000 lane count 2
[04:19:27] [PASSED] Link rate 540000 lane count 1
[04:19:27] [PASSED] Link rate 270000 lane count 4
[04:19:27] [PASSED] Link rate 270000 lane count 2
[04:19:27] [PASSED] Link rate 270000 lane count 1
[04:19:27] [PASSED] Link rate 162000 lane count 4
[04:19:27] [PASSED] Link rate 162000 lane count 2
[04:19:27] [PASSED] Link rate 162000 lane count 1
[04:19:27] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[04:19:27] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[04:19:27] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[04:19:27] [PASSED] DP_POWER_UP_PHY with port number
[04:19:27] [PASSED] DP_POWER_DOWN_PHY with port number
[04:19:27] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[04:19:27] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[04:19:27] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[04:19:27] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[04:19:27] [PASSED] DP_QUERY_PAYLOAD with port number
[04:19:27] [PASSED] DP_QUERY_PAYLOAD with VCPI
[04:19:27] [PASSED] DP_REMOTE_DPCD_READ with port number
[04:19:27] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[04:19:27] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[04:19:27] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[04:19:27] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[04:19:27] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[04:19:27] [PASSED] DP_REMOTE_I2C_READ with port number
[04:19:27] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[04:19:27] [PASSED] DP_REMOTE_I2C_READ with transactions array
[04:19:27] [PASSED] DP_REMOTE_I2C_WRITE with port number
[04:19:27] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[04:19:27] [PASSED] DP_REMOTE_I2C_WRITE with data array
[04:19:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[04:19:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[04:19:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[04:19:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[04:19:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[04:19:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[04:19:27] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[04:19:27] ================ [PASSED] drm_dp_mst_helper ================
[04:19:27] ================== drm_exec (7 subtests) ===================
[04:19:27] [PASSED] sanitycheck
[04:19:27] [PASSED] test_lock
[04:19:27] [PASSED] test_lock_unlock
[04:19:27] [PASSED] test_duplicates
[04:19:27] [PASSED] test_prepare
[04:19:27] [PASSED] test_prepare_array
[04:19:27] [PASSED] test_multiple_loops
[04:19:27] ==================== [PASSED] drm_exec =====================
[04:19:27] =========== drm_format_helper_test (17 subtests) ===========
[04:19:27] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[04:19:27] [PASSED] single_pixel_source_buffer
[04:19:27] [PASSED] single_pixel_clip_rectangle
[04:19:27] [PASSED] well_known_colors
[04:19:27] [PASSED] destination_pitch
[04:19:27] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[04:19:27] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[04:19:27] [PASSED] single_pixel_source_buffer
[04:19:27] [PASSED] single_pixel_clip_rectangle
[04:19:27] [PASSED] well_known_colors
[04:19:27] [PASSED] destination_pitch
[04:19:27] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[04:19:27] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[04:19:27] [PASSED] single_pixel_source_buffer
[04:19:27] [PASSED] single_pixel_clip_rectangle
[04:19:27] [PASSED] well_known_colors
[04:19:27] [PASSED] destination_pitch
[04:19:27] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[04:19:27] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[04:19:27] [PASSED] single_pixel_source_buffer
[04:19:27] [PASSED] single_pixel_clip_rectangle
[04:19:27] [PASSED] well_known_colors
[04:19:27] [PASSED] destination_pitch
[04:19:27] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[04:19:27] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[04:19:27] [PASSED] single_pixel_source_buffer
[04:19:27] [PASSED] single_pixel_clip_rectangle
[04:19:27] [PASSED] well_known_colors
[04:19:27] [PASSED] destination_pitch
[04:19:27] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[04:19:27] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[04:19:27] [PASSED] single_pixel_source_buffer
[04:19:27] [PASSED] single_pixel_clip_rectangle
[04:19:27] [PASSED] well_known_colors
[04:19:27] [PASSED] destination_pitch
[04:19:27] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[04:19:27] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[04:19:27] [PASSED] single_pixel_source_buffer
[04:19:27] [PASSED] single_pixel_clip_rectangle
[04:19:27] [PASSED] well_known_colors
[04:19:27] [PASSED] destination_pitch
[04:19:27] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[04:19:27] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[04:19:27] [PASSED] single_pixel_source_buffer
[04:19:27] [PASSED] single_pixel_clip_rectangle
[04:19:27] [PASSED] well_known_colors
[04:19:27] [PASSED] destination_pitch
[04:19:27] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[04:19:27] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[04:19:27] [PASSED] single_pixel_source_buffer
[04:19:27] [PASSED] single_pixel_clip_rectangle
[04:19:27] [PASSED] well_known_colors
[04:19:27] [PASSED] destination_pitch
[04:19:27] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[04:19:27] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[04:19:27] [PASSED] single_pixel_source_buffer
[04:19:27] [PASSED] single_pixel_clip_rectangle
[04:19:27] [PASSED] well_known_colors
[04:19:27] [PASSED] destination_pitch
[04:19:27] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[04:19:27] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[04:19:27] [PASSED] single_pixel_source_buffer
[04:19:27] [PASSED] single_pixel_clip_rectangle
[04:19:27] [PASSED] well_known_colors
[04:19:27] [PASSED] destination_pitch
[04:19:27] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[04:19:27] ============== drm_test_fb_xrgb8888_to_mono  ===============
[04:19:27] [PASSED] single_pixel_source_buffer
[04:19:27] [PASSED] single_pixel_clip_rectangle
[04:19:27] [PASSED] well_known_colors
[04:19:27] [PASSED] destination_pitch
[04:19:27] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[04:19:27] ==================== drm_test_fb_swab  =====================
[04:19:27] [PASSED] single_pixel_source_buffer
[04:19:27] [PASSED] single_pixel_clip_rectangle
[04:19:27] [PASSED] well_known_colors
[04:19:27] [PASSED] destination_pitch
[04:19:27] ================ [PASSED] drm_test_fb_swab =================
[04:19:27] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[04:19:27] [PASSED] single_pixel_source_buffer
[04:19:27] [PASSED] single_pixel_clip_rectangle
[04:19:27] [PASSED] well_known_colors
[04:19:27] [PASSED] destination_pitch
[04:19:27] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[04:19:27] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[04:19:27] [PASSED] single_pixel_source_buffer
[04:19:27] [PASSED] single_pixel_clip_rectangle
[04:19:27] [PASSED] well_known_colors
[04:19:27] [PASSED] destination_pitch
[04:19:27] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[04:19:27] ================= drm_test_fb_clip_offset  =================
[04:19:27] [PASSED] pass through
[04:19:27] [PASSED] horizontal offset
[04:19:27] [PASSED] vertical offset
[04:19:27] [PASSED] horizontal and vertical offset
[04:19:27] [PASSED] horizontal offset (custom pitch)
[04:19:27] [PASSED] vertical offset (custom pitch)
[04:19:27] [PASSED] horizontal and vertical offset (custom pitch)
[04:19:27] ============= [PASSED] drm_test_fb_clip_offset =============
[04:19:27] =================== drm_test_fb_memcpy  ====================
[04:19:27] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[04:19:27] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[04:19:27] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[04:19:27] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[04:19:27] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[04:19:27] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[04:19:27] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[04:19:27] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[04:19:27] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[04:19:27] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[04:19:27] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[04:19:27] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[04:19:27] =============== [PASSED] drm_test_fb_memcpy ================
[04:19:27] ============= [PASSED] drm_format_helper_test ==============
[04:19:27] ================= drm_format (18 subtests) =================
[04:19:27] [PASSED] drm_test_format_block_width_invalid
[04:19:27] [PASSED] drm_test_format_block_width_one_plane
[04:19:27] [PASSED] drm_test_format_block_width_two_plane
[04:19:27] [PASSED] drm_test_format_block_width_three_plane
[04:19:27] [PASSED] drm_test_format_block_width_tiled
[04:19:27] [PASSED] drm_test_format_block_height_invalid
[04:19:27] [PASSED] drm_test_format_block_height_one_plane
[04:19:27] [PASSED] drm_test_format_block_height_two_plane
[04:19:27] [PASSED] drm_test_format_block_height_three_plane
[04:19:27] [PASSED] drm_test_format_block_height_tiled
[04:19:27] [PASSED] drm_test_format_min_pitch_invalid
[04:19:27] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[04:19:27] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[04:19:27] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[04:19:27] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[04:19:27] [PASSED] drm_test_format_min_pitch_two_plane
[04:19:27] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[04:19:27] [PASSED] drm_test_format_min_pitch_tiled
[04:19:27] =================== [PASSED] drm_format ====================
[04:19:27] ============== drm_framebuffer (10 subtests) ===============
[04:19:27] ========== drm_test_framebuffer_check_src_coords  ==========
[04:19:27] [PASSED] Success: source fits into fb
[04:19:27] [PASSED] Fail: overflowing fb with x-axis coordinate
[04:19:27] [PASSED] Fail: overflowing fb with y-axis coordinate
[04:19:27] [PASSED] Fail: overflowing fb with source width
[04:19:27] [PASSED] Fail: overflowing fb with source height
[04:19:27] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[04:19:27] [PASSED] drm_test_framebuffer_cleanup
[04:19:27] =============== drm_test_framebuffer_create  ===============
[04:19:27] [PASSED] ABGR8888 normal sizes
[04:19:27] [PASSED] ABGR8888 max sizes
[04:19:27] [PASSED] ABGR8888 pitch greater than min required
[04:19:27] [PASSED] ABGR8888 pitch less than min required
[04:19:27] [PASSED] ABGR8888 Invalid width
[04:19:27] [PASSED] ABGR8888 Invalid buffer handle
[04:19:27] [PASSED] No pixel format
[04:19:27] [PASSED] ABGR8888 Width 0
[04:19:27] [PASSED] ABGR8888 Height 0
[04:19:27] [PASSED] ABGR8888 Out of bound height * pitch combination
[04:19:27] [PASSED] ABGR8888 Large buffer offset
[04:19:27] [PASSED] ABGR8888 Buffer offset for inexistent plane
[04:19:27] [PASSED] ABGR8888 Invalid flag
[04:19:27] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[04:19:27] [PASSED] ABGR8888 Valid buffer modifier
[04:19:27] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[04:19:27] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[04:19:27] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[04:19:27] [PASSED] NV12 Normal sizes
[04:19:27] [PASSED] NV12 Max sizes
[04:19:27] [PASSED] NV12 Invalid pitch
[04:19:27] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[04:19:27] [PASSED] NV12 different  modifier per-plane
[04:19:27] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[04:19:27] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[04:19:27] [PASSED] NV12 Modifier for inexistent plane
[04:19:27] [PASSED] NV12 Handle for inexistent plane
[04:19:27] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[04:19:27] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[04:19:27] [PASSED] YVU420 Normal sizes
[04:19:27] [PASSED] YVU420 Max sizes
[04:19:27] [PASSED] YVU420 Invalid pitch
[04:19:27] [PASSED] YVU420 Different pitches
[04:19:27] [PASSED] YVU420 Different buffer offsets/pitches
[04:19:27] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[04:19:27] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[04:19:27] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[04:19:27] [PASSED] YVU420 Valid modifier
[04:19:27] [PASSED] YVU420 Different modifiers per plane
[04:19:27] [PASSED] YVU420 Modifier for inexistent plane
[04:19:27] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[04:19:27] [PASSED] X0L2 Normal sizes
[04:19:27] [PASSED] X0L2 Max sizes
[04:19:27] [PASSED] X0L2 Invalid pitch
[04:19:27] [PASSED] X0L2 Pitch greater than minimum required
[04:19:27] [PASSED] X0L2 Handle for inexistent plane
[04:19:27] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[04:19:27] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[04:19:27] [PASSED] X0L2 Valid modifier
[04:19:27] [PASSED] X0L2 Modifier for inexistent plane
[04:19:27] =========== [PASSED] drm_test_framebuffer_create ===========
[04:19:27] [PASSED] drm_test_framebuffer_free
[04:19:27] [PASSED] drm_test_framebuffer_init
[04:19:27] [PASSED] drm_test_framebuffer_init_bad_format
[04:19:27] [PASSED] drm_test_framebuffer_init_dev_mismatch
[04:19:27] [PASSED] drm_test_framebuffer_lookup
[04:19:27] [PASSED] drm_test_framebuffer_lookup_inexistent
[04:19:27] [PASSED] drm_test_framebuffer_modifiers_not_supported
[04:19:27] ================= [PASSED] drm_framebuffer =================
[04:19:27] ================ drm_gem_shmem (8 subtests) ================
[04:19:27] [PASSED] drm_gem_shmem_test_obj_create
[04:19:27] [PASSED] drm_gem_shmem_test_obj_create_private
[04:19:27] [PASSED] drm_gem_shmem_test_pin_pages
[04:19:27] [PASSED] drm_gem_shmem_test_vmap
[04:19:27] [PASSED] drm_gem_shmem_test_get_sg_table
[04:19:27] [PASSED] drm_gem_shmem_test_get_pages_sgt
[04:19:27] [PASSED] drm_gem_shmem_test_madvise
[04:19:27] [PASSED] drm_gem_shmem_test_purge
[04:19:27] ================== [PASSED] drm_gem_shmem ==================
[04:19:27] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[04:19:27] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[04:19:27] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[04:19:27] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[04:19:27] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[04:19:27] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[04:19:27] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[04:19:27] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[04:19:27] [PASSED] Automatic
[04:19:27] [PASSED] Full
[04:19:27] [PASSED] Limited 16:235
[04:19:27] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[04:19:27] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[04:19:27] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[04:19:27] [PASSED] drm_test_check_disable_connector
[04:19:27] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[04:19:27] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[04:19:27] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[04:19:27] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[04:19:27] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[04:19:27] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[04:19:27] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[04:19:27] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[04:19:27] [PASSED] drm_test_check_output_bpc_dvi
[04:19:27] [PASSED] drm_test_check_output_bpc_format_vic_1
[04:19:27] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[04:19:27] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[04:19:27] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[04:19:27] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[04:19:27] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[04:19:27] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[04:19:27] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[04:19:27] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[04:19:27] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[04:19:27] [PASSED] drm_test_check_broadcast_rgb_value
[04:19:27] [PASSED] drm_test_check_bpc_8_value
[04:19:27] [PASSED] drm_test_check_bpc_10_value
[04:19:27] [PASSED] drm_test_check_bpc_12_value
[04:19:27] [PASSED] drm_test_check_format_value
[04:19:27] [PASSED] drm_test_check_tmds_char_value
[04:19:27] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[04:19:27] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[04:19:27] [PASSED] drm_test_check_mode_valid
[04:19:27] [PASSED] drm_test_check_mode_valid_reject
[04:19:27] [PASSED] drm_test_check_mode_valid_reject_rate
[04:19:27] [PASSED] drm_test_check_mode_valid_reject_max_clock
[04:19:27] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[04:19:27] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[04:19:27] [PASSED] drm_test_check_infoframes
[04:19:27] [PASSED] drm_test_check_reject_avi_infoframe
[04:19:27] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[04:19:27] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[04:19:27] [PASSED] drm_test_check_reject_audio_infoframe
[04:19:27] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[04:19:27] ================= drm_managed (2 subtests) =================
[04:19:27] [PASSED] drm_test_managed_release_action
[04:19:27] [PASSED] drm_test_managed_run_action
[04:19:27] =================== [PASSED] drm_managed ===================
[04:19:27] =================== drm_mm (6 subtests) ====================
[04:19:27] [PASSED] drm_test_mm_init
[04:19:27] [PASSED] drm_test_mm_debug
[04:19:27] [PASSED] drm_test_mm_align32
[04:19:27] [PASSED] drm_test_mm_align64
[04:19:27] [PASSED] drm_test_mm_lowest
[04:19:27] [PASSED] drm_test_mm_highest
[04:19:27] ===================== [PASSED] drm_mm ======================
[04:19:27] ============= drm_modes_analog_tv (5 subtests) =============
[04:19:27] [PASSED] drm_test_modes_analog_tv_mono_576i
[04:19:27] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[04:19:27] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[04:19:27] [PASSED] drm_test_modes_analog_tv_pal_576i
[04:19:27] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[04:19:27] =============== [PASSED] drm_modes_analog_tv ===============
[04:19:27] ============== drm_plane_helper (2 subtests) ===============
[04:19:27] =============== drm_test_check_plane_state  ================
[04:19:27] [PASSED] clipping_simple
[04:19:27] [PASSED] clipping_rotate_reflect
[04:19:27] [PASSED] positioning_simple
[04:19:27] [PASSED] upscaling
[04:19:27] [PASSED] downscaling
[04:19:27] [PASSED] rounding1
[04:19:27] [PASSED] rounding2
[04:19:27] [PASSED] rounding3
[04:19:27] [PASSED] rounding4
[04:19:27] =========== [PASSED] drm_test_check_plane_state ============
[04:19:27] =========== drm_test_check_invalid_plane_state  ============
[04:19:27] [PASSED] positioning_invalid
[04:19:27] [PASSED] upscaling_invalid
[04:19:27] [PASSED] downscaling_invalid
[04:19:27] ======= [PASSED] drm_test_check_invalid_plane_state ========
[04:19:27] ================ [PASSED] drm_plane_helper =================
[04:19:27] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[04:19:27] ====== drm_test_connector_helper_tv_get_modes_check  =======
[04:19:27] [PASSED] None
[04:19:27] [PASSED] PAL
[04:19:27] [PASSED] NTSC
[04:19:27] [PASSED] Both, NTSC Default
[04:19:27] [PASSED] Both, PAL Default
[04:19:27] [PASSED] Both, NTSC Default, with PAL on command-line
[04:19:27] [PASSED] Both, PAL Default, with NTSC on command-line
[04:19:27] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[04:19:27] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[04:19:27] ================== drm_rect (9 subtests) ===================
[04:19:27] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[04:19:27] [PASSED] drm_test_rect_clip_scaled_not_clipped
[04:19:27] [PASSED] drm_test_rect_clip_scaled_clipped
[04:19:27] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[04:19:27] ================= drm_test_rect_intersect  =================
[04:19:27] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[04:19:27] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[04:19:27] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[04:19:27] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[04:19:27] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[04:19:27] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[04:19:27] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[04:19:27] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[04:19:27] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[04:19:27] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[04:19:27] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[04:19:27] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[04:19:27] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[04:19:27] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[04:19:27] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[04:19:27] ============= [PASSED] drm_test_rect_intersect =============
[04:19:27] ================ drm_test_rect_calc_hscale  ================
[04:19:27] [PASSED] normal use
[04:19:27] [PASSED] out of max range
[04:19:27] [PASSED] out of min range
[04:19:27] [PASSED] zero dst
[04:19:27] [PASSED] negative src
[04:19:27] [PASSED] negative dst
[04:19:27] ============ [PASSED] drm_test_rect_calc_hscale ============
[04:19:27] ================ drm_test_rect_calc_vscale  ================
[04:19:27] [PASSED] normal use
[04:19:27] [PASSED] out of max range
[04:19:27] [PASSED] out of min range
[04:19:27] [PASSED] zero dst
[04:19:27] [PASSED] negative src
[04:19:27] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[04:19:27] ============ [PASSED] drm_test_rect_calc_vscale ============
[04:19:27] ================== drm_test_rect_rotate  ===================
[04:19:27] [PASSED] reflect-x
[04:19:27] [PASSED] reflect-y
[04:19:27] [PASSED] rotate-0
[04:19:27] [PASSED] rotate-90
[04:19:27] [PASSED] rotate-180
[04:19:27] [PASSED] rotate-270
[04:19:27] ============== [PASSED] drm_test_rect_rotate ===============
[04:19:27] ================ drm_test_rect_rotate_inv  =================
[04:19:27] [PASSED] reflect-x
[04:19:27] [PASSED] reflect-y
[04:19:27] [PASSED] rotate-0
[04:19:27] [PASSED] rotate-90
[04:19:27] [PASSED] rotate-180
[04:19:27] [PASSED] rotate-270
[04:19:27] ============ [PASSED] drm_test_rect_rotate_inv =============
[04:19:27] ==================== [PASSED] drm_rect =====================
[04:19:27] ============ drm_sysfb_modeset_test (1 subtest) ============
[04:19:27] ============ drm_test_sysfb_build_fourcc_list  =============
[04:19:27] [PASSED] no native formats
[04:19:27] [PASSED] XRGB8888 as native format
[04:19:27] [PASSED] remove duplicates
[04:19:27] [PASSED] convert alpha formats
[04:19:27] [PASSED] random formats
[04:19:27] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[04:19:27] ============= [PASSED] drm_sysfb_modeset_test ==============
[04:19:27] ================== drm_fixp (2 subtests) ===================
[04:19:27] [PASSED] drm_test_int2fixp
[04:19:27] [PASSED] drm_test_sm2fixp
[04:19:27] ==================== [PASSED] drm_fixp =====================
[04:19:27] ============================================================
[04:19:27] Testing complete. Ran 621 tests: passed: 621
[04:19:27] Elapsed time: 26.144s total, 1.709s configuring, 24.269s building, 0.113s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[04:19:27] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:19:28] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:19:38] Starting KUnit Kernel (1/1)...
[04:19:38] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:19:38] ================= ttm_device (5 subtests) ==================
[04:19:38] [PASSED] ttm_device_init_basic
[04:19:38] [PASSED] ttm_device_init_multiple
[04:19:38] [PASSED] ttm_device_fini_basic
[04:19:38] [PASSED] ttm_device_init_no_vma_man
[04:19:38] ================== ttm_device_init_pools  ==================
[04:19:38] [PASSED] No DMA allocations, no DMA32 required
[04:19:38] [PASSED] DMA allocations, DMA32 required
[04:19:38] [PASSED] No DMA allocations, DMA32 required
[04:19:38] [PASSED] DMA allocations, no DMA32 required
[04:19:38] ============== [PASSED] ttm_device_init_pools ==============
[04:19:38] =================== [PASSED] ttm_device ====================
[04:19:38] ================== ttm_pool (8 subtests) ===================
[04:19:38] ================== ttm_pool_alloc_basic  ===================
[04:19:38] [PASSED] One page
[04:19:38] [PASSED] More than one page
[04:19:38] [PASSED] Above the allocation limit
[04:19:38] [PASSED] One page, with coherent DMA mappings enabled
[04:19:38] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[04:19:38] ============== [PASSED] ttm_pool_alloc_basic ===============
[04:19:38] ============== ttm_pool_alloc_basic_dma_addr  ==============
[04:19:38] [PASSED] One page
[04:19:38] [PASSED] More than one page
[04:19:38] [PASSED] Above the allocation limit
[04:19:38] [PASSED] One page, with coherent DMA mappings enabled
[04:19:38] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[04:19:38] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[04:19:38] [PASSED] ttm_pool_alloc_order_caching_match
[04:19:38] [PASSED] ttm_pool_alloc_caching_mismatch
[04:19:38] [PASSED] ttm_pool_alloc_order_mismatch
[04:19:38] [PASSED] ttm_pool_free_dma_alloc
[04:19:38] [PASSED] ttm_pool_free_no_dma_alloc
[04:19:38] [PASSED] ttm_pool_fini_basic
[04:19:38] ==================== [PASSED] ttm_pool =====================
[04:19:38] ================ ttm_resource (8 subtests) =================
[04:19:38] ================= ttm_resource_init_basic  =================
[04:19:38] [PASSED] Init resource in TTM_PL_SYSTEM
[04:19:38] [PASSED] Init resource in TTM_PL_VRAM
[04:19:38] [PASSED] Init resource in a private placement
[04:19:38] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[04:19:38] ============= [PASSED] ttm_resource_init_basic =============
[04:19:38] [PASSED] ttm_resource_init_pinned
[04:19:38] [PASSED] ttm_resource_fini_basic
[04:19:38] [PASSED] ttm_resource_manager_init_basic
[04:19:38] [PASSED] ttm_resource_manager_usage_basic
[04:19:38] [PASSED] ttm_resource_manager_set_used_basic
[04:19:38] [PASSED] ttm_sys_man_alloc_basic
[04:19:38] [PASSED] ttm_sys_man_free_basic
[04:19:38] ================== [PASSED] ttm_resource ===================
[04:19:38] =================== ttm_tt (15 subtests) ===================
[04:19:38] ==================== ttm_tt_init_basic  ====================
[04:19:38] [PASSED] Page-aligned size
[04:19:38] [PASSED] Extra pages requested
[04:19:38] ================ [PASSED] ttm_tt_init_basic ================
[04:19:38] [PASSED] ttm_tt_init_misaligned
[04:19:38] [PASSED] ttm_tt_fini_basic
[04:19:38] [PASSED] ttm_tt_fini_sg
[04:19:38] [PASSED] ttm_tt_fini_shmem
[04:19:38] [PASSED] ttm_tt_create_basic
[04:19:38] [PASSED] ttm_tt_create_invalid_bo_type
[04:19:38] [PASSED] ttm_tt_create_ttm_exists
[04:19:38] [PASSED] ttm_tt_create_failed
[04:19:38] [PASSED] ttm_tt_destroy_basic
[04:19:38] [PASSED] ttm_tt_populate_null_ttm
[04:19:38] [PASSED] ttm_tt_populate_populated_ttm
[04:19:38] [PASSED] ttm_tt_unpopulate_basic
[04:19:38] [PASSED] ttm_tt_unpopulate_empty_ttm
[04:19:38] [PASSED] ttm_tt_swapin_basic
[04:19:38] ===================== [PASSED] ttm_tt ======================
[04:19:38] =================== ttm_bo (14 subtests) ===================
[04:19:38] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[04:19:38] [PASSED] Cannot be interrupted and sleeps
[04:19:38] [PASSED] Cannot be interrupted, locks straight away
[04:19:38] [PASSED] Can be interrupted, sleeps
[04:19:38] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[04:19:38] [PASSED] ttm_bo_reserve_locked_no_sleep
[04:19:38] [PASSED] ttm_bo_reserve_no_wait_ticket
[04:19:38] [PASSED] ttm_bo_reserve_double_resv
[04:19:38] [PASSED] ttm_bo_reserve_interrupted
[04:19:38] [PASSED] ttm_bo_reserve_deadlock
[04:19:38] [PASSED] ttm_bo_unreserve_basic
[04:19:38] [PASSED] ttm_bo_unreserve_pinned
[04:19:38] [PASSED] ttm_bo_unreserve_bulk
[04:19:38] [PASSED] ttm_bo_fini_basic
[04:19:38] [PASSED] ttm_bo_fini_shared_resv
[04:19:38] [PASSED] ttm_bo_pin_basic
[04:19:38] [PASSED] ttm_bo_pin_unpin_resource
[04:19:38] [PASSED] ttm_bo_multiple_pin_one_unpin
[04:19:38] ===================== [PASSED] ttm_bo ======================
[04:19:38] ============== ttm_bo_validate (22 subtests) ===============
[04:19:38] ============== ttm_bo_init_reserved_sys_man  ===============
[04:19:38] [PASSED] Buffer object for userspace
[04:19:38] [PASSED] Kernel buffer object
[04:19:38] [PASSED] Shared buffer object
[04:19:38] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[04:19:38] ============== ttm_bo_init_reserved_mock_man  ==============
[04:19:38] [PASSED] Buffer object for userspace
[04:19:38] [PASSED] Kernel buffer object
[04:19:38] [PASSED] Shared buffer object
[04:19:38] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[04:19:38] [PASSED] ttm_bo_init_reserved_resv
[04:19:38] ================== ttm_bo_validate_basic  ==================
[04:19:38] [PASSED] Buffer object for userspace
[04:19:38] [PASSED] Kernel buffer object
[04:19:38] [PASSED] Shared buffer object
[04:19:38] ============== [PASSED] ttm_bo_validate_basic ==============
[04:19:38] [PASSED] ttm_bo_validate_invalid_placement
[04:19:38] ============= ttm_bo_validate_same_placement  ==============
[04:19:38] [PASSED] System manager
[04:19:38] [PASSED] VRAM manager
[04:19:38] ========= [PASSED] ttm_bo_validate_same_placement ==========
[04:19:38] [PASSED] ttm_bo_validate_failed_alloc
[04:19:38] [PASSED] ttm_bo_validate_pinned
[04:19:38] [PASSED] ttm_bo_validate_busy_placement
[04:19:38] ================ ttm_bo_validate_multihop  =================
[04:19:38] [PASSED] Buffer object for userspace
[04:19:38] [PASSED] Kernel buffer object
[04:19:38] [PASSED] Shared buffer object
[04:19:38] ============ [PASSED] ttm_bo_validate_multihop =============
[04:19:38] ========== ttm_bo_validate_no_placement_signaled  ==========
[04:19:38] [PASSED] Buffer object in system domain, no page vector
[04:19:38] [PASSED] Buffer object in system domain with an existing page vector
[04:19:38] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[04:19:38] ======== ttm_bo_validate_no_placement_not_signaled  ========
[04:19:38] [PASSED] Buffer object for userspace
[04:19:38] [PASSED] Kernel buffer object
[04:19:38] [PASSED] Shared buffer object
[04:19:38] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[04:19:38] [PASSED] ttm_bo_validate_move_fence_signaled
[04:19:38] ========= ttm_bo_validate_move_fence_not_signaled  =========
[04:19:38] [PASSED] Waits for GPU
[04:19:38] [PASSED] Tries to lock straight away
[04:19:38] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[04:19:38] [PASSED] ttm_bo_validate_swapout
[04:19:38] [PASSED] ttm_bo_validate_happy_evict
[04:19:38] [PASSED] ttm_bo_validate_all_pinned_evict
[04:19:38] [PASSED] ttm_bo_validate_allowed_only_evict
[04:19:38] [PASSED] ttm_bo_validate_deleted_evict
[04:19:38] [PASSED] ttm_bo_validate_busy_domain_evict
[04:19:38] [PASSED] ttm_bo_validate_evict_gutting
[04:19:38] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[04:19:38] ================= [PASSED] ttm_bo_validate =================
[04:19:38] ============================================================
[04:19:38] Testing complete. Ran 102 tests: passed: 102
[04:19:38] Elapsed time: 11.281s total, 1.640s configuring, 9.424s building, 0.183s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Add support for Common SDP Transmission Line (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1509 bytes --]

== Series Details ==

Series: Add support for Common SDP Transmission Line (rev2)
URL   : https://patchwork.freedesktop.org/series/162623/
State : success

== Summary ==

CI Bug Log - changes from xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb_BAT -> xe-pw-162623v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 14)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-162623v2_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_waitfence@abstime:
    - bat-dg2-oem2:       [PASS][1] -> [TIMEOUT][2] ([Intel XE#6506])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/bat-dg2-oem2/igt@xe_waitfence@abstime.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/bat-dg2-oem2/igt@xe_waitfence@abstime.html

  
  [Intel XE#6506]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6506


Build changes
-------------

  * Linux: xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb -> xe-pw-162623v2

  IGT_8854: 93abaf0170728f69bc27577e5b405f7a2a01b6fd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb: afe01cbdd453cb1b141b29ea6153f64ef0f151fb
  xe-pw-162623v2: 162623v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/index.html

[-- Attachment #2: Type: text/html, Size: 2074 bytes --]

✗ Xe.CI.FULL: failure for Add support for Common SDP Transmission Line (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 34471 bytes --]

== Series Details ==

Series: Add support for Common SDP Transmission Line (rev2)
URL   : https://patchwork.freedesktop.org/series/162623/
State : failure

== Summary ==

CI Bug Log - changes from xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb_FULL -> xe-pw-162623v2_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-162623v2_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-162623v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-162623v2_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_fault_injection@vm-create-fail-xe_vm_create_scratch:
    - shard-lnl:          [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-lnl-8/igt@xe_fault_injection@vm-create-fail-xe_vm_create_scratch.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-lnl-4/igt@xe_fault_injection@vm-create-fail-xe_vm_create_scratch.html

  
Known issues
------------

  Here are the changes found in xe-pw-162623v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@linear-16bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#2327])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@kms_big_fb@linear-16bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#1124]) +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-9/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180.html

  * igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#7679]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-9/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#367] / [Intel XE#7354])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-d-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2652]) +8 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2887]) +3 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs.html

  * igt@kms_chamelium_hpd@dp-hpd-after-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2252]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-9/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html

  * igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][10] ([Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-offscreen-256x85:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#2320]) +2 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-9/igt@kms_cursor_crc@cursor-offscreen-256x85.html

  * igt@kms_cursor_crc@cursor-onscreen-128x42:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#1424])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-lnl-8/igt@kms_cursor_crc@cursor-onscreen-128x42.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#1340] / [Intel XE#7435])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3.html

  * igt@kms_feature_discovery@display-3x:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2373] / [Intel XE#7448])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-9/igt@kms_feature_discovery@display-3x.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#7178] / [Intel XE#7351])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#7179])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-9/igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2311]) +9 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen.html
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#6312] / [Intel XE#651])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-lnl-8/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#4141]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
    - shard-lnl:          NOTRUN -> [SKIP][20] ([Intel XE#656]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-lnl-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2313]) +9 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-argb161616f-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#7061] / [Intel XE#7356]) +3 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-9/igt@kms_frontbuffer_tracking@psr-argb161616f-draw-mmap-wc.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#6911] / [Intel XE#7378])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-9/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#7283]) +2 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping.html
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#7283])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-lnl-8/igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#3309] / [Intel XE#7368])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#1489]) +2 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-9/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr@psr2-sprite-blt:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@kms_psr@psr2-sprite-blt.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#1127] / [Intel XE#5813])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-lnl-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#2330] / [Intel XE#5813])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@sprite-rotation-270:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#3904] / [Intel XE#7342])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@kms_rotation_crc@sprite-rotation-270.html

  * igt@kms_sharpness_filter@filter-scaler-upscale:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#6503])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-9/igt@kms_sharpness_filter@filter-scaler-upscale.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#1499])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@xe_eudebug@basic-vm-access-parameters-faultable:
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#7636])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-lnl-8/igt@xe_eudebug@basic-vm-access-parameters-faultable.html

  * igt@xe_eudebug_online@set-breakpoint-faultable:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#7636]) +4 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@xe_eudebug_online@set-breakpoint-faultable.html

  * igt@xe_evict@evict-beng-large-cm:
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#6540] / [Intel XE#688])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-lnl-8/igt@xe_evict@evict-beng-large-cm.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [PASS][37] -> [INCOMPLETE][38] ([Intel XE#6321])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-2/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-5/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_evict@evict-small-external-multi-queue-cm:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#7140])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-9/igt@xe_evict@evict-small-external-multi-queue-cm.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#2322] / [Intel XE#7372]) +2 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-9/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap.html

  * igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-race-imm:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#7136]) +6 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-race-imm.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-imm:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#7136]) +1 other test skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-lnl-8/igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-imm.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#6874]) +5 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@xe_exec_multi_queue@few-execs-preempt-mode-userptr-invalidate.html

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-close-fd-smem:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#6874])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-lnl-8/igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-close-fd-smem.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-shared-remap:
    - shard-bmg:          [PASS][45] -> [DMESG-WARN][46] ([Intel XE#7725]) +3 other tests dmesg-warn
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-3/igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-shared-remap.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-6/igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-shared-remap.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#7138]) +4 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-userptr-rebind.html

  * igt@xe_prefetch_fault@prefetch-fault-svm:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#7599])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-9/igt@xe_prefetch_fault@prefetch-fault-svm.html

  * igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#4733] / [Intel XE#7417])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy.html

  * igt@xe_sriov_auto_provisioning@exclusive-ranges:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#4130] / [Intel XE#7366])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-lnl-8/igt@xe_sriov_auto_provisioning@exclusive-ranges.html

  * igt@xe_wedged@wedged-at-any-timeout:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][51] ([Intel XE#5545])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@xe_wedged@wedged-at-any-timeout.html

  
#### Possible fixes ####

  * igt@kms_atomic@crtc-invalid-params-fence@pipe-a-dp-2:
    - shard-bmg:          [DMESG-WARN][52] ([Intel XE#7725]) -> [PASS][53] +11 other tests pass
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@kms_atomic@crtc-invalid-params-fence@pipe-a-dp-2.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-3/igt@kms_atomic@crtc-invalid-params-fence@pipe-a-dp-2.html

  * igt@kms_color@deep-color:
    - shard-bmg:          [SKIP][54] -> [PASS][55]
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@kms_color@deep-color.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-3/igt@kms_color@deep-color.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
    - shard-bmg:          [SKIP][56] ([Intel XE#2291] / [Intel XE#7343]) -> [PASS][57]
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-3/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-bmg:          [DMESG-WARN][58] -> [PASS][59] +7 other tests pass
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@kms_flip@2x-blocking-wf_vblank.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-3/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][60] ([Intel XE#1503]) -> [PASS][61]
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@kms_hdr@invalid-hdr.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-3/igt@kms_hdr@invalid-hdr.html

  * igt@kms_universal_plane@universal-plane-functional@pipe-b-hdmi-a-3:
    - shard-bmg:          [FAIL][62] -> [PASS][63] +2 other tests pass
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-2/igt@kms_universal_plane@universal-plane-functional@pipe-b-hdmi-a-3.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-9/igt@kms_universal_plane@universal-plane-functional@pipe-b-hdmi-a-3.html

  * igt@kms_universal_plane@universal-plane-functional@pipe-c-dp-2:
    - shard-bmg:          [ABORT][64] ([Intel XE#5545] / [Intel XE#6652] / [Intel XE#7200]) -> [PASS][65] +1 other test pass
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-2/igt@kms_universal_plane@universal-plane-functional@pipe-c-dp-2.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-9/igt@kms_universal_plane@universal-plane-functional@pipe-c-dp-2.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma:
    - shard-lnl:          [FAIL][66] ([Intel XE#5625]) -> [PASS][67] +1 other test pass
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-lnl-3/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-lnl-8/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_pcode_probe_early:
    - shard-bmg:          [ABORT][68] ([Intel XE#7578]) -> [PASS][69]
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-1/igt@xe_fault_injection@inject-fault-probe-function-xe_pcode_probe_early.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@xe_fault_injection@inject-fault-probe-function-xe_pcode_probe_early.html

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-move:
    - shard-bmg:          [SKIP][70] ([Intel XE#2311]) -> [SKIP][71] ([Intel XE#2312])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-move.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][72] ([Intel XE#4141]) -> [SKIP][73] ([Intel XE#2312])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][74] ([Intel XE#2312]) -> [SKIP][75] ([Intel XE#4141])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt:
    - shard-bmg:          [SKIP][76] ([Intel XE#2312]) -> [SKIP][77] ([Intel XE#2311])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-move:
    - shard-bmg:          [SKIP][78] ([Intel XE#2312]) -> [SKIP][79] ([Intel XE#2313])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-move.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-move.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][80] ([Intel XE#3544]) -> [SKIP][81] ([Intel XE#3374] / [Intel XE#3544])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-10/igt@kms_hdr@brightness-with-hdr.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-7/igt@kms_hdr@brightness-with-hdr.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [SKIP][107]) ([Intel XE#2457] / [Intel XE#7405]) -> ([DMESG-WARN][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [DMESG-WARN][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132]) ([Intel XE#7725])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-2/igt@xe_module_load@load.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-1/igt@xe_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-10/igt@xe_module_load@load.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-5/igt@xe_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-2/igt@xe_module_load@load.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-9/igt@xe_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-9/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-8/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-10/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-7/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-10/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-5/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-5/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-9/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-3/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-3/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-3/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-8/igt@xe_module_load@load.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-8/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-7/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-7/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-2/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-1/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-3/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-6/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-7/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-7/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-8/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-10/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-1/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-8/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-2/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-10/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-9/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-9/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-9/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-5/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-5/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-5/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-8/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-6/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-6/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-6/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-2/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-2/igt@xe_module_load@load.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-3/igt@xe_module_load@load.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/shard-bmg-3/igt@xe_module_load@load.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7140
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7200]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7200
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7354
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7366
  [Intel XE#7368]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7368
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7378
  [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7435
  [Intel XE#7448]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7448
  [Intel XE#7578]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7578
  [Intel XE#7599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7599
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7725]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7725


Build changes
-------------

  * Linux: xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb -> xe-pw-162623v2

  IGT_8854: 93abaf0170728f69bc27577e5b405f7a2a01b6fd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb: afe01cbdd453cb1b141b29ea6153f64ef0f151fb
  xe-pw-162623v2: 162623v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162623v2/index.html

[-- Attachment #2: Type: text/html, Size: 37858 bytes --]

Re: [PATCH 01/12] drm/i915/vrr: Add HAS_EMP_AS_SDP_TL macro

[Jani Nikula]

On Mon, 13 Apr 2026, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
> double buffering point and transmission line for VRR packets for
> HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.

Okay, EMP AS SDP TL is where I draw the line. I don't understand this
acronym soup anymore. HAS_EMP_AS_SDL_TL() is meaningless to me.

The idea with the HAS_*() helpers is to make the code more *readable*.

The absolute minimum is to explain what these acronyms mean in commit
messages or comments, but you could just make the HAS_*() macro more
readable on its own.

I'm also not convinced we need to put all the HAS_*() macros in
intel_display_device.h when we could place some of them inside the
single .c file that uses them.


BR,
Jani.


>
> Add a macro for this and use it in intel_vrr.c
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
>  drivers/gpu/drm/i915/display/intel_vrr.c            | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 1170ac346615..9338ea087e92 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -173,6 +173,7 @@ struct intel_display_platforms {
>  #define HAS_DSC(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_dsc)
>  #define HAS_DSC_3ENGINES(__display)	(DISPLAY_VERx100(__display) == 1401 && HAS_DSC(__display))
>  #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
> +#define HAS_EMP_AS_SDP_TL(__display)	(DISPLAY_VERx100(__display) == 1401 || DISPLAY_VER(__display) >= 20)
>  #define HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
>  #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >= 30)
>  #define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx)
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index fae1186a90b2..1fed597439b0 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -656,7 +656,7 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>  	 * Since currently we support VRR only for DP/eDP, so this is programmed
>  	 * to for Adaptive Sync SDP to Vsync start.
>  	 */
> -	if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
> +	if (HAS_EMP_AS_SDP_TL(display))
>  		intel_de_write(display,
>  			       EMP_AS_SDP_TL(display, cpu_transcoder),
>  			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));

-- 
Jani Nikula, Intel

Re: [PATCH 02/12] drm/i915/vrr: Add helper to readback EMP_AS_SDP_TL

[Jani Nikula]

On Mon, 13 Apr 2026, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> EMP_AS_SDP_TL is used to program both DP Adaptive Sync SDP and HDMI
> Video Timing EMP for VRR operation. Add a helper to read back the
> programmed transmission line from hardware so VRR code can populate
> the corresponding CRTC state fields during get_config.
>
> This provides a common read-back path for VRR packet transmission
> line state.

Still no idea what "emp" means.

>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 13 +++++++++++++
>  drivers/gpu/drm/i915/display/intel_vrr.h |  1 +
>  2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 1fed597439b0..abdae7f1f8a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -1218,3 +1218,16 @@ int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_st
>  
>  	return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
>  }
> +
> +u16 intel_vrr_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 val;
> +
> +	if (!HAS_EMP_AS_SDP_TL(display))
> +		return 0;
> +
> +	val = intel_de_read(display, EMP_AS_SDP_TL(display, cpu_transcoder));
> +	return REG_FIELD_GET(EMP_AS_SDP_DB_TL_MASK, val);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 4f16ca4af91f..6659a8a53432 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -53,5 +53,6 @@ int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_sta
>  int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state);
>  int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
>  int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
> +u16 intel_vrr_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
>  
>  #endif /* __INTEL_VRR_H__ */

-- 
Jani Nikula, Intel

Re: [PATCH 04/12] drm/i915/dp: Add helper to get AS SDP Transmission Line

[Jani Nikula]

On Mon, 13 Apr 2026, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> Introduce a DP helper to compute the Adaptive Sync SDP transmission line
> and use it when programming the EMP_AS_SDP_TL register.
>
> Currently the AS SDP transmission line is programmed to the T1 position.
> This can be extended in the future to support programming the T2 position
> as well.
>
> While at it, improve the documentation: the AS SDP transmission line
> corresponds to the T1 position, which maps to the start of the VSYNC
> pulse.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c  | 12 ++++++++++++
>  drivers/gpu/drm/i915/display/intel_dp.h  |  2 ++
>  drivers/gpu/drm/i915/display/intel_vrr.c |  4 ++--
>  3 files changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4955bd8b11d7..fd668babd641 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -7415,3 +7415,15 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>  
>  	return true;
>  }
> +
> +int intel_dp_sdp_as_tl(const struct intel_crtc_state *crtc_state)

So the name of the function is Intel display port secondary data packet
adaptive sync transmission line.

The function name doesn't say what the function *does*.

> +{
> +	/*
> +	 * EMP_AS_SDP_TL defines the T1 position as the default AS SDP
> +	 * Transmission Line, which corresponds to the start of the
> +	 * VSYNC pulse.
> +	 *
> +	 * Use the T1 position for now.
> +	 */
> +	return crtc_state->vrr.vsync_start;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 2849b9ecdc71..7024fd0ace0a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -238,4 +238,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>  	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
>  		for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
>  
> +int intel_dp_sdp_as_tl(const struct intel_crtc_state *crtc_state);
> +
>  #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 5164d8c354e0..b700da4e9256 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -607,11 +607,11 @@ void intel_vrr_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
>  
>  	/*
>  	 * Since currently we support VRR only for DP/eDP, so this is programmed
> -	 * only for Adaptive Sync SDP to Vsync start.
> +	 * only for Adaptive Sync SDP.
>  	 */
>  	intel_de_write(display,
>  		       EMP_AS_SDP_TL(display, cpu_transcoder),
> -		       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
> +		       EMP_AS_SDP_DB_TL(intel_dp_sdp_as_tl(crtc_state)));
>  }
>  
>  void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)

-- 
Jani Nikula, Intel

Re: [PATCH 05/12] drm/i915/dp: Add crtc state for AS SDP transmission line

[Jani Nikula]

On Mon, 13 Apr 2026, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> The Adaptive Sync SDP is currently the only DisplayPort SDP with a
> programmable transmission line. Store the AS SDP transmission line
> in the crtc state and include it in the pipe configuration comparison.
>
> This provides a common place for SDP transmission lines and paves the way
> for supporting additional SDP TL programming, including the common base
> SDP transmission line introduced with Xe3p_lpd.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c       | 2 ++
>  drivers/gpu/drm/i915/display/intel_display_types.h | 8 ++++++++
>  2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 10b6c6fcb03f..c66541f26a09 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5434,6 +5434,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	}
>  	PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
>  
> +	PIPE_CONF_CHECK_I(dp_sdp_tl.as);
> +

Too short, too many acronyms.

>  	PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
>  	PIPE_CONF_CHECK_I(master_transcoder);
>  	PIPE_CONF_CHECK_X(joiner_pipes);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e2496db1642a..f58454c23859 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1298,6 +1298,14 @@ struct intel_crtc_state {
>  		struct drm_dp_as_sdp as_sdp;
>  	} infoframes;
>  
> +	struct {
> +		/*
> +		 * SDP Transmission line, relative to the Vtotal.
> +		 * The programmed transmit line is (Vtotal - value)
> +		 */
> +		u16 as;
> +	} dp_sdp_tl;

Why would this deserve to be a top level sub-struct in the crtc state?

> +
>  	u8 eld[MAX_ELD_BYTES];
>  
>  	/* HDMI scrambling status */

-- 
Jani Nikula, Intel

Re: [PATCH 08/12] drm/i915/display: Add HAS_CMN_SDP_TL macro

[Jani Nikula]

On Mon, 13 Apr 2026, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> Add a helper macro to detect CMN SDP TL support on platforms with display
> version 35 and above.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 9338ea087e92..36a8a956f54a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -154,6 +154,7 @@ struct intel_display_platforms {
>  #define HAS_CASF(__display)		(DISPLAY_VER(__display) >= 20)
>  #define HAS_CDCLK_CRAWL(__display)	(DISPLAY_INFO(__display)->has_cdclk_crawl)
>  #define HAS_CDCLK_SQUASH(__display)	(DISPLAY_INFO(__display)->has_cdclk_squash)
> +#define HAS_CMN_SDP_TL(__display)	(DISPLAY_VER(__display) >= 35)

Even if the register is called CMN, we can actually use the word COMMON
here.

>  #define HAS_CMRR(__display)		(DISPLAY_VER(__display) >= 20)
>  #define HAS_CMTG(__display)		(!(__display)->platform.dg2 && DISPLAY_VER(__display) >= 13)
>  #define HAS_CUR_FBC(__display)		(!HAS_GMCH(__display) && IS_DISPLAY_VER(__display, 7, 13))

-- 
Jani Nikula, Intel

Re: [PATCH 01/12] drm/i915/vrr: Add HAS_EMP_AS_SDP_TL macro

[Nautiyal, Ankit K]

On 4/13/2026 2:01 PM, Jani Nikula wrote:
> On Mon, 13 Apr 2026, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
>> double buffering point and transmission line for VRR packets for
>> HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
> Okay, EMP AS SDP TL is where I draw the line. I don't understand this
> acronym soup anymore. HAS_EMP_AS_SDL_TL() is meaningless to me.

Hmm I was short of naming it HAS_PROGRAMMABLE_VRR_PACKET_TL() or 
something, but then it become overly long and perhaps TL might also be 
very contextual and not very clear.

So I went ahead with EMP_AS_SDP_TL to align with the register we are 
trying to program.

I also realize that I have not mentioned full forms EMP and SDP, which I 
should have atleast in the first patch, especially for EMP (Extended 
Metadata Packet coming from HDMI2.1).

Thanks for pointing it out. I will try to be bit more clearer with the 
naming and provide the full form atleast in the place where they are 
first used.


>
> The idea with the HAS_*() helpers is to make the code more *readable*.
>
> The absolute minimum is to explain what these acronyms mean in commit
> messages or comments, but you could just make the HAS_*() macro more
> readable on its own.
>
> I'm also not convinced we need to put all the HAS_*() macros in
> intel_display_device.h when we could place some of them inside the
> single .c file that uses them.


Currently this is used in couple of files, but I got your point, if this 
finally used only in intel_vrr.c I will place it in the same file.


Thanks & Regards,

Ankit

>
>
> BR,
> Jani.
>
>
>> Add a macro for this and use it in intel_vrr.c
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
>>   drivers/gpu/drm/i915/display/intel_vrr.c            | 2 +-
>>   2 files changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
>> index 1170ac346615..9338ea087e92 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
>> @@ -173,6 +173,7 @@ struct intel_display_platforms {
>>   #define HAS_DSC(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_dsc)
>>   #define HAS_DSC_3ENGINES(__display)	(DISPLAY_VERx100(__display) == 1401 && HAS_DSC(__display))
>>   #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
>> +#define HAS_EMP_AS_SDP_TL(__display)	(DISPLAY_VERx100(__display) == 1401 || DISPLAY_VER(__display) >= 20)
>>   #define HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
>>   #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >= 30)
>>   #define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx)
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index fae1186a90b2..1fed597439b0 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -656,7 +656,7 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>>   	 * Since currently we support VRR only for DP/eDP, so this is programmed
>>   	 * to for Adaptive Sync SDP to Vsync start.
>>   	 */
>> -	if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
>> +	if (HAS_EMP_AS_SDP_TL(display))
>>   		intel_de_write(display,
>>   			       EMP_AS_SDP_TL(display, cpu_transcoder),
>>   			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));

Re: [PATCH 02/12] drm/i915/vrr: Add helper to readback EMP_AS_SDP_TL

[Ville Syrjälä]

On Mon, Apr 13, 2026 at 09:23:39AM +0530, Ankit Nautiyal wrote:
> EMP_AS_SDP_TL is used to program both DP Adaptive Sync SDP and HDMI
> Video Timing EMP for VRR operation. Add a helper to read back the
> programmed transmission line from hardware so VRR code can populate
> the corresponding CRTC state fields during get_config.
> 
> This provides a common read-back path for VRR packet transmission
> line state.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 13 +++++++++++++
>  drivers/gpu/drm/i915/display/intel_vrr.h |  1 +
>  2 files changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 1fed597439b0..abdae7f1f8a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -1218,3 +1218,16 @@ int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_st
>  
>  	return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
>  }
> +
> +u16 intel_vrr_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 val;
> +
> +	if (!HAS_EMP_AS_SDP_TL(display))
> +		return 0;
> +
> +	val = intel_de_read(display, EMP_AS_SDP_TL(display, cpu_transcoder));
> +	return REG_FIELD_GET(EMP_AS_SDP_DB_TL_MASK, val);

This stuff really doesn't seem to belong in intel_vrr.c. We probably need
some kind of infoframe/SDP file where all the relevant stuff lives. Long
ago I did attempt to extract all the infoframe stuff from intel_hdmi.c
into intel_dip.c (or something like that), but there were still far too
many HDMI specifics in the result for my liking.

So I think what's really needed is an effort to distill the core of the
video DIP implementation (really just the low level buffer read/write
stuff, and I suspect now also this transmission line stuff) into a new
file. You could perhaps introduce that new file here, and then we'll
try to get to extracting the DIP buffer stuff later.

> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 4f16ca4af91f..6659a8a53432 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -53,5 +53,6 @@ int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_sta
>  int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state);
>  int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
>  int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
> +u16 intel_vrr_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
>  
>  #endif /* __INTEL_VRR_H__ */
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 05/12] drm/i915/dp: Add crtc state for AS SDP transmission line

[Nautiyal, Ankit K]

On 4/13/2026 2:06 PM, Jani Nikula wrote:
> On Mon, 13 Apr 2026, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> The Adaptive Sync SDP is currently the only DisplayPort SDP with a
>> programmable transmission line. Store the AS SDP transmission line
>> in the crtc state and include it in the pipe configuration comparison.
>>
>> This provides a common place for SDP transmission lines and paves the way
>> for supporting additional SDP TL programming, including the common base
>> SDP transmission line introduced with Xe3p_lpd.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c       | 2 ++
>>   drivers/gpu/drm/i915/display/intel_display_types.h | 8 ++++++++
>>   2 files changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 10b6c6fcb03f..c66541f26a09 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -5434,6 +5434,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>>   	}
>>   	PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
>>   
>> +	PIPE_CONF_CHECK_I(dp_sdp_tl.as);
>> +
> Too short, too many acronyms.

Hmm I can make it `dp_sdp_transmission_line` or just 
`sdp_transmission_line` instead of `dp_sdp_tl`.

Instead of `as` I can use `adaptive_sync`, but then it will become an 
odd one out, unless we want to expand pps, vsc, gmp and all too.

I was thinking of as_sdp too, but then that is trading one acronym with 
other and also duplicate `sdp` in the naming.


>
>>   	PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
>>   	PIPE_CONF_CHECK_I(master_transcoder);
>>   	PIPE_CONF_CHECK_X(joiner_pipes);
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index e2496db1642a..f58454c23859 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1298,6 +1298,14 @@ struct intel_crtc_state {
>>   		struct drm_dp_as_sdp as_sdp;
>>   	} infoframes;
>>   
>> +	struct {
>> +		/*
>> +		 * SDP Transmission line, relative to the Vtotal.
>> +		 * The programmed transmit line is (Vtotal - value)
>> +		 */
>> +		u16 as;
>> +	} dp_sdp_tl;
> Why would this deserve to be a top level sub-struct in the crtc state?


Hmm.. the struct is designed to collect all SDP transmission lines (not 
just AS, as mentioned in the commit message). It made sense to me to add 
a separate struct for storing all SDP transmission lines.

I am open to suggestion for a new place to store this though.


Regards,

Ankit


>
>> +
>>   	u8 eld[MAX_ELD_BYTES];
>>   
>>   	/* HDMI scrambling status */

Re: [PATCH 04/12] drm/i915/dp: Add helper to get AS SDP Transmission Line

[Nautiyal, Ankit K]

On 4/13/2026 2:04 PM, Jani Nikula wrote:
> On Mon, 13 Apr 2026, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> Introduce a DP helper to compute the Adaptive Sync SDP transmission line
>> and use it when programming the EMP_AS_SDP_TL register.
>>
>> Currently the AS SDP transmission line is programmed to the T1 position.
>> This can be extended in the future to support programming the T2 position
>> as well.
>>
>> While at it, improve the documentation: the AS SDP transmission line
>> corresponds to the T1 position, which maps to the start of the VSYNC
>> pulse.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c  | 12 ++++++++++++
>>   drivers/gpu/drm/i915/display/intel_dp.h  |  2 ++
>>   drivers/gpu/drm/i915/display/intel_vrr.c |  4 ++--
>>   3 files changed, 16 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 4955bd8b11d7..fd668babd641 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -7415,3 +7415,15 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>>   
>>   	return true;
>>   }
>> +
>> +int intel_dp_sdp_as_tl(const struct intel_crtc_state *crtc_state)
> So the name of the function is Intel display port secondary data packet
> adaptive sync transmission line.
>
> The function name doesn't say what the function *does*.

I agree. I will make the function reflect what the function does.


Thanks & Regards,

Ankit


>
>> +{
>> +	/*
>> +	 * EMP_AS_SDP_TL defines the T1 position as the default AS SDP
>> +	 * Transmission Line, which corresponds to the start of the
>> +	 * VSYNC pulse.
>> +	 *
>> +	 * Use the T1 position for now.
>> +	 */
>> +	return crtc_state->vrr.vsync_start;
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>> index 2849b9ecdc71..7024fd0ace0a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -238,4 +238,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>>   	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
>>   		for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
>>   
>> +int intel_dp_sdp_as_tl(const struct intel_crtc_state *crtc_state);
>> +
>>   #endif /* __INTEL_DP_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 5164d8c354e0..b700da4e9256 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -607,11 +607,11 @@ void intel_vrr_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
>>   
>>   	/*
>>   	 * Since currently we support VRR only for DP/eDP, so this is programmed
>> -	 * only for Adaptive Sync SDP to Vsync start.
>> +	 * only for Adaptive Sync SDP.
>>   	 */
>>   	intel_de_write(display,
>>   		       EMP_AS_SDP_TL(display, cpu_transcoder),
>> -		       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
>> +		       EMP_AS_SDP_DB_TL(intel_dp_sdp_as_tl(crtc_state)));
>>   }
>>   
>>   void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)

Re: [PATCH 02/12] drm/i915/vrr: Add helper to readback EMP_AS_SDP_TL

[Nautiyal, Ankit K]

On 4/13/2026 2:55 PM, Ville Syrjälä wrote:
> On Mon, Apr 13, 2026 at 09:23:39AM +0530, Ankit Nautiyal wrote:
>> EMP_AS_SDP_TL is used to program both DP Adaptive Sync SDP and HDMI
>> Video Timing EMP for VRR operation. Add a helper to read back the
>> programmed transmission line from hardware so VRR code can populate
>> the corresponding CRTC state fields during get_config.
>>
>> This provides a common read-back path for VRR packet transmission
>> line state.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_vrr.c | 13 +++++++++++++
>>   drivers/gpu/drm/i915/display/intel_vrr.h |  1 +
>>   2 files changed, 14 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 1fed597439b0..abdae7f1f8a8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -1218,3 +1218,16 @@ int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_st
>>   
>>   	return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
>>   }
>> +
>> +u16 intel_vrr_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
>> +{
>> +	struct intel_display *display = to_intel_display(crtc_state);
>> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> +	u32 val;
>> +
>> +	if (!HAS_EMP_AS_SDP_TL(display))
>> +		return 0;
>> +
>> +	val = intel_de_read(display, EMP_AS_SDP_TL(display, cpu_transcoder));
>> +	return REG_FIELD_GET(EMP_AS_SDP_DB_TL_MASK, val);
> This stuff really doesn't seem to belong in intel_vrr.c. We probably need
> some kind of infoframe/SDP file where all the relevant stuff lives. Long
> ago I did attempt to extract all the infoframe stuff from intel_hdmi.c
> into intel_dip.c (or something like that), but there were still far too
> many HDMI specifics in the result for my liking.
>
> So I think what's really needed is an effort to distill the core of the
> video DIP implementation (really just the low level buffer read/write
> stuff, and I suspect now also this transmission line stuff) into a new
> file. You could perhaps introduce that new file here, and then we'll
> try to get to extracting the DIP buffer stuff later.
Alright. I can start with a new file for SDP transmission line stuff.

Since we are on the topic, I had a query:
The hsw_infoframe_enable() switch mixes HDMI packet types and DP SDP 
types in a single namespace.
The types currently used don't collide, but I think these might collide 
at some point, (if not already).
Do we need to change this? OR these are guaranteed to be non-overlapping?

Regards,

Ankit


>
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
>> index 4f16ca4af91f..6659a8a53432 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
>> @@ -53,5 +53,6 @@ int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_sta
>>   int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state);
>>   int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
>>   int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
>> +u16 intel_vrr_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
>>   
>>   #endif /* __INTEL_VRR_H__ */
>> -- 
>> 2.45.2

Re: [PATCH 02/12] drm/i915/vrr: Add helper to readback EMP_AS_SDP_TL

[Ville Syrjälä]

On Mon, Apr 13, 2026 at 03:24:30PM +0530, Nautiyal, Ankit K wrote:
> 
> On 4/13/2026 2:55 PM, Ville Syrjälä wrote:
> > On Mon, Apr 13, 2026 at 09:23:39AM +0530, Ankit Nautiyal wrote:
> >> EMP_AS_SDP_TL is used to program both DP Adaptive Sync SDP and HDMI
> >> Video Timing EMP for VRR operation. Add a helper to read back the
> >> programmed transmission line from hardware so VRR code can populate
> >> the corresponding CRTC state fields during get_config.
> >>
> >> This provides a common read-back path for VRR packet transmission
> >> line state.
> >>
> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/display/intel_vrr.c | 13 +++++++++++++
> >>   drivers/gpu/drm/i915/display/intel_vrr.h |  1 +
> >>   2 files changed, 14 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> >> index 1fed597439b0..abdae7f1f8a8 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> >> @@ -1218,3 +1218,16 @@ int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_st
> >>   
> >>   	return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
> >>   }
> >> +
> >> +u16 intel_vrr_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
> >> +{
> >> +	struct intel_display *display = to_intel_display(crtc_state);
> >> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >> +	u32 val;
> >> +
> >> +	if (!HAS_EMP_AS_SDP_TL(display))
> >> +		return 0;
> >> +
> >> +	val = intel_de_read(display, EMP_AS_SDP_TL(display, cpu_transcoder));
> >> +	return REG_FIELD_GET(EMP_AS_SDP_DB_TL_MASK, val);
> > This stuff really doesn't seem to belong in intel_vrr.c. We probably need
> > some kind of infoframe/SDP file where all the relevant stuff lives. Long
> > ago I did attempt to extract all the infoframe stuff from intel_hdmi.c
> > into intel_dip.c (or something like that), but there were still far too
> > many HDMI specifics in the result for my liking.
> >
> > So I think what's really needed is an effort to distill the core of the
> > video DIP implementation (really just the low level buffer read/write
> > stuff, and I suspect now also this transmission line stuff) into a new
> > file. You could perhaps introduce that new file here, and then we'll
> > try to get to extracting the DIP buffer stuff later.
> Alright. I can start with a new file for SDP transmission line stuff.
> 
> Since we are on the topic, I had a query:
> The hsw_infoframe_enable() switch mixes HDMI packet types and DP SDP 
> types in a single namespace.
> The types currently used don't collide, but I think these might collide 
> at some point, (if not already).
> Do we need to change this? OR these are guaranteed to be non-overlapping?

We should perhaps introduce a DIP type enum and have the higher level
code convert the HDMI/DP specific types into that.


-- 
Ville Syrjälä
Intel

[PATCH 04/12] drm/i915/dp: Add helper to get AS SDP Transmission Line

[Ankit Nautiyal]

Introduce a DP helper to compute the Adaptive Sync SDP transmission line
and use it when programming the EMP_AS_SDP_TL register.

Currently the AS SDP transmission line is programmed to the T1 position.
This can be extended in the future to support programming the T2 position
as well.

While at it, improve the documentation: the AS SDP transmission line
corresponds to the T1 position, which maps to the start of the VSYNC
pulse.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dip.c |  5 +++--
 drivers/gpu/drm/i915/display/intel_dp.c  | 12 ++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h  |  2 ++
 3 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dip.c b/drivers/gpu/drm/i915/display/intel_dip.c
index 2e3f303de74b..2ec07148801e 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.c
+++ b/drivers/gpu/drm/i915/display/intel_dip.c
@@ -8,6 +8,7 @@
 #include "intel_dip.h"
 #include "intel_dip_regs.h"
 #include "intel_display_types.h"
+#include "intel_dp.h"
 
 u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
 {
@@ -31,10 +32,10 @@ void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
 		return;
 	/*
 	 * Since currently we support VRR only for DP/eDP, so this is programmed
-	 * only for Adaptive Sync SDP to Vsync start.
+	 * only for Adaptive Sync SDP.
 	 */
 	if (intel_crtc_has_dp_encoder(crtc_state))
 		intel_de_write(display,
 			       EMP_AS_SDP_TL(display, cpu_transcoder),
-			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
+			       EMP_AS_SDP_DB_TL(intel_dp_get_as_sdp_transmission_line(crtc_state)));
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4955bd8b11d7..cab7db9902e2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7415,3 +7415,15 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 
 	return true;
 }
+
+int intel_dp_get_as_sdp_transmission_line(const struct intel_crtc_state *crtc_state)
+{
+	/*
+	 * EMP_AS_SDP_TL defines the T1 position as the default AS SDP
+	 * Transmission Line, which corresponds to the start of the
+	 * VSYNC pulse.
+	 *
+	 * Use the T1 position for now.
+	 */
+	return crtc_state->vrr.vsync_start;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 2849b9ecdc71..e10f21c06fe9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -238,4 +238,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
 		for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
 
+int intel_dp_get_as_sdp_transmission_line(const struct intel_crtc_state *crtc_state);
+
 #endif /* __INTEL_DP_H__ */
-- 
2.45.2