[PATCH 0/9] drm/i915/wm: Clean up pre-icl NV12 watermarks

[PATCH 0/9] drm/i915/wm: Clean up pre-icl NV12 watermarks

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Clean up the NV12 DDB/watermark handling for pre-icl platforms.

Ville Syrjälä (9):
  drm/i915/wm: Nuke is_planar from skl+ wm structures
  drm/i915/wm: Reorder the arguments to skl_allocate_plane_ddb()
  drm/i915/wm: s/skl_check_nv12_wm_level()/skl_check_wm_level_nv12()/
  drm/i915/wm: Extract skl_allocate_plane_ddb_nv12()
  drm/i915/wm: Nuke wm->uv_wm[]
  drm/i915/wm: s/skl_print_plane_changes()/skl_print_plane_wm_changes()/
  drm/i915/wm: Extract skl_print_plane_ddb_changes()
  drm/i915/wm: Include ddb_y in skl_print_wm_changes() on pre-icl
  drm/i915/wm: Include .min_ddb_alloc_uv in the wm dumps

 .../drm/i915/display/intel_display_types.h    |   3 +-
 drivers/gpu/drm/i915/display/skl_watermark.c  | 160 ++++++++++++------
 2 files changed, 105 insertions(+), 58 deletions(-)

-- 
2.52.0

[PATCH 1/9] drm/i915/wm: Nuke is_planar from skl+ wm structures

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We don't need is_planar in either the actual watermarks or the
wm_params structure used during the wm computation. Get rid
of both.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 1 -
 drivers/gpu/drm/i915/display/skl_watermark.c       | 6 +-----
 2 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d3a9ace4c9d1..93b8b2f91484 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -851,7 +851,6 @@ struct skl_plane_wm {
 		struct skl_wm_level wm0;
 		struct skl_wm_level trans_wm;
 	} sagv;
-	bool is_planar;
 };
 
 struct skl_pipe_wm {
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index b1f9546b8cda..0f99a3264f05 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -63,7 +63,6 @@ static void skl_sagv_disable(struct intel_display *display);
 struct skl_wm_params {
 	bool x_tiled, y_tiled;
 	bool rc_surface;
-	bool is_planar;
 	u32 width;
 	u8 cpp;
 	u32 plane_pixel_rate;
@@ -1675,10 +1674,9 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
 	wp->y_tiled = modifier != I915_FORMAT_MOD_X_TILED &&
 		intel_fb_is_tiled_modifier(modifier);
 	wp->rc_surface = intel_fb_is_ccs_modifier(modifier);
-	wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier);
 
 	wp->width = width;
-	if (color_plane == 1 && wp->is_planar)
+	if (color_plane == 1 && intel_format_info_is_yuv_semiplanar(format, modifier))
 		wp->width /= 2;
 
 	wp->cpp = format->cpp[color_plane];
@@ -2073,8 +2071,6 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
 	struct skl_wm_params wm_params;
 	int ret;
 
-	wm->is_planar = true;
-
 	/* uv plane watermarks must also be validated for NV12/Planar */
 	ret = skl_compute_plane_wm_params(crtc_state, plane_state,
 					  &wm_params, 1);
-- 
2.52.0

Re: [PATCH 1/9] drm/i915/wm: Nuke is_planar from skl+ wm structures

[Jani Nikula]

On Thu, 19 Mar 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We don't need is_planar in either the actual watermarks or the
> wm_params structure used during the wm computation. Get rid
> of both.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h | 1 -
>  drivers/gpu/drm/i915/display/skl_watermark.c       | 6 +-----
>  2 files changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d3a9ace4c9d1..93b8b2f91484 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -851,7 +851,6 @@ struct skl_plane_wm {
>  		struct skl_wm_level wm0;
>  		struct skl_wm_level trans_wm;
>  	} sagv;
> -	bool is_planar;
>  };
>  
>  struct skl_pipe_wm {
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index b1f9546b8cda..0f99a3264f05 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -63,7 +63,6 @@ static void skl_sagv_disable(struct intel_display *display);
>  struct skl_wm_params {
>  	bool x_tiled, y_tiled;
>  	bool rc_surface;
> -	bool is_planar;
>  	u32 width;
>  	u8 cpp;
>  	u32 plane_pixel_rate;
> @@ -1675,10 +1674,9 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
>  	wp->y_tiled = modifier != I915_FORMAT_MOD_X_TILED &&
>  		intel_fb_is_tiled_modifier(modifier);
>  	wp->rc_surface = intel_fb_is_ccs_modifier(modifier);
> -	wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier);
>  
>  	wp->width = width;
> -	if (color_plane == 1 && wp->is_planar)
> +	if (color_plane == 1 && intel_format_info_is_yuv_semiplanar(format, modifier))
>  		wp->width /= 2;
>  
>  	wp->cpp = format->cpp[color_plane];
> @@ -2073,8 +2071,6 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
>  	struct skl_wm_params wm_params;
>  	int ret;
>  
> -	wm->is_planar = true;
> -
>  	/* uv plane watermarks must also be validated for NV12/Planar */
>  	ret = skl_compute_plane_wm_params(crtc_state, plane_state,
>  					  &wm_params, 1);

-- 
Jani Nikula, Intel

[PATCH 2/9] drm/i915/wm: Reorder the arguments to skl_allocate_plane_ddb()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Group the ddb and data_rate together in the skl_allocate_plane_ddb()
arguments. Upcoming changes will adjust the UV plane handling and
keeing the ddb allocation and the data rate used to calculate it
together will help with clarity.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 0f99a3264f05..1664b84d0387 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -1391,9 +1391,8 @@ struct skl_plane_ddb_iter {
 
 static void
 skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
-		       struct skl_ddb_entry *ddb,
 		       const struct skl_wm_level *wm,
-		       u64 data_rate)
+		       struct skl_ddb_entry *ddb, u64 data_rate)
 {
 	u16 size, extra = 0;
 
@@ -1523,13 +1522,13 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 
 		if (DISPLAY_VER(display) < 11 &&
 		    crtc_state->nv12_planes & BIT(plane_id)) {
-			skl_allocate_plane_ddb(&iter, ddb_y, &wm->wm[level],
-					       crtc_state->rel_data_rate_y[plane_id]);
-			skl_allocate_plane_ddb(&iter, ddb, &wm->uv_wm[level],
-					       crtc_state->rel_data_rate[plane_id]);
+			skl_allocate_plane_ddb(&iter, &wm->wm[level],
+					       ddb_y, crtc_state->rel_data_rate_y[plane_id]);
+			skl_allocate_plane_ddb(&iter, &wm->uv_wm[level],
+					       ddb, crtc_state->rel_data_rate[plane_id]);
 		} else {
-			skl_allocate_plane_ddb(&iter, ddb, &wm->wm[level],
-					       crtc_state->rel_data_rate[plane_id]);
+			skl_allocate_plane_ddb(&iter, &wm->wm[level],
+					       ddb, crtc_state->rel_data_rate[plane_id]);
 		}
 
 		if (DISPLAY_VER(display) >= 30) {
-- 
2.52.0

Re: [PATCH 2/9] drm/i915/wm: Reorder the arguments to skl_allocate_plane_ddb()

[Jani Nikula]

On Thu, 19 Mar 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Group the ddb and data_rate together in the skl_allocate_plane_ddb()
> arguments. Upcoming changes will adjust the UV plane handling and
> keeing the ddb allocation and the data rate used to calculate it
> together will help with clarity.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 15 +++++++--------
>  1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 0f99a3264f05..1664b84d0387 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -1391,9 +1391,8 @@ struct skl_plane_ddb_iter {
>  
>  static void
>  skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
> -		       struct skl_ddb_entry *ddb,
>  		       const struct skl_wm_level *wm,
> -		       u64 data_rate)
> +		       struct skl_ddb_entry *ddb, u64 data_rate)
>  {
>  	u16 size, extra = 0;
>  
> @@ -1523,13 +1522,13 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  
>  		if (DISPLAY_VER(display) < 11 &&
>  		    crtc_state->nv12_planes & BIT(plane_id)) {
> -			skl_allocate_plane_ddb(&iter, ddb_y, &wm->wm[level],
> -					       crtc_state->rel_data_rate_y[plane_id]);
> -			skl_allocate_plane_ddb(&iter, ddb, &wm->uv_wm[level],
> -					       crtc_state->rel_data_rate[plane_id]);
> +			skl_allocate_plane_ddb(&iter, &wm->wm[level],
> +					       ddb_y, crtc_state->rel_data_rate_y[plane_id]);
> +			skl_allocate_plane_ddb(&iter, &wm->uv_wm[level],
> +					       ddb, crtc_state->rel_data_rate[plane_id]);
>  		} else {
> -			skl_allocate_plane_ddb(&iter, ddb, &wm->wm[level],
> -					       crtc_state->rel_data_rate[plane_id]);
> +			skl_allocate_plane_ddb(&iter, &wm->wm[level],
> +					       ddb, crtc_state->rel_data_rate[plane_id]);
>  		}
>  
>  		if (DISPLAY_VER(display) >= 30) {

-- 
Jani Nikula, Intel

[PATCH 3/9] drm/i915/wm: s/skl_check_nv12_wm_level()/skl_check_wm_level_nv12()/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rename skl_check_nv12_wm_level() to skl_check_wm_level_nv12(). There
will be a sort of DDB counterparts to skl_check_wm_level*(), and
putting the "nv12" part to the end will allow consistent naming.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 1664b84d0387..24978f312fec 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -1356,7 +1356,7 @@ skl_check_wm_level(struct skl_wm_level *wm, const struct skl_ddb_entry *ddb)
 }
 
 static void
-skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
+skl_check_wm_level_nv12(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
 			const struct skl_ddb_entry *ddb_y, const struct skl_ddb_entry *ddb)
 {
 	if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb_y) ||
@@ -1555,7 +1555,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 
 			if (DISPLAY_VER(display) < 11 &&
 			    crtc_state->nv12_planes & BIT(plane_id))
-				skl_check_nv12_wm_level(&wm->wm[level],
+				skl_check_wm_level_nv12(&wm->wm[level],
 							&wm->uv_wm[level],
 							ddb_y, ddb);
 			else
-- 
2.52.0

Re: [PATCH 3/9] drm/i915/wm: s/skl_check_nv12_wm_level()/skl_check_wm_level_nv12()/

[Jani Nikula]

On Thu, 19 Mar 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename skl_check_nv12_wm_level() to skl_check_wm_level_nv12(). There
> will be a sort of DDB counterparts to skl_check_wm_level*(), and
> putting the "nv12" part to the end will allow consistent naming.

Overall I dislike "check" in function names. What does it check? What
does it mean? Should it have a return value? Or is it like an assert?

In skl_watermark.c, there are three types of check functions, all
behaving differently. check_mbus_joined() is really just
is_mbus_joined(). I don't know what skl_check_wm_level() or
skl_check_nv12_wm_level() should be called, because they conditionally
clear the watermarks. And "checking" doesn't sound like something that
should modify its arguments. Then you have skl_wm_check_vblank(), which
modifies its arguments and returns an error code, and I really don't
know what about it is "checking".

/rant

Anyway, for the patch at hand,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 1664b84d0387..24978f312fec 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -1356,7 +1356,7 @@ skl_check_wm_level(struct skl_wm_level *wm, const struct skl_ddb_entry *ddb)
>  }
>  
>  static void
> -skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
> +skl_check_wm_level_nv12(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
>  			const struct skl_ddb_entry *ddb_y, const struct skl_ddb_entry *ddb)
>  {
>  	if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb_y) ||
> @@ -1555,7 +1555,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  
>  			if (DISPLAY_VER(display) < 11 &&
>  			    crtc_state->nv12_planes & BIT(plane_id))
> -				skl_check_nv12_wm_level(&wm->wm[level],
> +				skl_check_wm_level_nv12(&wm->wm[level],
>  							&wm->uv_wm[level],
>  							ddb_y, ddb);
>  			else

-- 
Jani Nikula, Intel

[PATCH 4/9] drm/i915/wm: Extract skl_allocate_plane_ddb_nv12()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract skl_allocate_plane_ddb_nv12() as the compute counterpart to
skl_check_wm_level_nv12(). Mainly to hide some of the clutter from
skl_crtc_allocate_plane_ddb().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 40 ++++++++++++++------
 1 file changed, 29 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 24978f312fec..7c4c42dde991 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -1390,9 +1390,9 @@ struct skl_plane_ddb_iter {
 };
 
 static void
-skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
-		       const struct skl_wm_level *wm,
-		       struct skl_ddb_entry *ddb, u64 data_rate)
+_skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
+			u16 min_ddb_alloc,
+			struct skl_ddb_entry *ddb, u64 data_rate)
 {
 	u16 size, extra = 0;
 
@@ -1409,12 +1409,31 @@ skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
 	 * to avoid skl_ddb_add_affected_planes() adding them to
 	 * the state when other planes change their allocations.
 	 */
-	size = wm->min_ddb_alloc + extra;
+	size = min_ddb_alloc + extra;
 	if (size)
 		iter->start = skl_ddb_entry_init(ddb, iter->start,
 						 iter->start + size);
 }
 
+static void
+skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
+		       const struct skl_wm_level *wm,
+		       struct skl_ddb_entry *ddb, u64 data_rate)
+{
+	_skl_allocate_plane_ddb(iter, wm->min_ddb_alloc, ddb, data_rate);
+}
+
+static void
+skl_allocate_plane_ddb_nv12(struct skl_plane_ddb_iter *iter,
+			    const struct skl_wm_level *wm,
+			    struct skl_ddb_entry *ddb_y, u64 data_rate_y,
+			    const struct skl_wm_level *uv_wm,
+			    struct skl_ddb_entry *ddb, u64 data_rate)
+{
+	_skl_allocate_plane_ddb(iter, wm->min_ddb_alloc, ddb_y, data_rate_y);
+	_skl_allocate_plane_ddb(iter, uv_wm->min_ddb_alloc, ddb, data_rate);
+}
+
 static int
 skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 			    struct intel_crtc *crtc)
@@ -1521,15 +1540,14 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 			continue;
 
 		if (DISPLAY_VER(display) < 11 &&
-		    crtc_state->nv12_planes & BIT(plane_id)) {
+		    crtc_state->nv12_planes & BIT(plane_id))
+			skl_allocate_plane_ddb_nv12(&iter, &wm->wm[level],
+						    ddb_y, crtc_state->rel_data_rate_y[plane_id],
+						    &wm->uv_wm[level],
+						    ddb, crtc_state->rel_data_rate[plane_id]);
+		else
 			skl_allocate_plane_ddb(&iter, &wm->wm[level],
-					       ddb_y, crtc_state->rel_data_rate_y[plane_id]);
-			skl_allocate_plane_ddb(&iter, &wm->uv_wm[level],
 					       ddb, crtc_state->rel_data_rate[plane_id]);
-		} else {
-			skl_allocate_plane_ddb(&iter, &wm->wm[level],
-					       ddb, crtc_state->rel_data_rate[plane_id]);
-		}
 
 		if (DISPLAY_VER(display) >= 30) {
 			*min_ddb = wm->wm[0].min_ddb_alloc;
-- 
2.52.0

Re: [PATCH 4/9] drm/i915/wm: Extract skl_allocate_plane_ddb_nv12()

[Jani Nikula]

On Thu, 19 Mar 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract skl_allocate_plane_ddb_nv12() as the compute counterpart to
> skl_check_wm_level_nv12(). Mainly to hide some of the clutter from
> skl_crtc_allocate_plane_ddb().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 40 ++++++++++++++------
>  1 file changed, 29 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 24978f312fec..7c4c42dde991 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -1390,9 +1390,9 @@ struct skl_plane_ddb_iter {
>  };
>  
>  static void
> -skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
> -		       const struct skl_wm_level *wm,
> -		       struct skl_ddb_entry *ddb, u64 data_rate)
> +_skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
> +			u16 min_ddb_alloc,
> +			struct skl_ddb_entry *ddb, u64 data_rate)
>  {
>  	u16 size, extra = 0;
>  
> @@ -1409,12 +1409,31 @@ skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
>  	 * to avoid skl_ddb_add_affected_planes() adding them to
>  	 * the state when other planes change their allocations.
>  	 */
> -	size = wm->min_ddb_alloc + extra;
> +	size = min_ddb_alloc + extra;
>  	if (size)
>  		iter->start = skl_ddb_entry_init(ddb, iter->start,
>  						 iter->start + size);
>  }
>  
> +static void
> +skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
> +		       const struct skl_wm_level *wm,
> +		       struct skl_ddb_entry *ddb, u64 data_rate)
> +{
> +	_skl_allocate_plane_ddb(iter, wm->min_ddb_alloc, ddb, data_rate);
> +}
> +
> +static void
> +skl_allocate_plane_ddb_nv12(struct skl_plane_ddb_iter *iter,
> +			    const struct skl_wm_level *wm,
> +			    struct skl_ddb_entry *ddb_y, u64 data_rate_y,
> +			    const struct skl_wm_level *uv_wm,
> +			    struct skl_ddb_entry *ddb, u64 data_rate)
> +{
> +	_skl_allocate_plane_ddb(iter, wm->min_ddb_alloc, ddb_y, data_rate_y);
> +	_skl_allocate_plane_ddb(iter, uv_wm->min_ddb_alloc, ddb, data_rate);
> +}
> +
>  static int
>  skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  			    struct intel_crtc *crtc)
> @@ -1521,15 +1540,14 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  			continue;
>  
>  		if (DISPLAY_VER(display) < 11 &&
> -		    crtc_state->nv12_planes & BIT(plane_id)) {
> +		    crtc_state->nv12_planes & BIT(plane_id))
> +			skl_allocate_plane_ddb_nv12(&iter, &wm->wm[level],
> +						    ddb_y, crtc_state->rel_data_rate_y[plane_id],
> +						    &wm->uv_wm[level],
> +						    ddb, crtc_state->rel_data_rate[plane_id]);
> +		else
>  			skl_allocate_plane_ddb(&iter, &wm->wm[level],
> -					       ddb_y, crtc_state->rel_data_rate_y[plane_id]);
> -			skl_allocate_plane_ddb(&iter, &wm->uv_wm[level],
>  					       ddb, crtc_state->rel_data_rate[plane_id]);
> -		} else {
> -			skl_allocate_plane_ddb(&iter, &wm->wm[level],
> -					       ddb, crtc_state->rel_data_rate[plane_id]);
> -		}
>  
>  		if (DISPLAY_VER(display) >= 30) {
>  			*min_ddb = wm->wm[0].min_ddb_alloc;

-- 
Jani Nikula, Intel

[PATCH 5/9] drm/i915/wm: Nuke wm->uv_wm[]

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We currently keep around the full watermarks for the UV plane
on pre-icl, even though the hardware doesn't need most of this
information. The only thing we need to keep is the min_ddb_alloc
for the UV plane. Move that into the main wm->wm[].min_ddb_alloc_uv
alongside the other min_ddb_alloc (used for Y/RGB).

This makes our state tracking match the hardware more closely,
and avoids having to justify everwhere why uv_wm[] is being
ignored.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  2 +-
 drivers/gpu/drm/i915/display/skl_watermark.c  | 43 ++++++++-----------
 2 files changed, 19 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 93b8b2f91484..e2496db1642a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -835,6 +835,7 @@ struct intel_pipe_wm {
 
 struct skl_wm_level {
 	u16 min_ddb_alloc;
+	u16 min_ddb_alloc_uv; /* for pre-icl */
 	u16 blocks;
 	u8 lines;
 	bool enable;
@@ -845,7 +846,6 @@ struct skl_wm_level {
 
 struct skl_plane_wm {
 	struct skl_wm_level wm[8];
-	struct skl_wm_level uv_wm[8];
 	struct skl_wm_level trans_wm;
 	struct {
 		struct skl_wm_level wm0;
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 7c4c42dde991..8b1b371fbfab 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -1356,14 +1356,13 @@ skl_check_wm_level(struct skl_wm_level *wm, const struct skl_ddb_entry *ddb)
 }
 
 static void
-skl_check_wm_level_nv12(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
-			const struct skl_ddb_entry *ddb_y, const struct skl_ddb_entry *ddb)
+skl_check_wm_level_nv12(struct skl_wm_level *wm,
+			const struct skl_ddb_entry *ddb_y,
+			const struct skl_ddb_entry *ddb)
 {
 	if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb_y) ||
-	    uv_wm->min_ddb_alloc > skl_ddb_entry_size(ddb)) {
+	    wm->min_ddb_alloc_uv > skl_ddb_entry_size(ddb))
 		memset(wm, 0, sizeof(*wm));
-		memset(uv_wm, 0, sizeof(*uv_wm));
-	}
 }
 
 static bool skl_need_wm_copy_wa(struct intel_display *display, int level,
@@ -1427,11 +1426,10 @@ static void
 skl_allocate_plane_ddb_nv12(struct skl_plane_ddb_iter *iter,
 			    const struct skl_wm_level *wm,
 			    struct skl_ddb_entry *ddb_y, u64 data_rate_y,
-			    const struct skl_wm_level *uv_wm,
 			    struct skl_ddb_entry *ddb, u64 data_rate)
 {
 	_skl_allocate_plane_ddb(iter, wm->min_ddb_alloc, ddb_y, data_rate_y);
-	_skl_allocate_plane_ddb(iter, uv_wm->min_ddb_alloc, ddb, data_rate);
+	_skl_allocate_plane_ddb(iter, wm->min_ddb_alloc_uv, ddb, data_rate);
 }
 
 static int
@@ -1499,7 +1497,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 			}
 
 			blocks += wm->wm[level].min_ddb_alloc;
-			blocks += wm->uv_wm[level].min_ddb_alloc;
+			blocks += wm->wm[level].min_ddb_alloc_uv;
 		}
 
 		if (blocks <= iter.size) {
@@ -1543,7 +1541,6 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 		    crtc_state->nv12_planes & BIT(plane_id))
 			skl_allocate_plane_ddb_nv12(&iter, &wm->wm[level],
 						    ddb_y, crtc_state->rel_data_rate_y[plane_id],
-						    &wm->uv_wm[level],
 						    ddb, crtc_state->rel_data_rate[plane_id]);
 		else
 			skl_allocate_plane_ddb(&iter, &wm->wm[level],
@@ -1573,9 +1570,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 
 			if (DISPLAY_VER(display) < 11 &&
 			    crtc_state->nv12_planes & BIT(plane_id))
-				skl_check_wm_level_nv12(&wm->wm[level],
-							&wm->uv_wm[level],
-							ddb_y, ddb);
+				skl_check_wm_level_nv12(&wm->wm[level], ddb_y, ddb);
 			else
 				skl_check_wm_level(&wm->wm[level], ddb);
 
@@ -2084,9 +2079,11 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
 				 const struct intel_plane_state *plane_state,
 				 struct intel_plane *plane)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];
+	struct skl_wm_level uv_wm[ARRAY_SIZE(wm->wm)] = {};
 	struct skl_wm_params wm_params;
-	int ret;
+	int ret, level;
 
 	/* uv plane watermarks must also be validated for NV12/Planar */
 	ret = skl_compute_plane_wm_params(crtc_state, plane_state,
@@ -2094,7 +2091,14 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
 	if (ret)
 		return ret;
 
-	skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->uv_wm);
+	skl_compute_wm_levels(crtc_state, plane, &wm_params, uv_wm);
+
+	/*
+	 * Only keep the min_ddb_alloc for UV as
+	 * the hardware needs nothing else.
+	 */
+	for (level = 0; level < display->wm.num_levels; level++)
+		wm->wm[level].min_ddb_alloc_uv = uv_wm[level].min_ddb_alloc;
 
 	return 0;
 }
@@ -2317,7 +2321,6 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
 			 * thing as bad via min_ddb_alloc=U16_MAX?
 			 */
 			wm->wm[level].enable = false;
-			wm->uv_wm[level].enable = false;
 		}
 	}
 
@@ -2388,11 +2391,6 @@ static bool skl_plane_wm_equals(struct intel_display *display,
 	int level;
 
 	for (level = 0; level < display->wm.num_levels; level++) {
-		/*
-		 * We don't check uv_wm as the hardware doesn't actually
-		 * use it. It only gets used for calculating the required
-		 * ddb allocation.
-		 */
 		if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]))
 			return false;
 	}
@@ -2753,11 +2751,6 @@ static bool skl_plane_selected_wm_equals(struct intel_plane *plane,
 	int level;
 
 	for (level = 0; level < display->wm.num_levels; level++) {
-		/*
-		 * We don't check uv_wm as the hardware doesn't actually
-		 * use it. It only gets used for calculating the required
-		 * ddb allocation.
-		 */
 		if (!skl_wm_level_equals(skl_plane_wm_level(old_pipe_wm, plane->id, level),
 					 skl_plane_wm_level(new_pipe_wm, plane->id, level)))
 			return false;
-- 
2.52.0

Re: [PATCH 5/9] drm/i915/wm: Nuke wm->uv_wm[]

[Jani Nikula]

On Thu, 19 Mar 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We currently keep around the full watermarks for the UV plane
> on pre-icl, even though the hardware doesn't need most of this
> information. The only thing we need to keep is the min_ddb_alloc
> for the UV plane. Move that into the main wm->wm[].min_ddb_alloc_uv
> alongside the other min_ddb_alloc (used for Y/RGB).
>
> This makes our state tracking match the hardware more closely,
> and avoids having to justify everwhere why uv_wm[] is being
> ignored.

Somehow found this change difficult to follow, but didn't spot anything
obviously wrong either.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  2 +-
>  drivers/gpu/drm/i915/display/skl_watermark.c  | 43 ++++++++-----------
>  2 files changed, 19 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 93b8b2f91484..e2496db1642a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -835,6 +835,7 @@ struct intel_pipe_wm {
>  
>  struct skl_wm_level {
>  	u16 min_ddb_alloc;
> +	u16 min_ddb_alloc_uv; /* for pre-icl */
>  	u16 blocks;
>  	u8 lines;
>  	bool enable;
> @@ -845,7 +846,6 @@ struct skl_wm_level {
>  
>  struct skl_plane_wm {
>  	struct skl_wm_level wm[8];
> -	struct skl_wm_level uv_wm[8];
>  	struct skl_wm_level trans_wm;
>  	struct {
>  		struct skl_wm_level wm0;
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 7c4c42dde991..8b1b371fbfab 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -1356,14 +1356,13 @@ skl_check_wm_level(struct skl_wm_level *wm, const struct skl_ddb_entry *ddb)
>  }
>  
>  static void
> -skl_check_wm_level_nv12(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
> -			const struct skl_ddb_entry *ddb_y, const struct skl_ddb_entry *ddb)
> +skl_check_wm_level_nv12(struct skl_wm_level *wm,
> +			const struct skl_ddb_entry *ddb_y,
> +			const struct skl_ddb_entry *ddb)
>  {
>  	if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb_y) ||
> -	    uv_wm->min_ddb_alloc > skl_ddb_entry_size(ddb)) {
> +	    wm->min_ddb_alloc_uv > skl_ddb_entry_size(ddb))
>  		memset(wm, 0, sizeof(*wm));
> -		memset(uv_wm, 0, sizeof(*uv_wm));
> -	}
>  }
>  
>  static bool skl_need_wm_copy_wa(struct intel_display *display, int level,
> @@ -1427,11 +1426,10 @@ static void
>  skl_allocate_plane_ddb_nv12(struct skl_plane_ddb_iter *iter,
>  			    const struct skl_wm_level *wm,
>  			    struct skl_ddb_entry *ddb_y, u64 data_rate_y,
> -			    const struct skl_wm_level *uv_wm,
>  			    struct skl_ddb_entry *ddb, u64 data_rate)
>  {
>  	_skl_allocate_plane_ddb(iter, wm->min_ddb_alloc, ddb_y, data_rate_y);
> -	_skl_allocate_plane_ddb(iter, uv_wm->min_ddb_alloc, ddb, data_rate);
> +	_skl_allocate_plane_ddb(iter, wm->min_ddb_alloc_uv, ddb, data_rate);
>  }
>  
>  static int
> @@ -1499,7 +1497,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  			}
>  
>  			blocks += wm->wm[level].min_ddb_alloc;
> -			blocks += wm->uv_wm[level].min_ddb_alloc;
> +			blocks += wm->wm[level].min_ddb_alloc_uv;
>  		}
>  
>  		if (blocks <= iter.size) {
> @@ -1543,7 +1541,6 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  		    crtc_state->nv12_planes & BIT(plane_id))
>  			skl_allocate_plane_ddb_nv12(&iter, &wm->wm[level],
>  						    ddb_y, crtc_state->rel_data_rate_y[plane_id],
> -						    &wm->uv_wm[level],
>  						    ddb, crtc_state->rel_data_rate[plane_id]);
>  		else
>  			skl_allocate_plane_ddb(&iter, &wm->wm[level],
> @@ -1573,9 +1570,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  
>  			if (DISPLAY_VER(display) < 11 &&
>  			    crtc_state->nv12_planes & BIT(plane_id))
> -				skl_check_wm_level_nv12(&wm->wm[level],
> -							&wm->uv_wm[level],
> -							ddb_y, ddb);
> +				skl_check_wm_level_nv12(&wm->wm[level], ddb_y, ddb);
>  			else
>  				skl_check_wm_level(&wm->wm[level], ddb);
>  
> @@ -2084,9 +2079,11 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
>  				 const struct intel_plane_state *plane_state,
>  				 struct intel_plane *plane)
>  {
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];
> +	struct skl_wm_level uv_wm[ARRAY_SIZE(wm->wm)] = {};
>  	struct skl_wm_params wm_params;
> -	int ret;
> +	int ret, level;
>  
>  	/* uv plane watermarks must also be validated for NV12/Planar */
>  	ret = skl_compute_plane_wm_params(crtc_state, plane_state,
> @@ -2094,7 +2091,14 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
>  	if (ret)
>  		return ret;
>  
> -	skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->uv_wm);
> +	skl_compute_wm_levels(crtc_state, plane, &wm_params, uv_wm);
> +
> +	/*
> +	 * Only keep the min_ddb_alloc for UV as
> +	 * the hardware needs nothing else.
> +	 */
> +	for (level = 0; level < display->wm.num_levels; level++)
> +		wm->wm[level].min_ddb_alloc_uv = uv_wm[level].min_ddb_alloc;
>  
>  	return 0;
>  }
> @@ -2317,7 +2321,6 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
>  			 * thing as bad via min_ddb_alloc=U16_MAX?
>  			 */
>  			wm->wm[level].enable = false;
> -			wm->uv_wm[level].enable = false;
>  		}
>  	}
>  
> @@ -2388,11 +2391,6 @@ static bool skl_plane_wm_equals(struct intel_display *display,
>  	int level;
>  
>  	for (level = 0; level < display->wm.num_levels; level++) {
> -		/*
> -		 * We don't check uv_wm as the hardware doesn't actually
> -		 * use it. It only gets used for calculating the required
> -		 * ddb allocation.
> -		 */
>  		if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]))
>  			return false;
>  	}
> @@ -2753,11 +2751,6 @@ static bool skl_plane_selected_wm_equals(struct intel_plane *plane,
>  	int level;
>  
>  	for (level = 0; level < display->wm.num_levels; level++) {
> -		/*
> -		 * We don't check uv_wm as the hardware doesn't actually
> -		 * use it. It only gets used for calculating the required
> -		 * ddb allocation.
> -		 */
>  		if (!skl_wm_level_equals(skl_plane_wm_level(old_pipe_wm, plane->id, level),
>  					 skl_plane_wm_level(new_pipe_wm, plane->id, level)))
>  			return false;

-- 
Jani Nikula, Intel

[PATCH 6/9] drm/i915/wm: s/skl_print_plane_changes()/skl_print_plane_wm_changes()/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rename skl_print_plane_changes() to skl_print_plane_wm_changes()
to better reflect what it does.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 8b1b371fbfab..6c8dab847ae2 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2602,11 +2602,12 @@ static char enast(bool enable)
 }
 
 static noinline_for_stack void
-skl_print_plane_changes(struct intel_display *display,
-			struct intel_plane *plane,
-			const struct skl_plane_wm *old_wm,
-			const struct skl_plane_wm *new_wm)
+skl_print_plane_wm_changes(struct intel_plane *plane,
+			   const struct skl_plane_wm *old_wm,
+			   const struct skl_plane_wm *new_wm)
 {
+	struct intel_display *display = to_intel_display(plane);
+
 	drm_dbg_kms(display->drm,
 		    "[PLANE:%d:%s]   level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
 		    " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n",
@@ -2738,7 +2739,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 			if (skl_plane_wm_equals(display, old_wm, new_wm))
 				continue;
 
-			skl_print_plane_changes(display, plane, old_wm, new_wm);
+			skl_print_plane_wm_changes(plane, old_wm, new_wm);
 		}
 	}
 }
-- 
2.52.0

Re: [PATCH 6/9] drm/i915/wm: s/skl_print_plane_changes()/skl_print_plane_wm_changes()/

[Jani Nikula]

On Thu, 19 Mar 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename skl_print_plane_changes() to skl_print_plane_wm_changes()
> to better reflect what it does.

Could also go for skl_wm_* naming, but *shrug* for static functions.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 8b1b371fbfab..6c8dab847ae2 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2602,11 +2602,12 @@ static char enast(bool enable)
>  }
>  
>  static noinline_for_stack void
> -skl_print_plane_changes(struct intel_display *display,
> -			struct intel_plane *plane,
> -			const struct skl_plane_wm *old_wm,
> -			const struct skl_plane_wm *new_wm)
> +skl_print_plane_wm_changes(struct intel_plane *plane,
> +			   const struct skl_plane_wm *old_wm,
> +			   const struct skl_plane_wm *new_wm)
>  {
> +	struct intel_display *display = to_intel_display(plane);
> +
>  	drm_dbg_kms(display->drm,
>  		    "[PLANE:%d:%s]   level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
>  		    " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n",
> @@ -2738,7 +2739,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
>  			if (skl_plane_wm_equals(display, old_wm, new_wm))
>  				continue;
>  
> -			skl_print_plane_changes(display, plane, old_wm, new_wm);
> +			skl_print_plane_wm_changes(plane, old_wm, new_wm);
>  		}
>  	}
>  }

-- 
Jani Nikula, Intel

[PATCH 7/9] drm/i915/wm: Extract skl_print_plane_ddb_changes()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We have skl_print_plane_wm_changes() but the DDB counterpart is
just inline in the main loop. Extract it into a function. We'll
ave a second use for this soon.

The "ddb" part is already parametrized in anticipation of the
second user.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 22 +++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 6c8dab847ae2..8687026935e9 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2601,6 +2601,21 @@ static char enast(bool enable)
 	return enable ? '*' : ' ';
 }
 
+static void
+skl_print_plane_ddb_changes(struct intel_plane *plane,
+			    const struct skl_ddb_entry *old,
+			    const struct skl_ddb_entry *new,
+			    const char *ddb_name)
+{
+	struct intel_display *display = to_intel_display(plane);
+
+	drm_dbg_kms(display->drm,
+		    "[PLANE:%d:%s] %s (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n",
+		    plane->base.base.id, plane->base.name, ddb_name,
+		    old->start, old->end, new->start, new->end,
+		    skl_ddb_entry_size(old), skl_ddb_entry_size(new));
+}
+
 static noinline_for_stack void
 skl_print_plane_wm_changes(struct intel_plane *plane,
 			   const struct skl_plane_wm *old_wm,
@@ -2722,11 +2737,8 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 
 			if (skl_ddb_entry_equal(old, new))
 				continue;
-			drm_dbg_kms(display->drm,
-				    "[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n",
-				    plane->base.base.id, plane->base.name,
-				    old->start, old->end, new->start, new->end,
-				    skl_ddb_entry_size(old), skl_ddb_entry_size(new));
+
+			skl_print_plane_ddb_changes(plane, old, new, "ddb");
 		}
 
 		for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
-- 
2.52.0

Re: [PATCH 7/9] drm/i915/wm: Extract skl_print_plane_ddb_changes()

[Jani Nikula]

On Thu, 19 Mar 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We have skl_print_plane_wm_changes() but the DDB counterpart is
> just inline in the main loop. Extract it into a function. We'll
> ave a second use for this soon.

*have

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
> The "ddb" part is already parametrized in anticipation of the
> second user.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 22 +++++++++++++++-----
>  1 file changed, 17 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 6c8dab847ae2..8687026935e9 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2601,6 +2601,21 @@ static char enast(bool enable)
>  	return enable ? '*' : ' ';
>  }
>  
> +static void
> +skl_print_plane_ddb_changes(struct intel_plane *plane,
> +			    const struct skl_ddb_entry *old,
> +			    const struct skl_ddb_entry *new,
> +			    const char *ddb_name)
> +{
> +	struct intel_display *display = to_intel_display(plane);
> +
> +	drm_dbg_kms(display->drm,
> +		    "[PLANE:%d:%s] %s (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n",
> +		    plane->base.base.id, plane->base.name, ddb_name,
> +		    old->start, old->end, new->start, new->end,
> +		    skl_ddb_entry_size(old), skl_ddb_entry_size(new));
> +}
> +
>  static noinline_for_stack void
>  skl_print_plane_wm_changes(struct intel_plane *plane,
>  			   const struct skl_plane_wm *old_wm,
> @@ -2722,11 +2737,8 @@ skl_print_wm_changes(struct intel_atomic_state *state)
>  
>  			if (skl_ddb_entry_equal(old, new))
>  				continue;
> -			drm_dbg_kms(display->drm,
> -				    "[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n",
> -				    plane->base.base.id, plane->base.name,
> -				    old->start, old->end, new->start, new->end,
> -				    skl_ddb_entry_size(old), skl_ddb_entry_size(new));
> +
> +			skl_print_plane_ddb_changes(plane, old, new, "ddb");
>  		}
>  
>  		for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

-- 
Jani Nikula, Intel

[PATCH 8/9] drm/i915/wm: Include ddb_y in skl_print_wm_changes() on pre-icl

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pre-icl doesn't use a separate hardware plane for Y scanout,
and instead it's all handled magially by the hardware. We
do still need to allocate DDB space for the Y color plane
though (PLANE_NV12_BUF_CFG). Include that information in the
debugs so that we know where it ended up.

On icl+ the equivalent information is dumped as the hardware
Y plane's normal ddb allocation.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 8687026935e9..345767349988 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2735,10 +2735,17 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 			old = &old_crtc_state->wm.skl.plane_ddb[plane_id];
 			new = &new_crtc_state->wm.skl.plane_ddb[plane_id];
 
-			if (skl_ddb_entry_equal(old, new))
+			if (!skl_ddb_entry_equal(old, new))
+				skl_print_plane_ddb_changes(plane, old, new, "  ddb");
+
+			if (DISPLAY_VER(display) >= 11)
 				continue;
 
-			skl_print_plane_ddb_changes(plane, old, new, "ddb");
+			old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
+			new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
+
+			if (!skl_ddb_entry_equal(old, new))
+				skl_print_plane_ddb_changes(plane, old, new, "ddb_y");
 		}
 
 		for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
-- 
2.52.0

Re: [PATCH 8/9] drm/i915/wm: Include ddb_y in skl_print_wm_changes() on pre-icl

[Jani Nikula]

On Thu, 19 Mar 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pre-icl doesn't use a separate hardware plane for Y scanout,
> and instead it's all handled magially by the hardware. We

*magically

> do still need to allocate DDB space for the Y color plane
> though (PLANE_NV12_BUF_CFG). Include that information in the
> debugs so that we know where it ended up.
>
> On icl+ the equivalent information is dumped as the hardware
> Y plane's normal ddb allocation.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 8687026935e9..345767349988 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2735,10 +2735,17 @@ skl_print_wm_changes(struct intel_atomic_state *state)
>  			old = &old_crtc_state->wm.skl.plane_ddb[plane_id];
>  			new = &new_crtc_state->wm.skl.plane_ddb[plane_id];
>  
> -			if (skl_ddb_entry_equal(old, new))
> +			if (!skl_ddb_entry_equal(old, new))
> +				skl_print_plane_ddb_changes(plane, old, new, "  ddb");

Superfluous whitespace in "  ddb"?

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> +
> +			if (DISPLAY_VER(display) >= 11)
>  				continue;
>  
> -			skl_print_plane_ddb_changes(plane, old, new, "ddb");
> +			old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
> +			new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
> +
> +			if (!skl_ddb_entry_equal(old, new))
> +				skl_print_plane_ddb_changes(plane, old, new, "ddb_y");
>  		}
>  
>  		for_each_intel_plane_on_crtc(display->drm, crtc, plane) {

-- 
Jani Nikula, Intel

Re: [PATCH 8/9] drm/i915/wm: Include ddb_y in skl_print_wm_changes() on pre-icl

[Ville Syrjälä]

On Thu, Mar 19, 2026 at 03:44:29PM +0200, Jani Nikula wrote:
> On Thu, 19 Mar 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Pre-icl doesn't use a separate hardware plane for Y scanout,
> > and instead it's all handled magially by the hardware. We
> 
> *magically
> 
> > do still need to allocate DDB space for the Y color plane
> > though (PLANE_NV12_BUF_CFG). Include that information in the
> > debugs so that we know where it ended up.
> >
> > On icl+ the equivalent information is dumped as the hardware
> > Y plane's normal ddb allocation.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/skl_watermark.c | 11 +++++++++--
> >  1 file changed, 9 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> > index 8687026935e9..345767349988 100644
> > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> > @@ -2735,10 +2735,17 @@ skl_print_wm_changes(struct intel_atomic_state *state)
> >  			old = &old_crtc_state->wm.skl.plane_ddb[plane_id];
> >  			new = &new_crtc_state->wm.skl.plane_ddb[plane_id];
> >  
> > -			if (skl_ddb_entry_equal(old, new))
> > +			if (!skl_ddb_entry_equal(old, new))
> > +				skl_print_plane_ddb_changes(plane, old, new, "  ddb");
> 
> Superfluous whitespace in "  ddb"?

It's there to align the columns in the "ddb" and "ddb_y" prints.
Perhaps I should use the printk field width for that instead...

> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> 
> > +
> > +			if (DISPLAY_VER(display) >= 11)
> >  				continue;
> >  
> > -			skl_print_plane_ddb_changes(plane, old, new, "ddb");
> > +			old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
> > +			new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
> > +
> > +			if (!skl_ddb_entry_equal(old, new))
> > +				skl_print_plane_ddb_changes(plane, old, new, "ddb_y");
> >  		}
> >  
> >  		for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

[PATCH 9/9] drm/i915/wm: Include .min_ddb_alloc_uv in the wm dumps

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We include the Y/RGB .min_ddb_alloc in the wm state change dumps.
Do the same for .min_ddb_alloc_uv, on the platforms where it is
used.

Also adjust the whitespace in the other debug prints to keep
the values for each wm level lined up across all the lines.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 30 +++++++++++++++++---
 1 file changed, 26 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 345767349988..4725927acfd4 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2624,7 +2624,7 @@ skl_print_plane_wm_changes(struct intel_plane *plane,
 	struct intel_display *display = to_intel_display(plane);
 
 	drm_dbg_kms(display->drm,
-		    "[PLANE:%d:%s]   level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
+		    "[PLANE:%d:%s]      level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
 		    " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n",
 		    plane->base.base.id, plane->base.name,
 		    enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable),
@@ -2643,7 +2643,7 @@ skl_print_plane_wm_changes(struct intel_plane *plane,
 		    enast(new_wm->sagv.trans_wm.enable));
 
 	drm_dbg_kms(display->drm,
-		    "[PLANE:%d:%s]   lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d"
+		    "[PLANE:%d:%s]      lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d"
 		      " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n",
 		    plane->base.base.id, plane->base.name,
 		    enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines,
@@ -2670,7 +2670,7 @@ skl_print_plane_wm_changes(struct intel_plane *plane,
 		    enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines);
 
 	drm_dbg_kms(display->drm,
-		    "[PLANE:%d:%s]  blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
+		    "[PLANE:%d:%s]     blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
 		    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
 		    plane->base.base.id, plane->base.name,
 		    old_wm->wm[0].blocks, old_wm->wm[1].blocks,
@@ -2689,7 +2689,7 @@ skl_print_plane_wm_changes(struct intel_plane *plane,
 		    new_wm->sagv.trans_wm.blocks);
 
 	drm_dbg_kms(display->drm,
-		    "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
+		    "[PLANE:%d:%s]    min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
 		    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
 		    plane->base.base.id, plane->base.name,
 		    old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
@@ -2706,6 +2706,28 @@ skl_print_plane_wm_changes(struct intel_plane *plane,
 		    new_wm->trans_wm.min_ddb_alloc,
 		    new_wm->sagv.wm0.min_ddb_alloc,
 		    new_wm->sagv.trans_wm.min_ddb_alloc);
+
+	if (DISPLAY_VER(display) >= 11)
+		return;
+
+	drm_dbg_kms(display->drm,
+		    "[PLANE:%d:%s] min_ddb_uv %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
+		    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
+		    plane->base.base.id, plane->base.name,
+		    old_wm->wm[0].min_ddb_alloc_uv, old_wm->wm[1].min_ddb_alloc_uv,
+		    old_wm->wm[2].min_ddb_alloc_uv, old_wm->wm[3].min_ddb_alloc_uv,
+		    old_wm->wm[4].min_ddb_alloc_uv, old_wm->wm[5].min_ddb_alloc_uv,
+		    old_wm->wm[6].min_ddb_alloc_uv, old_wm->wm[7].min_ddb_alloc_uv,
+		    old_wm->trans_wm.min_ddb_alloc_uv,
+		    old_wm->sagv.wm0.min_ddb_alloc_uv,
+		    old_wm->sagv.trans_wm.min_ddb_alloc_uv,
+		    new_wm->wm[0].min_ddb_alloc_uv, new_wm->wm[1].min_ddb_alloc_uv,
+		    new_wm->wm[2].min_ddb_alloc_uv, new_wm->wm[3].min_ddb_alloc_uv,
+		    new_wm->wm[4].min_ddb_alloc_uv, new_wm->wm[5].min_ddb_alloc_uv,
+		    new_wm->wm[6].min_ddb_alloc_uv, new_wm->wm[7].min_ddb_alloc_uv,
+		    new_wm->trans_wm.min_ddb_alloc_uv,
+		    new_wm->sagv.wm0.min_ddb_alloc_uv,
+		    new_wm->sagv.trans_wm.min_ddb_alloc_uv);
 }
 
 static void
-- 
2.52.0

Re: [PATCH 9/9] drm/i915/wm: Include .min_ddb_alloc_uv in the wm dumps

[Jani Nikula]

On Thu, 19 Mar 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We include the Y/RGB .min_ddb_alloc in the wm state change dumps.
> Do the same for .min_ddb_alloc_uv, on the platforms where it is
> used.
>
> Also adjust the whitespace in the other debug prints to keep
> the values for each wm level lined up across all the lines.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 30 +++++++++++++++++---
>  1 file changed, 26 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 345767349988..4725927acfd4 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2624,7 +2624,7 @@ skl_print_plane_wm_changes(struct intel_plane *plane,
>  	struct intel_display *display = to_intel_display(plane);
>  
>  	drm_dbg_kms(display->drm,
> -		    "[PLANE:%d:%s]   level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
> +		    "[PLANE:%d:%s]      level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
>  		    " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n",
>  		    plane->base.base.id, plane->base.name,
>  		    enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable),
> @@ -2643,7 +2643,7 @@ skl_print_plane_wm_changes(struct intel_plane *plane,
>  		    enast(new_wm->sagv.trans_wm.enable));
>  
>  	drm_dbg_kms(display->drm,
> -		    "[PLANE:%d:%s]   lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d"
> +		    "[PLANE:%d:%s]      lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d"
>  		      " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n",
>  		    plane->base.base.id, plane->base.name,
>  		    enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines,
> @@ -2670,7 +2670,7 @@ skl_print_plane_wm_changes(struct intel_plane *plane,
>  		    enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines);
>  
>  	drm_dbg_kms(display->drm,
> -		    "[PLANE:%d:%s]  blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
> +		    "[PLANE:%d:%s]     blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
>  		    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
>  		    plane->base.base.id, plane->base.name,
>  		    old_wm->wm[0].blocks, old_wm->wm[1].blocks,
> @@ -2689,7 +2689,7 @@ skl_print_plane_wm_changes(struct intel_plane *plane,
>  		    new_wm->sagv.trans_wm.blocks);
>  
>  	drm_dbg_kms(display->drm,
> -		    "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
> +		    "[PLANE:%d:%s]    min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"

I wonder if the space changes would've been cleared with something like:

"[PLANE:%d:%s] min_ddb:   %4d...

but *shrug*.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>  		    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
>  		    plane->base.base.id, plane->base.name,
>  		    old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
> @@ -2706,6 +2706,28 @@ skl_print_plane_wm_changes(struct intel_plane *plane,
>  		    new_wm->trans_wm.min_ddb_alloc,
>  		    new_wm->sagv.wm0.min_ddb_alloc,
>  		    new_wm->sagv.trans_wm.min_ddb_alloc);
> +
> +	if (DISPLAY_VER(display) >= 11)
> +		return;
> +
> +	drm_dbg_kms(display->drm,
> +		    "[PLANE:%d:%s] min_ddb_uv %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
> +		    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
> +		    plane->base.base.id, plane->base.name,
> +		    old_wm->wm[0].min_ddb_alloc_uv, old_wm->wm[1].min_ddb_alloc_uv,
> +		    old_wm->wm[2].min_ddb_alloc_uv, old_wm->wm[3].min_ddb_alloc_uv,
> +		    old_wm->wm[4].min_ddb_alloc_uv, old_wm->wm[5].min_ddb_alloc_uv,
> +		    old_wm->wm[6].min_ddb_alloc_uv, old_wm->wm[7].min_ddb_alloc_uv,
> +		    old_wm->trans_wm.min_ddb_alloc_uv,
> +		    old_wm->sagv.wm0.min_ddb_alloc_uv,
> +		    old_wm->sagv.trans_wm.min_ddb_alloc_uv,
> +		    new_wm->wm[0].min_ddb_alloc_uv, new_wm->wm[1].min_ddb_alloc_uv,
> +		    new_wm->wm[2].min_ddb_alloc_uv, new_wm->wm[3].min_ddb_alloc_uv,
> +		    new_wm->wm[4].min_ddb_alloc_uv, new_wm->wm[5].min_ddb_alloc_uv,
> +		    new_wm->wm[6].min_ddb_alloc_uv, new_wm->wm[7].min_ddb_alloc_uv,
> +		    new_wm->trans_wm.min_ddb_alloc_uv,
> +		    new_wm->sagv.wm0.min_ddb_alloc_uv,
> +		    new_wm->sagv.trans_wm.min_ddb_alloc_uv);
>  }
>  
>  static void

-- 
Jani Nikula, Intel

✓ CI.KUnit: success for drm/i915/wm: Clean up pre-icl NV12 watermarks

[Patchwork]

== Series Details ==

Series: drm/i915/wm: Clean up pre-icl NV12 watermarks
URL   : https://patchwork.freedesktop.org/series/163523/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[11:46:46] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:46:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:47:21] Starting KUnit Kernel (1/1)...
[11:47:21] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:47:21] ================== guc_buf (11 subtests) ===================
[11:47:21] [PASSED] test_smallest
[11:47:21] [PASSED] test_largest
[11:47:21] [PASSED] test_granular
[11:47:21] [PASSED] test_unique
[11:47:21] [PASSED] test_overlap
[11:47:21] [PASSED] test_reusable
[11:47:21] [PASSED] test_too_big
[11:47:21] [PASSED] test_flush
[11:47:21] [PASSED] test_lookup
[11:47:21] [PASSED] test_data
[11:47:21] [PASSED] test_class
[11:47:21] ===================== [PASSED] guc_buf =====================
[11:47:21] =================== guc_dbm (7 subtests) ===================
[11:47:21] [PASSED] test_empty
[11:47:21] [PASSED] test_default
[11:47:21] ======================== test_size  ========================
[11:47:21] [PASSED] 4
[11:47:21] [PASSED] 8
[11:47:21] [PASSED] 32
[11:47:21] [PASSED] 256
[11:47:21] ==================== [PASSED] test_size ====================
[11:47:21] ======================= test_reuse  ========================
[11:47:21] [PASSED] 4
[11:47:21] [PASSED] 8
[11:47:21] [PASSED] 32
[11:47:21] [PASSED] 256
[11:47:21] =================== [PASSED] test_reuse ====================
[11:47:21] =================== test_range_overlap  ====================
[11:47:21] [PASSED] 4
[11:47:21] [PASSED] 8
[11:47:21] [PASSED] 32
[11:47:21] [PASSED] 256
[11:47:21] =============== [PASSED] test_range_overlap ================
[11:47:21] =================== test_range_compact  ====================
[11:47:21] [PASSED] 4
[11:47:21] [PASSED] 8
[11:47:21] [PASSED] 32
[11:47:21] [PASSED] 256
[11:47:21] =============== [PASSED] test_range_compact ================
[11:47:21] ==================== test_range_spare  =====================
[11:47:21] [PASSED] 4
[11:47:21] [PASSED] 8
[11:47:21] [PASSED] 32
[11:47:21] [PASSED] 256
[11:47:21] ================ [PASSED] test_range_spare =================
[11:47:21] ===================== [PASSED] guc_dbm =====================
[11:47:21] =================== guc_idm (6 subtests) ===================
[11:47:21] [PASSED] bad_init
[11:47:21] [PASSED] no_init
[11:47:21] [PASSED] init_fini
[11:47:21] [PASSED] check_used
[11:47:21] [PASSED] check_quota
[11:47:21] [PASSED] check_all
[11:47:21] ===================== [PASSED] guc_idm =====================
[11:47:21] ================== no_relay (3 subtests) ===================
[11:47:21] [PASSED] xe_drops_guc2pf_if_not_ready
[11:47:21] [PASSED] xe_drops_guc2vf_if_not_ready
[11:47:21] [PASSED] xe_rejects_send_if_not_ready
[11:47:21] ==================== [PASSED] no_relay =====================
[11:47:21] ================== pf_relay (14 subtests) ==================
[11:47:21] [PASSED] pf_rejects_guc2pf_too_short
[11:47:21] [PASSED] pf_rejects_guc2pf_too_long
[11:47:21] [PASSED] pf_rejects_guc2pf_no_payload
[11:47:21] [PASSED] pf_fails_no_payload
[11:47:21] [PASSED] pf_fails_bad_origin
[11:47:21] [PASSED] pf_fails_bad_type
[11:47:21] [PASSED] pf_txn_reports_error
[11:47:21] [PASSED] pf_txn_sends_pf2guc
[11:47:21] [PASSED] pf_sends_pf2guc
[11:47:21] [SKIPPED] pf_loopback_nop
[11:47:21] [SKIPPED] pf_loopback_echo
[11:47:21] [SKIPPED] pf_loopback_fail
[11:47:21] [SKIPPED] pf_loopback_busy
[11:47:21] [SKIPPED] pf_loopback_retry
[11:47:21] ==================== [PASSED] pf_relay =====================
[11:47:21] ================== vf_relay (3 subtests) ===================
[11:47:21] [PASSED] vf_rejects_guc2vf_too_short
[11:47:21] [PASSED] vf_rejects_guc2vf_too_long
[11:47:21] [PASSED] vf_rejects_guc2vf_no_payload
[11:47:21] ==================== [PASSED] vf_relay =====================
[11:47:21] ================ pf_gt_config (9 subtests) =================
[11:47:21] [PASSED] fair_contexts_1vf
[11:47:21] [PASSED] fair_doorbells_1vf
[11:47:21] [PASSED] fair_ggtt_1vf
[11:47:21] ====================== fair_vram_1vf  ======================
[11:47:21] [PASSED] 3.50 GiB
[11:47:21] [PASSED] 11.5 GiB
[11:47:21] [PASSED] 15.5 GiB
[11:47:21] [PASSED] 31.5 GiB
[11:47:21] [PASSED] 63.5 GiB
[11:47:21] [PASSED] 1.91 GiB
[11:47:21] ================== [PASSED] fair_vram_1vf ==================
[11:47:21] ================ fair_vram_1vf_admin_only  =================
[11:47:21] [PASSED] 3.50 GiB
[11:47:21] [PASSED] 11.5 GiB
[11:47:21] [PASSED] 15.5 GiB
[11:47:21] [PASSED] 31.5 GiB
[11:47:21] [PASSED] 63.5 GiB
[11:47:21] [PASSED] 1.91 GiB
[11:47:21] ============ [PASSED] fair_vram_1vf_admin_only =============
[11:47:21] ====================== fair_contexts  ======================
[11:47:21] [PASSED] 1 VF
[11:47:21] [PASSED] 2 VFs
[11:47:21] [PASSED] 3 VFs
[11:47:21] [PASSED] 4 VFs
[11:47:21] [PASSED] 5 VFs
[11:47:21] [PASSED] 6 VFs
[11:47:21] [PASSED] 7 VFs
[11:47:21] [PASSED] 8 VFs
[11:47:21] [PASSED] 9 VFs
[11:47:21] [PASSED] 10 VFs
[11:47:21] [PASSED] 11 VFs
[11:47:21] [PASSED] 12 VFs
[11:47:21] [PASSED] 13 VFs
[11:47:21] [PASSED] 14 VFs
[11:47:21] [PASSED] 15 VFs
[11:47:21] [PASSED] 16 VFs
[11:47:21] [PASSED] 17 VFs
[11:47:21] [PASSED] 18 VFs
[11:47:21] [PASSED] 19 VFs
[11:47:21] [PASSED] 20 VFs
[11:47:21] [PASSED] 21 VFs
[11:47:21] [PASSED] 22 VFs
[11:47:21] [PASSED] 23 VFs
[11:47:21] [PASSED] 24 VFs
[11:47:21] [PASSED] 25 VFs
[11:47:21] [PASSED] 26 VFs
[11:47:21] [PASSED] 27 VFs
[11:47:21] [PASSED] 28 VFs
[11:47:21] [PASSED] 29 VFs
[11:47:21] [PASSED] 30 VFs
[11:47:21] [PASSED] 31 VFs
[11:47:21] [PASSED] 32 VFs
[11:47:21] [PASSED] 33 VFs
[11:47:21] [PASSED] 34 VFs
[11:47:21] [PASSED] 35 VFs
[11:47:21] [PASSED] 36 VFs
[11:47:21] [PASSED] 37 VFs
[11:47:21] [PASSED] 38 VFs
[11:47:21] [PASSED] 39 VFs
[11:47:21] [PASSED] 40 VFs
[11:47:21] [PASSED] 41 VFs
[11:47:21] [PASSED] 42 VFs
[11:47:21] [PASSED] 43 VFs
[11:47:21] [PASSED] 44 VFs
[11:47:21] [PASSED] 45 VFs
[11:47:21] [PASSED] 46 VFs
[11:47:21] [PASSED] 47 VFs
[11:47:21] [PASSED] 48 VFs
[11:47:21] [PASSED] 49 VFs
[11:47:21] [PASSED] 50 VFs
[11:47:21] [PASSED] 51 VFs
[11:47:21] [PASSED] 52 VFs
[11:47:21] [PASSED] 53 VFs
[11:47:21] [PASSED] 54 VFs
[11:47:21] [PASSED] 55 VFs
[11:47:21] [PASSED] 56 VFs
[11:47:21] [PASSED] 57 VFs
[11:47:21] [PASSED] 58 VFs
[11:47:21] [PASSED] 59 VFs
[11:47:21] [PASSED] 60 VFs
[11:47:21] [PASSED] 61 VFs
[11:47:21] [PASSED] 62 VFs
[11:47:21] [PASSED] 63 VFs
[11:47:21] ================== [PASSED] fair_contexts ==================
[11:47:21] ===================== fair_doorbells  ======================
[11:47:21] [PASSED] 1 VF
[11:47:21] [PASSED] 2 VFs
[11:47:21] [PASSED] 3 VFs
[11:47:21] [PASSED] 4 VFs
[11:47:21] [PASSED] 5 VFs
[11:47:21] [PASSED] 6 VFs
[11:47:21] [PASSED] 7 VFs
[11:47:21] [PASSED] 8 VFs
[11:47:21] [PASSED] 9 VFs
[11:47:21] [PASSED] 10 VFs
[11:47:21] [PASSED] 11 VFs
[11:47:21] [PASSED] 12 VFs
[11:47:21] [PASSED] 13 VFs
[11:47:21] [PASSED] 14 VFs
[11:47:21] [PASSED] 15 VFs
[11:47:21] [PASSED] 16 VFs
[11:47:21] [PASSED] 17 VFs
[11:47:21] [PASSED] 18 VFs
[11:47:21] [PASSED] 19 VFs
[11:47:21] [PASSED] 20 VFs
[11:47:21] [PASSED] 21 VFs
[11:47:21] [PASSED] 22 VFs
[11:47:21] [PASSED] 23 VFs
[11:47:21] [PASSED] 24 VFs
[11:47:21] [PASSED] 25 VFs
[11:47:21] [PASSED] 26 VFs
[11:47:21] [PASSED] 27 VFs
[11:47:21] [PASSED] 28 VFs
[11:47:21] [PASSED] 29 VFs
[11:47:21] [PASSED] 30 VFs
[11:47:21] [PASSED] 31 VFs
[11:47:21] [PASSED] 32 VFs
[11:47:21] [PASSED] 33 VFs
[11:47:21] [PASSED] 34 VFs
[11:47:21] [PASSED] 35 VFs
[11:47:21] [PASSED] 36 VFs
[11:47:21] [PASSED] 37 VFs
[11:47:21] [PASSED] 38 VFs
[11:47:21] [PASSED] 39 VFs
[11:47:21] [PASSED] 40 VFs
[11:47:21] [PASSED] 41 VFs
[11:47:21] [PASSED] 42 VFs
[11:47:21] [PASSED] 43 VFs
[11:47:21] [PASSED] 44 VFs
[11:47:21] [PASSED] 45 VFs
[11:47:21] [PASSED] 46 VFs
[11:47:21] [PASSED] 47 VFs
[11:47:21] [PASSED] 48 VFs
[11:47:21] [PASSED] 49 VFs
[11:47:21] [PASSED] 50 VFs
[11:47:21] [PASSED] 51 VFs
[11:47:21] [PASSED] 52 VFs
[11:47:21] [PASSED] 53 VFs
[11:47:21] [PASSED] 54 VFs
[11:47:21] [PASSED] 55 VFs
[11:47:21] [PASSED] 56 VFs
[11:47:21] [PASSED] 57 VFs
[11:47:21] [PASSED] 58 VFs
[11:47:21] [PASSED] 59 VFs
[11:47:21] [PASSED] 60 VFs
[11:47:21] [PASSED] 61 VFs
[11:47:21] [PASSED] 62 VFs
[11:47:21] [PASSED] 63 VFs
[11:47:21] ================= [PASSED] fair_doorbells ==================
[11:47:21] ======================== fair_ggtt  ========================
[11:47:21] [PASSED] 1 VF
[11:47:21] [PASSED] 2 VFs
[11:47:21] [PASSED] 3 VFs
[11:47:21] [PASSED] 4 VFs
[11:47:21] [PASSED] 5 VFs
[11:47:21] [PASSED] 6 VFs
[11:47:21] [PASSED] 7 VFs
[11:47:21] [PASSED] 8 VFs
[11:47:21] [PASSED] 9 VFs
[11:47:21] [PASSED] 10 VFs
[11:47:21] [PASSED] 11 VFs
[11:47:21] [PASSED] 12 VFs
[11:47:21] [PASSED] 13 VFs
[11:47:21] [PASSED] 14 VFs
[11:47:21] [PASSED] 15 VFs
[11:47:21] [PASSED] 16 VFs
[11:47:21] [PASSED] 17 VFs
[11:47:21] [PASSED] 18 VFs
[11:47:21] [PASSED] 19 VFs
[11:47:21] [PASSED] 20 VFs
[11:47:21] [PASSED] 21 VFs
[11:47:21] [PASSED] 22 VFs
[11:47:21] [PASSED] 23 VFs
[11:47:21] [PASSED] 24 VFs
[11:47:21] [PASSED] 25 VFs
[11:47:21] [PASSED] 26 VFs
[11:47:21] [PASSED] 27 VFs
[11:47:21] [PASSED] 28 VFs
[11:47:21] [PASSED] 29 VFs
[11:47:21] [PASSED] 30 VFs
[11:47:21] [PASSED] 31 VFs
[11:47:21] [PASSED] 32 VFs
[11:47:21] [PASSED] 33 VFs
[11:47:21] [PASSED] 34 VFs
[11:47:21] [PASSED] 35 VFs
[11:47:21] [PASSED] 36 VFs
[11:47:21] [PASSED] 37 VFs
[11:47:21] [PASSED] 38 VFs
[11:47:21] [PASSED] 39 VFs
[11:47:21] [PASSED] 40 VFs
[11:47:21] [PASSED] 41 VFs
[11:47:21] [PASSED] 42 VFs
[11:47:21] [PASSED] 43 VFs
[11:47:21] [PASSED] 44 VFs
[11:47:21] [PASSED] 45 VFs
[11:47:21] [PASSED] 46 VFs
[11:47:21] [PASSED] 47 VFs
[11:47:21] [PASSED] 48 VFs
[11:47:21] [PASSED] 49 VFs
[11:47:21] [PASSED] 50 VFs
[11:47:21] [PASSED] 51 VFs
[11:47:21] [PASSED] 52 VFs
[11:47:21] [PASSED] 53 VFs
[11:47:21] [PASSED] 54 VFs
[11:47:21] [PASSED] 55 VFs
[11:47:21] [PASSED] 56 VFs
[11:47:21] [PASSED] 57 VFs
[11:47:21] [PASSED] 58 VFs
[11:47:21] [PASSED] 59 VFs
[11:47:21] [PASSED] 60 VFs
[11:47:21] [PASSED] 61 VFs
[11:47:21] [PASSED] 62 VFs
[11:47:21] [PASSED] 63 VFs
[11:47:21] ==================== [PASSED] fair_ggtt ====================
[11:47:21] ======================== fair_vram  ========================
[11:47:21] [PASSED] 1 VF
[11:47:21] [PASSED] 2 VFs
[11:47:21] [PASSED] 3 VFs
[11:47:21] [PASSED] 4 VFs
[11:47:21] [PASSED] 5 VFs
[11:47:21] [PASSED] 6 VFs
[11:47:21] [PASSED] 7 VFs
[11:47:21] [PASSED] 8 VFs
[11:47:21] [PASSED] 9 VFs
[11:47:21] [PASSED] 10 VFs
[11:47:21] [PASSED] 11 VFs
[11:47:21] [PASSED] 12 VFs
[11:47:21] [PASSED] 13 VFs
[11:47:21] [PASSED] 14 VFs
[11:47:21] [PASSED] 15 VFs
[11:47:21] [PASSED] 16 VFs
[11:47:21] [PASSED] 17 VFs
[11:47:21] [PASSED] 18 VFs
[11:47:21] [PASSED] 19 VFs
[11:47:21] [PASSED] 20 VFs
[11:47:21] [PASSED] 21 VFs
[11:47:21] [PASSED] 22 VFs
[11:47:21] [PASSED] 23 VFs
[11:47:21] [PASSED] 24 VFs
[11:47:21] [PASSED] 25 VFs
[11:47:21] [PASSED] 26 VFs
[11:47:21] [PASSED] 27 VFs
[11:47:21] [PASSED] 28 VFs
[11:47:21] [PASSED] 29 VFs
[11:47:21] [PASSED] 30 VFs
[11:47:21] [PASSED] 31 VFs
[11:47:21] [PASSED] 32 VFs
[11:47:21] [PASSED] 33 VFs
[11:47:21] [PASSED] 34 VFs
[11:47:21] [PASSED] 35 VFs
[11:47:21] [PASSED] 36 VFs
[11:47:21] [PASSED] 37 VFs
[11:47:21] [PASSED] 38 VFs
[11:47:21] [PASSED] 39 VFs
[11:47:21] [PASSED] 40 VFs
[11:47:21] [PASSED] 41 VFs
[11:47:21] [PASSED] 42 VFs
[11:47:21] [PASSED] 43 VFs
[11:47:21] [PASSED] 44 VFs
[11:47:21] [PASSED] 45 VFs
[11:47:21] [PASSED] 46 VFs
[11:47:21] [PASSED] 47 VFs
[11:47:21] [PASSED] 48 VFs
[11:47:21] [PASSED] 49 VFs
[11:47:21] [PASSED] 50 VFs
[11:47:21] [PASSED] 51 VFs
[11:47:21] [PASSED] 52 VFs
[11:47:21] [PASSED] 53 VFs
[11:47:21] [PASSED] 54 VFs
[11:47:21] [PASSED] 55 VFs
[11:47:21] [PASSED] 56 VFs
[11:47:21] [PASSED] 57 VFs
[11:47:21] [PASSED] 58 VFs
[11:47:21] [PASSED] 59 VFs
[11:47:21] [PASSED] 60 VFs
[11:47:21] [PASSED] 61 VFs
[11:47:21] [PASSED] 62 VFs
[11:47:21] [PASSED] 63 VFs
[11:47:21] ==================== [PASSED] fair_vram ====================
[11:47:21] ================== [PASSED] pf_gt_config ===================
[11:47:21] ===================== lmtt (1 subtest) =====================
[11:47:21] ======================== test_ops  =========================
[11:47:21] [PASSED] 2-level
[11:47:21] [PASSED] multi-level
[11:47:21] ==================== [PASSED] test_ops =====================
[11:47:21] ====================== [PASSED] lmtt =======================
[11:47:21] ================= pf_service (11 subtests) =================
[11:47:21] [PASSED] pf_negotiate_any
[11:47:21] [PASSED] pf_negotiate_base_match
[11:47:21] [PASSED] pf_negotiate_base_newer
[11:47:21] [PASSED] pf_negotiate_base_next
[11:47:21] [SKIPPED] pf_negotiate_base_older
[11:47:21] [PASSED] pf_negotiate_base_prev
[11:47:21] [PASSED] pf_negotiate_latest_match
[11:47:21] [PASSED] pf_negotiate_latest_newer
[11:47:21] [PASSED] pf_negotiate_latest_next
[11:47:21] [SKIPPED] pf_negotiate_latest_older
[11:47:21] [SKIPPED] pf_negotiate_latest_prev
[11:47:21] =================== [PASSED] pf_service ====================
[11:47:21] ================= xe_guc_g2g (2 subtests) ==================
[11:47:21] ============== xe_live_guc_g2g_kunit_default  ==============
[11:47:21] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[11:47:21] ============== xe_live_guc_g2g_kunit_allmem  ===============
[11:47:21] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[11:47:21] =================== [SKIPPED] xe_guc_g2g ===================
[11:47:21] =================== xe_mocs (2 subtests) ===================
[11:47:21] ================ xe_live_mocs_kernel_kunit  ================
[11:47:21] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[11:47:21] ================ xe_live_mocs_reset_kunit  =================
[11:47:21] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[11:47:21] ==================== [SKIPPED] xe_mocs =====================
[11:47:21] ================= xe_migrate (2 subtests) ==================
[11:47:21] ================= xe_migrate_sanity_kunit  =================
[11:47:21] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[11:47:21] ================== xe_validate_ccs_kunit  ==================
[11:47:21] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[11:47:21] =================== [SKIPPED] xe_migrate ===================
[11:47:21] ================== xe_dma_buf (1 subtest) ==================
[11:47:21] ==================== xe_dma_buf_kunit  =====================
[11:47:21] ================ [SKIPPED] xe_dma_buf_kunit ================
[11:47:21] =================== [SKIPPED] xe_dma_buf ===================
[11:47:21] ================= xe_bo_shrink (1 subtest) =================
[11:47:21] =================== xe_bo_shrink_kunit  ====================
[11:47:21] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[11:47:21] ================== [SKIPPED] xe_bo_shrink ==================
[11:47:21] ==================== xe_bo (2 subtests) ====================
[11:47:21] ================== xe_ccs_migrate_kunit  ===================
[11:47:21] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[11:47:21] ==================== xe_bo_evict_kunit  ====================
[11:47:21] =============== [SKIPPED] xe_bo_evict_kunit ================
[11:47:21] ===================== [SKIPPED] xe_bo ======================
[11:47:21] ==================== args (13 subtests) ====================
[11:47:21] [PASSED] count_args_test
[11:47:21] [PASSED] call_args_example
[11:47:21] [PASSED] call_args_test
[11:47:21] [PASSED] drop_first_arg_example
[11:47:21] [PASSED] drop_first_arg_test
[11:47:21] [PASSED] first_arg_example
[11:47:21] [PASSED] first_arg_test
[11:47:21] [PASSED] last_arg_example
[11:47:21] [PASSED] last_arg_test
[11:47:21] [PASSED] pick_arg_example
[11:47:21] [PASSED] if_args_example
[11:47:21] [PASSED] if_args_test
[11:47:21] [PASSED] sep_comma_example
[11:47:21] ====================== [PASSED] args =======================
[11:47:21] =================== xe_pci (3 subtests) ====================
[11:47:21] ==================== check_graphics_ip  ====================
[11:47:21] [PASSED] 12.00 Xe_LP
[11:47:21] [PASSED] 12.10 Xe_LP+
[11:47:21] [PASSED] 12.55 Xe_HPG
[11:47:21] [PASSED] 12.60 Xe_HPC
[11:47:21] [PASSED] 12.70 Xe_LPG
[11:47:21] [PASSED] 12.71 Xe_LPG
[11:47:21] [PASSED] 12.74 Xe_LPG+
[11:47:21] [PASSED] 20.01 Xe2_HPG
[11:47:21] [PASSED] 20.02 Xe2_HPG
[11:47:21] [PASSED] 20.04 Xe2_LPG
[11:47:21] [PASSED] 30.00 Xe3_LPG
[11:47:21] [PASSED] 30.01 Xe3_LPG
[11:47:21] [PASSED] 30.03 Xe3_LPG
[11:47:21] [PASSED] 30.04 Xe3_LPG
[11:47:21] [PASSED] 30.05 Xe3_LPG
[11:47:21] [PASSED] 35.10 Xe3p_LPG
[11:47:21] [PASSED] 35.11 Xe3p_XPC
[11:47:21] ================ [PASSED] check_graphics_ip ================
[11:47:21] ===================== check_media_ip  ======================
[11:47:21] [PASSED] 12.00 Xe_M
[11:47:21] [PASSED] 12.55 Xe_HPM
[11:47:21] [PASSED] 13.00 Xe_LPM+
[11:47:21] [PASSED] 13.01 Xe2_HPM
[11:47:21] [PASSED] 20.00 Xe2_LPM
[11:47:21] [PASSED] 30.00 Xe3_LPM
[11:47:21] [PASSED] 30.02 Xe3_LPM
[11:47:21] [PASSED] 35.00 Xe3p_LPM
[11:47:21] [PASSED] 35.03 Xe3p_HPM
[11:47:21] ================= [PASSED] check_media_ip ==================
[11:47:21] =================== check_platform_desc  ===================
[11:47:21] [PASSED] 0x9A60 (TIGERLAKE)
[11:47:21] [PASSED] 0x9A68 (TIGERLAKE)
[11:47:21] [PASSED] 0x9A70 (TIGERLAKE)
[11:47:21] [PASSED] 0x9A40 (TIGERLAKE)
[11:47:21] [PASSED] 0x9A49 (TIGERLAKE)
[11:47:21] [PASSED] 0x9A59 (TIGERLAKE)
[11:47:21] [PASSED] 0x9A78 (TIGERLAKE)
[11:47:21] [PASSED] 0x9AC0 (TIGERLAKE)
[11:47:21] [PASSED] 0x9AC9 (TIGERLAKE)
[11:47:21] [PASSED] 0x9AD9 (TIGERLAKE)
[11:47:21] [PASSED] 0x9AF8 (TIGERLAKE)
[11:47:21] [PASSED] 0x4C80 (ROCKETLAKE)
[11:47:21] [PASSED] 0x4C8A (ROCKETLAKE)
[11:47:21] [PASSED] 0x4C8B (ROCKETLAKE)
[11:47:21] [PASSED] 0x4C8C (ROCKETLAKE)
[11:47:21] [PASSED] 0x4C90 (ROCKETLAKE)
[11:47:21] [PASSED] 0x4C9A (ROCKETLAKE)
[11:47:21] [PASSED] 0x4680 (ALDERLAKE_S)
[11:47:21] [PASSED] 0x4682 (ALDERLAKE_S)
[11:47:21] [PASSED] 0x4688 (ALDERLAKE_S)
[11:47:21] [PASSED] 0x468A (ALDERLAKE_S)
[11:47:21] [PASSED] 0x468B (ALDERLAKE_S)
[11:47:21] [PASSED] 0x4690 (ALDERLAKE_S)
[11:47:21] [PASSED] 0x4692 (ALDERLAKE_S)
[11:47:21] [PASSED] 0x4693 (ALDERLAKE_S)
[11:47:21] [PASSED] 0x46A0 (ALDERLAKE_P)
[11:47:21] [PASSED] 0x46A1 (ALDERLAKE_P)
[11:47:21] [PASSED] 0x46A2 (ALDERLAKE_P)
[11:47:21] [PASSED] 0x46A3 (ALDERLAKE_P)
[11:47:21] [PASSED] 0x46A6 (ALDERLAKE_P)
[11:47:21] [PASSED] 0x46A8 (ALDERLAKE_P)
[11:47:21] [PASSED] 0x46AA (ALDERLAKE_P)
[11:47:21] [PASSED] 0x462A (ALDERLAKE_P)
[11:47:21] [PASSED] 0x4626 (ALDERLAKE_P)
[11:47:21] [PASSED] 0x4628 (ALDERLAKE_P)
[11:47:21] [PASSED] 0x46B0 (ALDERLAKE_P)
[11:47:21] [PASSED] 0x46B1 (ALDERLAKE_P)
[11:47:21] [PASSED] 0x46B2 (ALDERLAKE_P)
[11:47:21] [PASSED] 0x46B3 (ALDERLAKE_P)
[11:47:21] [PASSED] 0x46C0 (ALDERLAKE_P)
[11:47:21] [PASSED] 0x46C1 (ALDERLAKE_P)
[11:47:21] [PASSED] 0x46C2 (ALDERLAKE_P)
[11:47:21] [PASSED] 0x46C3 (ALDERLAKE_P)
[11:47:21] [PASSED] 0x46D0 (ALDERLAKE_N)
[11:47:21] [PASSED] 0x46D1 (ALDERLAKE_N)
[11:47:21] [PASSED] 0x46D2 (ALDERLAKE_N)
[11:47:21] [PASSED] 0x46D3 (ALDERLAKE_N)
[11:47:21] [PASSED] 0x46D4 (ALDERLAKE_N)
[11:47:21] [PASSED] 0xA721 (ALDERLAKE_P)
[11:47:21] [PASSED] 0xA7A1 (ALDERLAKE_P)
[11:47:21] [PASSED] 0xA7A9 (ALDERLAKE_P)
[11:47:21] [PASSED] 0xA7AC (ALDERLAKE_P)
[11:47:21] [PASSED] 0xA7AD (ALDERLAKE_P)
[11:47:21] [PASSED] 0xA720 (ALDERLAKE_P)
[11:47:21] [PASSED] 0xA7A0 (ALDERLAKE_P)
[11:47:21] [PASSED] 0xA7A8 (ALDERLAKE_P)
[11:47:21] [PASSED] 0xA7AA (ALDERLAKE_P)
[11:47:21] [PASSED] 0xA7AB (ALDERLAKE_P)
[11:47:21] [PASSED] 0xA780 (ALDERLAKE_S)
[11:47:21] [PASSED] 0xA781 (ALDERLAKE_S)
[11:47:21] [PASSED] 0xA782 (ALDERLAKE_S)
[11:47:21] [PASSED] 0xA783 (ALDERLAKE_S)
[11:47:21] [PASSED] 0xA788 (ALDERLAKE_S)
[11:47:21] [PASSED] 0xA789 (ALDERLAKE_S)
[11:47:21] [PASSED] 0xA78A (ALDERLAKE_S)
[11:47:21] [PASSED] 0xA78B (ALDERLAKE_S)
[11:47:21] [PASSED] 0x4905 (DG1)
[11:47:21] [PASSED] 0x4906 (DG1)
[11:47:21] [PASSED] 0x4907 (DG1)
[11:47:21] [PASSED] 0x4908 (DG1)
[11:47:21] [PASSED] 0x4909 (DG1)
[11:47:21] [PASSED] 0x56C0 (DG2)
[11:47:21] [PASSED] 0x56C2 (DG2)
[11:47:21] [PASSED] 0x56C1 (DG2)
[11:47:21] [PASSED] 0x7D51 (METEORLAKE)
[11:47:21] [PASSED] 0x7DD1 (METEORLAKE)
[11:47:21] [PASSED] 0x7D41 (METEORLAKE)
[11:47:21] [PASSED] 0x7D67 (METEORLAKE)
[11:47:21] [PASSED] 0xB640 (METEORLAKE)
[11:47:21] [PASSED] 0x56A0 (DG2)
[11:47:21] [PASSED] 0x56A1 (DG2)
[11:47:21] [PASSED] 0x56A2 (DG2)
[11:47:21] [PASSED] 0x56BE (DG2)
[11:47:21] [PASSED] 0x56BF (DG2)
[11:47:21] [PASSED] 0x5690 (DG2)
[11:47:21] [PASSED] 0x5691 (DG2)
[11:47:21] [PASSED] 0x5692 (DG2)
[11:47:21] [PASSED] 0x56A5 (DG2)
[11:47:21] [PASSED] 0x56A6 (DG2)
[11:47:21] [PASSED] 0x56B0 (DG2)
[11:47:21] [PASSED] 0x56B1 (DG2)
[11:47:21] [PASSED] 0x56BA (DG2)
[11:47:21] [PASSED] 0x56BB (DG2)
[11:47:21] [PASSED] 0x56BC (DG2)
[11:47:21] [PASSED] 0x56BD (DG2)
[11:47:21] [PASSED] 0x5693 (DG2)
[11:47:21] [PASSED] 0x5694 (DG2)
[11:47:21] [PASSED] 0x5695 (DG2)
[11:47:21] [PASSED] 0x56A3 (DG2)
[11:47:21] [PASSED] 0x56A4 (DG2)
[11:47:21] [PASSED] 0x56B2 (DG2)
[11:47:21] [PASSED] 0x56B3 (DG2)
[11:47:21] [PASSED] 0x5696 (DG2)
[11:47:21] [PASSED] 0x5697 (DG2)
[11:47:21] [PASSED] 0xB69 (PVC)
[11:47:21] [PASSED] 0xB6E (PVC)
[11:47:21] [PASSED] 0xBD4 (PVC)
[11:47:21] [PASSED] 0xBD5 (PVC)
[11:47:21] [PASSED] 0xBD6 (PVC)
[11:47:21] [PASSED] 0xBD7 (PVC)
[11:47:21] [PASSED] 0xBD8 (PVC)
[11:47:21] [PASSED] 0xBD9 (PVC)
[11:47:21] [PASSED] 0xBDA (PVC)
[11:47:21] [PASSED] 0xBDB (PVC)
[11:47:21] [PASSED] 0xBE0 (PVC)
[11:47:21] [PASSED] 0xBE1 (PVC)
[11:47:21] [PASSED] 0xBE5 (PVC)
[11:47:21] [PASSED] 0x7D40 (METEORLAKE)
[11:47:21] [PASSED] 0x7D45 (METEORLAKE)
[11:47:21] [PASSED] 0x7D55 (METEORLAKE)
[11:47:21] [PASSED] 0x7D60 (METEORLAKE)
[11:47:21] [PASSED] 0x7DD5 (METEORLAKE)
[11:47:21] [PASSED] 0x6420 (LUNARLAKE)
[11:47:21] [PASSED] 0x64A0 (LUNARLAKE)
[11:47:21] [PASSED] 0x64B0 (LUNARLAKE)
[11:47:21] [PASSED] 0xE202 (BATTLEMAGE)
[11:47:21] [PASSED] 0xE209 (BATTLEMAGE)
[11:47:21] [PASSED] 0xE20B (BATTLEMAGE)
[11:47:21] [PASSED] 0xE20C (BATTLEMAGE)
[11:47:21] [PASSED] 0xE20D (BATTLEMAGE)
[11:47:21] [PASSED] 0xE210 (BATTLEMAGE)
[11:47:21] [PASSED] 0xE211 (BATTLEMAGE)
[11:47:21] [PASSED] 0xE212 (BATTLEMAGE)
[11:47:21] [PASSED] 0xE216 (BATTLEMAGE)
[11:47:21] [PASSED] 0xE220 (BATTLEMAGE)
[11:47:21] [PASSED] 0xE221 (BATTLEMAGE)
[11:47:21] [PASSED] 0xE222 (BATTLEMAGE)
[11:47:21] [PASSED] 0xE223 (BATTLEMAGE)
[11:47:21] [PASSED] 0xB080 (PANTHERLAKE)
[11:47:21] [PASSED] 0xB081 (PANTHERLAKE)
[11:47:21] [PASSED] 0xB082 (PANTHERLAKE)
[11:47:21] [PASSED] 0xB083 (PANTHERLAKE)
[11:47:21] [PASSED] 0xB084 (PANTHERLAKE)
[11:47:21] [PASSED] 0xB085 (PANTHERLAKE)
[11:47:21] [PASSED] 0xB086 (PANTHERLAKE)
[11:47:21] [PASSED] 0xB087 (PANTHERLAKE)
[11:47:21] [PASSED] 0xB08F (PANTHERLAKE)
[11:47:21] [PASSED] 0xB090 (PANTHERLAKE)
[11:47:21] [PASSED] 0xB0A0 (PANTHERLAKE)
[11:47:21] [PASSED] 0xB0B0 (PANTHERLAKE)
[11:47:21] [PASSED] 0xFD80 (PANTHERLAKE)
[11:47:21] [PASSED] 0xFD81 (PANTHERLAKE)
[11:47:21] [PASSED] 0xD740 (NOVALAKE_S)
[11:47:21] [PASSED] 0xD741 (NOVALAKE_S)
[11:47:21] [PASSED] 0xD742 (NOVALAKE_S)
[11:47:21] [PASSED] 0xD743 (NOVALAKE_S)
[11:47:21] [PASSED] 0xD744 (NOVALAKE_S)
[11:47:21] [PASSED] 0xD745 (NOVALAKE_S)
[11:47:21] [PASSED] 0x674C (CRESCENTISLAND)
[11:47:21] [PASSED] 0xD750 (NOVALAKE_P)
[11:47:21] [PASSED] 0xD751 (NOVALAKE_P)
[11:47:21] [PASSED] 0xD752 (NOVALAKE_P)
[11:47:21] [PASSED] 0xD753 (NOVALAKE_P)
[11:47:21] [PASSED] 0xD754 (NOVALAKE_P)
[11:47:21] [PASSED] 0xD755 (NOVALAKE_P)
[11:47:21] [PASSED] 0xD756 (NOVALAKE_P)
[11:47:21] [PASSED] 0xD757 (NOVALAKE_P)
[11:47:21] [PASSED] 0xD75F (NOVALAKE_P)
[11:47:21] =============== [PASSED] check_platform_desc ===============
[11:47:21] ===================== [PASSED] xe_pci ======================
[11:47:21] =================== xe_rtp (2 subtests) ====================
[11:47:21] =============== xe_rtp_process_to_sr_tests  ================
[11:47:21] [PASSED] coalesce-same-reg
[11:47:21] [PASSED] no-match-no-add
[11:47:21] [PASSED] match-or
[11:47:21] [PASSED] match-or-xfail
[11:47:21] [PASSED] no-match-no-add-multiple-rules
[11:47:21] [PASSED] two-regs-two-entries
[11:47:21] [PASSED] clr-one-set-other
[11:47:21] [PASSED] set-field
[11:47:21] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[11:47:21] [PASSED] conflict-not-disjoint
[11:47:21] [PASSED] conflict-reg-type
[11:47:21] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[11:47:21] ================== xe_rtp_process_tests  ===================
[11:47:21] [PASSED] active1
[11:47:21] [PASSED] active2
[11:47:21] [PASSED] active-inactive
[11:47:21] [PASSED] inactive-active
[11:47:21] [PASSED] inactive-1st_or_active-inactive
[11:47:21] [PASSED] inactive-2nd_or_active-inactive
[11:47:21] [PASSED] inactive-last_or_active-inactive
[11:47:21] [PASSED] inactive-no_or_active-inactive
[11:47:21] ============== [PASSED] xe_rtp_process_tests ===============
[11:47:21] ===================== [PASSED] xe_rtp ======================
[11:47:21] ==================== xe_wa (1 subtest) =====================
[11:47:21] ======================== xe_wa_gt  =========================
[11:47:21] [PASSED] TIGERLAKE B0
[11:47:21] [PASSED] DG1 A0
[11:47:21] [PASSED] DG1 B0
[11:47:21] [PASSED] ALDERLAKE_S A0
[11:47:21] [PASSED] ALDERLAKE_S B0
[11:47:21] [PASSED] ALDERLAKE_S C0
[11:47:21] [PASSED] ALDERLAKE_S D0
[11:47:21] [PASSED] ALDERLAKE_P A0
[11:47:21] [PASSED] ALDERLAKE_P B0
[11:47:21] [PASSED] ALDERLAKE_P C0
[11:47:21] [PASSED] ALDERLAKE_S RPLS D0
[11:47:21] [PASSED] ALDERLAKE_P RPLU E0
[11:47:21] [PASSED] DG2 G10 C0
[11:47:21] [PASSED] DG2 G11 B1
[11:47:21] [PASSED] DG2 G12 A1
[11:47:21] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:47:21] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:47:21] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[11:47:21] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[11:47:21] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[11:47:21] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[11:47:21] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[11:47:21] ==================== [PASSED] xe_wa_gt =====================
[11:47:21] ====================== [PASSED] xe_wa ======================
[11:47:21] ============================================================
[11:47:21] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[11:47:21] Elapsed time: 35.428s total, 4.254s configuring, 30.557s building, 0.603s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[11:47:21] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:47:23] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:47:47] Starting KUnit Kernel (1/1)...
[11:47:47] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:47:47] ============ drm_test_pick_cmdline (2 subtests) ============
[11:47:47] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[11:47:47] =============== drm_test_pick_cmdline_named  ===============
[11:47:47] [PASSED] NTSC
[11:47:47] [PASSED] NTSC-J
[11:47:47] [PASSED] PAL
[11:47:47] [PASSED] PAL-M
[11:47:47] =========== [PASSED] drm_test_pick_cmdline_named ===========
[11:47:47] ============== [PASSED] drm_test_pick_cmdline ==============
[11:47:47] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[11:47:47] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[11:47:47] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[11:47:47] =========== drm_validate_clone_mode (2 subtests) ===========
[11:47:47] ============== drm_test_check_in_clone_mode  ===============
[11:47:47] [PASSED] in_clone_mode
[11:47:47] [PASSED] not_in_clone_mode
[11:47:47] ========== [PASSED] drm_test_check_in_clone_mode ===========
[11:47:47] =============== drm_test_check_valid_clones  ===============
[11:47:47] [PASSED] not_in_clone_mode
[11:47:47] [PASSED] valid_clone
[11:47:47] [PASSED] invalid_clone
[11:47:47] =========== [PASSED] drm_test_check_valid_clones ===========
[11:47:47] ============= [PASSED] drm_validate_clone_mode =============
[11:47:47] ============= drm_validate_modeset (1 subtest) =============
[11:47:47] [PASSED] drm_test_check_connector_changed_modeset
[11:47:47] ============== [PASSED] drm_validate_modeset ===============
[11:47:47] ====== drm_test_bridge_get_current_state (2 subtests) ======
[11:47:47] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[11:47:47] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[11:47:47] ======== [PASSED] drm_test_bridge_get_current_state ========
[11:47:47] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[11:47:47] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[11:47:47] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[11:47:47] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[11:47:47] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[11:47:47] ============== drm_bridge_alloc (2 subtests) ===============
[11:47:47] [PASSED] drm_test_drm_bridge_alloc_basic
[11:47:47] [PASSED] drm_test_drm_bridge_alloc_get_put
[11:47:47] ================ [PASSED] drm_bridge_alloc =================
[11:47:47] ============= drm_cmdline_parser (40 subtests) =============
[11:47:47] [PASSED] drm_test_cmdline_force_d_only
[11:47:47] [PASSED] drm_test_cmdline_force_D_only_dvi
[11:47:47] [PASSED] drm_test_cmdline_force_D_only_hdmi
[11:47:47] [PASSED] drm_test_cmdline_force_D_only_not_digital
[11:47:47] [PASSED] drm_test_cmdline_force_e_only
[11:47:47] [PASSED] drm_test_cmdline_res
[11:47:47] [PASSED] drm_test_cmdline_res_vesa
[11:47:47] [PASSED] drm_test_cmdline_res_vesa_rblank
[11:47:47] [PASSED] drm_test_cmdline_res_rblank
[11:47:47] [PASSED] drm_test_cmdline_res_bpp
[11:47:47] [PASSED] drm_test_cmdline_res_refresh
[11:47:47] [PASSED] drm_test_cmdline_res_bpp_refresh
[11:47:47] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[11:47:47] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[11:47:47] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[11:47:47] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[11:47:47] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[11:47:47] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[11:47:47] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[11:47:47] [PASSED] drm_test_cmdline_res_margins_force_on
[11:47:47] [PASSED] drm_test_cmdline_res_vesa_margins
[11:47:47] [PASSED] drm_test_cmdline_name
[11:47:47] [PASSED] drm_test_cmdline_name_bpp
[11:47:47] [PASSED] drm_test_cmdline_name_option
[11:47:47] [PASSED] drm_test_cmdline_name_bpp_option
[11:47:47] [PASSED] drm_test_cmdline_rotate_0
[11:47:47] [PASSED] drm_test_cmdline_rotate_90
[11:47:47] [PASSED] drm_test_cmdline_rotate_180
[11:47:47] [PASSED] drm_test_cmdline_rotate_270
[11:47:47] [PASSED] drm_test_cmdline_hmirror
[11:47:47] [PASSED] drm_test_cmdline_vmirror
[11:47:47] [PASSED] drm_test_cmdline_margin_options
[11:47:47] [PASSED] drm_test_cmdline_multiple_options
[11:47:47] [PASSED] drm_test_cmdline_bpp_extra_and_option
[11:47:47] [PASSED] drm_test_cmdline_extra_and_option
[11:47:47] [PASSED] drm_test_cmdline_freestanding_options
[11:47:47] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[11:47:47] [PASSED] drm_test_cmdline_panel_orientation
[11:47:47] ================ drm_test_cmdline_invalid  =================
[11:47:47] [PASSED] margin_only
[11:47:47] [PASSED] interlace_only
[11:47:47] [PASSED] res_missing_x
[11:47:47] [PASSED] res_missing_y
[11:47:47] [PASSED] res_bad_y
[11:47:47] [PASSED] res_missing_y_bpp
[11:47:47] [PASSED] res_bad_bpp
[11:47:47] [PASSED] res_bad_refresh
[11:47:47] [PASSED] res_bpp_refresh_force_on_off
[11:47:47] [PASSED] res_invalid_mode
[11:47:47] [PASSED] res_bpp_wrong_place_mode
[11:47:47] [PASSED] name_bpp_refresh
[11:47:47] [PASSED] name_refresh
[11:47:47] [PASSED] name_refresh_wrong_mode
[11:47:47] [PASSED] name_refresh_invalid_mode
[11:47:47] [PASSED] rotate_multiple
[11:47:47] [PASSED] rotate_invalid_val
[11:47:47] [PASSED] rotate_truncated
[11:47:47] [PASSED] invalid_option
[11:47:47] [PASSED] invalid_tv_option
[11:47:47] [PASSED] truncated_tv_option
[11:47:47] ============ [PASSED] drm_test_cmdline_invalid =============
[11:47:47] =============== drm_test_cmdline_tv_options  ===============
[11:47:47] [PASSED] NTSC
[11:47:47] [PASSED] NTSC_443
[11:47:47] [PASSED] NTSC_J
[11:47:47] [PASSED] PAL
[11:47:47] [PASSED] PAL_M
[11:47:47] [PASSED] PAL_N
[11:47:47] [PASSED] SECAM
[11:47:47] [PASSED] MONO_525
[11:47:47] [PASSED] MONO_625
[11:47:47] =========== [PASSED] drm_test_cmdline_tv_options ===========
[11:47:47] =============== [PASSED] drm_cmdline_parser ================
[11:47:47] ========== drmm_connector_hdmi_init (20 subtests) ==========
[11:47:47] [PASSED] drm_test_connector_hdmi_init_valid
[11:47:47] [PASSED] drm_test_connector_hdmi_init_bpc_8
[11:47:47] [PASSED] drm_test_connector_hdmi_init_bpc_10
[11:47:47] [PASSED] drm_test_connector_hdmi_init_bpc_12
[11:47:47] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[11:47:47] [PASSED] drm_test_connector_hdmi_init_bpc_null
[11:47:47] [PASSED] drm_test_connector_hdmi_init_formats_empty
[11:47:47] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[11:47:47] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[11:47:47] [PASSED] supported_formats=0x9 yuv420_allowed=1
[11:47:47] [PASSED] supported_formats=0x9 yuv420_allowed=0
[11:47:47] [PASSED] supported_formats=0x3 yuv420_allowed=1
[11:47:47] [PASSED] supported_formats=0x3 yuv420_allowed=0
[11:47:47] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:47:47] [PASSED] drm_test_connector_hdmi_init_null_ddc
[11:47:47] [PASSED] drm_test_connector_hdmi_init_null_product
[11:47:47] [PASSED] drm_test_connector_hdmi_init_null_vendor
[11:47:47] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[11:47:47] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[11:47:47] [PASSED] drm_test_connector_hdmi_init_product_valid
[11:47:47] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[11:47:47] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[11:47:47] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[11:47:47] ========= drm_test_connector_hdmi_init_type_valid  =========
[11:47:47] [PASSED] HDMI-A
[11:47:47] [PASSED] HDMI-B
[11:47:47] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[11:47:47] ======== drm_test_connector_hdmi_init_type_invalid  ========
[11:47:47] [PASSED] Unknown
[11:47:47] [PASSED] VGA
[11:47:47] [PASSED] DVI-I
[11:47:47] [PASSED] DVI-D
[11:47:47] [PASSED] DVI-A
[11:47:47] [PASSED] Composite
[11:47:47] [PASSED] SVIDEO
[11:47:47] [PASSED] LVDS
[11:47:47] [PASSED] Component
[11:47:47] [PASSED] DIN
[11:47:47] [PASSED] DP
[11:47:47] [PASSED] TV
[11:47:47] [PASSED] eDP
[11:47:47] [PASSED] Virtual
[11:47:47] [PASSED] DSI
[11:47:47] [PASSED] DPI
[11:47:47] [PASSED] Writeback
[11:47:47] [PASSED] SPI
[11:47:47] [PASSED] USB
[11:47:47] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[11:47:47] ============ [PASSED] drmm_connector_hdmi_init =============
[11:47:47] ============= drmm_connector_init (3 subtests) =============
[11:47:47] [PASSED] drm_test_drmm_connector_init
[11:47:47] [PASSED] drm_test_drmm_connector_init_null_ddc
[11:47:47] ========= drm_test_drmm_connector_init_type_valid  =========
[11:47:47] [PASSED] Unknown
[11:47:47] [PASSED] VGA
[11:47:47] [PASSED] DVI-I
[11:47:47] [PASSED] DVI-D
[11:47:47] [PASSED] DVI-A
[11:47:47] [PASSED] Composite
[11:47:47] [PASSED] SVIDEO
[11:47:47] [PASSED] LVDS
[11:47:47] [PASSED] Component
[11:47:47] [PASSED] DIN
[11:47:47] [PASSED] DP
[11:47:47] [PASSED] HDMI-A
[11:47:47] [PASSED] HDMI-B
[11:47:47] [PASSED] TV
[11:47:47] [PASSED] eDP
[11:47:47] [PASSED] Virtual
[11:47:47] [PASSED] DSI
[11:47:47] [PASSED] DPI
[11:47:47] [PASSED] Writeback
[11:47:47] [PASSED] SPI
[11:47:47] [PASSED] USB
[11:47:47] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[11:47:47] =============== [PASSED] drmm_connector_init ===============
[11:47:47] ========= drm_connector_dynamic_init (6 subtests) ==========
[11:47:47] [PASSED] drm_test_drm_connector_dynamic_init
[11:47:47] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[11:47:47] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[11:47:47] [PASSED] drm_test_drm_connector_dynamic_init_properties
[11:47:47] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[11:47:47] [PASSED] Unknown
[11:47:47] [PASSED] VGA
[11:47:47] [PASSED] DVI-I
[11:47:47] [PASSED] DVI-D
[11:47:47] [PASSED] DVI-A
[11:47:47] [PASSED] Composite
[11:47:47] [PASSED] SVIDEO
[11:47:47] [PASSED] LVDS
[11:47:47] [PASSED] Component
[11:47:47] [PASSED] DIN
[11:47:47] [PASSED] DP
[11:47:47] [PASSED] HDMI-A
[11:47:47] [PASSED] HDMI-B
[11:47:47] [PASSED] TV
[11:47:47] [PASSED] eDP
[11:47:47] [PASSED] Virtual
[11:47:47] [PASSED] DSI
[11:47:47] [PASSED] DPI
[11:47:47] [PASSED] Writeback
[11:47:47] [PASSED] SPI
[11:47:47] [PASSED] USB
[11:47:47] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[11:47:47] ======== drm_test_drm_connector_dynamic_init_name  =========
[11:47:47] [PASSED] Unknown
[11:47:47] [PASSED] VGA
[11:47:47] [PASSED] DVI-I
[11:47:47] [PASSED] DVI-D
[11:47:47] [PASSED] DVI-A
[11:47:47] [PASSED] Composite
[11:47:47] [PASSED] SVIDEO
[11:47:47] [PASSED] LVDS
[11:47:47] [PASSED] Component
[11:47:47] [PASSED] DIN
[11:47:47] [PASSED] DP
[11:47:47] [PASSED] HDMI-A
[11:47:47] [PASSED] HDMI-B
[11:47:47] [PASSED] TV
[11:47:47] [PASSED] eDP
[11:47:47] [PASSED] Virtual
[11:47:47] [PASSED] DSI
[11:47:47] [PASSED] DPI
[11:47:47] [PASSED] Writeback
[11:47:47] [PASSED] SPI
[11:47:47] [PASSED] USB
[11:47:47] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[11:47:47] =========== [PASSED] drm_connector_dynamic_init ============
[11:47:47] ==== drm_connector_dynamic_register_early (4 subtests) =====
[11:47:47] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[11:47:47] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[11:47:47] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[11:47:47] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[11:47:47] ====== [PASSED] drm_connector_dynamic_register_early =======
[11:47:47] ======= drm_connector_dynamic_register (7 subtests) ========
[11:47:47] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[11:47:47] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[11:47:47] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[11:47:47] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[11:47:47] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[11:47:47] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[11:47:47] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[11:47:47] ========= [PASSED] drm_connector_dynamic_register ==========
[11:47:47] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[11:47:47] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[11:47:47] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[11:47:47] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[11:47:47] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[11:47:47] ========== drm_test_get_tv_mode_from_name_valid  ===========
[11:47:47] [PASSED] NTSC
[11:47:47] [PASSED] NTSC-443
[11:47:47] [PASSED] NTSC-J
[11:47:47] [PASSED] PAL
[11:47:47] [PASSED] PAL-M
[11:47:47] [PASSED] PAL-N
[11:47:47] [PASSED] SECAM
[11:47:47] [PASSED] Mono
[11:47:47] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[11:47:47] [PASSED] drm_test_get_tv_mode_from_name_truncated
[11:47:47] ============ [PASSED] drm_get_tv_mode_from_name ============
[11:47:47] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[11:47:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[11:47:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[11:47:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[11:47:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[11:47:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[11:47:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[11:47:47] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[11:47:47] [PASSED] VIC 96
[11:47:47] [PASSED] VIC 97
[11:47:47] [PASSED] VIC 101
[11:47:47] [PASSED] VIC 102
[11:47:47] [PASSED] VIC 106
[11:47:47] [PASSED] VIC 107
[11:47:47] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[11:47:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[11:47:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[11:47:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[11:47:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[11:47:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[11:47:47] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[11:47:47] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[11:47:47] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[11:47:47] [PASSED] Automatic
[11:47:47] [PASSED] Full
[11:47:47] [PASSED] Limited 16:235
[11:47:47] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[11:47:47] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[11:47:47] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[11:47:47] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[11:47:47] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[11:47:47] [PASSED] RGB
[11:47:47] [PASSED] YUV 4:2:0
[11:47:47] [PASSED] YUV 4:2:2
[11:47:47] [PASSED] YUV 4:4:4
[11:47:47] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[11:47:47] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[11:47:47] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[11:47:47] ============= drm_damage_helper (21 subtests) ==============
[11:47:47] [PASSED] drm_test_damage_iter_no_damage
[11:47:47] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[11:47:47] [PASSED] drm_test_damage_iter_no_damage_src_moved
[11:47:47] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[11:47:47] [PASSED] drm_test_damage_iter_no_damage_not_visible
[11:47:47] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[11:47:47] [PASSED] drm_test_damage_iter_no_damage_no_fb
[11:47:47] [PASSED] drm_test_damage_iter_simple_damage
[11:47:47] [PASSED] drm_test_damage_iter_single_damage
[11:47:47] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[11:47:47] [PASSED] drm_test_damage_iter_single_damage_outside_src
[11:47:47] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[11:47:47] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[11:47:47] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[11:47:47] [PASSED] drm_test_damage_iter_single_damage_src_moved
[11:47:47] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[11:47:47] [PASSED] drm_test_damage_iter_damage
[11:47:47] [PASSED] drm_test_damage_iter_damage_one_intersect
[11:47:47] [PASSED] drm_test_damage_iter_damage_one_outside
[11:47:47] [PASSED] drm_test_damage_iter_damage_src_moved
[11:47:47] [PASSED] drm_test_damage_iter_damage_not_visible
[11:47:47] ================ [PASSED] drm_damage_helper ================
[11:47:47] ============== drm_dp_mst_helper (3 subtests) ==============
[11:47:47] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[11:47:47] [PASSED] Clock 154000 BPP 30 DSC disabled
[11:47:47] [PASSED] Clock 234000 BPP 30 DSC disabled
[11:47:47] [PASSED] Clock 297000 BPP 24 DSC disabled
[11:47:47] [PASSED] Clock 332880 BPP 24 DSC enabled
[11:47:47] [PASSED] Clock 324540 BPP 24 DSC enabled
[11:47:47] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[11:47:47] ============== drm_test_dp_mst_calc_pbn_div  ===============
[11:47:47] [PASSED] Link rate 2000000 lane count 4
[11:47:47] [PASSED] Link rate 2000000 lane count 2
[11:47:47] [PASSED] Link rate 2000000 lane count 1
[11:47:47] [PASSED] Link rate 1350000 lane count 4
[11:47:47] [PASSED] Link rate 1350000 lane count 2
[11:47:47] [PASSED] Link rate 1350000 lane count 1
[11:47:47] [PASSED] Link rate 1000000 lane count 4
[11:47:47] [PASSED] Link rate 1000000 lane count 2
[11:47:47] [PASSED] Link rate 1000000 lane count 1
[11:47:47] [PASSED] Link rate 810000 lane count 4
[11:47:47] [PASSED] Link rate 810000 lane count 2
[11:47:47] [PASSED] Link rate 810000 lane count 1
[11:47:47] [PASSED] Link rate 540000 lane count 4
[11:47:47] [PASSED] Link rate 540000 lane count 2
[11:47:47] [PASSED] Link rate 540000 lane count 1
[11:47:47] [PASSED] Link rate 270000 lane count 4
[11:47:47] [PASSED] Link rate 270000 lane count 2
[11:47:47] [PASSED] Link rate 270000 lane count 1
[11:47:47] [PASSED] Link rate 162000 lane count 4
[11:47:47] [PASSED] Link rate 162000 lane count 2
[11:47:47] [PASSED] Link rate 162000 lane count 1
[11:47:47] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[11:47:47] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[11:47:47] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[11:47:47] [PASSED] DP_POWER_UP_PHY with port number
[11:47:47] [PASSED] DP_POWER_DOWN_PHY with port number
[11:47:47] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[11:47:47] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[11:47:47] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[11:47:47] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[11:47:47] [PASSED] DP_QUERY_PAYLOAD with port number
[11:47:47] [PASSED] DP_QUERY_PAYLOAD with VCPI
[11:47:47] [PASSED] DP_REMOTE_DPCD_READ with port number
[11:47:47] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[11:47:47] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[11:47:47] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[11:47:47] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[11:47:47] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[11:47:47] [PASSED] DP_REMOTE_I2C_READ with port number
[11:47:47] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[11:47:47] [PASSED] DP_REMOTE_I2C_READ with transactions array
[11:47:47] [PASSED] DP_REMOTE_I2C_WRITE with port number
[11:47:47] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[11:47:47] [PASSED] DP_REMOTE_I2C_WRITE with data array
[11:47:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[11:47:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[11:47:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[11:47:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[11:47:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[11:47:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[11:47:47] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[11:47:47] ================ [PASSED] drm_dp_mst_helper ================
[11:47:47] ================== drm_exec (7 subtests) ===================
[11:47:47] [PASSED] sanitycheck
[11:47:47] [PASSED] test_lock
[11:47:47] [PASSED] test_lock_unlock
[11:47:47] [PASSED] test_duplicates
[11:47:47] [PASSED] test_prepare
[11:47:47] [PASSED] test_prepare_array
[11:47:47] [PASSED] test_multiple_loops
[11:47:47] ==================== [PASSED] drm_exec =====================
[11:47:47] =========== drm_format_helper_test (17 subtests) ===========
[11:47:47] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[11:47:47] [PASSED] single_pixel_source_buffer
[11:47:47] [PASSED] single_pixel_clip_rectangle
[11:47:47] [PASSED] well_known_colors
[11:47:47] [PASSED] destination_pitch
[11:47:47] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[11:47:47] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[11:47:47] [PASSED] single_pixel_source_buffer
[11:47:47] [PASSED] single_pixel_clip_rectangle
[11:47:47] [PASSED] well_known_colors
[11:47:47] [PASSED] destination_pitch
[11:47:47] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[11:47:47] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[11:47:47] [PASSED] single_pixel_source_buffer
[11:47:47] [PASSED] single_pixel_clip_rectangle
[11:47:47] [PASSED] well_known_colors
[11:47:47] [PASSED] destination_pitch
[11:47:47] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[11:47:47] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[11:47:47] [PASSED] single_pixel_source_buffer
[11:47:47] [PASSED] single_pixel_clip_rectangle
[11:47:47] [PASSED] well_known_colors
[11:47:47] [PASSED] destination_pitch
[11:47:47] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[11:47:47] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[11:47:47] [PASSED] single_pixel_source_buffer
[11:47:47] [PASSED] single_pixel_clip_rectangle
[11:47:47] [PASSED] well_known_colors
[11:47:47] [PASSED] destination_pitch
[11:47:47] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[11:47:47] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[11:47:47] [PASSED] single_pixel_source_buffer
[11:47:47] [PASSED] single_pixel_clip_rectangle
[11:47:47] [PASSED] well_known_colors
[11:47:47] [PASSED] destination_pitch
[11:47:47] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[11:47:47] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[11:47:47] [PASSED] single_pixel_source_buffer
[11:47:47] [PASSED] single_pixel_clip_rectangle
[11:47:47] [PASSED] well_known_colors
[11:47:47] [PASSED] destination_pitch
[11:47:47] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[11:47:47] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[11:47:47] [PASSED] single_pixel_source_buffer
[11:47:47] [PASSED] single_pixel_clip_rectangle
[11:47:47] [PASSED] well_known_colors
[11:47:47] [PASSED] destination_pitch
[11:47:47] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[11:47:47] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[11:47:47] [PASSED] single_pixel_source_buffer
[11:47:47] [PASSED] single_pixel_clip_rectangle
[11:47:47] [PASSED] well_known_colors
[11:47:47] [PASSED] destination_pitch
[11:47:47] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[11:47:47] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[11:47:47] [PASSED] single_pixel_source_buffer
[11:47:47] [PASSED] single_pixel_clip_rectangle
[11:47:47] [PASSED] well_known_colors
[11:47:47] [PASSED] destination_pitch
[11:47:47] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[11:47:47] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[11:47:47] [PASSED] single_pixel_source_buffer
[11:47:47] [PASSED] single_pixel_clip_rectangle
[11:47:47] [PASSED] well_known_colors
[11:47:47] [PASSED] destination_pitch
[11:47:47] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[11:47:47] ============== drm_test_fb_xrgb8888_to_mono  ===============
[11:47:47] [PASSED] single_pixel_source_buffer
[11:47:47] [PASSED] single_pixel_clip_rectangle
[11:47:47] [PASSED] well_known_colors
[11:47:47] [PASSED] destination_pitch
[11:47:47] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[11:47:47] ==================== drm_test_fb_swab  =====================
[11:47:47] [PASSED] single_pixel_source_buffer
[11:47:47] [PASSED] single_pixel_clip_rectangle
[11:47:47] [PASSED] well_known_colors
[11:47:47] [PASSED] destination_pitch
[11:47:47] ================ [PASSED] drm_test_fb_swab =================
[11:47:47] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[11:47:47] [PASSED] single_pixel_source_buffer
[11:47:47] [PASSED] single_pixel_clip_rectangle
[11:47:47] [PASSED] well_known_colors
[11:47:47] [PASSED] destination_pitch
[11:47:47] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[11:47:47] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[11:47:47] [PASSED] single_pixel_source_buffer
[11:47:47] [PASSED] single_pixel_clip_rectangle
[11:47:47] [PASSED] well_known_colors
[11:47:47] [PASSED] destination_pitch
[11:47:47] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[11:47:47] ================= drm_test_fb_clip_offset  =================
[11:47:47] [PASSED] pass through
[11:47:47] [PASSED] horizontal offset
[11:47:47] [PASSED] vertical offset
[11:47:47] [PASSED] horizontal and vertical offset
[11:47:47] [PASSED] horizontal offset (custom pitch)
[11:47:47] [PASSED] vertical offset (custom pitch)
[11:47:47] [PASSED] horizontal and vertical offset (custom pitch)
[11:47:47] ============= [PASSED] drm_test_fb_clip_offset =============
[11:47:47] =================== drm_test_fb_memcpy  ====================
[11:47:47] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[11:47:47] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[11:47:47] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[11:47:47] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[11:47:47] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[11:47:47] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[11:47:47] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[11:47:47] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[11:47:47] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[11:47:47] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[11:47:47] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[11:47:47] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[11:47:47] =============== [PASSED] drm_test_fb_memcpy ================
[11:47:47] ============= [PASSED] drm_format_helper_test ==============
[11:47:47] ================= drm_format (18 subtests) =================
[11:47:47] [PASSED] drm_test_format_block_width_invalid
[11:47:47] [PASSED] drm_test_format_block_width_one_plane
[11:47:47] [PASSED] drm_test_format_block_width_two_plane
[11:47:47] [PASSED] drm_test_format_block_width_three_plane
[11:47:47] [PASSED] drm_test_format_block_width_tiled
[11:47:47] [PASSED] drm_test_format_block_height_invalid
[11:47:47] [PASSED] drm_test_format_block_height_one_plane
[11:47:47] [PASSED] drm_test_format_block_height_two_plane
[11:47:47] [PASSED] drm_test_format_block_height_three_plane
[11:47:47] [PASSED] drm_test_format_block_height_tiled
[11:47:47] [PASSED] drm_test_format_min_pitch_invalid
[11:47:47] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[11:47:47] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[11:47:47] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[11:47:47] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[11:47:47] [PASSED] drm_test_format_min_pitch_two_plane
[11:47:47] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[11:47:47] [PASSED] drm_test_format_min_pitch_tiled
[11:47:47] =================== [PASSED] drm_format ====================
[11:47:47] ============== drm_framebuffer (10 subtests) ===============
[11:47:47] ========== drm_test_framebuffer_check_src_coords  ==========
[11:47:47] [PASSED] Success: source fits into fb
[11:47:47] [PASSED] Fail: overflowing fb with x-axis coordinate
[11:47:47] [PASSED] Fail: overflowing fb with y-axis coordinate
[11:47:47] [PASSED] Fail: overflowing fb with source width
[11:47:47] [PASSED] Fail: overflowing fb with source height
[11:47:47] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[11:47:47] [PASSED] drm_test_framebuffer_cleanup
[11:47:47] =============== drm_test_framebuffer_create  ===============
[11:47:47] [PASSED] ABGR8888 normal sizes
[11:47:47] [PASSED] ABGR8888 max sizes
[11:47:47] [PASSED] ABGR8888 pitch greater than min required
[11:47:47] [PASSED] ABGR8888 pitch less than min required
[11:47:47] [PASSED] ABGR8888 Invalid width
[11:47:47] [PASSED] ABGR8888 Invalid buffer handle
[11:47:47] [PASSED] No pixel format
[11:47:47] [PASSED] ABGR8888 Width 0
[11:47:47] [PASSED] ABGR8888 Height 0
[11:47:47] [PASSED] ABGR8888 Out of bound height * pitch combination
[11:47:47] [PASSED] ABGR8888 Large buffer offset
[11:47:47] [PASSED] ABGR8888 Buffer offset for inexistent plane
[11:47:47] [PASSED] ABGR8888 Invalid flag
[11:47:47] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[11:47:47] [PASSED] ABGR8888 Valid buffer modifier
[11:47:47] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[11:47:47] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[11:47:47] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[11:47:47] [PASSED] NV12 Normal sizes
[11:47:47] [PASSED] NV12 Max sizes
[11:47:47] [PASSED] NV12 Invalid pitch
[11:47:47] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[11:47:47] [PASSED] NV12 different  modifier per-plane
[11:47:47] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[11:47:47] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[11:47:47] [PASSED] NV12 Modifier for inexistent plane
[11:47:47] [PASSED] NV12 Handle for inexistent plane
[11:47:47] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[11:47:47] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[11:47:47] [PASSED] YVU420 Normal sizes
[11:47:47] [PASSED] YVU420 Max sizes
[11:47:47] [PASSED] YVU420 Invalid pitch
[11:47:47] [PASSED] YVU420 Different pitches
[11:47:47] [PASSED] YVU420 Different buffer offsets/pitches
[11:47:47] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[11:47:47] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[11:47:47] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[11:47:47] [PASSED] YVU420 Valid modifier
[11:47:47] [PASSED] YVU420 Different modifiers per plane
[11:47:47] [PASSED] YVU420 Modifier for inexistent plane
[11:47:47] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[11:47:47] [PASSED] X0L2 Normal sizes
[11:47:47] [PASSED] X0L2 Max sizes
[11:47:47] [PASSED] X0L2 Invalid pitch
[11:47:47] [PASSED] X0L2 Pitch greater than minimum required
[11:47:47] [PASSED] X0L2 Handle for inexistent plane
[11:47:47] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[11:47:47] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[11:47:47] [PASSED] X0L2 Valid modifier
[11:47:47] [PASSED] X0L2 Modifier for inexistent plane
[11:47:47] =========== [PASSED] drm_test_framebuffer_create ===========
[11:47:47] [PASSED] drm_test_framebuffer_free
[11:47:47] [PASSED] drm_test_framebuffer_init
[11:47:47] [PASSED] drm_test_framebuffer_init_bad_format
[11:47:47] [PASSED] drm_test_framebuffer_init_dev_mismatch
[11:47:47] [PASSED] drm_test_framebuffer_lookup
[11:47:47] [PASSED] drm_test_framebuffer_lookup_inexistent
[11:47:47] [PASSED] drm_test_framebuffer_modifiers_not_supported
[11:47:47] ================= [PASSED] drm_framebuffer =================
[11:47:47] ================ drm_gem_shmem (8 subtests) ================
[11:47:47] [PASSED] drm_gem_shmem_test_obj_create
[11:47:47] [PASSED] drm_gem_shmem_test_obj_create_private
[11:47:47] [PASSED] drm_gem_shmem_test_pin_pages
[11:47:47] [PASSED] drm_gem_shmem_test_vmap
[11:47:47] [PASSED] drm_gem_shmem_test_get_sg_table
[11:47:47] [PASSED] drm_gem_shmem_test_get_pages_sgt
[11:47:47] [PASSED] drm_gem_shmem_test_madvise
[11:47:47] [PASSED] drm_gem_shmem_test_purge
[11:47:47] ================== [PASSED] drm_gem_shmem ==================
[11:47:47] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[11:47:47] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[11:47:47] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[11:47:47] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[11:47:47] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[11:47:47] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[11:47:47] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[11:47:47] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[11:47:47] [PASSED] Automatic
[11:47:47] [PASSED] Full
[11:47:47] [PASSED] Limited 16:235
[11:47:47] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[11:47:47] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[11:47:47] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[11:47:47] [PASSED] drm_test_check_disable_connector
[11:47:47] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[11:47:47] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[11:47:47] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[11:47:47] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[11:47:47] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[11:47:47] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[11:47:47] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[11:47:47] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[11:47:47] [PASSED] drm_test_check_output_bpc_dvi
[11:47:47] [PASSED] drm_test_check_output_bpc_format_vic_1
[11:47:47] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[11:47:47] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[11:47:47] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[11:47:47] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[11:47:47] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[11:47:47] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[11:47:47] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[11:47:47] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[11:47:47] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[11:47:47] [PASSED] drm_test_check_broadcast_rgb_value
[11:47:47] [PASSED] drm_test_check_bpc_8_value
[11:47:47] [PASSED] drm_test_check_bpc_10_value
[11:47:47] [PASSED] drm_test_check_bpc_12_value
[11:47:47] [PASSED] drm_test_check_format_value
[11:47:47] [PASSED] drm_test_check_tmds_char_value
[11:47:47] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[11:47:47] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[11:47:47] [PASSED] drm_test_check_mode_valid
[11:47:47] [PASSED] drm_test_check_mode_valid_reject
[11:47:47] [PASSED] drm_test_check_mode_valid_reject_rate
[11:47:47] [PASSED] drm_test_check_mode_valid_reject_max_clock
[11:47:47] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[11:47:47] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[11:47:47] [PASSED] drm_test_check_infoframes
[11:47:47] [PASSED] drm_test_check_reject_avi_infoframe
[11:47:47] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[11:47:47] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[11:47:47] [PASSED] drm_test_check_reject_audio_infoframe
[11:47:47] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[11:47:47] ================= drm_managed (2 subtests) =================
[11:47:47] [PASSED] drm_test_managed_release_action
[11:47:47] [PASSED] drm_test_managed_run_action
[11:47:47] =================== [PASSED] drm_managed ===================
[11:47:47] =================== drm_mm (6 subtests) ====================
[11:47:47] [PASSED] drm_test_mm_init
[11:47:47] [PASSED] drm_test_mm_debug
[11:47:47] [PASSED] drm_test_mm_align32
[11:47:47] [PASSED] drm_test_mm_align64
[11:47:47] [PASSED] drm_test_mm_lowest
[11:47:47] [PASSED] drm_test_mm_highest
[11:47:47] ===================== [PASSED] drm_mm ======================
[11:47:47] ============= drm_modes_analog_tv (5 subtests) =============
[11:47:47] [PASSED] drm_test_modes_analog_tv_mono_576i
[11:47:47] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[11:47:47] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[11:47:47] [PASSED] drm_test_modes_analog_tv_pal_576i
[11:47:47] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[11:47:47] =============== [PASSED] drm_modes_analog_tv ===============
[11:47:47] ============== drm_plane_helper (2 subtests) ===============
[11:47:47] =============== drm_test_check_plane_state  ================
[11:47:47] [PASSED] clipping_simple
[11:47:47] [PASSED] clipping_rotate_reflect
[11:47:47] [PASSED] positioning_simple
[11:47:47] [PASSED] upscaling
[11:47:47] [PASSED] downscaling
[11:47:47] [PASSED] rounding1
[11:47:47] [PASSED] rounding2
[11:47:47] [PASSED] rounding3
[11:47:47] [PASSED] rounding4
[11:47:47] =========== [PASSED] drm_test_check_plane_state ============
[11:47:47] =========== drm_test_check_invalid_plane_state  ============
[11:47:47] [PASSED] positioning_invalid
[11:47:47] [PASSED] upscaling_invalid
[11:47:47] [PASSED] downscaling_invalid
[11:47:47] ======= [PASSED] drm_test_check_invalid_plane_state ========
[11:47:47] ================ [PASSED] drm_plane_helper =================
[11:47:47] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[11:47:47] ====== drm_test_connector_helper_tv_get_modes_check  =======
[11:47:47] [PASSED] None
[11:47:47] [PASSED] PAL
[11:47:47] [PASSED] NTSC
[11:47:47] [PASSED] Both, NTSC Default
[11:47:47] [PASSED] Both, PAL Default
[11:47:47] [PASSED] Both, NTSC Default, with PAL on command-line
[11:47:47] [PASSED] Both, PAL Default, with NTSC on command-line
[11:47:47] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[11:47:47] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[11:47:47] ================== drm_rect (9 subtests) ===================
[11:47:47] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[11:47:47] [PASSED] drm_test_rect_clip_scaled_not_clipped
[11:47:47] [PASSED] drm_test_rect_clip_scaled_clipped
[11:47:47] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[11:47:47] ================= drm_test_rect_intersect  =================
[11:47:47] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[11:47:47] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[11:47:47] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[11:47:47] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[11:47:47] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[11:47:47] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[11:47:47] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[11:47:47] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[11:47:47] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[11:47:47] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[11:47:47] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[11:47:47] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[11:47:47] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[11:47:47] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[11:47:47] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[11:47:47] ============= [PASSED] drm_test_rect_intersect =============
[11:47:47] ================ drm_test_rect_calc_hscale  ================
[11:47:47] [PASSED] normal use
[11:47:47] [PASSED] out of max range
[11:47:47] [PASSED] out of min range
[11:47:47] [PASSED] zero dst
[11:47:47] [PASSED] negative src
[11:47:47] [PASSED] negative dst
[11:47:47] ============ [PASSED] drm_test_rect_calc_hscale ============
[11:47:47] ================ drm_test_rect_calc_vscale  ================
[11:47:47] [PASSED] normal use
[11:47:47] [PASSED] out of max range
[11:47:47] [PASSED] out of min range
[11:47:47] [PASSED] zero dst
[11:47:47] [PASSED] negative src
[11:47:47] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[11:47:47] ============ [PASSED] drm_test_rect_calc_vscale ============
[11:47:47] ================== drm_test_rect_rotate  ===================
[11:47:47] [PASSED] reflect-x
[11:47:47] [PASSED] reflect-y
[11:47:47] [PASSED] rotate-0
[11:47:47] [PASSED] rotate-90
[11:47:47] [PASSED] rotate-180
[11:47:47] [PASSED] rotate-270
[11:47:47] ============== [PASSED] drm_test_rect_rotate ===============
[11:47:47] ================ drm_test_rect_rotate_inv  =================
[11:47:47] [PASSED] reflect-x
[11:47:47] [PASSED] reflect-y
[11:47:47] [PASSED] rotate-0
[11:47:47] [PASSED] rotate-90
[11:47:47] [PASSED] rotate-180
[11:47:47] [PASSED] rotate-270
[11:47:47] ============ [PASSED] drm_test_rect_rotate_inv =============
[11:47:47] ==================== [PASSED] drm_rect =====================
[11:47:47] ============ drm_sysfb_modeset_test (1 subtest) ============
[11:47:47] ============ drm_test_sysfb_build_fourcc_list  =============
[11:47:47] [PASSED] no native formats
[11:47:47] [PASSED] XRGB8888 as native format
[11:47:47] [PASSED] remove duplicates
[11:47:47] [PASSED] convert alpha formats
[11:47:47] [PASSED] random formats
[11:47:47] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[11:47:47] ============= [PASSED] drm_sysfb_modeset_test ==============
[11:47:47] ================== drm_fixp (2 subtests) ===================
[11:47:47] [PASSED] drm_test_int2fixp
[11:47:47] [PASSED] drm_test_sm2fixp
[11:47:47] ==================== [PASSED] drm_fixp =====================
[11:47:47] ============================================================
[11:47:47] Testing complete. Ran 621 tests: passed: 621
[11:47:48] Elapsed time: 26.002s total, 1.731s configuring, 24.102s building, 0.137s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[11:47:48] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:47:49] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:47:59] Starting KUnit Kernel (1/1)...
[11:47:59] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:47:59] ================= ttm_device (5 subtests) ==================
[11:47:59] [PASSED] ttm_device_init_basic
[11:47:59] [PASSED] ttm_device_init_multiple
[11:47:59] [PASSED] ttm_device_fini_basic
[11:47:59] [PASSED] ttm_device_init_no_vma_man
[11:47:59] ================== ttm_device_init_pools  ==================
[11:47:59] [PASSED] No DMA allocations, no DMA32 required
[11:47:59] [PASSED] DMA allocations, DMA32 required
[11:47:59] [PASSED] No DMA allocations, DMA32 required
[11:47:59] [PASSED] DMA allocations, no DMA32 required
[11:47:59] ============== [PASSED] ttm_device_init_pools ==============
[11:47:59] =================== [PASSED] ttm_device ====================
[11:47:59] ================== ttm_pool (8 subtests) ===================
[11:47:59] ================== ttm_pool_alloc_basic  ===================
[11:47:59] [PASSED] One page
[11:47:59] [PASSED] More than one page
[11:47:59] [PASSED] Above the allocation limit
[11:47:59] [PASSED] One page, with coherent DMA mappings enabled
[11:47:59] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:47:59] ============== [PASSED] ttm_pool_alloc_basic ===============
[11:47:59] ============== ttm_pool_alloc_basic_dma_addr  ==============
[11:47:59] [PASSED] One page
[11:47:59] [PASSED] More than one page
[11:47:59] [PASSED] Above the allocation limit
[11:47:59] [PASSED] One page, with coherent DMA mappings enabled
[11:47:59] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:47:59] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[11:47:59] [PASSED] ttm_pool_alloc_order_caching_match
[11:47:59] [PASSED] ttm_pool_alloc_caching_mismatch
[11:47:59] [PASSED] ttm_pool_alloc_order_mismatch
[11:47:59] [PASSED] ttm_pool_free_dma_alloc
[11:47:59] [PASSED] ttm_pool_free_no_dma_alloc
[11:47:59] [PASSED] ttm_pool_fini_basic
[11:47:59] ==================== [PASSED] ttm_pool =====================
[11:47:59] ================ ttm_resource (8 subtests) =================
[11:47:59] ================= ttm_resource_init_basic  =================
[11:47:59] [PASSED] Init resource in TTM_PL_SYSTEM
[11:47:59] [PASSED] Init resource in TTM_PL_VRAM
[11:47:59] [PASSED] Init resource in a private placement
[11:47:59] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[11:47:59] ============= [PASSED] ttm_resource_init_basic =============
[11:47:59] [PASSED] ttm_resource_init_pinned
[11:47:59] [PASSED] ttm_resource_fini_basic
[11:47:59] [PASSED] ttm_resource_manager_init_basic
[11:47:59] [PASSED] ttm_resource_manager_usage_basic
[11:47:59] [PASSED] ttm_resource_manager_set_used_basic
[11:47:59] [PASSED] ttm_sys_man_alloc_basic
[11:47:59] [PASSED] ttm_sys_man_free_basic
[11:47:59] ================== [PASSED] ttm_resource ===================
[11:47:59] =================== ttm_tt (15 subtests) ===================
[11:47:59] ==================== ttm_tt_init_basic  ====================
[11:47:59] [PASSED] Page-aligned size
[11:47:59] [PASSED] Extra pages requested
[11:47:59] ================ [PASSED] ttm_tt_init_basic ================
[11:47:59] [PASSED] ttm_tt_init_misaligned
[11:47:59] [PASSED] ttm_tt_fini_basic
[11:47:59] [PASSED] ttm_tt_fini_sg
[11:47:59] [PASSED] ttm_tt_fini_shmem
[11:47:59] [PASSED] ttm_tt_create_basic
[11:47:59] [PASSED] ttm_tt_create_invalid_bo_type
[11:47:59] [PASSED] ttm_tt_create_ttm_exists
[11:47:59] [PASSED] ttm_tt_create_failed
[11:47:59] [PASSED] ttm_tt_destroy_basic
[11:47:59] [PASSED] ttm_tt_populate_null_ttm
[11:47:59] [PASSED] ttm_tt_populate_populated_ttm
[11:47:59] [PASSED] ttm_tt_unpopulate_basic
[11:47:59] [PASSED] ttm_tt_unpopulate_empty_ttm
[11:47:59] [PASSED] ttm_tt_swapin_basic
[11:47:59] ===================== [PASSED] ttm_tt ======================
[11:47:59] =================== ttm_bo (14 subtests) ===================
[11:47:59] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[11:47:59] [PASSED] Cannot be interrupted and sleeps
[11:47:59] [PASSED] Cannot be interrupted, locks straight away
[11:47:59] [PASSED] Can be interrupted, sleeps
[11:47:59] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[11:47:59] [PASSED] ttm_bo_reserve_locked_no_sleep
[11:47:59] [PASSED] ttm_bo_reserve_no_wait_ticket
[11:47:59] [PASSED] ttm_bo_reserve_double_resv
[11:47:59] [PASSED] ttm_bo_reserve_interrupted
[11:47:59] [PASSED] ttm_bo_reserve_deadlock
[11:47:59] [PASSED] ttm_bo_unreserve_basic
[11:47:59] [PASSED] ttm_bo_unreserve_pinned
[11:47:59] [PASSED] ttm_bo_unreserve_bulk
[11:47:59] [PASSED] ttm_bo_fini_basic
[11:47:59] [PASSED] ttm_bo_fini_shared_resv
[11:47:59] [PASSED] ttm_bo_pin_basic
[11:47:59] [PASSED] ttm_bo_pin_unpin_resource
[11:47:59] [PASSED] ttm_bo_multiple_pin_one_unpin
[11:47:59] ===================== [PASSED] ttm_bo ======================
[11:47:59] ============== ttm_bo_validate (22 subtests) ===============
[11:47:59] ============== ttm_bo_init_reserved_sys_man  ===============
[11:47:59] [PASSED] Buffer object for userspace
[11:47:59] [PASSED] Kernel buffer object
[11:47:59] [PASSED] Shared buffer object
[11:47:59] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[11:47:59] ============== ttm_bo_init_reserved_mock_man  ==============
[11:47:59] [PASSED] Buffer object for userspace
[11:47:59] [PASSED] Kernel buffer object
[11:47:59] [PASSED] Shared buffer object
[11:47:59] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[11:47:59] [PASSED] ttm_bo_init_reserved_resv
[11:47:59] ================== ttm_bo_validate_basic  ==================
[11:47:59] [PASSED] Buffer object for userspace
[11:47:59] [PASSED] Kernel buffer object
[11:47:59] [PASSED] Shared buffer object
[11:47:59] ============== [PASSED] ttm_bo_validate_basic ==============
[11:47:59] [PASSED] ttm_bo_validate_invalid_placement
[11:47:59] ============= ttm_bo_validate_same_placement  ==============
[11:47:59] [PASSED] System manager
[11:47:59] [PASSED] VRAM manager
[11:47:59] ========= [PASSED] ttm_bo_validate_same_placement ==========
[11:47:59] [PASSED] ttm_bo_validate_failed_alloc
[11:47:59] [PASSED] ttm_bo_validate_pinned
[11:47:59] [PASSED] ttm_bo_validate_busy_placement
[11:47:59] ================ ttm_bo_validate_multihop  =================
[11:47:59] [PASSED] Buffer object for userspace
[11:47:59] [PASSED] Kernel buffer object
[11:47:59] [PASSED] Shared buffer object
[11:47:59] ============ [PASSED] ttm_bo_validate_multihop =============
[11:47:59] ========== ttm_bo_validate_no_placement_signaled  ==========
[11:47:59] [PASSED] Buffer object in system domain, no page vector
[11:47:59] [PASSED] Buffer object in system domain with an existing page vector
[11:47:59] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[11:47:59] ======== ttm_bo_validate_no_placement_not_signaled  ========
[11:47:59] [PASSED] Buffer object for userspace
[11:47:59] [PASSED] Kernel buffer object
[11:47:59] [PASSED] Shared buffer object
[11:47:59] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[11:47:59] [PASSED] ttm_bo_validate_move_fence_signaled
[11:47:59] ========= ttm_bo_validate_move_fence_not_signaled  =========
[11:47:59] [PASSED] Waits for GPU
[11:47:59] [PASSED] Tries to lock straight away
[11:47:59] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[11:47:59] [PASSED] ttm_bo_validate_swapout
[11:47:59] [PASSED] ttm_bo_validate_happy_evict
[11:47:59] [PASSED] ttm_bo_validate_all_pinned_evict
[11:47:59] [PASSED] ttm_bo_validate_allowed_only_evict
[11:47:59] [PASSED] ttm_bo_validate_deleted_evict
[11:47:59] [PASSED] ttm_bo_validate_busy_domain_evict
[11:47:59] [PASSED] ttm_bo_validate_evict_gutting
[11:47:59] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[11:47:59] ================= [PASSED] ttm_bo_validate =================
[11:47:59] ============================================================
[11:47:59] Testing complete. Ran 102 tests: passed: 102
[11:47:59] Elapsed time: 11.478s total, 1.732s configuring, 9.480s building, 0.231s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/wm: Clean up pre-icl NV12 watermarks

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 959 bytes --]

== Series Details ==

Series: drm/i915/wm: Clean up pre-icl NV12 watermarks
URL   : https://patchwork.freedesktop.org/series/163523/
State : success

== Summary ==

CI Bug Log - changes from xe-4746-73694175c9632682b410199c5987a3420bd5444c_BAT -> xe-pw-163523v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 14)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-4746-73694175c9632682b410199c5987a3420bd5444c -> xe-pw-163523v1

  IGT_8810: eb9035ba642724dc0a7711672805f26d1f34f712 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4746-73694175c9632682b410199c5987a3420bd5444c: 73694175c9632682b410199c5987a3420bd5444c
  xe-pw-163523v1: 163523v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/index.html

[-- Attachment #2: Type: text/html, Size: 1507 bytes --]

✓ Xe.CI.FULL: success for drm/i915/wm: Clean up pre-icl NV12 watermarks

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 38239 bytes --]

== Series Details ==

Series: drm/i915/wm: Clean up pre-icl NV12 watermarks
URL   : https://patchwork.freedesktop.org/series/163523/
State : success

== Summary ==

CI Bug Log - changes from xe-4746-73694175c9632682b410199c5987a3420bd5444c_FULL -> xe-pw-163523v1_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-163523v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][1] ([Intel XE#2327]) +3 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-10/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][2] ([Intel XE#7059] / [Intel XE#7085])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-7/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#1124])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#2887]) +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs.html

  * igt@kms_chamelium_hpd@dp-hpd-storm:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2252]) +2 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-7/igt@kms_chamelium_hpd@dp-hpd-storm.html

  * igt@kms_content_protection@atomic-hdcp14:
    - shard-bmg:          NOTRUN -> [FAIL][6] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +2 other tests fail
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@kms_content_protection@atomic-hdcp14.html

  * igt@kms_cursor_crc@cursor-offscreen-32x32:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2320])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@kms_cursor_crc@cursor-offscreen-32x32.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-bmg:          [PASS][8] -> [SKIP][9] ([Intel XE#2291])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-10/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
    - shard-bmg:          [PASS][10] -> [SKIP][11] ([Intel XE#2291] / [Intel XE#7343])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-9/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html

  * igt@kms_dp_aux_dev:
    - shard-bmg:          [PASS][12] -> [SKIP][13] ([Intel XE#3009])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-10/igt@kms_dp_aux_dev.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-3/igt@kms_dp_aux_dev.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-bmg:          [PASS][14] -> [SKIP][15] ([Intel XE#4294])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-9/igt@kms_dp_linktrain_fallback@dp-fallback.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#4422] / [Intel XE#7442])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-bmg:          [PASS][17] -> [SKIP][18] ([Intel XE#2316]) +2 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-2/igt@kms_flip@2x-flip-vs-dpms.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2316]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#7178] / [Intel XE#7351]) +2 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2311]) +7 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#7061] / [Intel XE#7356])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#4141]) +4 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2312]) +2 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#2313]) +7 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_hdr@static-swap:
    - shard-bmg:          [PASS][26] -> [SKIP][27] ([Intel XE#1503])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-10/igt@kms_hdr@static-swap.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-3/igt@kms_hdr@static-swap.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#6911] / [Intel XE#7378])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#7283])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-7/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#4596])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383] / [Intel XE#836])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#1489]) +3 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#2387] / [Intel XE#7429])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@psr2-sprite-render:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@kms_psr@psr2-sprite-render.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#1406] / [Intel XE#2414])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_sharpness_filter@invalid-plane-with-filter:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#6503])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@kms_sharpness_filter@invalid-plane-with-filter.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [PASS][37] -> [FAIL][38] ([Intel XE#2142]) +1 other test fail
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-lnl-4/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-lnl-4/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  * igt@xe_eudebug@attach-debug-metadata:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#4837]) +3 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@xe_eudebug@attach-debug-metadata.html

  * igt@xe_eudebug_online@resume-one:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#4837] / [Intel XE#6665]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@xe_eudebug_online@resume-one.html

  * igt@xe_evict@evict-cm-threads-small-multi-queue:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#7140])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-10/igt@xe_evict@evict-cm-threads-small-multi-queue.html

  * igt@xe_exec_basic@multigpu-no-exec-null:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2322] / [Intel XE#7372]) +3 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-10/igt@xe_exec_basic@multigpu-no-exec-null.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#7136]) +4 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-7/igt@xe_exec_fault_mode@twice-multi-queue-userptr-rebind.html

  * igt@xe_exec_multi_queue@max-queues-basic:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#6874]) +7 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@xe_exec_multi_queue@max-queues-basic.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#7138]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-rebind.html

  * igt@xe_multigpu_svm@mgpu-coherency-fail-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#6964])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-10/igt@xe_multigpu_svm@mgpu-coherency-fail-prefetch.html

  * igt@xe_pm@d3cold-i2c:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#5694] / [Intel XE#7370])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@xe_pm@d3cold-i2c.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-rpm:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#4733] / [Intel XE#7417])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@xe_pxp@pxp-stale-bo-exec-post-rpm.html

  
#### Possible fixes ####

  * igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p:
    - shard-bmg:          [SKIP][49] ([Intel XE#2314] / [Intel XE#2894] / [Intel XE#7373]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html

  * igt@kms_cursor_crc@cursor-random-64x64:
    - shard-bmg:          [SKIP][51] ([Intel XE#2320]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-6/igt@kms_cursor_crc@cursor-random-64x64.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@kms_cursor_crc@cursor-random-64x64.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-legacy:
    - shard-bmg:          [SKIP][53] ([Intel XE#2291] / [Intel XE#7343]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-9/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc@pipe-a-dp-2:
    - shard-bmg:          [SKIP][55] -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-6/igt@kms_dither@fb-8bpc-vs-panel-8bpc@pipe-a-dp-2.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-7/igt@kms_dither@fb-8bpc-vs-panel-8bpc@pipe-a-dp-2.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc@pipe-a-hdmi-a-3:
    - shard-bmg:          [FAIL][57] -> [PASS][58] +1 other test pass
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-6/igt@kms_dither@fb-8bpc-vs-panel-8bpc@pipe-a-hdmi-a-3.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-7/igt@kms_dither@fb-8bpc-vs-panel-8bpc@pipe-a-hdmi-a-3.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-bmg:          [SKIP][59] ([Intel XE#2316]) -> [PASS][60] +2 other tests pass
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-5/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-6/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-bmg:          [FAIL][61] ([Intel XE#3149] / [Intel XE#5408] / [Intel XE#6266]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-6/igt@kms_flip@2x-plain-flip-fb-recreate.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip@2x-plain-flip-fb-recreate@ab-dp2-hdmi-a3:
    - shard-bmg:          [FAIL][63] ([Intel XE#6266]) -> [PASS][64] +1 other test pass
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-6/igt@kms_flip@2x-plain-flip-fb-recreate@ab-dp2-hdmi-a3.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@kms_flip@2x-plain-flip-fb-recreate@ab-dp2-hdmi-a3.html

  * igt@kms_flip@2x-plain-flip-fb-recreate@cd-dp2-hdmi-a3:
    - shard-bmg:          [FAIL][65] ([Intel XE#3149] / [Intel XE#6266]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-6/igt@kms_flip@2x-plain-flip-fb-recreate@cd-dp2-hdmi-a3.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@kms_flip@2x-plain-flip-fb-recreate@cd-dp2-hdmi-a3.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][67] ([Intel XE#1503]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-2/igt@kms_hdr@invalid-hdr.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@kms_hdr@invalid-hdr.html

  * igt@kms_plane_alpha_blend@alpha-7efc:
    - shard-bmg:          [SKIP][69] ([Intel XE#7082]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-6/igt@kms_plane_alpha_blend@alpha-7efc.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-7/igt@kms_plane_alpha_blend@alpha-7efc.html

  * igt@kms_plane_lowres@tiling-4:
    - shard-bmg:          [INCOMPLETE][71] ([Intel XE#5681]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-2/igt@kms_plane_lowres@tiling-4.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-10/igt@kms_plane_lowres@tiling-4.html

  * igt@kms_plane_lowres@tiling-4@pipe-b-hdmi-a-3:
    - shard-bmg:          [INCOMPLETE][73] -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-2/igt@kms_plane_lowres@tiling-4@pipe-b-hdmi-a-3.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-10/igt@kms_plane_lowres@tiling-4@pipe-b-hdmi-a-3.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-bmg:          [SKIP][75] ([Intel XE#1435]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-6/igt@kms_setmode@clone-exclusive-crtc.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][77], [PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [SKIP][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102]) ([Intel XE#2457] / [Intel XE#7405]) -> ([PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-1/igt@xe_module_load@load.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-7/igt@xe_module_load@load.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-7/igt@xe_module_load@load.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-5/igt@xe_module_load@load.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-5/igt@xe_module_load@load.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-3/igt@xe_module_load@load.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-5/igt@xe_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-4/igt@xe_module_load@load.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-4/igt@xe_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-9/igt@xe_module_load@load.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-9/igt@xe_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-9/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-10/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-10/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-10/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-8/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-8/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-8/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-6/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-6/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-5/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-3/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-3/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-1/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-2/igt@xe_module_load@load.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-2/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-9/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-7/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-8/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-8/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-10/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-10/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-2/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-3/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-10/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-6/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-3/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-4/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-4/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-8/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-3/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-7/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-7/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-9/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-2/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@xe_module_load@load.html

  
#### Warnings ####

  * igt@kms_content_protection@lic-type-0:
    - shard-bmg:          [FAIL][128] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) -> [SKIP][129] ([Intel XE#2341])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-10/igt@kms_content_protection@lic-type-0.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-3/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@srm:
    - shard-bmg:          [SKIP][130] ([Intel XE#2341]) -> [FAIL][131] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374])
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-5/igt@kms_content_protection@srm.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-9/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-bmg:          [SKIP][132] ([Intel XE#2320]) -> [SKIP][133] ([Intel XE#2321] / [Intel XE#7355]) +1 other test skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-6/igt@kms_cursor_crc@cursor-offscreen-512x512.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-bmg:          [INCOMPLETE][134] -> [SKIP][135] ([Intel XE#2316])
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][136] ([Intel XE#2312]) -> [SKIP][137] ([Intel XE#4141]) +4 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][138] ([Intel XE#4141]) -> [SKIP][139] ([Intel XE#2312]) +5 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-10/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][140] ([Intel XE#2312]) -> [SKIP][141] ([Intel XE#2311]) +10 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-mmap-wc.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt:
    - shard-bmg:          [SKIP][142] ([Intel XE#2311]) -> [SKIP][143] ([Intel XE#2312]) +8 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff:
    - shard-bmg:          [SKIP][144] ([Intel XE#2313]) -> [SKIP][145] ([Intel XE#2312]) +8 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][146] ([Intel XE#2312]) -> [SKIP][147] ([Intel XE#2313]) +8 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-9/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-bmg:          [SKIP][148] ([Intel XE#4596]) -> [SKIP][149] ([Intel XE#5021] / [Intel XE#7377])
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-yf.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-9/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-bmg:          [SKIP][150] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342]) -> [SKIP][151] ([Intel XE#3904] / [Intel XE#7342])
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][152] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][153] ([Intel XE#1729] / [Intel XE#7424])
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4746-73694175c9632682b410199c5987a3420bd5444c/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4294
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5408
  [Intel XE#5681]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5681
  [Intel XE#5694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5694
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#6266]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6266
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7082]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7082
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7140
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7373
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7377]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7377
  [Intel XE#7378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7378
  [Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
  [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7429]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7429
  [Intel XE#7442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7442
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836


Build changes
-------------

  * Linux: xe-4746-73694175c9632682b410199c5987a3420bd5444c -> xe-pw-163523v1

  IGT_8810: eb9035ba642724dc0a7711672805f26d1f34f712 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4746-73694175c9632682b410199c5987a3420bd5444c: 73694175c9632682b410199c5987a3420bd5444c
  xe-pw-163523v1: 163523v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163523v1/index.html

[-- Attachment #2: Type: text/html, Size: 42956 bytes --]