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From: Raag Jadav <raag.jadav@intel.com>
To: Badal Nilawar <badal.nilawar@intel.com>
Cc: intel-xe@lists.freedesktop.org, anshuman.gupta@intel.com,
	rodrigo.vivi@intel.com, daniele.ceraolospurio@intel.com,
	riana.tauro@intel.com, mallesh.koujalagi@intel.com,
	aravind.iddamsetty@intel.com, himal.prasad.ghimiray@intel.com,
	arvind.yadav@intel.com, syed.abdul.muqthyar.ahmed@intel.com,
	nitin.r.gote@intel.com, pravalika.gurram@intel.com
Subject: Re: [PATCH v4 06/12] drm/xe/cper: Prepare Intel CPER error info records
Date: Thu, 15 Oct 2026 11:45:51 +0200	[thread overview]
Message-ID: <atCgz0lfetLrUyao@black.igk.intel.com> (raw)
In-Reply-To: <20261009104602.1075405-20-badal.nilawar@intel.com>

On Fri, Oct 09, 2026 at 04:16:09PM +0530, Badal Nilawar wrote:
> Prepare xe_cper_sec_intel_error_info records from RAS info queue data.
> Depending on the error class type, detail or aggregate, one or more error
> info records may be generated and embedded in the CPER record.
> 
> Assisted-by: Copilot:Claude-Opus-5.5
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> v4:
>  - Move struct xe_cper_einfo_entry to xe_cper_types.h (Raag)
>  - Use kzalloc_flex()/kzalloc_objs() (Raag)
>  - Allocate info queue buffer from reported total size (Raag)
> ---
>  drivers/gpu/drm/xe/xe_cper.c       | 247 +++++++++++++++++++++++++++--
>  drivers/gpu/drm/xe/xe_cper_types.h |  54 ++++++-
>  2 files changed, 290 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> index 1000c78b41e9..7acb503efd11 100644
> --- a/drivers/gpu/drm/xe/xe_cper.c
> +++ b/drivers/gpu/drm/xe/xe_cper.c
> @@ -78,16 +78,22 @@ static u64 cper_timestamp_now(void)
>  	return ts;
>  }
>  
> +static void fill_cper_error_class(struct xe_cper_error_class *dst,
> +				  const struct xe_ras_error_class *src)
> +{
> +	dst->error_type = src->common.severity;
> +	dst->error_component = src->common.component;
> +	dst->tile = src->product.unit.tile;
> +	dst->instance = src->product.unit.instance;
> +	dst->cause = src->product.cause.cause;
> +}

No needless refactoring, please introduce this function in the original
patch. Assuming you'll reuse struct xe_ras_error_class here, this can
simply be a memcpy().

...

> +/**
> + * struct xe_cper_sec_intel_error_info - Variable-length Intel GPU error payload

Do we really need to add 'error' everywhere?

> + * Appended after &xe_cper_sec_intel_err_hdr when detailed per-event data
> + * is available. The @event_queue flexible array holds @event_queue_count
> + * packed &xe_intel_priv_event_entry records.
> + */
> +struct xe_cper_sec_intel_error_info {
> +	/** @error_class: Error classification */
> +	struct xe_cper_error_class error_class;

'counter'

> +	/** @error_count: Total number of errors recorded */
> +	u32 error_count;

'count'

> +	/** @event_queue_length: Total byte size of the @event_queue array */
> +	u32 event_queue_length;

'queue_length'

> +	/** @event_queue_count: Number of entries in @event_queue */
> +	u32 event_queue_count;

'queue_count'

> +	/** @event_queue: Packed array of &xe_intel_priv_event_entry records */
> +	u8 event_queue[];

'queue'

> +};
> +
> +/**
> + * struct xe_intel_priv_event_entry - Single error event in the event queue

All cper struct must contain 'cper' naming. Also, redundant 'event'.

> + * Each entry is variable-length; @entry_length gives the byte size of
> + * @metadata only (not including @entry_length or @timestamp).
> + */
> +struct xe_intel_priv_event_entry {
> +	/** @entry_length: Byte length of the @metadata payload */
> +	u32 entry_length;

'length'

> +	/** @timestamp: Timestamp of this event, in firmware ticks */
> +	u64 timestamp;
> +	/** @metadata: Event-specific payload bytes */
> +	u8  metadata[];

Nit: Fix the spacing.

> +};
> +
>  /**
>   * struct xe_cper_nonstd_record - Intel GPU CPER record
>   *
>   * Contains the standard CPER record header, section descriptor, and the
> - * Intel error section header.
> + * Intel error section header. A &xe_cper_sec_intel_error_info payload
> + * may be appended dynamically.
>   */
>  struct xe_cper_nonstd_record {
>  	/** @record_hdr: Standard CPER record header (UEFI Appendix N.2.1) */
> @@ -122,4 +160,18 @@ struct xe_platform_id_entry {
>  	guid_t    platform_id;
>  };
>  
> +/**
> + * struct xe_cper_einfo_entry - One CPER error info payload and its source counter
> + */
> +struct xe_cper_einfo_entry {
> +	/** @hdr: Error class and counter value used for the CPER section header */
> +	struct xe_ras_info_queue_dynamic_counter_hdr hdr;
> +	/** @einfo: Allocated error info payload, NULL if none */
> +	struct xe_cper_sec_intel_error_info *einfo;
> +	/** @einfo_size: Byte size of @einfo including the event queue */
> +	u32 einfo_size;

You're using length and size interchangeably. Whatever your preference,
please use consistent naming for the terminology (in all places where
applicable).

Raag

> +	/** @timestamp: Timestamp of the first occurrence of this error class */
> +	u64 timestamp;
> +};
> +
>  #endif
> -- 
> 2.54.0
> 

  parent reply	other threads:[~2026-10-15  9:46 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-09 10:46 [PATCH v4 00/12] Add CPER logging support for CRI Badal Nilawar
2026-10-09 10:46 ` [PATCH v4 01/12] drm/xe/cper: Add CPER reporting entry point for xe_log Badal Nilawar
2026-10-09 10:43   ` sashiko-bot
2026-10-09 12:17     ` Nilawar, Badal
2026-10-12  6:18   ` Raag Jadav
2026-10-09 10:46 ` [PATCH v4 02/12] drm/xe/cper: Retrieve the error counter record for CPER reporting Badal Nilawar
2026-10-09 10:46   ` sashiko-bot
2026-10-09 12:27     ` Nilawar, Badal
2026-10-12  9:07   ` Raag Jadav
2026-10-09 10:46 ` [PATCH v4 03/12] drm/xe/cper: Initialize Intel-specific error section header Badal Nilawar
2026-10-14  7:27   ` Raag Jadav
2026-10-09 10:46 ` [PATCH v4 04/12] drm/xe/cper: Construct CPER record for hardware errors Badal Nilawar
2026-10-14 10:30   ` Raag Jadav
2026-10-09 10:46 ` [PATCH v4 05/12] drm/xe/xe_ras: Add support to retrieve info queue data for CRI Badal Nilawar
2026-10-09 10:40   ` sashiko-bot
2026-10-09 12:45     ` Nilawar, Badal
2026-10-14 15:19   ` Raag Jadav
2026-10-09 10:46 ` [PATCH v4 06/12] drm/xe/cper: Prepare Intel CPER error info records Badal Nilawar
2026-10-09 10:41   ` sashiko-bot
2026-10-09 13:07     ` Nilawar, Badal
2026-10-15  9:45   ` Raag Jadav [this message]
2026-10-09 10:46 ` [PATCH v4 07/12] drm/xe/cper: Log CPER records for aggregate counter retrieval Badal Nilawar
2026-10-15 10:36   ` Raag Jadav
2026-10-09 10:46 ` [PATCH v4 08/12] drm/xe/cper: Emit cper record to trace buf Badal Nilawar
2026-10-09 10:38   ` sashiko-bot
2026-10-09 10:46 ` [PATCH v4 09/12] drm/xe/xe_ras: Report device memory errors using SIGID Badal Nilawar
2026-10-14  9:05   ` Mallesh, Koujalagi
2026-10-09 10:46 ` [PATCH v4 10/12] drm/xe/xe_ras: Report core compute " Badal Nilawar
2026-10-14  9:28   ` Mallesh, Koujalagi
2026-10-14  9:30     ` Tauro, Riana
2026-10-16  2:55   ` Raag Jadav
2026-10-09 10:46 ` [PATCH v4 11/12] drm/xe/xe_ras: Report soc internal " Badal Nilawar
2026-10-14  9:31   ` Mallesh, Koujalagi
2026-10-16  3:01   ` Raag Jadav
2026-10-09 10:46 ` [PATCH v4 12/12] drm/xe/xe_ras: Report correctable " Badal Nilawar
2026-10-09 10:50   ` sashiko-bot
2026-10-16  3:05   ` Raag Jadav
2026-10-09 10:54 ` ✗ CI.checkpatch: warning for Add CPER logging support for CRI (rev4) Patchwork
2026-10-09 10:56 ` ✓ CI.KUnit: success " Patchwork
2026-10-09 12:03 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-10-09 15:13 ` ✓ Xe.CI.FULL: success " Patchwork
2026-10-12  6:14 ` [PATCH v4 00/12] Add CPER logging support for CRI Raag Jadav

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