* [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P
@ 2026-02-05 23:39 Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 01/15] drm/xe/xe3p_lpg: Add support for graphics IP 35.10 Gustavo Sousa
` (18 more replies)
0 siblings, 19 replies; 23+ messages in thread
From: Gustavo Sousa @ 2026-02-05 23:39 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: Gustavo Sousa, Shekhar Chauhan, Matt Roper, Nitin Gote,
Tangudu Tilak Tirumalesh, Mallesh Koujalagi, Tejas Upadhyay,
Matt Atwood, Dnyaneshwar Bhadane, Aradhya Bhatia, Suraj Kandpal
NVL-P is a new Intel platform that comes with the following IPs:
- Xe3p_LPG graphics;
- Xe3p_LPM media;
- Xe3p_LPD display.
Enabling patches for Xe3p_LPM and Xe3p_LPD are already integrated in our
driver. In this series we add patches enabling Xe3p_LPG and then follow
up with patches enabling NVL-P as a platform in our driver.
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
Changes in v2:
- Added patch "drm/xe/nvlp: Bump maximum WOPCM size", which was missing
in v1.
- Incorporated review feedback. Please see the changelog in the
individual patches for details.
- Dropped patch "drm/xe/nvlp: Define GuC firmware for NVL-P". I'll
apply this separately to topic/xe-for-CI and decided to drop from v2
to avoid accidentally applying it to drm-xe-next.
- Link to v1: https://patch.msgid.link/20260202-nvl-p-upstreaming-v1-0-653e4ff105dc@intel.com
---
Aradhya Bhatia (1):
drm/xe/xe3p_lpg: Set STLB bank hash mode to 4KB
Dnyaneshwar Bhadane (1):
drm/xe/nvlp: Attach MOCS table for nvlp
Gustavo Sousa (3):
drm/xe/pat: Differentiate between primary and media for PTA
drm/xe/xe3p_lpg: Update LRC sizes
drm/xe/nvlp: Bump maximum WOPCM size
Matt Roper (7):
drm/xe/xe3p_lpg: Add new PAT table
drm/xe/xe3p_lpg: Add MCR steering
drm/xe/xe3p_lpg: Add LRC parsing for additional RCS engine state
drm/xe/xe3p_lpg: Disable reporting of context switch status to GHWSP
drm/xe/xe3p_lpg: Drop unnecessary tuning settings
drm/xe/xe3p_lpg: Extend 'group ID' mask size
drm/i915/nvlp: Hook up display support
Shekhar Chauhan (3):
drm/xe/xe3p_lpg: Add support for graphics IP 35.10
drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10
drm/xe/nvlp: Add NVL-P platform definition
.../gpu/drm/i915/display/intel_display_device.c | 1 +
.../gpu/drm/xe/instructions/xe_gfxpipe_commands.h | 10 +++
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 20 +++++-
drivers/gpu/drm/xe/xe_bo.c | 4 +-
drivers/gpu/drm/xe/xe_device_types.h | 8 ++-
drivers/gpu/drm/xe/xe_gt_mcr.c | 18 ++++-
drivers/gpu/drm/xe/xe_lrc.c | 18 ++++-
drivers/gpu/drm/xe/xe_mocs.c | 1 +
drivers/gpu/drm/xe/xe_pat.c | 82 +++++++++++++++++++---
drivers/gpu/drm/xe/xe_pci.c | 21 ++++++
drivers/gpu/drm/xe/xe_platform_types.h | 1 +
drivers/gpu/drm/xe/xe_reg_whitelist.c | 8 +++
drivers/gpu/drm/xe/xe_tuning.c | 22 +++++-
drivers/gpu/drm/xe/xe_wa.c | 43 ++++++++++++
drivers/gpu/drm/xe/xe_wopcm.c | 15 +++-
include/drm/intel/pciids.h | 12 ++++
16 files changed, 259 insertions(+), 25 deletions(-)
---
base-commit: 75acb0a8b6f69c6429941e6845df2af94ed15939
change-id: 20260130-nvl-p-upstreaming-e69efaf1db91
Best regards,
--
Gustavo Sousa <gustavo.sousa@intel.com>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 01/15] drm/xe/xe3p_lpg: Add support for graphics IP 35.10
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
@ 2026-02-05 23:39 ` Gustavo Sousa
2026-02-06 15:26 ` Matt Roper
2026-02-05 23:39 ` [PATCH v2 02/15] drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10 Gustavo Sousa
` (17 subsequent siblings)
18 siblings, 1 reply; 23+ messages in thread
From: Gustavo Sousa @ 2026-02-05 23:39 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Gustavo Sousa, Shekhar Chauhan, Matt Roper
From: Shekhar Chauhan <shekhar.chauhan@intel.com>
Add Xe3p_LPG graphics IP version 35.10. Xe3p_LPG supports all features
described by XE2_GFX_FEATURES and also multi-queue feature on BCS and
CCS engines. As such, create a new struct xe_graphics_desc named
graphics_xe3p_lpg that inherits from XE2_GFX_FEATURES and also includes
the necessary .multi_queue_engine_class_mask.
Here is a list of fields and associated Bspec references for the members
of the IP descriptor:
.hw_engine_mask (Bspec 60149)
.multi_queue_engine_class_mask (Bspec 74110)
.has_asid (Bspec 71132)
.has_atomic_enable_pte_bit (Bspec 59510, 74675)
.has_indirect_ring_state (Bspec 67296)
.has_range_tlb_inval (Bspec 71126)
.has_usm (Bspec 59651)
.has_64bit_timestamp (Bspec 60318)
v2:
- Drop non-existing fields from the list in the commit message. (Matt)
- Squash patch adding .multi_queue_engine_class_mask here. (Matt)
- Rename graphics_xe3p to graphics_xe3p_lpg. (Matt)
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/xe/xe_pci.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index b5e8935fff1d..08e0ff9f75e8 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -106,6 +106,11 @@ static const struct xe_graphics_desc graphics_xe2 = {
XE2_GFX_FEATURES,
};
+static const struct xe_graphics_desc graphics_xe3p_lpg = {
+ XE2_GFX_FEATURES,
+ .multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | BIT(XE_ENGINE_CLASS_COMPUTE),
+};
+
static const struct xe_graphics_desc graphics_xe3p_xpc = {
XE2_GFX_FEATURES,
.has_indirect_ring_state = 1,
@@ -148,6 +153,7 @@ static const struct xe_ip graphics_ips[] = {
{ 3003, "Xe3_LPG", &graphics_xe2 },
{ 3004, "Xe3_LPG", &graphics_xe2 },
{ 3005, "Xe3_LPG", &graphics_xe2 },
+ { 3510, "Xe3p_LPG", &graphics_xe3p_lpg },
{ 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
};
--
2.52.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 02/15] drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 01/15] drm/xe/xe3p_lpg: Add support for graphics IP 35.10 Gustavo Sousa
@ 2026-02-05 23:39 ` Gustavo Sousa
2026-02-06 15:25 ` Matt Roper
2026-02-05 23:39 ` [PATCH v2 03/15] drm/xe/pat: Differentiate between primary and media for PTA Gustavo Sousa
` (16 subsequent siblings)
18 siblings, 1 reply; 23+ messages in thread
From: Gustavo Sousa @ 2026-02-05 23:39 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: Gustavo Sousa, Shekhar Chauhan, Matt Roper, Nitin Gote,
Tangudu Tilak Tirumalesh, Mallesh Koujalagi
From: Shekhar Chauhan <shekhar.chauhan@intel.com>
Add the initial set of workarounds for Xe3p_LPG graphics version 35.10.
v2:
- Fix spacing style for field LOCALITYDIS. (Matt)
- Drop unnecessary Wa_14025780377. (Matt)
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Co-developed-by: Nitin Gote <nitin.r.gote@intel.com>
Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
Co-developed-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
Co-developed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
Signed-off-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
Co-developed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 16 +++++++++++++
drivers/gpu/drm/xe/xe_reg_whitelist.c | 8 +++++++
drivers/gpu/drm/xe/xe_wa.c | 43 +++++++++++++++++++++++++++++++++++
3 files changed, 67 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 24fc64fc832e..55f5be7283db 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -100,6 +100,9 @@
#define VE1_AUX_INV XE_REG(0x42b8)
#define AUX_INV REG_BIT(0)
+#define GAMSTLB_CTRL2 XE_REG_MCR(0x4788)
+#define STLB_SINGLE_BANK_MODE REG_BIT(11)
+
#define XE2_LMEM_CFG XE_REG(0x48b0)
#define XE2_GAMWALK_CTRL 0x47e4
@@ -107,6 +110,9 @@
#define XE2_GAMWALK_CTRL_3D XE_REG_MCR(XE2_GAMWALK_CTRL)
#define EN_CMP_1WCOH_GW REG_BIT(14)
+#define MMIOATSREQLIMIT_GAM_WALK_3D XE_REG_MCR(0x47f8)
+#define DIS_ATS_WRONLY_PG REG_BIT(18)
+
#define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910)
#define XEHP_FLAT_CCS_PTR REG_GENMASK(31, 8)
@@ -210,6 +216,9 @@
#define GSCPSMI_BASE XE_REG(0x880c)
+#define CCCHKNREG2 XE_REG_MCR(0x881c)
+#define LOCALITYDIS REG_BIT(7)
+
#define CCCHKNREG1 XE_REG_MCR(0x8828)
#define L3CMPCTRL REG_BIT(23)
#define ENCOMPPERFFIX REG_BIT(18)
@@ -420,6 +429,8 @@
#define LSN_DIM_Z_WGT(value) REG_FIELD_PREP(LSN_DIM_Z_WGT_MASK, value)
#define L3SQCREG2 XE_REG_MCR(0xb104)
+#define L3_SQ_DISABLE_COAMA_2WAY_COH REG_BIT(30)
+#define L3_SQ_DISABLE_COAMA REG_BIT(22)
#define COMPMEMRD256BOVRFETCHEN REG_BIT(20)
#define L3SQCREG3 XE_REG_MCR(0xb108)
@@ -550,11 +561,16 @@
#define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32)
#define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32)
#define XE2_ALLOC_DPA_STARVE_FIX_DIS REG_BIT(47 - 32)
+#define SAMPLER_LD_LSC_DISABLE REG_BIT(45 - 32)
#define ENABLE_SMP_LD_RENDER_SURFACE_CONTROL REG_BIT(44 - 32)
#define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32)
#define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32)
#define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32)
#define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32)
+#define LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE REG_BIT(35 - 32)
+
+#define ROW_CHICKEN5 XE_REG_MCR(0xe7f0)
+#define CPSS_AWARE_DIS REG_BIT(3)
#define SARB_CHICKEN1 XE_REG_MCR(0xe90c)
#define COMP_CKN_IN REG_GENMASK(30, 29)
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index 1d36c09681aa..9c513778d370 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -81,6 +81,14 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
WHITELIST(VFLSKPD,
RING_FORCE_TO_NONPRIV_ACCESS_RW))
},
+ { XE_RTP_NAME("14024997852"),
+ XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
+ ENGINE_CLASS(RENDER)),
+ XE_RTP_ACTIONS(WHITELIST(FF_MODE,
+ RING_FORCE_TO_NONPRIV_ACCESS_RW),
+ WHITELIST(VFLSKPD,
+ RING_FORCE_TO_NONPRIV_ACCESS_RW))
+ },
#define WHITELIST_OA_MMIO_TRG(trg, status, head) \
WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 1e8d61ac581b..682865f1fc16 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -325,6 +325,31 @@ static const struct xe_rtp_entry_sr gt_was[] = {
XE_RTP_RULES(MEDIA_VERSION(3500)),
XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
},
+
+ /* Xe3P_LPG */
+
+ { XE_RTP_NAME("14025160223"),
+ XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
+ XE_RTP_ACTIONS(SET(MMIOATSREQLIMIT_GAM_WALK_3D,
+ DIS_ATS_WRONLY_PG))
+ },
+ { XE_RTP_NAME("16028780921"),
+ XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
+ XE_RTP_ACTIONS(SET(CCCHKNREG2, LOCALITYDIS))
+ },
+ { XE_RTP_NAME("14026144927"),
+ XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
+ XE_RTP_ACTIONS(SET(L3SQCREG2, L3_SQ_DISABLE_COAMA_2WAY_COH |
+ L3_SQ_DISABLE_COAMA))
+ },
+ { XE_RTP_NAME("14025635424"),
+ XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
+ XE_RTP_ACTIONS(SET(GAMSTLB_CTRL2, STLB_SINGLE_BANK_MODE))
+ },
+ { XE_RTP_NAME("16028005424"),
+ XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
+ XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
+ },
};
static const struct xe_rtp_entry_sr engine_was[] = {
@@ -699,6 +724,24 @@ static const struct xe_rtp_entry_sr engine_was[] = {
FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
},
+
+ /* Xe3p_LPG*/
+
+ { XE_RTP_NAME("22021149932"),
+ XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
+ FUNC(xe_rtp_match_first_render_or_compute)),
+ XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, SAMPLER_LD_LSC_DISABLE))
+ },
+ { XE_RTP_NAME("14025676848"),
+ XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
+ FUNC(xe_rtp_match_first_render_or_compute)),
+ XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE))
+ },
+ { XE_RTP_NAME("16028951944"),
+ XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
+ FUNC(xe_rtp_match_first_render_or_compute)),
+ XE_RTP_ACTIONS(SET(ROW_CHICKEN5, CPSS_AWARE_DIS))
+ },
};
static const struct xe_rtp_entry_sr lrc_was[] = {
--
2.52.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 03/15] drm/xe/pat: Differentiate between primary and media for PTA
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 01/15] drm/xe/xe3p_lpg: Add support for graphics IP 35.10 Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 02/15] drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10 Gustavo Sousa
@ 2026-02-05 23:39 ` Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 04/15] drm/xe/xe3p_lpg: Add new PAT table Gustavo Sousa
` (15 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Gustavo Sousa @ 2026-02-05 23:39 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Gustavo Sousa, Matt Roper, Tejas Upadhyay
Differently from currently supported platforms, in upcoming changes we
will need to have different PAT entries for PTA based on the GT type. As
such, let's prepare the code to support that by having two separate
PTA-specific members in the pat struct, one for each type of GT.
While at it, also fix the kerneldoc for pat_ats.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Co-developed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 8 +++++---
drivers/gpu/drm/xe/xe_pat.c | 27 ++++++++++++++++++---------
2 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 14bf2c027f89..059f026e80d5 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -400,10 +400,12 @@ struct xe_device {
const struct xe_pat_table_entry *table;
/** @pat.n_entries: Number of PAT entries */
int n_entries;
- /** @pat.ats_entry: PAT entry for PCIe ATS responses */
+ /** @pat.pat_ats: PAT entry for PCIe ATS responses */
const struct xe_pat_table_entry *pat_ats;
- /** @pat.pta_entry: PAT entry for page table accesses */
- const struct xe_pat_table_entry *pat_pta;
+ /** @pat.pat_primary_pta: primary GT PAT entry for page table accesses */
+ const struct xe_pat_table_entry *pat_primary_pta;
+ /** @pat.pat_media_pta: media GT PAT entry for page table accesses */
+ const struct xe_pat_table_entry *pat_media_pta;
u32 idx[__XE_CACHE_LEVEL_COUNT];
} pat;
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index 2cd3fd1c3953..5ba650948a4a 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -285,8 +285,10 @@ static void program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[
if (xe->pat.pat_ats)
xe_mmio_write32(>->mmio, XE_REG(_PAT_ATS), xe->pat.pat_ats->value);
- if (xe->pat.pat_pta)
- xe_mmio_write32(>->mmio, XE_REG(_PAT_PTA), xe->pat.pat_pta->value);
+ if (xe->pat.pat_primary_pta && xe_gt_is_main_type(gt))
+ xe_mmio_write32(>->mmio, XE_REG(_PAT_PTA), xe->pat.pat_primary_pta->value);
+ if (xe->pat.pat_media_pta && xe_gt_is_media_type(gt))
+ xe_mmio_write32(>->mmio, XE_REG(_PAT_PTA), xe->pat.pat_media_pta->value);
}
static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry table[],
@@ -302,8 +304,10 @@ static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry ta
if (xe->pat.pat_ats)
xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), xe->pat.pat_ats->value);
- if (xe->pat.pat_pta)
- xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe->pat.pat_pta->value);
+ if (xe->pat.pat_primary_pta && xe_gt_is_main_type(gt))
+ xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe->pat.pat_primary_pta->value);
+ if (xe->pat.pat_media_pta && xe_gt_is_media_type(gt))
+ xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe->pat.pat_media_pta->value);
}
static int xelp_dump(struct xe_gt *gt, struct drm_printer *p)
@@ -498,7 +502,8 @@ void xe_pat_init_early(struct xe_device *xe)
xe->pat.ops = &xe3p_xpc_pat_ops;
xe->pat.table = xe3p_xpc_pat_table;
xe->pat.pat_ats = &xe3p_xpc_pat_ats;
- xe->pat.pat_pta = &xe3p_xpc_pat_pta;
+ xe->pat.pat_primary_pta = &xe3p_xpc_pat_pta;
+ xe->pat.pat_media_pta = &xe3p_xpc_pat_pta;
xe->pat.n_entries = ARRAY_SIZE(xe3p_xpc_pat_table);
xe->pat.idx[XE_CACHE_NONE] = 3;
xe->pat.idx[XE_CACHE_WT] = 3; /* N/A (no display); use UC */
@@ -512,8 +517,10 @@ void xe_pat_init_early(struct xe_device *xe)
xe->pat.table = xe2_pat_table;
}
xe->pat.pat_ats = &xe2_pat_ats;
- if (IS_DGFX(xe))
- xe->pat.pat_pta = &xe2_pat_pta;
+ if (IS_DGFX(xe)) {
+ xe->pat.pat_primary_pta = &xe2_pat_pta;
+ xe->pat.pat_media_pta = &xe2_pat_pta;
+ }
/* Wa_16023588340. XXX: Should use XE_WA */
if (GRAPHICS_VERx100(xe) == 2001)
@@ -617,6 +624,8 @@ int xe_pat_dump(struct xe_gt *gt, struct drm_printer *p)
int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p)
{
struct xe_device *xe = gt_to_xe(gt);
+ const struct xe_pat_table_entry *pta_entry = xe_gt_is_main_type(gt) ?
+ xe->pat.pat_primary_pta : xe->pat.pat_media_pta;
char label[PAT_LABEL_LEN];
if (!xe->pat.table || !xe->pat.n_entries)
@@ -640,8 +649,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p)
}
}
- if (xe->pat.pat_pta) {
- u32 pat = xe->pat.pat_pta->value;
+ if (pta_entry) {
+ u32 pat = pta_entry->value;
drm_printf(p, "Page Table Access:\n");
xe->pat.ops->entry_dump(p, "PTA_MODE", pat, false);
--
2.52.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 04/15] drm/xe/xe3p_lpg: Add new PAT table
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
` (2 preceding siblings ...)
2026-02-05 23:39 ` [PATCH v2 03/15] drm/xe/pat: Differentiate between primary and media for PTA Gustavo Sousa
@ 2026-02-05 23:39 ` Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 05/15] drm/xe/xe3p_lpg: Add MCR steering Gustavo Sousa
` (14 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Gustavo Sousa @ 2026-02-05 23:39 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Gustavo Sousa, Matt Roper, Matt Atwood
From: Matt Roper <matthew.d.roper@intel.com>
PAT programming for Xe3p_LPG is more similar to Xe2 and Xe3 than it is
to Xe3p_XPC. Compared to Xe2/Xe3 we have:
* There's a slight update to the PAT table, where two new indices (18
and 19) are added to expose a new "WB - Transient App" L3 caching
mode.
* The PTA_MODE entry must be programmed differently according to the
media type, and both differ from Xe2.
There are no changes to the underlying registers, so the Xe2 ops can be
re-used for Xe3p.
Bspec: 71582, 74160
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/xe/xe_pat.c | 55 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 54 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index 5ba650948a4a..f840d9a58740 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -124,7 +124,8 @@ static const struct xe_pat_table_entry xelpg_pat_table[] = {
* - no_promote: 0=promotable, 1=no promote
* - comp_en: 0=disable, 1=enable
* - l3clos: L3 class of service (0-3)
- * - l3_policy: 0=WB, 1=XD ("WB - Transient Display"), 3=UC
+ * - l3_policy: 0=WB, 1=XD ("WB - Transient Display"),
+ * 2=XA ("WB - Transient App" for Xe3p), 3=UC
* - l4_policy: 0=WB, 1=WT, 3=UC
* - coh_mode: 0=no snoop, 2=1-way coherent, 3=2-way coherent
*
@@ -253,6 +254,44 @@ static const struct xe_pat_table_entry xe3p_xpc_pat_table[] = {
[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),
};
+static const struct xe_pat_table_entry xe3p_primary_pat_pta = XE2_PAT(0, 0, 0, 0, 0, 3);
+static const struct xe_pat_table_entry xe3p_media_pat_pta = XE2_PAT(0, 0, 0, 0, 0, 2);
+
+static const struct xe_pat_table_entry xe3p_lpg_pat_table[] = {
+ [ 0] = XE2_PAT( 0, 0, 0, 0, 3, 0 ),
+ [ 1] = XE2_PAT( 0, 0, 0, 0, 3, 2 ),
+ [ 2] = XE2_PAT( 0, 0, 0, 0, 3, 3 ),
+ [ 3] = XE2_PAT( 0, 0, 0, 3, 3, 0 ),
+ [ 4] = XE2_PAT( 0, 0, 0, 3, 0, 2 ),
+ [ 5] = XE2_PAT( 0, 0, 0, 3, 3, 2 ),
+ [ 6] = XE2_PAT( 1, 0, 0, 1, 3, 0 ),
+ [ 7] = XE2_PAT( 0, 0, 0, 3, 0, 3 ),
+ [ 8] = XE2_PAT( 0, 0, 0, 3, 0, 0 ),
+ [ 9] = XE2_PAT( 0, 1, 0, 0, 3, 0 ),
+ [10] = XE2_PAT( 0, 1, 0, 3, 0, 0 ),
+ [11] = XE2_PAT( 1, 1, 0, 1, 3, 0 ),
+ [12] = XE2_PAT( 0, 1, 0, 3, 3, 0 ),
+ [13] = XE2_PAT( 0, 0, 0, 0, 0, 0 ),
+ [14] = XE2_PAT( 0, 1, 0, 0, 0, 0 ),
+ [15] = XE2_PAT( 1, 1, 0, 1, 1, 0 ),
+ [16] = XE2_PAT( 0, 1, 0, 0, 3, 2 ),
+ /* 17 is reserved; leave set to all 0's */
+ [18] = XE2_PAT( 1, 0, 0, 2, 3, 0 ),
+ [19] = XE2_PAT( 1, 0, 0, 2, 3, 2 ),
+ [20] = XE2_PAT( 0, 0, 1, 0, 3, 0 ),
+ [21] = XE2_PAT( 0, 1, 1, 0, 3, 0 ),
+ [22] = XE2_PAT( 0, 0, 1, 0, 3, 2 ),
+ [23] = XE2_PAT( 0, 0, 1, 0, 3, 3 ),
+ [24] = XE2_PAT( 0, 0, 2, 0, 3, 0 ),
+ [25] = XE2_PAT( 0, 1, 2, 0, 3, 0 ),
+ [26] = XE2_PAT( 0, 0, 2, 0, 3, 2 ),
+ [27] = XE2_PAT( 0, 0, 2, 0, 3, 3 ),
+ [28] = XE2_PAT( 0, 0, 3, 0, 3, 0 ),
+ [29] = XE2_PAT( 0, 1, 3, 0, 3, 0 ),
+ [30] = XE2_PAT( 0, 0, 3, 0, 3, 2 ),
+ [31] = XE2_PAT( 0, 0, 3, 0, 3, 3 ),
+};
+
u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index)
{
WARN_ON(pat_index >= xe->pat.n_entries);
@@ -508,6 +547,20 @@ void xe_pat_init_early(struct xe_device *xe)
xe->pat.idx[XE_CACHE_NONE] = 3;
xe->pat.idx[XE_CACHE_WT] = 3; /* N/A (no display); use UC */
xe->pat.idx[XE_CACHE_WB] = 2;
+ } else if (GRAPHICS_VER(xe) == 35) {
+ xe->pat.ops = &xe2_pat_ops;
+ xe->pat.table = xe3p_lpg_pat_table;
+ xe->pat.pat_ats = &xe2_pat_ats;
+ if (!IS_DGFX(xe)) {
+ xe->pat.pat_primary_pta = &xe3p_primary_pat_pta;
+ xe->pat.pat_media_pta = &xe3p_media_pat_pta;
+ }
+ xe->pat.n_entries = ARRAY_SIZE(xe3p_lpg_pat_table);
+ xe->pat.idx[XE_CACHE_NONE] = 3;
+ xe->pat.idx[XE_CACHE_WT] = 15;
+ xe->pat.idx[XE_CACHE_WB] = 2;
+ xe->pat.idx[XE_CACHE_NONE_COMPRESSION] = 12;
+ xe->pat.idx[XE_CACHE_WB_COMPRESSION] = 16;
} else if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
xe->pat.ops = &xe2_pat_ops;
if (GRAPHICS_VER(xe) == 30) {
--
2.52.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 05/15] drm/xe/xe3p_lpg: Add MCR steering
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
` (3 preceding siblings ...)
2026-02-05 23:39 ` [PATCH v2 04/15] drm/xe/xe3p_lpg: Add new PAT table Gustavo Sousa
@ 2026-02-05 23:39 ` Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 06/15] drm/xe/xe3p_lpg: Add LRC parsing for additional RCS engine state Gustavo Sousa
` (13 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Gustavo Sousa @ 2026-02-05 23:39 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Gustavo Sousa, Matt Roper
From: Matt Roper <matthew.d.roper@intel.com>
Xe3p_LPG has nearly identical steering to Xe2 and Xe3. The only
DSS/XeCore change from those IPs is an additional range from
0xDE00-0xDE7F that was previously reserved, so we can simply grow one of
the existing ranges in the Xe2 table to include it. Similarly, the
"instance0" table is also almost identical, but gains one additional
PSMI range and requires a separate table.
Bspec: 75242
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/xe/xe_gt_mcr.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index 7c1fe9ac120d..b112e551fc79 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -201,7 +201,7 @@ static const struct xe_mmio_range xe2lpg_dss_steering_table[] = {
{ 0x009680, 0x0096FF }, /* DSS */
{ 0x00D800, 0x00D87F }, /* SLICE */
{ 0x00DC00, 0x00DCFF }, /* SLICE */
- { 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */
+ { 0x00DE00, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */
{ 0x00E980, 0x00E9FF }, /* SLICE */
{ 0x013000, 0x0133FF }, /* DSS (0x13000-0x131FF), SLICE (0x13200-0x133FF) */
{},
@@ -280,6 +280,19 @@ static const struct xe_mmio_range xe3p_xpc_instance0_steering_table[] = {
{},
};
+static const struct xe_mmio_range xe3p_lpg_instance0_steering_table[] = {
+ { 0x004000, 0x004AFF }, /* GAM, rsvd, GAMWKR */
+ { 0x008700, 0x00887F }, /* NODE */
+ { 0x00B000, 0x00B3FF }, /* NODE, L3BANK */
+ { 0x00B500, 0x00B6FF }, /* PSMI */
+ { 0x00C800, 0x00CFFF }, /* GAM */
+ { 0x00D880, 0x00D8FF }, /* NODE */
+ { 0x00DD00, 0x00DDFF }, /* MEMPIPE */
+ { 0x00F000, 0x00FFFF }, /* GAM, GAMWKR */
+ { 0x013400, 0x0135FF }, /* MEMPIPE */
+ {},
+};
+
static void init_steering_l3bank(struct xe_gt *gt)
{
struct xe_device *xe = gt_to_xe(gt);
@@ -533,6 +546,9 @@ void xe_gt_mcr_init_early(struct xe_gt *gt)
gt->steering[INSTANCE0].ranges = xe3p_xpc_instance0_steering_table;
gt->steering[L3BANK].ranges = xelpg_l3bank_steering_table;
gt->steering[NODE].ranges = xe3p_xpc_node_steering_table;
+ } else if (GRAPHICS_VERx100(xe) >= 3510) {
+ gt->steering[DSS].ranges = xe2lpg_dss_steering_table;
+ gt->steering[INSTANCE0].ranges = xe3p_lpg_instance0_steering_table;
} else if (GRAPHICS_VER(xe) >= 20) {
gt->steering[DSS].ranges = xe2lpg_dss_steering_table;
gt->steering[SQIDI_PSMI].ranges = xe2lpg_sqidi_psmi_steering_table;
--
2.52.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 06/15] drm/xe/xe3p_lpg: Add LRC parsing for additional RCS engine state
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
` (4 preceding siblings ...)
2026-02-05 23:39 ` [PATCH v2 05/15] drm/xe/xe3p_lpg: Add MCR steering Gustavo Sousa
@ 2026-02-05 23:39 ` Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 07/15] drm/xe/xe3p_lpg: Disable reporting of context switch status to GHWSP Gustavo Sousa
` (12 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Gustavo Sousa @ 2026-02-05 23:39 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Gustavo Sousa, Matt Roper, Matt Atwood
From: Matt Roper <matthew.d.roper@intel.com>
Xe3p_LPG adds some additional state instructions to the RCS engine's
LRC. Add support for these to the debugfs LRC parser.
Note that the bspec's LRC description page seems to have a few mistakes
in the name/spelling of these new instructions (e.g.,
"3DSTATE_TASK_DATA_EXT" instead of "3DSTATE_TASK_SHADER_DATA_EXT" or
"3DSTATE_VIEWPORT_STATE_POINTERS_CL_SF_2" instead of
"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_2").
Bspec: 65182
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h | 10 ++++++++++
drivers/gpu/drm/xe/xe_lrc.c | 10 ++++++++++
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h b/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h
index 457881af8af9..4d854c85e588 100644
--- a/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h
+++ b/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h
@@ -55,6 +55,7 @@
#define PIPELINE_SELECT GFXPIPE_SINGLE_DW_CMD(0x1, 0x4)
#define CMD_3DSTATE_DRAWING_RECTANGLE_FAST GFXPIPE_3D_CMD(0x0, 0x0)
+#define CMD_3DSTATE_CUSTOM_SAMPLE_PATTERN GFXPIPE_3D_CMD(0x0, 0x2)
#define CMD_3DSTATE_CLEAR_PARAMS GFXPIPE_3D_CMD(0x0, 0x4)
#define CMD_3DSTATE_DEPTH_BUFFER GFXPIPE_3D_CMD(0x0, 0x5)
#define CMD_3DSTATE_STENCIL_BUFFER GFXPIPE_3D_CMD(0x0, 0x6)
@@ -138,8 +139,16 @@
#define CMD_3DSTATE_SBE_MESH GFXPIPE_3D_CMD(0x0, 0x82)
#define CMD_3DSTATE_CPSIZE_CONTROL_BUFFER GFXPIPE_3D_CMD(0x0, 0x83)
#define CMD_3DSTATE_COARSE_PIXEL GFXPIPE_3D_CMD(0x0, 0x89)
+#define CMD_3DSTATE_MESH_SHADER_DATA_EXT GFXPIPE_3D_CMD(0x0, 0x8A)
+#define CMD_3DSTATE_TASK_SHADER_DATA_EXT GFXPIPE_3D_CMD(0x0, 0x8B)
+#define CMD_3DSTATE_VIEWPORT_STATE_POINTERS_CC_2 GFXPIPE_3D_CMD(0x0, 0x8D)
+#define CMD_3DSTATE_CC_STATE_POINTERS_2 GFXPIPE_3D_CMD(0x0, 0x8E)
+#define CMD_3DSTATE_SCISSOR_STATE_POINTERS_2 GFXPIPE_3D_CMD(0x0, 0x8F)
+#define CMD_3DSTATE_BLEND_STATE_POINTERS_2 GFXPIPE_3D_CMD(0x0, 0xA0)
+#define CMD_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_2 GFXPIPE_3D_CMD(0x0, 0xA1)
#define CMD_3DSTATE_DRAWING_RECTANGLE GFXPIPE_3D_CMD(0x1, 0x0)
+#define CMD_3DSTATE_URB_MEMORY GFXPIPE_3D_CMD(0x1, 0x1)
#define CMD_3DSTATE_CHROMA_KEY GFXPIPE_3D_CMD(0x1, 0x4)
#define CMD_3DSTATE_POLY_STIPPLE_OFFSET GFXPIPE_3D_CMD(0x1, 0x6)
#define CMD_3DSTATE_POLY_STIPPLE_PATTERN GFXPIPE_3D_CMD(0x1, 0x7)
@@ -160,5 +169,6 @@
#define CMD_3DSTATE_SUBSLICE_HASH_TABLE GFXPIPE_3D_CMD(0x1, 0x1F)
#define CMD_3DSTATE_SLICE_TABLE_STATE_POINTERS GFXPIPE_3D_CMD(0x1, 0x20)
#define CMD_3DSTATE_PTBR_TILE_PASS_INFO GFXPIPE_3D_CMD(0x1, 0x22)
+#define CMD_3DSTATE_SLICE_TABLE_STATE_POINTER_2 GFXPIPE_3D_CMD(0x1, 0xA0)
#endif
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 3db7968aa5e2..e58eb8b9db78 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -1966,6 +1966,7 @@ static int dump_gfxpipe_command(struct drm_printer *p,
MATCH(PIPELINE_SELECT);
MATCH3D(3DSTATE_DRAWING_RECTANGLE_FAST);
+ MATCH3D(3DSTATE_CUSTOM_SAMPLE_PATTERN);
MATCH3D(3DSTATE_CLEAR_PARAMS);
MATCH3D(3DSTATE_DEPTH_BUFFER);
MATCH3D(3DSTATE_STENCIL_BUFFER);
@@ -2049,8 +2050,16 @@ static int dump_gfxpipe_command(struct drm_printer *p,
MATCH3D(3DSTATE_SBE_MESH);
MATCH3D(3DSTATE_CPSIZE_CONTROL_BUFFER);
MATCH3D(3DSTATE_COARSE_PIXEL);
+ MATCH3D(3DSTATE_MESH_SHADER_DATA_EXT);
+ MATCH3D(3DSTATE_TASK_SHADER_DATA_EXT);
+ MATCH3D(3DSTATE_VIEWPORT_STATE_POINTERS_CC_2);
+ MATCH3D(3DSTATE_CC_STATE_POINTERS_2);
+ MATCH3D(3DSTATE_SCISSOR_STATE_POINTERS_2);
+ MATCH3D(3DSTATE_BLEND_STATE_POINTERS_2);
+ MATCH3D(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_2);
MATCH3D(3DSTATE_DRAWING_RECTANGLE);
+ MATCH3D(3DSTATE_URB_MEMORY);
MATCH3D(3DSTATE_CHROMA_KEY);
MATCH3D(3DSTATE_POLY_STIPPLE_OFFSET);
MATCH3D(3DSTATE_POLY_STIPPLE_PATTERN);
@@ -2070,6 +2079,7 @@ static int dump_gfxpipe_command(struct drm_printer *p,
MATCH3D(3DSTATE_SUBSLICE_HASH_TABLE);
MATCH3D(3DSTATE_SLICE_TABLE_STATE_POINTERS);
MATCH3D(3DSTATE_PTBR_TILE_PASS_INFO);
+ MATCH3D(3DSTATE_SLICE_TABLE_STATE_POINTER_2);
default:
drm_printf(p, "[%#010x] unknown GFXPIPE command (pipeline=%#x, opcode=%#x, subopcode=%#x), likely %d dwords\n",
--
2.52.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 07/15] drm/xe/xe3p_lpg: Disable reporting of context switch status to GHWSP
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
` (5 preceding siblings ...)
2026-02-05 23:39 ` [PATCH v2 06/15] drm/xe/xe3p_lpg: Add LRC parsing for additional RCS engine state Gustavo Sousa
@ 2026-02-05 23:39 ` Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 08/15] drm/xe/xe3p_lpg: Drop unnecessary tuning settings Gustavo Sousa
` (11 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Gustavo Sousa @ 2026-02-05 23:39 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Gustavo Sousa, Matt Roper, Matt Atwood
From: Matt Roper <matthew.d.roper@intel.com>
By default the hardware reports context switch status into the global
hardware status page. The Xe driver doesn't use this information for
anything, and as of Xe3p, leaving this setting enabled will prevent
other hardware optimizations from being enabled. Disable this reporting
as suggested by the tuning guide.
Bspec: 72161
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/xe/xe_tuning.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index 5766fa7742d3..a97872b3214b 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -10,6 +10,7 @@
#include <drm/drm_managed.h>
#include <drm/drm_print.h>
+#include "regs/xe_engine_regs.h"
#include "regs/xe_gt_regs.h"
#include "xe_gt_types.h"
#include "xe_platform_types.h"
@@ -107,6 +108,12 @@ static const struct xe_rtp_entry_sr engine_tunings[] = {
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(RT_CTRL, DIS_NULL_QUERY))
},
+ { XE_RTP_NAME("Tuning: disable HW reporting of ctx switch to GHWSP"),
+ XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3500, XE_RTP_END_VERSION_UNDEFINED)),
+ XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
+ GHWSP_CSB_REPORT_DIS,
+ XE_RTP_ACTION_FLAG(ENGINE_BASE)))
+ },
};
static const struct xe_rtp_entry_sr lrc_tunings[] = {
--
2.52.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 08/15] drm/xe/xe3p_lpg: Drop unnecessary tuning settings
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
` (6 preceding siblings ...)
2026-02-05 23:39 ` [PATCH v2 07/15] drm/xe/xe3p_lpg: Disable reporting of context switch status to GHWSP Gustavo Sousa
@ 2026-02-05 23:39 ` Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 09/15] drm/xe/xe3p_lpg: Extend 'group ID' mask size Gustavo Sousa
` (10 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Gustavo Sousa @ 2026-02-05 23:39 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Gustavo Sousa, Matt Roper, Matt Atwood
From: Matt Roper <matthew.d.roper@intel.com>
From Xe3p onward, the desired settings are now the hardware's
default values and the driver does not need to program them explicitly.
Since 35.xx seems to be the starting point for "Xe3p" version numbers;
we'll adjust the bounds of the old programming to stop at 34.99. Even
though there's no platform with version 35.00 at the moment, this is
simplest in case one does show up in the future.
Bspec: 72161, 59928, 59930
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/xe/xe_tuning.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index a97872b3214b..694385ae75f1 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -32,12 +32,12 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
/* Xe2 */
{ XE_RTP_NAME("Tuning: L3 cache"),
- XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+ XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3499)),
XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
},
{ XE_RTP_NAME("Tuning: L3 cache - media"),
- XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
+ XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, 3499)),
XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
},
@@ -53,7 +53,7 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
SET(XE2LPM_CCCHKNREG1, L3CMPCTRL))
},
{ XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3"),
- XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+ XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3499)),
XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
},
{ XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3 - media"),
--
2.52.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 09/15] drm/xe/xe3p_lpg: Extend 'group ID' mask size
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
` (7 preceding siblings ...)
2026-02-05 23:39 ` [PATCH v2 08/15] drm/xe/xe3p_lpg: Drop unnecessary tuning settings Gustavo Sousa
@ 2026-02-05 23:39 ` Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 10/15] drm/xe/xe3p_lpg: Update LRC sizes Gustavo Sousa
` (9 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Gustavo Sousa @ 2026-02-05 23:39 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Gustavo Sousa, Matt Roper, Dnyaneshwar Bhadane
From: Matt Roper <matthew.d.roper@intel.com>
Xe3p_LPG extends the 'group ID' register mask by one bit. Since the new
upper bit (12) was unused on previous platforms, we can safely extend
the existing mask size without worrying about adding conditional version
checks to the register programming.
Bspec: 67175
Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 55f5be7283db..f626cc584bd9 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -58,7 +58,7 @@
#define MCR_SLICE(slice) REG_FIELD_PREP(MCR_SLICE_MASK, slice)
#define MCR_SUBSLICE_MASK REG_GENMASK(26, 24)
#define MCR_SUBSLICE(subslice) REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice)
-#define MTL_MCR_GROUPID REG_GENMASK(11, 8)
+#define MTL_MCR_GROUPID REG_GENMASK(12, 8)
#define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
#define PS_INVOCATION_COUNT XE_REG(0x2348)
--
2.52.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 10/15] drm/xe/xe3p_lpg: Update LRC sizes
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
` (8 preceding siblings ...)
2026-02-05 23:39 ` [PATCH v2 09/15] drm/xe/xe3p_lpg: Extend 'group ID' mask size Gustavo Sousa
@ 2026-02-05 23:39 ` Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 11/15] drm/xe/xe3p_lpg: Set STLB bank hash mode to 4KB Gustavo Sousa
` (8 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Gustavo Sousa @ 2026-02-05 23:39 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Gustavo Sousa, Matt Roper
Like with previous generations, the engine context images for of both
RCS and CCS in Xe3p_LPG contain a common layout at the end for the
context related to the "Compute Pipeline".
The size of the memory area written to such section varies; it depends
on the type of preemption has taken place during the execution and type
of command streamer instruction that was used on the pipeline. For
Xe3p_LPG, the maximum possible size, including NOOPs for cache line
alignment, is 4368 dwords, which would be the case of a mid-thread
preemption during the execution of a COMPUTE_WALKER_2 instruction.
The maximum size has increased in such a way that we need to update
xe_gt_lrc_size() to match the new sizing requirement. When we add that
to the engine-specific parts, we have:
- RCS context image: 6672 dwords = 26688 bytes -> 7 pages
- CCS context image: 5024 dwords = 20096 bytes -> 5 pages
Bspec: 65182, 55793, 73590
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/xe/xe_lrc.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index e58eb8b9db78..38f648b98868 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -113,13 +113,17 @@ size_t xe_gt_lrc_hang_replay_size(struct xe_gt *gt, enum xe_engine_class class)
/* Engine context image */
switch (class) {
case XE_ENGINE_CLASS_RENDER:
- if (GRAPHICS_VER(xe) >= 20)
+ if (GRAPHICS_VERx100(xe) >= 3510)
+ size += 7 * SZ_4K;
+ else if (GRAPHICS_VER(xe) >= 20)
size += 3 * SZ_4K;
else
size += 13 * SZ_4K;
break;
case XE_ENGINE_CLASS_COMPUTE:
- if (GRAPHICS_VER(xe) >= 20)
+ if (GRAPHICS_VERx100(xe) >= 3510)
+ size += 5 * SZ_4K;
+ else if (GRAPHICS_VER(xe) >= 20)
size += 2 * SZ_4K;
else
size += 13 * SZ_4K;
--
2.52.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 11/15] drm/xe/xe3p_lpg: Set STLB bank hash mode to 4KB
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
` (9 preceding siblings ...)
2026-02-05 23:39 ` [PATCH v2 10/15] drm/xe/xe3p_lpg: Update LRC sizes Gustavo Sousa
@ 2026-02-05 23:39 ` Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 12/15] drm/xe/nvlp: Add NVL-P platform definition Gustavo Sousa
` (7 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Gustavo Sousa @ 2026-02-05 23:39 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Gustavo Sousa, Aradhya Bhatia, Matt Roper
From: Aradhya Bhatia <aradhya.bhatia@intel.com>
Since the dominant size of the pages referred in an i-gpu, such as
Xe3p_LPG, will be 4KB, the HW default of mix of 64K and 2M for STLB bank
hash mode does not make sense.
Allow the SW to change it to 4KB Mode, for Xe3p_LPG.
v2:
- Add Bspec reference. (Matt)
Bspec: 78248
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aradhya Bhatia <aradhya.bhatia@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 ++
drivers/gpu/drm/xe/xe_tuning.c | 9 +++++++++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index f626cc584bd9..1d652266f4f3 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -470,6 +470,8 @@
#define FORCE_MISS_FTLB REG_BIT(3)
#define XEHP_GAMSTLB_CTRL XE_REG_MCR(0xcf4c)
+#define BANK_HASH_MODE REG_GENMASK(27, 26)
+#define BANK_HASH_4KB_MODE REG_FIELD_PREP(BANK_HASH_MODE, 0x3)
#define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12)
#define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11)
#define TAG_BLOCK_CLKGATE_DIS REG_BIT(7)
diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index 694385ae75f1..316f5e2b2e48 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -90,6 +90,15 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
XE_RTP_RULES(MEDIA_VERSION(2000)),
XE_RTP_ACTIONS(SET(XE2LPM_SCRATCH3_LBCF, RWFLUSHALLEN))
},
+
+ /* Xe3p */
+
+ { XE_RTP_NAME("Tuning: Set STLB Bank Hash Mode to 4KB"),
+ XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3510, XE_RTP_END_VERSION_UNDEFINED),
+ IS_INTEGRATED),
+ XE_RTP_ACTIONS(FIELD_SET(XEHP_GAMSTLB_CTRL, BANK_HASH_MODE,
+ BANK_HASH_4KB_MODE))
+ },
};
static const struct xe_rtp_entry_sr engine_tunings[] = {
--
2.52.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 12/15] drm/xe/nvlp: Add NVL-P platform definition
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
` (10 preceding siblings ...)
2026-02-05 23:39 ` [PATCH v2 11/15] drm/xe/xe3p_lpg: Set STLB bank hash mode to 4KB Gustavo Sousa
@ 2026-02-05 23:39 ` Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 13/15] drm/xe/nvlp: Attach MOCS table for nvlp Gustavo Sousa
` (6 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Gustavo Sousa @ 2026-02-05 23:39 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Gustavo Sousa, Shekhar Chauhan, Matt Roper
From: Shekhar Chauhan <shekhar.chauhan@intel.com>
Add platform definition along with device IDs for NVL-P. Here is the
list of device descriptor fields and associated Bspec references:
.dma_mask_size (Bspec 74198)
.has_cached_pt (Bspec 71582)
.has_display (Bspec 74196)
.has_flat_ccs (Bspec 74110)
.has_page_reclaim_hw_assist (Bspec 73451)
.max_gt_per_tile (Bspec 74196)
.va_bits (Bspec 74198)
.vm_max_level (Bspec 59507)
v2:
- Add list of descriptor fields and Bspec references. (Matt)
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/xe/xe_bo.c | 4 ++--
drivers/gpu/drm/xe/xe_pci.c | 15 +++++++++++++++
drivers/gpu/drm/xe/xe_platform_types.h | 1 +
include/drm/intel/pciids.h | 12 ++++++++++++
4 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index 8bf16d60b9a5..9e998f9708df 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -512,8 +512,8 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo,
/*
* Display scanout is always non-coherent with the CPU cache.
*
- * For Xe_LPG and beyond, PPGTT PTE lookups are also
- * non-coherent and require a CPU:WC mapping.
+ * For Xe_LPG and beyond up to NVL-P (excluding), PPGTT PTE
+ * lookups are also non-coherent and require a CPU:WC mapping.
*/
if ((!bo->cpu_caching && bo->flags & XE_BO_FLAG_SCANOUT) ||
(!xe->info.has_cached_pt && bo->flags & XE_BO_FLAG_PAGETABLE))
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 08e0ff9f75e8..a90129d8e15b 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -438,6 +438,20 @@ static const struct xe_device_desc cri_desc = {
.vm_max_level = 4,
};
+static const struct xe_device_desc nvlp_desc = {
+ PLATFORM(NOVALAKE_P),
+ .dma_mask_size = 46,
+ .has_cached_pt = true,
+ .has_display = true,
+ .has_flat_ccs = 1,
+ .has_page_reclaim_hw_assist = true,
+ .has_pre_prod_wa = true,
+ .max_gt_per_tile = 2,
+ .require_force_probe = true,
+ .va_bits = 48,
+ .vm_max_level = 4,
+};
+
#undef PLATFORM
__diag_pop();
@@ -468,6 +482,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
INTEL_CRI_IDS(INTEL_PCI_DEVICE, &cri_desc),
+ INTEL_NVLP_IDS(INTEL_VGA_DEVICE, &nvlp_desc),
{ }
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
index f516dbddfd88..6cff385227ea 100644
--- a/drivers/gpu/drm/xe/xe_platform_types.h
+++ b/drivers/gpu/drm/xe/xe_platform_types.h
@@ -26,6 +26,7 @@ enum xe_platform {
XE_PANTHERLAKE,
XE_NOVALAKE_S,
XE_CRESCENTISLAND,
+ XE_NOVALAKE_P,
};
enum xe_subplatform {
diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
index 52520e684ab1..33b91cb2e684 100644
--- a/include/drm/intel/pciids.h
+++ b/include/drm/intel/pciids.h
@@ -900,4 +900,16 @@
#define INTEL_CRI_IDS(MACRO__, ...) \
MACRO__(0x674C, ## __VA_ARGS__)
+/* NVL-P */
+#define INTEL_NVLP_IDS(MACRO__, ...) \
+ MACRO__(0xD750, ## __VA_ARGS__), \
+ MACRO__(0xD751, ## __VA_ARGS__), \
+ MACRO__(0xD752, ## __VA_ARGS__), \
+ MACRO__(0xD753, ## __VA_ARGS__), \
+ MACRO__(0XD754, ## __VA_ARGS__), \
+ MACRO__(0XD755, ## __VA_ARGS__), \
+ MACRO__(0XD756, ## __VA_ARGS__), \
+ MACRO__(0XD757, ## __VA_ARGS__), \
+ MACRO__(0xD75F, ## __VA_ARGS__)
+
#endif /* __PCIIDS_H__ */
--
2.52.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 13/15] drm/xe/nvlp: Attach MOCS table for nvlp
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
` (11 preceding siblings ...)
2026-02-05 23:39 ` [PATCH v2 12/15] drm/xe/nvlp: Add NVL-P platform definition Gustavo Sousa
@ 2026-02-05 23:39 ` Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 14/15] drm/i915/nvlp: Hook up display support Gustavo Sousa
` (5 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Gustavo Sousa @ 2026-02-05 23:39 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Gustavo Sousa, Dnyaneshwar Bhadane, Matt Roper
From: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
The MOCS table for NVL-P is same as for Xe2/Xe3 platforms.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/xe/xe_mocs.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
index 54822497c21e..1d19df860bea 100644
--- a/drivers/gpu/drm/xe/xe_mocs.c
+++ b/drivers/gpu/drm/xe/xe_mocs.c
@@ -600,6 +600,7 @@ static unsigned int get_mocs_settings(struct xe_device *xe,
info->wb_index = 4;
info->unused_entries_index = 4;
break;
+ case XE_NOVALAKE_P:
case XE_NOVALAKE_S:
case XE_PANTHERLAKE:
case XE_LUNARLAKE:
--
2.52.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 14/15] drm/i915/nvlp: Hook up display support
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
` (12 preceding siblings ...)
2026-02-05 23:39 ` [PATCH v2 13/15] drm/xe/nvlp: Attach MOCS table for nvlp Gustavo Sousa
@ 2026-02-05 23:39 ` Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 15/15] drm/xe/nvlp: Bump maximum WOPCM size Gustavo Sousa
` (4 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Gustavo Sousa @ 2026-02-05 23:39 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Gustavo Sousa, Matt Roper, Suraj Kandpal
From: Matt Roper <matthew.d.roper@intel.com>
Although NVL-S and NVL-P are quite different on the GT side, they use
identical Xe3p_LPD display IP and should take all the same codepaths.
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_device.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 471f236c9ddf..1a7f3ca079e8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1500,6 +1500,7 @@ static const struct {
INTEL_PTL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc),
INTEL_WCL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc),
INTEL_NVLS_IDS(INTEL_DISPLAY_DEVICE, &nvl_desc),
+ INTEL_NVLP_IDS(INTEL_DISPLAY_DEVICE, &nvl_desc),
};
static const struct {
--
2.52.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 15/15] drm/xe/nvlp: Bump maximum WOPCM size
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
` (13 preceding siblings ...)
2026-02-05 23:39 ` [PATCH v2 14/15] drm/i915/nvlp: Hook up display support Gustavo Sousa
@ 2026-02-05 23:39 ` Gustavo Sousa
2026-02-06 8:39 ` Bhadane, Dnyaneshwar
2026-02-05 23:47 ` ✗ CI.checkpatch: warning for Basic enabling patches for Xe3p_LPG and NVL-P (rev2) Patchwork
` (3 subsequent siblings)
18 siblings, 1 reply; 23+ messages in thread
From: Gustavo Sousa @ 2026-02-05 23:39 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: Gustavo Sousa
On NVL-P, the primary GT's WOPCM gained an extra 8MiB for the Memory
URB. As such, we need to bump the maximum size in the driver so that
the driver is able to load without erroring out thinking that the WOPCM
is too small.
FIXME: The wopcm code in xe driver is a bit confusing. For the case
where the offsets for GUC WOPCM are already locked, it appears we are
using the maximum overall WOPCM size instead of the sizes relative to
each type of GT. The function __check_layout() should be checking
against the latter.
Bspec: 67090
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/xe/xe_wopcm.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_wopcm.c b/drivers/gpu/drm/xe/xe_wopcm.c
index dde4f4967ca3..900daf1d1b1b 100644
--- a/drivers/gpu/drm/xe/xe_wopcm.c
+++ b/drivers/gpu/drm/xe/xe_wopcm.c
@@ -55,8 +55,6 @@
#define MTL_WOPCM_SIZE SZ_4M
#define WOPCM_SIZE SZ_2M
-#define MAX_WOPCM_SIZE SZ_8M
-
/* 16KB WOPCM (RSVD WOPCM) is reserved from HuC firmware top. */
#define WOPCM_RESERVED_SIZE SZ_16K
@@ -186,6 +184,14 @@ u32 xe_wopcm_size(struct xe_device *xe)
WOPCM_SIZE;
}
+static u32 max_wopcm_size(struct xe_device *xe)
+{
+ if (xe->info.platform == XE_NOVALAKE_P)
+ return SZ_16M;
+ else
+ return SZ_8M;
+}
+
/**
* xe_wopcm_init() - Initialize the WOPCM structure.
* @wopcm: pointer to xe_wopcm.
@@ -227,8 +233,11 @@ int xe_wopcm_init(struct xe_wopcm *wopcm)
* When the GuC wopcm base and size are preprogrammed by
* BIOS/IFWI, check against the max allowed wopcm size to
* validate if the programmed values align to the wopcm layout.
+ *
+ * FIXME: This is giving the maximum overall WOPCM size and not
+ * the size relative to each GT.
*/
- wopcm->size = MAX_WOPCM_SIZE;
+ wopcm->size = max_wopcm_size(xe);
goto check;
}
--
2.52.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* ✗ CI.checkpatch: warning for Basic enabling patches for Xe3p_LPG and NVL-P (rev2)
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
` (14 preceding siblings ...)
2026-02-05 23:39 ` [PATCH v2 15/15] drm/xe/nvlp: Bump maximum WOPCM size Gustavo Sousa
@ 2026-02-05 23:47 ` Patchwork
2026-02-05 23:48 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2026-02-05 23:47 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-xe
== Series Details ==
Series: Basic enabling patches for Xe3p_LPG and NVL-P (rev2)
URL : https://patchwork.freedesktop.org/series/161037/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit ecd8058a778041d4a088cecc4ba06ff757eed7a7
Author: Gustavo Sousa <gustavo.sousa@intel.com>
Date: Thu Feb 5 20:39:43 2026 -0300
drm/xe/nvlp: Bump maximum WOPCM size
On NVL-P, the primary GT's WOPCM gained an extra 8MiB for the Memory
URB. As such, we need to bump the maximum size in the driver so that
the driver is able to load without erroring out thinking that the WOPCM
is too small.
FIXME: The wopcm code in xe driver is a bit confusing. For the case
where the offsets for GUC WOPCM are already locked, it appears we are
using the maximum overall WOPCM size instead of the sizes relative to
each type of GT. The function __check_layout() should be checking
against the latter.
Bspec: 67090
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
+ /mt/dim checkpatch 75acb0a8b6f69c6429941e6845df2af94ed15939 drm-intel
b2b780e0c91d drm/xe/xe3p_lpg: Add support for graphics IP 35.10
ae21edefdf89 drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10
dfc9c565603f drm/xe/pat: Differentiate between primary and media for PTA
8de41e026697 drm/xe/xe3p_lpg: Add new PAT table
-:46: ERROR:SPACING: space prohibited after that open square bracket '['
#46: FILE: drivers/gpu/drm/xe/xe_pat.c:261:
+ [ 0] = XE2_PAT( 0, 0, 0, 0, 3, 0 ),
-:46: ERROR:SPACING: space prohibited after that open parenthesis '('
#46: FILE: drivers/gpu/drm/xe/xe_pat.c:261:
+ [ 0] = XE2_PAT( 0, 0, 0, 0, 3, 0 ),
-:46: ERROR:SPACING: space prohibited before that close parenthesis ')'
#46: FILE: drivers/gpu/drm/xe/xe_pat.c:261:
+ [ 0] = XE2_PAT( 0, 0, 0, 0, 3, 0 ),
-:47: ERROR:SPACING: space prohibited after that open square bracket '['
#47: FILE: drivers/gpu/drm/xe/xe_pat.c:262:
+ [ 1] = XE2_PAT( 0, 0, 0, 0, 3, 2 ),
-:47: ERROR:SPACING: space prohibited after that open parenthesis '('
#47: FILE: drivers/gpu/drm/xe/xe_pat.c:262:
+ [ 1] = XE2_PAT( 0, 0, 0, 0, 3, 2 ),
-:47: ERROR:SPACING: space prohibited before that close parenthesis ')'
#47: FILE: drivers/gpu/drm/xe/xe_pat.c:262:
+ [ 1] = XE2_PAT( 0, 0, 0, 0, 3, 2 ),
-:48: ERROR:SPACING: space prohibited after that open square bracket '['
#48: FILE: drivers/gpu/drm/xe/xe_pat.c:263:
+ [ 2] = XE2_PAT( 0, 0, 0, 0, 3, 3 ),
-:48: ERROR:SPACING: space prohibited after that open parenthesis '('
#48: FILE: drivers/gpu/drm/xe/xe_pat.c:263:
+ [ 2] = XE2_PAT( 0, 0, 0, 0, 3, 3 ),
-:48: ERROR:SPACING: space prohibited before that close parenthesis ')'
#48: FILE: drivers/gpu/drm/xe/xe_pat.c:263:
+ [ 2] = XE2_PAT( 0, 0, 0, 0, 3, 3 ),
-:49: ERROR:SPACING: space prohibited after that open square bracket '['
#49: FILE: drivers/gpu/drm/xe/xe_pat.c:264:
+ [ 3] = XE2_PAT( 0, 0, 0, 3, 3, 0 ),
-:49: ERROR:SPACING: space prohibited after that open parenthesis '('
#49: FILE: drivers/gpu/drm/xe/xe_pat.c:264:
+ [ 3] = XE2_PAT( 0, 0, 0, 3, 3, 0 ),
-:49: ERROR:SPACING: space prohibited before that close parenthesis ')'
#49: FILE: drivers/gpu/drm/xe/xe_pat.c:264:
+ [ 3] = XE2_PAT( 0, 0, 0, 3, 3, 0 ),
-:50: ERROR:SPACING: space prohibited after that open square bracket '['
#50: FILE: drivers/gpu/drm/xe/xe_pat.c:265:
+ [ 4] = XE2_PAT( 0, 0, 0, 3, 0, 2 ),
-:50: ERROR:SPACING: space prohibited after that open parenthesis '('
#50: FILE: drivers/gpu/drm/xe/xe_pat.c:265:
+ [ 4] = XE2_PAT( 0, 0, 0, 3, 0, 2 ),
-:50: ERROR:SPACING: space prohibited before that close parenthesis ')'
#50: FILE: drivers/gpu/drm/xe/xe_pat.c:265:
+ [ 4] = XE2_PAT( 0, 0, 0, 3, 0, 2 ),
-:51: ERROR:SPACING: space prohibited after that open square bracket '['
#51: FILE: drivers/gpu/drm/xe/xe_pat.c:266:
+ [ 5] = XE2_PAT( 0, 0, 0, 3, 3, 2 ),
-:51: ERROR:SPACING: space prohibited after that open parenthesis '('
#51: FILE: drivers/gpu/drm/xe/xe_pat.c:266:
+ [ 5] = XE2_PAT( 0, 0, 0, 3, 3, 2 ),
-:51: ERROR:SPACING: space prohibited before that close parenthesis ')'
#51: FILE: drivers/gpu/drm/xe/xe_pat.c:266:
+ [ 5] = XE2_PAT( 0, 0, 0, 3, 3, 2 ),
-:52: ERROR:SPACING: space prohibited after that open square bracket '['
#52: FILE: drivers/gpu/drm/xe/xe_pat.c:267:
+ [ 6] = XE2_PAT( 1, 0, 0, 1, 3, 0 ),
-:52: ERROR:SPACING: space prohibited after that open parenthesis '('
#52: FILE: drivers/gpu/drm/xe/xe_pat.c:267:
+ [ 6] = XE2_PAT( 1, 0, 0, 1, 3, 0 ),
-:52: ERROR:SPACING: space prohibited before that close parenthesis ')'
#52: FILE: drivers/gpu/drm/xe/xe_pat.c:267:
+ [ 6] = XE2_PAT( 1, 0, 0, 1, 3, 0 ),
-:53: ERROR:SPACING: space prohibited after that open square bracket '['
#53: FILE: drivers/gpu/drm/xe/xe_pat.c:268:
+ [ 7] = XE2_PAT( 0, 0, 0, 3, 0, 3 ),
-:53: ERROR:SPACING: space prohibited after that open parenthesis '('
#53: FILE: drivers/gpu/drm/xe/xe_pat.c:268:
+ [ 7] = XE2_PAT( 0, 0, 0, 3, 0, 3 ),
-:53: ERROR:SPACING: space prohibited before that close parenthesis ')'
#53: FILE: drivers/gpu/drm/xe/xe_pat.c:268:
+ [ 7] = XE2_PAT( 0, 0, 0, 3, 0, 3 ),
-:54: ERROR:SPACING: space prohibited after that open square bracket '['
#54: FILE: drivers/gpu/drm/xe/xe_pat.c:269:
+ [ 8] = XE2_PAT( 0, 0, 0, 3, 0, 0 ),
-:54: ERROR:SPACING: space prohibited after that open parenthesis '('
#54: FILE: drivers/gpu/drm/xe/xe_pat.c:269:
+ [ 8] = XE2_PAT( 0, 0, 0, 3, 0, 0 ),
-:54: ERROR:SPACING: space prohibited before that close parenthesis ')'
#54: FILE: drivers/gpu/drm/xe/xe_pat.c:269:
+ [ 8] = XE2_PAT( 0, 0, 0, 3, 0, 0 ),
-:55: ERROR:SPACING: space prohibited after that open square bracket '['
#55: FILE: drivers/gpu/drm/xe/xe_pat.c:270:
+ [ 9] = XE2_PAT( 0, 1, 0, 0, 3, 0 ),
-:55: ERROR:SPACING: space prohibited after that open parenthesis '('
#55: FILE: drivers/gpu/drm/xe/xe_pat.c:270:
+ [ 9] = XE2_PAT( 0, 1, 0, 0, 3, 0 ),
-:55: ERROR:SPACING: space prohibited before that close parenthesis ')'
#55: FILE: drivers/gpu/drm/xe/xe_pat.c:270:
+ [ 9] = XE2_PAT( 0, 1, 0, 0, 3, 0 ),
-:56: ERROR:SPACING: space prohibited after that open parenthesis '('
#56: FILE: drivers/gpu/drm/xe/xe_pat.c:271:
+ [10] = XE2_PAT( 0, 1, 0, 3, 0, 0 ),
-:56: ERROR:SPACING: space prohibited before that close parenthesis ')'
#56: FILE: drivers/gpu/drm/xe/xe_pat.c:271:
+ [10] = XE2_PAT( 0, 1, 0, 3, 0, 0 ),
-:57: ERROR:SPACING: space prohibited after that open parenthesis '('
#57: FILE: drivers/gpu/drm/xe/xe_pat.c:272:
+ [11] = XE2_PAT( 1, 1, 0, 1, 3, 0 ),
-:57: ERROR:SPACING: space prohibited before that close parenthesis ')'
#57: FILE: drivers/gpu/drm/xe/xe_pat.c:272:
+ [11] = XE2_PAT( 1, 1, 0, 1, 3, 0 ),
-:58: ERROR:SPACING: space prohibited after that open parenthesis '('
#58: FILE: drivers/gpu/drm/xe/xe_pat.c:273:
+ [12] = XE2_PAT( 0, 1, 0, 3, 3, 0 ),
-:58: ERROR:SPACING: space prohibited before that close parenthesis ')'
#58: FILE: drivers/gpu/drm/xe/xe_pat.c:273:
+ [12] = XE2_PAT( 0, 1, 0, 3, 3, 0 ),
-:59: ERROR:SPACING: space prohibited after that open parenthesis '('
#59: FILE: drivers/gpu/drm/xe/xe_pat.c:274:
+ [13] = XE2_PAT( 0, 0, 0, 0, 0, 0 ),
-:59: ERROR:SPACING: space prohibited before that close parenthesis ')'
#59: FILE: drivers/gpu/drm/xe/xe_pat.c:274:
+ [13] = XE2_PAT( 0, 0, 0, 0, 0, 0 ),
-:60: ERROR:SPACING: space prohibited after that open parenthesis '('
#60: FILE: drivers/gpu/drm/xe/xe_pat.c:275:
+ [14] = XE2_PAT( 0, 1, 0, 0, 0, 0 ),
-:60: ERROR:SPACING: space prohibited before that close parenthesis ')'
#60: FILE: drivers/gpu/drm/xe/xe_pat.c:275:
+ [14] = XE2_PAT( 0, 1, 0, 0, 0, 0 ),
-:61: ERROR:SPACING: space prohibited after that open parenthesis '('
#61: FILE: drivers/gpu/drm/xe/xe_pat.c:276:
+ [15] = XE2_PAT( 1, 1, 0, 1, 1, 0 ),
-:61: ERROR:SPACING: space prohibited before that close parenthesis ')'
#61: FILE: drivers/gpu/drm/xe/xe_pat.c:276:
+ [15] = XE2_PAT( 1, 1, 0, 1, 1, 0 ),
-:62: ERROR:SPACING: space prohibited after that open parenthesis '('
#62: FILE: drivers/gpu/drm/xe/xe_pat.c:277:
+ [16] = XE2_PAT( 0, 1, 0, 0, 3, 2 ),
-:62: ERROR:SPACING: space prohibited before that close parenthesis ')'
#62: FILE: drivers/gpu/drm/xe/xe_pat.c:277:
+ [16] = XE2_PAT( 0, 1, 0, 0, 3, 2 ),
-:64: ERROR:SPACING: space prohibited after that open parenthesis '('
#64: FILE: drivers/gpu/drm/xe/xe_pat.c:279:
+ [18] = XE2_PAT( 1, 0, 0, 2, 3, 0 ),
-:64: ERROR:SPACING: space prohibited before that close parenthesis ')'
#64: FILE: drivers/gpu/drm/xe/xe_pat.c:279:
+ [18] = XE2_PAT( 1, 0, 0, 2, 3, 0 ),
-:65: ERROR:SPACING: space prohibited after that open parenthesis '('
#65: FILE: drivers/gpu/drm/xe/xe_pat.c:280:
+ [19] = XE2_PAT( 1, 0, 0, 2, 3, 2 ),
-:65: ERROR:SPACING: space prohibited before that close parenthesis ')'
#65: FILE: drivers/gpu/drm/xe/xe_pat.c:280:
+ [19] = XE2_PAT( 1, 0, 0, 2, 3, 2 ),
-:66: ERROR:SPACING: space prohibited after that open parenthesis '('
#66: FILE: drivers/gpu/drm/xe/xe_pat.c:281:
+ [20] = XE2_PAT( 0, 0, 1, 0, 3, 0 ),
-:66: ERROR:SPACING: space prohibited before that close parenthesis ')'
#66: FILE: drivers/gpu/drm/xe/xe_pat.c:281:
+ [20] = XE2_PAT( 0, 0, 1, 0, 3, 0 ),
-:67: ERROR:SPACING: space prohibited after that open parenthesis '('
#67: FILE: drivers/gpu/drm/xe/xe_pat.c:282:
+ [21] = XE2_PAT( 0, 1, 1, 0, 3, 0 ),
-:67: ERROR:SPACING: space prohibited before that close parenthesis ')'
#67: FILE: drivers/gpu/drm/xe/xe_pat.c:282:
+ [21] = XE2_PAT( 0, 1, 1, 0, 3, 0 ),
-:68: ERROR:SPACING: space prohibited after that open parenthesis '('
#68: FILE: drivers/gpu/drm/xe/xe_pat.c:283:
+ [22] = XE2_PAT( 0, 0, 1, 0, 3, 2 ),
-:68: ERROR:SPACING: space prohibited before that close parenthesis ')'
#68: FILE: drivers/gpu/drm/xe/xe_pat.c:283:
+ [22] = XE2_PAT( 0, 0, 1, 0, 3, 2 ),
-:69: ERROR:SPACING: space prohibited after that open parenthesis '('
#69: FILE: drivers/gpu/drm/xe/xe_pat.c:284:
+ [23] = XE2_PAT( 0, 0, 1, 0, 3, 3 ),
-:69: ERROR:SPACING: space prohibited before that close parenthesis ')'
#69: FILE: drivers/gpu/drm/xe/xe_pat.c:284:
+ [23] = XE2_PAT( 0, 0, 1, 0, 3, 3 ),
-:70: ERROR:SPACING: space prohibited after that open parenthesis '('
#70: FILE: drivers/gpu/drm/xe/xe_pat.c:285:
+ [24] = XE2_PAT( 0, 0, 2, 0, 3, 0 ),
-:70: ERROR:SPACING: space prohibited before that close parenthesis ')'
#70: FILE: drivers/gpu/drm/xe/xe_pat.c:285:
+ [24] = XE2_PAT( 0, 0, 2, 0, 3, 0 ),
-:71: ERROR:SPACING: space prohibited after that open parenthesis '('
#71: FILE: drivers/gpu/drm/xe/xe_pat.c:286:
+ [25] = XE2_PAT( 0, 1, 2, 0, 3, 0 ),
-:71: ERROR:SPACING: space prohibited before that close parenthesis ')'
#71: FILE: drivers/gpu/drm/xe/xe_pat.c:286:
+ [25] = XE2_PAT( 0, 1, 2, 0, 3, 0 ),
-:72: ERROR:SPACING: space prohibited after that open parenthesis '('
#72: FILE: drivers/gpu/drm/xe/xe_pat.c:287:
+ [26] = XE2_PAT( 0, 0, 2, 0, 3, 2 ),
-:72: ERROR:SPACING: space prohibited before that close parenthesis ')'
#72: FILE: drivers/gpu/drm/xe/xe_pat.c:287:
+ [26] = XE2_PAT( 0, 0, 2, 0, 3, 2 ),
-:73: ERROR:SPACING: space prohibited after that open parenthesis '('
#73: FILE: drivers/gpu/drm/xe/xe_pat.c:288:
+ [27] = XE2_PAT( 0, 0, 2, 0, 3, 3 ),
-:73: ERROR:SPACING: space prohibited before that close parenthesis ')'
#73: FILE: drivers/gpu/drm/xe/xe_pat.c:288:
+ [27] = XE2_PAT( 0, 0, 2, 0, 3, 3 ),
-:74: ERROR:SPACING: space prohibited after that open parenthesis '('
#74: FILE: drivers/gpu/drm/xe/xe_pat.c:289:
+ [28] = XE2_PAT( 0, 0, 3, 0, 3, 0 ),
-:74: ERROR:SPACING: space prohibited before that close parenthesis ')'
#74: FILE: drivers/gpu/drm/xe/xe_pat.c:289:
+ [28] = XE2_PAT( 0, 0, 3, 0, 3, 0 ),
-:75: ERROR:SPACING: space prohibited after that open parenthesis '('
#75: FILE: drivers/gpu/drm/xe/xe_pat.c:290:
+ [29] = XE2_PAT( 0, 1, 3, 0, 3, 0 ),
-:75: ERROR:SPACING: space prohibited before that close parenthesis ')'
#75: FILE: drivers/gpu/drm/xe/xe_pat.c:290:
+ [29] = XE2_PAT( 0, 1, 3, 0, 3, 0 ),
-:76: ERROR:SPACING: space prohibited after that open parenthesis '('
#76: FILE: drivers/gpu/drm/xe/xe_pat.c:291:
+ [30] = XE2_PAT( 0, 0, 3, 0, 3, 2 ),
-:76: ERROR:SPACING: space prohibited before that close parenthesis ')'
#76: FILE: drivers/gpu/drm/xe/xe_pat.c:291:
+ [30] = XE2_PAT( 0, 0, 3, 0, 3, 2 ),
-:77: ERROR:SPACING: space prohibited after that open parenthesis '('
#77: FILE: drivers/gpu/drm/xe/xe_pat.c:292:
+ [31] = XE2_PAT( 0, 0, 3, 0, 3, 3 ),
-:77: ERROR:SPACING: space prohibited before that close parenthesis ')'
#77: FILE: drivers/gpu/drm/xe/xe_pat.c:292:
+ [31] = XE2_PAT( 0, 0, 3, 0, 3, 3 ),
total: 72 errors, 0 warnings, 0 checks, 73 lines checked
335b06da9e67 drm/xe/xe3p_lpg: Add MCR steering
a6927fd6d575 drm/xe/xe3p_lpg: Add LRC parsing for additional RCS engine state
d83afeeb5d53 drm/xe/xe3p_lpg: Disable reporting of context switch status to GHWSP
8ada7a5bba5c drm/xe/xe3p_lpg: Drop unnecessary tuning settings
338a4f4ad148 drm/xe/xe3p_lpg: Extend 'group ID' mask size
7b450706ba8f drm/xe/xe3p_lpg: Update LRC sizes
a1ae53d975ae drm/xe/xe3p_lpg: Set STLB bank hash mode to 4KB
f7936f8f32ff drm/xe/nvlp: Add NVL-P platform definition
-:94: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#94: FILE: include/drm/intel/pciids.h:904:
+#define INTEL_NVLP_IDS(MACRO__, ...) \
+ MACRO__(0xD750, ## __VA_ARGS__), \
+ MACRO__(0xD751, ## __VA_ARGS__), \
+ MACRO__(0xD752, ## __VA_ARGS__), \
+ MACRO__(0xD753, ## __VA_ARGS__), \
+ MACRO__(0XD754, ## __VA_ARGS__), \
+ MACRO__(0XD755, ## __VA_ARGS__), \
+ MACRO__(0XD756, ## __VA_ARGS__), \
+ MACRO__(0XD757, ## __VA_ARGS__), \
+ MACRO__(0xD75F, ## __VA_ARGS__)
BUT SEE:
do {} while (0) advice is over-stated in a few situations:
The more obvious case is macros, like MODULE_PARM_DESC, invoked at
file-scope, where C disallows code (it must be in functions). See
$exceptions if you have one to add by name.
More troublesome is declarative macros used at top of new scope,
like DECLARE_PER_CPU. These might just compile with a do-while-0
wrapper, but would be incorrect. Most of these are handled by
detecting struct,union,etc declaration primitives in $exceptions.
Theres also macros called inside an if (block), which "return" an
expression. These cannot do-while, and need a ({}) wrapper.
Enjoy this qualification while we work to improve our heuristics.
-:94: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#94: FILE: include/drm/intel/pciids.h:904:
+#define INTEL_NVLP_IDS(MACRO__, ...) \
+ MACRO__(0xD750, ## __VA_ARGS__), \
+ MACRO__(0xD751, ## __VA_ARGS__), \
+ MACRO__(0xD752, ## __VA_ARGS__), \
+ MACRO__(0xD753, ## __VA_ARGS__), \
+ MACRO__(0XD754, ## __VA_ARGS__), \
+ MACRO__(0XD755, ## __VA_ARGS__), \
+ MACRO__(0XD756, ## __VA_ARGS__), \
+ MACRO__(0XD757, ## __VA_ARGS__), \
+ MACRO__(0xD75F, ## __VA_ARGS__)
total: 1 errors, 0 warnings, 1 checks, 60 lines checked
aef0e5496007 drm/xe/nvlp: Attach MOCS table for nvlp
5aad60945d1d drm/i915/nvlp: Hook up display support
ecd8058a7780 drm/xe/nvlp: Bump maximum WOPCM size
^ permalink raw reply [flat|nested] 23+ messages in thread
* ✓ CI.KUnit: success for Basic enabling patches for Xe3p_LPG and NVL-P (rev2)
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
` (15 preceding siblings ...)
2026-02-05 23:47 ` ✗ CI.checkpatch: warning for Basic enabling patches for Xe3p_LPG and NVL-P (rev2) Patchwork
@ 2026-02-05 23:48 ` Patchwork
2026-02-06 0:04 ` ✗ CI.checksparse: warning " Patchwork
2026-02-06 0:47 ` ✓ Xe.CI.BAT: success " Patchwork
18 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2026-02-05 23:48 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-xe
== Series Details ==
Series: Basic enabling patches for Xe3p_LPG and NVL-P (rev2)
URL : https://patchwork.freedesktop.org/series/161037/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[23:47:09] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:47:13] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:47:46] Starting KUnit Kernel (1/1)...
[23:47:46] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:47:47] ================== guc_buf (11 subtests) ===================
[23:47:47] [PASSED] test_smallest
[23:47:47] [PASSED] test_largest
[23:47:47] [PASSED] test_granular
[23:47:47] [PASSED] test_unique
[23:47:47] [PASSED] test_overlap
[23:47:47] [PASSED] test_reusable
[23:47:47] [PASSED] test_too_big
[23:47:47] [PASSED] test_flush
[23:47:47] [PASSED] test_lookup
[23:47:47] [PASSED] test_data
[23:47:47] [PASSED] test_class
[23:47:47] ===================== [PASSED] guc_buf =====================
[23:47:47] =================== guc_dbm (7 subtests) ===================
[23:47:47] [PASSED] test_empty
[23:47:47] [PASSED] test_default
[23:47:47] ======================== test_size ========================
[23:47:47] [PASSED] 4
[23:47:47] [PASSED] 8
[23:47:47] [PASSED] 32
[23:47:47] [PASSED] 256
[23:47:47] ==================== [PASSED] test_size ====================
[23:47:47] ======================= test_reuse ========================
[23:47:47] [PASSED] 4
[23:47:47] [PASSED] 8
[23:47:47] [PASSED] 32
[23:47:47] [PASSED] 256
[23:47:47] =================== [PASSED] test_reuse ====================
[23:47:47] =================== test_range_overlap ====================
[23:47:47] [PASSED] 4
[23:47:47] [PASSED] 8
[23:47:47] [PASSED] 32
[23:47:47] [PASSED] 256
[23:47:47] =============== [PASSED] test_range_overlap ================
[23:47:47] =================== test_range_compact ====================
[23:47:47] [PASSED] 4
[23:47:47] [PASSED] 8
[23:47:47] [PASSED] 32
[23:47:47] [PASSED] 256
[23:47:47] =============== [PASSED] test_range_compact ================
[23:47:47] ==================== test_range_spare =====================
[23:47:47] [PASSED] 4
[23:47:47] [PASSED] 8
[23:47:47] [PASSED] 32
[23:47:47] [PASSED] 256
[23:47:47] ================ [PASSED] test_range_spare =================
[23:47:47] ===================== [PASSED] guc_dbm =====================
[23:47:47] =================== guc_idm (6 subtests) ===================
[23:47:47] [PASSED] bad_init
[23:47:47] [PASSED] no_init
[23:47:47] [PASSED] init_fini
[23:47:47] [PASSED] check_used
[23:47:47] [PASSED] check_quota
[23:47:47] [PASSED] check_all
[23:47:47] ===================== [PASSED] guc_idm =====================
[23:47:47] ================== no_relay (3 subtests) ===================
[23:47:47] [PASSED] xe_drops_guc2pf_if_not_ready
[23:47:47] [PASSED] xe_drops_guc2vf_if_not_ready
[23:47:47] [PASSED] xe_rejects_send_if_not_ready
[23:47:47] ==================== [PASSED] no_relay =====================
[23:47:47] ================== pf_relay (14 subtests) ==================
[23:47:47] [PASSED] pf_rejects_guc2pf_too_short
[23:47:47] [PASSED] pf_rejects_guc2pf_too_long
[23:47:47] [PASSED] pf_rejects_guc2pf_no_payload
[23:47:47] [PASSED] pf_fails_no_payload
[23:47:47] [PASSED] pf_fails_bad_origin
[23:47:47] [PASSED] pf_fails_bad_type
[23:47:47] [PASSED] pf_txn_reports_error
[23:47:47] [PASSED] pf_txn_sends_pf2guc
[23:47:47] [PASSED] pf_sends_pf2guc
[23:47:47] [SKIPPED] pf_loopback_nop
[23:47:47] [SKIPPED] pf_loopback_echo
[23:47:47] [SKIPPED] pf_loopback_fail
[23:47:47] [SKIPPED] pf_loopback_busy
[23:47:47] [SKIPPED] pf_loopback_retry
[23:47:47] ==================== [PASSED] pf_relay =====================
[23:47:47] ================== vf_relay (3 subtests) ===================
[23:47:47] [PASSED] vf_rejects_guc2vf_too_short
[23:47:47] [PASSED] vf_rejects_guc2vf_too_long
[23:47:47] [PASSED] vf_rejects_guc2vf_no_payload
[23:47:47] ==================== [PASSED] vf_relay =====================
[23:47:47] ================ pf_gt_config (6 subtests) =================
[23:47:47] [PASSED] fair_contexts_1vf
[23:47:47] [PASSED] fair_doorbells_1vf
[23:47:47] [PASSED] fair_ggtt_1vf
[23:47:47] ====================== fair_contexts ======================
[23:47:47] [PASSED] 1 VF
[23:47:47] [PASSED] 2 VFs
[23:47:47] [PASSED] 3 VFs
[23:47:47] [PASSED] 4 VFs
[23:47:47] [PASSED] 5 VFs
[23:47:47] [PASSED] 6 VFs
[23:47:47] [PASSED] 7 VFs
[23:47:47] [PASSED] 8 VFs
[23:47:47] [PASSED] 9 VFs
[23:47:47] [PASSED] 10 VFs
[23:47:47] [PASSED] 11 VFs
[23:47:47] [PASSED] 12 VFs
[23:47:47] [PASSED] 13 VFs
[23:47:47] [PASSED] 14 VFs
[23:47:47] [PASSED] 15 VFs
[23:47:47] [PASSED] 16 VFs
[23:47:47] [PASSED] 17 VFs
[23:47:47] [PASSED] 18 VFs
[23:47:47] [PASSED] 19 VFs
[23:47:47] [PASSED] 20 VFs
[23:47:47] [PASSED] 21 VFs
[23:47:47] [PASSED] 22 VFs
[23:47:47] [PASSED] 23 VFs
[23:47:47] [PASSED] 24 VFs
[23:47:47] [PASSED] 25 VFs
[23:47:47] [PASSED] 26 VFs
[23:47:47] [PASSED] 27 VFs
[23:47:47] [PASSED] 28 VFs
[23:47:47] [PASSED] 29 VFs
[23:47:47] [PASSED] 30 VFs
[23:47:47] [PASSED] 31 VFs
[23:47:47] [PASSED] 32 VFs
[23:47:47] [PASSED] 33 VFs
[23:47:47] [PASSED] 34 VFs
[23:47:47] [PASSED] 35 VFs
[23:47:47] [PASSED] 36 VFs
[23:47:47] [PASSED] 37 VFs
[23:47:47] [PASSED] 38 VFs
[23:47:47] [PASSED] 39 VFs
[23:47:47] [PASSED] 40 VFs
[23:47:47] [PASSED] 41 VFs
[23:47:47] [PASSED] 42 VFs
[23:47:47] [PASSED] 43 VFs
[23:47:47] [PASSED] 44 VFs
[23:47:47] [PASSED] 45 VFs
[23:47:47] [PASSED] 46 VFs
[23:47:47] [PASSED] 47 VFs
[23:47:47] [PASSED] 48 VFs
[23:47:47] [PASSED] 49 VFs
[23:47:47] [PASSED] 50 VFs
[23:47:47] [PASSED] 51 VFs
[23:47:47] [PASSED] 52 VFs
[23:47:47] [PASSED] 53 VFs
[23:47:47] [PASSED] 54 VFs
[23:47:47] [PASSED] 55 VFs
[23:47:47] [PASSED] 56 VFs
[23:47:47] [PASSED] 57 VFs
[23:47:47] [PASSED] 58 VFs
[23:47:47] [PASSED] 59 VFs
[23:47:47] [PASSED] 60 VFs
[23:47:47] [PASSED] 61 VFs
[23:47:47] [PASSED] 62 VFs
[23:47:47] [PASSED] 63 VFs
[23:47:47] ================== [PASSED] fair_contexts ==================
[23:47:47] ===================== fair_doorbells ======================
[23:47:47] [PASSED] 1 VF
[23:47:47] [PASSED] 2 VFs
[23:47:47] [PASSED] 3 VFs
[23:47:47] [PASSED] 4 VFs
[23:47:47] [PASSED] 5 VFs
[23:47:47] [PASSED] 6 VFs
[23:47:47] [PASSED] 7 VFs
[23:47:47] [PASSED] 8 VFs
[23:47:47] [PASSED] 9 VFs
[23:47:47] [PASSED] 10 VFs
[23:47:47] [PASSED] 11 VFs
[23:47:47] [PASSED] 12 VFs
[23:47:47] [PASSED] 13 VFs
[23:47:47] [PASSED] 14 VFs
[23:47:47] [PASSED] 15 VFs
[23:47:47] [PASSED] 16 VFs
[23:47:47] [PASSED] 17 VFs
[23:47:47] [PASSED] 18 VFs
[23:47:47] [PASSED] 19 VFs
[23:47:47] [PASSED] 20 VFs
[23:47:47] [PASSED] 21 VFs
[23:47:47] [PASSED] 22 VFs
[23:47:47] [PASSED] 23 VFs
[23:47:47] [PASSED] 24 VFs
[23:47:47] [PASSED] 25 VFs
[23:47:47] [PASSED] 26 VFs
[23:47:47] [PASSED] 27 VFs
[23:47:47] [PASSED] 28 VFs
[23:47:47] [PASSED] 29 VFs
[23:47:47] [PASSED] 30 VFs
[23:47:47] [PASSED] 31 VFs
[23:47:47] [PASSED] 32 VFs
[23:47:47] [PASSED] 33 VFs
[23:47:47] [PASSED] 34 VFs
[23:47:47] [PASSED] 35 VFs
[23:47:47] [PASSED] 36 VFs
[23:47:47] [PASSED] 37 VFs
[23:47:47] [PASSED] 38 VFs
[23:47:47] [PASSED] 39 VFs
[23:47:47] [PASSED] 40 VFs
[23:47:47] [PASSED] 41 VFs
[23:47:47] [PASSED] 42 VFs
[23:47:47] [PASSED] 43 VFs
[23:47:47] [PASSED] 44 VFs
[23:47:47] [PASSED] 45 VFs
[23:47:47] [PASSED] 46 VFs
[23:47:47] [PASSED] 47 VFs
[23:47:47] [PASSED] 48 VFs
[23:47:47] [PASSED] 49 VFs
[23:47:47] [PASSED] 50 VFs
[23:47:47] [PASSED] 51 VFs
[23:47:47] [PASSED] 52 VFs
[23:47:47] [PASSED] 53 VFs
[23:47:47] [PASSED] 54 VFs
[23:47:47] [PASSED] 55 VFs
[23:47:47] [PASSED] 56 VFs
[23:47:47] [PASSED] 57 VFs
[23:47:47] [PASSED] 58 VFs
[23:47:47] [PASSED] 59 VFs
[23:47:47] [PASSED] 60 VFs
[23:47:47] [PASSED] 61 VFs
[23:47:47] [PASSED] 62 VFs
[23:47:47] [PASSED] 63 VFs
[23:47:47] ================= [PASSED] fair_doorbells ==================
[23:47:47] ======================== fair_ggtt ========================
[23:47:47] [PASSED] 1 VF
[23:47:47] [PASSED] 2 VFs
[23:47:47] [PASSED] 3 VFs
[23:47:47] [PASSED] 4 VFs
[23:47:47] [PASSED] 5 VFs
[23:47:47] [PASSED] 6 VFs
[23:47:47] [PASSED] 7 VFs
[23:47:47] [PASSED] 8 VFs
[23:47:47] [PASSED] 9 VFs
[23:47:47] [PASSED] 10 VFs
[23:47:47] [PASSED] 11 VFs
[23:47:47] [PASSED] 12 VFs
[23:47:47] [PASSED] 13 VFs
[23:47:47] [PASSED] 14 VFs
[23:47:47] [PASSED] 15 VFs
[23:47:47] [PASSED] 16 VFs
[23:47:47] [PASSED] 17 VFs
[23:47:47] [PASSED] 18 VFs
[23:47:47] [PASSED] 19 VFs
[23:47:47] [PASSED] 20 VFs
[23:47:47] [PASSED] 21 VFs
[23:47:47] [PASSED] 22 VFs
[23:47:47] [PASSED] 23 VFs
[23:47:47] [PASSED] 24 VFs
[23:47:47] [PASSED] 25 VFs
[23:47:47] [PASSED] 26 VFs
[23:47:47] [PASSED] 27 VFs
[23:47:47] [PASSED] 28 VFs
[23:47:47] [PASSED] 29 VFs
[23:47:47] [PASSED] 30 VFs
[23:47:47] [PASSED] 31 VFs
[23:47:47] [PASSED] 32 VFs
[23:47:47] [PASSED] 33 VFs
[23:47:47] [PASSED] 34 VFs
[23:47:47] [PASSED] 35 VFs
[23:47:47] [PASSED] 36 VFs
[23:47:47] [PASSED] 37 VFs
[23:47:47] [PASSED] 38 VFs
[23:47:47] [PASSED] 39 VFs
[23:47:47] [PASSED] 40 VFs
[23:47:47] [PASSED] 41 VFs
[23:47:47] [PASSED] 42 VFs
[23:47:47] [PASSED] 43 VFs
[23:47:47] [PASSED] 44 VFs
[23:47:47] [PASSED] 45 VFs
[23:47:47] [PASSED] 46 VFs
[23:47:47] [PASSED] 47 VFs
[23:47:47] [PASSED] 48 VFs
[23:47:47] [PASSED] 49 VFs
[23:47:47] [PASSED] 50 VFs
[23:47:47] [PASSED] 51 VFs
[23:47:47] [PASSED] 52 VFs
[23:47:47] [PASSED] 53 VFs
[23:47:47] [PASSED] 54 VFs
[23:47:47] [PASSED] 55 VFs
[23:47:47] [PASSED] 56 VFs
[23:47:47] [PASSED] 57 VFs
[23:47:47] [PASSED] 58 VFs
[23:47:47] [PASSED] 59 VFs
[23:47:47] [PASSED] 60 VFs
[23:47:47] [PASSED] 61 VFs
[23:47:47] [PASSED] 62 VFs
[23:47:47] [PASSED] 63 VFs
[23:47:47] ==================== [PASSED] fair_ggtt ====================
[23:47:47] ================== [PASSED] pf_gt_config ===================
[23:47:47] ===================== lmtt (1 subtest) =====================
[23:47:47] ======================== test_ops =========================
[23:47:47] [PASSED] 2-level
[23:47:47] [PASSED] multi-level
[23:47:47] ==================== [PASSED] test_ops =====================
[23:47:47] ====================== [PASSED] lmtt =======================
[23:47:47] ================= pf_service (11 subtests) =================
[23:47:47] [PASSED] pf_negotiate_any
[23:47:47] [PASSED] pf_negotiate_base_match
[23:47:47] [PASSED] pf_negotiate_base_newer
[23:47:47] [PASSED] pf_negotiate_base_next
[23:47:47] [SKIPPED] pf_negotiate_base_older
[23:47:47] [PASSED] pf_negotiate_base_prev
[23:47:47] [PASSED] pf_negotiate_latest_match
[23:47:47] [PASSED] pf_negotiate_latest_newer
[23:47:47] [PASSED] pf_negotiate_latest_next
[23:47:47] [SKIPPED] pf_negotiate_latest_older
[23:47:47] [SKIPPED] pf_negotiate_latest_prev
[23:47:47] =================== [PASSED] pf_service ====================
[23:47:47] ================= xe_guc_g2g (2 subtests) ==================
[23:47:47] ============== xe_live_guc_g2g_kunit_default ==============
[23:47:47] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[23:47:47] ============== xe_live_guc_g2g_kunit_allmem ===============
[23:47:47] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[23:47:47] =================== [SKIPPED] xe_guc_g2g ===================
[23:47:47] =================== xe_mocs (2 subtests) ===================
[23:47:47] ================ xe_live_mocs_kernel_kunit ================
[23:47:47] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[23:47:47] ================ xe_live_mocs_reset_kunit =================
[23:47:47] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[23:47:47] ==================== [SKIPPED] xe_mocs =====================
[23:47:47] ================= xe_migrate (2 subtests) ==================
[23:47:47] ================= xe_migrate_sanity_kunit =================
[23:47:47] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[23:47:47] ================== xe_validate_ccs_kunit ==================
[23:47:47] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[23:47:47] =================== [SKIPPED] xe_migrate ===================
[23:47:47] ================== xe_dma_buf (1 subtest) ==================
[23:47:47] ==================== xe_dma_buf_kunit =====================
[23:47:47] ================ [SKIPPED] xe_dma_buf_kunit ================
[23:47:47] =================== [SKIPPED] xe_dma_buf ===================
[23:47:47] ================= xe_bo_shrink (1 subtest) =================
[23:47:47] =================== xe_bo_shrink_kunit ====================
[23:47:47] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[23:47:47] ================== [SKIPPED] xe_bo_shrink ==================
[23:47:47] ==================== xe_bo (2 subtests) ====================
[23:47:47] ================== xe_ccs_migrate_kunit ===================
[23:47:47] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[23:47:47] ==================== xe_bo_evict_kunit ====================
[23:47:47] =============== [SKIPPED] xe_bo_evict_kunit ================
[23:47:47] ===================== [SKIPPED] xe_bo ======================
[23:47:47] ==================== args (13 subtests) ====================
[23:47:47] [PASSED] count_args_test
[23:47:47] [PASSED] call_args_example
[23:47:47] [PASSED] call_args_test
[23:47:47] [PASSED] drop_first_arg_example
[23:47:47] [PASSED] drop_first_arg_test
[23:47:47] [PASSED] first_arg_example
[23:47:47] [PASSED] first_arg_test
[23:47:47] [PASSED] last_arg_example
[23:47:47] [PASSED] last_arg_test
[23:47:47] [PASSED] pick_arg_example
[23:47:47] [PASSED] if_args_example
[23:47:47] [PASSED] if_args_test
[23:47:47] [PASSED] sep_comma_example
[23:47:47] ====================== [PASSED] args =======================
[23:47:47] =================== xe_pci (3 subtests) ====================
[23:47:47] ==================== check_graphics_ip ====================
[23:47:47] [PASSED] 12.00 Xe_LP
[23:47:47] [PASSED] 12.10 Xe_LP+
[23:47:47] [PASSED] 12.55 Xe_HPG
[23:47:47] [PASSED] 12.60 Xe_HPC
[23:47:47] [PASSED] 12.70 Xe_LPG
[23:47:47] [PASSED] 12.71 Xe_LPG
[23:47:47] [PASSED] 12.74 Xe_LPG+
[23:47:47] [PASSED] 20.01 Xe2_HPG
[23:47:47] [PASSED] 20.02 Xe2_HPG
[23:47:47] [PASSED] 20.04 Xe2_LPG
[23:47:47] [PASSED] 30.00 Xe3_LPG
[23:47:47] [PASSED] 30.01 Xe3_LPG
[23:47:47] [PASSED] 30.03 Xe3_LPG
[23:47:47] [PASSED] 30.04 Xe3_LPG
[23:47:47] [PASSED] 30.05 Xe3_LPG
[23:47:47] [PASSED] 35.10 Xe3p_LPG
[23:47:47] [PASSED] 35.11 Xe3p_XPC
[23:47:47] ================ [PASSED] check_graphics_ip ================
[23:47:47] ===================== check_media_ip ======================
[23:47:47] [PASSED] 12.00 Xe_M
[23:47:47] [PASSED] 12.55 Xe_HPM
[23:47:47] [PASSED] 13.00 Xe_LPM+
[23:47:47] [PASSED] 13.01 Xe2_HPM
[23:47:47] [PASSED] 20.00 Xe2_LPM
[23:47:47] [PASSED] 30.00 Xe3_LPM
[23:47:47] [PASSED] 30.02 Xe3_LPM
[23:47:47] [PASSED] 35.00 Xe3p_LPM
[23:47:47] [PASSED] 35.03 Xe3p_HPM
[23:47:47] ================= [PASSED] check_media_ip ==================
[23:47:47] =================== check_platform_desc ===================
[23:47:47] [PASSED] 0x9A60 (TIGERLAKE)
[23:47:47] [PASSED] 0x9A68 (TIGERLAKE)
[23:47:47] [PASSED] 0x9A70 (TIGERLAKE)
[23:47:47] [PASSED] 0x9A40 (TIGERLAKE)
[23:47:47] [PASSED] 0x9A49 (TIGERLAKE)
[23:47:47] [PASSED] 0x9A59 (TIGERLAKE)
[23:47:47] [PASSED] 0x9A78 (TIGERLAKE)
[23:47:47] [PASSED] 0x9AC0 (TIGERLAKE)
[23:47:47] [PASSED] 0x9AC9 (TIGERLAKE)
[23:47:47] [PASSED] 0x9AD9 (TIGERLAKE)
[23:47:47] [PASSED] 0x9AF8 (TIGERLAKE)
[23:47:47] [PASSED] 0x4C80 (ROCKETLAKE)
[23:47:47] [PASSED] 0x4C8A (ROCKETLAKE)
[23:47:47] [PASSED] 0x4C8B (ROCKETLAKE)
[23:47:47] [PASSED] 0x4C8C (ROCKETLAKE)
[23:47:47] [PASSED] 0x4C90 (ROCKETLAKE)
[23:47:47] [PASSED] 0x4C9A (ROCKETLAKE)
[23:47:47] [PASSED] 0x4680 (ALDERLAKE_S)
[23:47:47] [PASSED] 0x4682 (ALDERLAKE_S)
[23:47:47] [PASSED] 0x4688 (ALDERLAKE_S)
[23:47:47] [PASSED] 0x468A (ALDERLAKE_S)
[23:47:47] [PASSED] 0x468B (ALDERLAKE_S)
[23:47:47] [PASSED] 0x4690 (ALDERLAKE_S)
[23:47:47] [PASSED] 0x4692 (ALDERLAKE_S)
[23:47:47] [PASSED] 0x4693 (ALDERLAKE_S)
[23:47:47] [PASSED] 0x46A0 (ALDERLAKE_P)
[23:47:47] [PASSED] 0x46A1 (ALDERLAKE_P)
[23:47:47] [PASSED] 0x46A2 (ALDERLAKE_P)
[23:47:47] [PASSED] 0x46A3 (ALDERLAKE_P)
[23:47:47] [PASSED] 0x46A6 (ALDERLAKE_P)
[23:47:47] [PASSED] 0x46A8 (ALDERLAKE_P)
[23:47:47] [PASSED] 0x46AA (ALDERLAKE_P)
[23:47:47] [PASSED] 0x462A (ALDERLAKE_P)
[23:47:47] [PASSED] 0x4626 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[23:47:47] [PASSED] 0x4628 (ALDERLAKE_P)
[23:47:47] [PASSED] 0x46B0 (ALDERLAKE_P)
[23:47:47] [PASSED] 0x46B1 (ALDERLAKE_P)
[23:47:47] [PASSED] 0x46B2 (ALDERLAKE_P)
[23:47:47] [PASSED] 0x46B3 (ALDERLAKE_P)
[23:47:47] [PASSED] 0x46C0 (ALDERLAKE_P)
[23:47:47] [PASSED] 0x46C1 (ALDERLAKE_P)
[23:47:47] [PASSED] 0x46C2 (ALDERLAKE_P)
[23:47:47] [PASSED] 0x46C3 (ALDERLAKE_P)
[23:47:47] [PASSED] 0x46D0 (ALDERLAKE_N)
[23:47:47] [PASSED] 0x46D1 (ALDERLAKE_N)
[23:47:47] [PASSED] 0x46D2 (ALDERLAKE_N)
[23:47:47] [PASSED] 0x46D3 (ALDERLAKE_N)
[23:47:47] [PASSED] 0x46D4 (ALDERLAKE_N)
[23:47:47] [PASSED] 0xA721 (ALDERLAKE_P)
[23:47:47] [PASSED] 0xA7A1 (ALDERLAKE_P)
[23:47:47] [PASSED] 0xA7A9 (ALDERLAKE_P)
[23:47:47] [PASSED] 0xA7AC (ALDERLAKE_P)
[23:47:47] [PASSED] 0xA7AD (ALDERLAKE_P)
[23:47:47] [PASSED] 0xA720 (ALDERLAKE_P)
[23:47:47] [PASSED] 0xA7A0 (ALDERLAKE_P)
[23:47:47] [PASSED] 0xA7A8 (ALDERLAKE_P)
[23:47:47] [PASSED] 0xA7AA (ALDERLAKE_P)
[23:47:47] [PASSED] 0xA7AB (ALDERLAKE_P)
[23:47:47] [PASSED] 0xA780 (ALDERLAKE_S)
[23:47:47] [PASSED] 0xA781 (ALDERLAKE_S)
[23:47:47] [PASSED] 0xA782 (ALDERLAKE_S)
[23:47:47] [PASSED] 0xA783 (ALDERLAKE_S)
[23:47:47] [PASSED] 0xA788 (ALDERLAKE_S)
[23:47:47] [PASSED] 0xA789 (ALDERLAKE_S)
[23:47:47] [PASSED] 0xA78A (ALDERLAKE_S)
[23:47:47] [PASSED] 0xA78B (ALDERLAKE_S)
[23:47:47] [PASSED] 0x4905 (DG1)
[23:47:47] [PASSED] 0x4906 (DG1)
[23:47:47] [PASSED] 0x4907 (DG1)
[23:47:47] [PASSED] 0x4908 (DG1)
[23:47:47] [PASSED] 0x4909 (DG1)
[23:47:47] [PASSED] 0x56C0 (DG2)
[23:47:47] [PASSED] 0x56C2 (DG2)
[23:47:47] [PASSED] 0x56C1 (DG2)
[23:47:47] [PASSED] 0x7D51 (METEORLAKE)
[23:47:47] [PASSED] 0x7DD1 (METEORLAKE)
[23:47:47] [PASSED] 0x7D41 (METEORLAKE)
[23:47:47] [PASSED] 0x7D67 (METEORLAKE)
[23:47:47] [PASSED] 0xB640 (METEORLAKE)
[23:47:47] [PASSED] 0x56A0 (DG2)
[23:47:47] [PASSED] 0x56A1 (DG2)
[23:47:47] [PASSED] 0x56A2 (DG2)
[23:47:47] [PASSED] 0x56BE (DG2)
[23:47:47] [PASSED] 0x56BF (DG2)
[23:47:47] [PASSED] 0x5690 (DG2)
[23:47:47] [PASSED] 0x5691 (DG2)
[23:47:47] [PASSED] 0x5692 (DG2)
[23:47:47] [PASSED] 0x56A5 (DG2)
[23:47:47] [PASSED] 0x56A6 (DG2)
[23:47:47] [PASSED] 0x56B0 (DG2)
[23:47:47] [PASSED] 0x56B1 (DG2)
[23:47:47] [PASSED] 0x56BA (DG2)
[23:47:47] [PASSED] 0x56BB (DG2)
[23:47:47] [PASSED] 0x56BC (DG2)
[23:47:47] [PASSED] 0x56BD (DG2)
[23:47:47] [PASSED] 0x5693 (DG2)
[23:47:47] [PASSED] 0x5694 (DG2)
[23:47:47] [PASSED] 0x5695 (DG2)
[23:47:47] [PASSED] 0x56A3 (DG2)
[23:47:47] [PASSED] 0x56A4 (DG2)
[23:47:47] [PASSED] 0x56B2 (DG2)
[23:47:47] [PASSED] 0x56B3 (DG2)
[23:47:47] [PASSED] 0x5696 (DG2)
[23:47:47] [PASSED] 0x5697 (DG2)
[23:47:47] [PASSED] 0xB69 (PVC)
[23:47:47] [PASSED] 0xB6E (PVC)
[23:47:47] [PASSED] 0xBD4 (PVC)
[23:47:47] [PASSED] 0xBD5 (PVC)
[23:47:47] [PASSED] 0xBD6 (PVC)
[23:47:47] [PASSED] 0xBD7 (PVC)
[23:47:47] [PASSED] 0xBD8 (PVC)
[23:47:47] [PASSED] 0xBD9 (PVC)
[23:47:47] [PASSED] 0xBDA (PVC)
[23:47:47] [PASSED] 0xBDB (PVC)
[23:47:47] [PASSED] 0xBE0 (PVC)
[23:47:47] [PASSED] 0xBE1 (PVC)
[23:47:47] [PASSED] 0xBE5 (PVC)
[23:47:47] [PASSED] 0x7D40 (METEORLAKE)
[23:47:47] [PASSED] 0x7D45 (METEORLAKE)
[23:47:47] [PASSED] 0x7D55 (METEORLAKE)
[23:47:47] [PASSED] 0x7D60 (METEORLAKE)
[23:47:47] [PASSED] 0x7DD5 (METEORLAKE)
[23:47:47] [PASSED] 0x6420 (LUNARLAKE)
[23:47:47] [PASSED] 0x64A0 (LUNARLAKE)
[23:47:47] [PASSED] 0x64B0 (LUNARLAKE)
[23:47:47] [PASSED] 0xE202 (BATTLEMAGE)
[23:47:47] [PASSED] 0xE209 (BATTLEMAGE)
[23:47:47] [PASSED] 0xE20B (BATTLEMAGE)
[23:47:47] [PASSED] 0xE20C (BATTLEMAGE)
[23:47:47] [PASSED] 0xE20D (BATTLEMAGE)
[23:47:47] [PASSED] 0xE210 (BATTLEMAGE)
[23:47:47] [PASSED] 0xE211 (BATTLEMAGE)
[23:47:47] [PASSED] 0xE212 (BATTLEMAGE)
[23:47:47] [PASSED] 0xE216 (BATTLEMAGE)
[23:47:47] [PASSED] 0xE220 (BATTLEMAGE)
[23:47:47] [PASSED] 0xE221 (BATTLEMAGE)
[23:47:47] [PASSED] 0xE222 (BATTLEMAGE)
[23:47:47] [PASSED] 0xE223 (BATTLEMAGE)
[23:47:47] [PASSED] 0xB080 (PANTHERLAKE)
[23:47:47] [PASSED] 0xB081 (PANTHERLAKE)
[23:47:47] [PASSED] 0xB082 (PANTHERLAKE)
[23:47:47] [PASSED] 0xB083 (PANTHERLAKE)
[23:47:47] [PASSED] 0xB084 (PANTHERLAKE)
[23:47:47] [PASSED] 0xB085 (PANTHERLAKE)
[23:47:47] [PASSED] 0xB086 (PANTHERLAKE)
[23:47:47] [PASSED] 0xB087 (PANTHERLAKE)
[23:47:47] [PASSED] 0xB08F (PANTHERLAKE)
[23:47:47] [PASSED] 0xB090 (PANTHERLAKE)
[23:47:47] [PASSED] 0xB0A0 (PANTHERLAKE)
[23:47:47] [PASSED] 0xB0B0 (PANTHERLAKE)
[23:47:47] [PASSED] 0xFD80 (PANTHERLAKE)
[23:47:47] [PASSED] 0xFD81 (PANTHERLAKE)
[23:47:47] [PASSED] 0xD740 (NOVALAKE_S)
[23:47:47] [PASSED] 0xD741 (NOVALAKE_S)
[23:47:47] [PASSED] 0xD742 (NOVALAKE_S)
[23:47:47] [PASSED] 0xD743 (NOVALAKE_S)
[23:47:47] [PASSED] 0xD744 (NOVALAKE_S)
[23:47:47] [PASSED] 0xD745 (NOVALAKE_S)
[23:47:47] [PASSED] 0x674C (CRESCENTISLAND)
[23:47:47] [PASSED] 0xD750 (NOVALAKE_P)
[23:47:47] [PASSED] 0xD751 (NOVALAKE_P)
[23:47:47] [PASSED] 0xD752 (NOVALAKE_P)
[23:47:47] [PASSED] 0xD753 (NOVALAKE_P)
[23:47:47] [PASSED] 0xD754 (NOVALAKE_P)
[23:47:47] [PASSED] 0xD755 (NOVALAKE_P)
[23:47:47] [PASSED] 0xD756 (NOVALAKE_P)
[23:47:47] [PASSED] 0xD757 (NOVALAKE_P)
[23:47:47] [PASSED] 0xD75F (NOVALAKE_P)
[23:47:47] =============== [PASSED] check_platform_desc ===============
[23:47:47] ===================== [PASSED] xe_pci ======================
[23:47:47] =================== xe_rtp (2 subtests) ====================
[23:47:47] =============== xe_rtp_process_to_sr_tests ================
[23:47:47] [PASSED] coalesce-same-reg
[23:47:47] [PASSED] no-match-no-add
[23:47:47] [PASSED] match-or
[23:47:47] [PASSED] match-or-xfail
[23:47:47] [PASSED] no-match-no-add-multiple-rules
[23:47:47] [PASSED] two-regs-two-entries
[23:47:47] [PASSED] clr-one-set-other
[23:47:47] [PASSED] set-field
[23:47:47] [PASSED] conflict-duplicate
[23:47:47] [PASSED] conflict-not-disjoint
[23:47:47] [PASSED] conflict-reg-type
[23:47:47] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[23:47:47] ================== xe_rtp_process_tests ===================
[23:47:47] [PASSED] active1
[23:47:47] [PASSED] active2
[23:47:47] [PASSED] active-inactive
[23:47:47] [PASSED] inactive-active
[23:47:47] [PASSED] inactive-1st_or_active-inactive
[23:47:47] [PASSED] inactive-2nd_or_active-inactive
[23:47:47] [PASSED] inactive-last_or_active-inactive
[23:47:47] [PASSED] inactive-no_or_active-inactive
[23:47:47] ============== [PASSED] xe_rtp_process_tests ===============
[23:47:47] ===================== [PASSED] xe_rtp ======================
[23:47:47] ==================== xe_wa (1 subtest) =====================
[23:47:47] ======================== xe_wa_gt =========================
[23:47:47] [PASSED] TIGERLAKE B0
[23:47:47] [PASSED] DG1 A0
[23:47:47] [PASSED] DG1 B0
[23:47:47] [PASSED] ALDERLAKE_S A0
[23:47:47] [PASSED] ALDERLAKE_S B0
[23:47:47] [PASSED] ALDERLAKE_S C0
[23:47:47] [PASSED] ALDERLAKE_S D0
[23:47:47] [PASSED] ALDERLAKE_P A0
[23:47:47] [PASSED] ALDERLAKE_P B0
[23:47:47] [PASSED] ALDERLAKE_P C0
[23:47:47] [PASSED] ALDERLAKE_S RPLS D0
[23:47:47] [PASSED] ALDERLAKE_P RPLU E0
[23:47:47] [PASSED] DG2 G10 C0
[23:47:47] [PASSED] DG2 G11 B1
[23:47:47] [PASSED] DG2 G12 A1
[23:47:47] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:47:47] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:47:47] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[23:47:47] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[23:47:47] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[23:47:47] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[23:47:47] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[23:47:47] ==================== [PASSED] xe_wa_gt =====================
[23:47:47] ====================== [PASSED] xe_wa ======================
[23:47:47] ============================================================
[23:47:47] Testing complete. Ran 522 tests: passed: 504, skipped: 18
[23:47:47] Elapsed time: 37.746s total, 4.213s configuring, 33.016s building, 0.464s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[23:47:47] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:47:49] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:48:15] Starting KUnit Kernel (1/1)...
[23:48:15] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:48:15] ============ drm_test_pick_cmdline (2 subtests) ============
[23:48:15] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[23:48:15] =============== drm_test_pick_cmdline_named ===============
[23:48:15] [PASSED] NTSC
[23:48:15] [PASSED] NTSC-J
[23:48:15] [PASSED] PAL
[23:48:15] [PASSED] PAL-M
[23:48:15] =========== [PASSED] drm_test_pick_cmdline_named ===========
[23:48:15] ============== [PASSED] drm_test_pick_cmdline ==============
[23:48:15] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[23:48:15] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[23:48:15] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[23:48:15] =========== drm_validate_clone_mode (2 subtests) ===========
[23:48:15] ============== drm_test_check_in_clone_mode ===============
[23:48:15] [PASSED] in_clone_mode
[23:48:15] [PASSED] not_in_clone_mode
[23:48:15] ========== [PASSED] drm_test_check_in_clone_mode ===========
[23:48:15] =============== drm_test_check_valid_clones ===============
[23:48:15] [PASSED] not_in_clone_mode
[23:48:15] [PASSED] valid_clone
[23:48:15] [PASSED] invalid_clone
[23:48:15] =========== [PASSED] drm_test_check_valid_clones ===========
[23:48:15] ============= [PASSED] drm_validate_clone_mode =============
[23:48:15] ============= drm_validate_modeset (1 subtest) =============
[23:48:15] [PASSED] drm_test_check_connector_changed_modeset
[23:48:15] ============== [PASSED] drm_validate_modeset ===============
[23:48:15] ====== drm_test_bridge_get_current_state (2 subtests) ======
[23:48:15] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[23:48:15] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[23:48:15] ======== [PASSED] drm_test_bridge_get_current_state ========
[23:48:15] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[23:48:15] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[23:48:15] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[23:48:15] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[23:48:15] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[23:48:15] ============== drm_bridge_alloc (2 subtests) ===============
[23:48:15] [PASSED] drm_test_drm_bridge_alloc_basic
[23:48:15] [PASSED] drm_test_drm_bridge_alloc_get_put
[23:48:15] ================ [PASSED] drm_bridge_alloc =================
[23:48:15] ================== drm_buddy (9 subtests) ==================
[23:48:15] [PASSED] drm_test_buddy_alloc_limit
[23:48:15] [PASSED] drm_test_buddy_alloc_optimistic
[23:48:15] [PASSED] drm_test_buddy_alloc_pessimistic
[23:48:15] [PASSED] drm_test_buddy_alloc_pathological
[23:48:15] [PASSED] drm_test_buddy_alloc_contiguous
[23:48:15] [PASSED] drm_test_buddy_alloc_clear
[23:48:15] [PASSED] drm_test_buddy_alloc_range_bias
[23:48:15] [PASSED] drm_test_buddy_fragmentation_performance
[23:48:15] [PASSED] drm_test_buddy_alloc_exceeds_max_order
[23:48:15] ==================== [PASSED] drm_buddy ====================
[23:48:15] ============= drm_cmdline_parser (40 subtests) =============
[23:48:15] [PASSED] drm_test_cmdline_force_d_only
[23:48:15] [PASSED] drm_test_cmdline_force_D_only_dvi
[23:48:15] [PASSED] drm_test_cmdline_force_D_only_hdmi
[23:48:15] [PASSED] drm_test_cmdline_force_D_only_not_digital
[23:48:15] [PASSED] drm_test_cmdline_force_e_only
[23:48:15] [PASSED] drm_test_cmdline_res
[23:48:15] [PASSED] drm_test_cmdline_res_vesa
[23:48:15] [PASSED] drm_test_cmdline_res_vesa_rblank
[23:48:15] [PASSED] drm_test_cmdline_res_rblank
[23:48:15] [PASSED] drm_test_cmdline_res_bpp
[23:48:15] [PASSED] drm_test_cmdline_res_refresh
[23:48:15] [PASSED] drm_test_cmdline_res_bpp_refresh
[23:48:15] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[23:48:15] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[23:48:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[23:48:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[23:48:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[23:48:15] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[23:48:15] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[23:48:15] [PASSED] drm_test_cmdline_res_margins_force_on
[23:48:15] [PASSED] drm_test_cmdline_res_vesa_margins
[23:48:15] [PASSED] drm_test_cmdline_name
[23:48:15] [PASSED] drm_test_cmdline_name_bpp
[23:48:15] [PASSED] drm_test_cmdline_name_option
[23:48:15] [PASSED] drm_test_cmdline_name_bpp_option
[23:48:15] [PASSED] drm_test_cmdline_rotate_0
[23:48:15] [PASSED] drm_test_cmdline_rotate_90
[23:48:15] [PASSED] drm_test_cmdline_rotate_180
[23:48:15] [PASSED] drm_test_cmdline_rotate_270
[23:48:15] [PASSED] drm_test_cmdline_hmirror
[23:48:15] [PASSED] drm_test_cmdline_vmirror
[23:48:15] [PASSED] drm_test_cmdline_margin_options
[23:48:15] [PASSED] drm_test_cmdline_multiple_options
[23:48:15] [PASSED] drm_test_cmdline_bpp_extra_and_option
[23:48:15] [PASSED] drm_test_cmdline_extra_and_option
[23:48:15] [PASSED] drm_test_cmdline_freestanding_options
[23:48:15] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[23:48:15] [PASSED] drm_test_cmdline_panel_orientation
[23:48:15] ================ drm_test_cmdline_invalid =================
[23:48:15] [PASSED] margin_only
[23:48:15] [PASSED] interlace_only
[23:48:15] [PASSED] res_missing_x
[23:48:15] [PASSED] res_missing_y
[23:48:15] [PASSED] res_bad_y
[23:48:15] [PASSED] res_missing_y_bpp
[23:48:15] [PASSED] res_bad_bpp
[23:48:15] [PASSED] res_bad_refresh
[23:48:15] [PASSED] res_bpp_refresh_force_on_off
[23:48:15] [PASSED] res_invalid_mode
[23:48:15] [PASSED] res_bpp_wrong_place_mode
[23:48:15] [PASSED] name_bpp_refresh
[23:48:15] [PASSED] name_refresh
[23:48:15] [PASSED] name_refresh_wrong_mode
[23:48:15] [PASSED] name_refresh_invalid_mode
[23:48:15] [PASSED] rotate_multiple
[23:48:15] [PASSED] rotate_invalid_val
[23:48:15] [PASSED] rotate_truncated
[23:48:15] [PASSED] invalid_option
[23:48:15] [PASSED] invalid_tv_option
[23:48:15] [PASSED] truncated_tv_option
[23:48:15] ============ [PASSED] drm_test_cmdline_invalid =============
[23:48:15] =============== drm_test_cmdline_tv_options ===============
[23:48:15] [PASSED] NTSC
[23:48:15] [PASSED] NTSC_443
[23:48:15] [PASSED] NTSC_J
[23:48:15] [PASSED] PAL
[23:48:15] [PASSED] PAL_M
[23:48:15] [PASSED] PAL_N
[23:48:15] [PASSED] SECAM
[23:48:15] [PASSED] MONO_525
[23:48:15] [PASSED] MONO_625
[23:48:15] =========== [PASSED] drm_test_cmdline_tv_options ===========
[23:48:15] =============== [PASSED] drm_cmdline_parser ================
[23:48:15] ========== drmm_connector_hdmi_init (20 subtests) ==========
[23:48:15] [PASSED] drm_test_connector_hdmi_init_valid
[23:48:15] [PASSED] drm_test_connector_hdmi_init_bpc_8
[23:48:15] [PASSED] drm_test_connector_hdmi_init_bpc_10
[23:48:15] [PASSED] drm_test_connector_hdmi_init_bpc_12
[23:48:15] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[23:48:15] [PASSED] drm_test_connector_hdmi_init_bpc_null
[23:48:15] [PASSED] drm_test_connector_hdmi_init_formats_empty
[23:48:15] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[23:48:15] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[23:48:15] [PASSED] supported_formats=0x9 yuv420_allowed=1
[23:48:15] [PASSED] supported_formats=0x9 yuv420_allowed=0
[23:48:15] [PASSED] supported_formats=0x3 yuv420_allowed=1
[23:48:15] [PASSED] supported_formats=0x3 yuv420_allowed=0
[23:48:15] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[23:48:15] [PASSED] drm_test_connector_hdmi_init_null_ddc
[23:48:15] [PASSED] drm_test_connector_hdmi_init_null_product
[23:48:15] [PASSED] drm_test_connector_hdmi_init_null_vendor
[23:48:15] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[23:48:15] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[23:48:15] [PASSED] drm_test_connector_hdmi_init_product_valid
[23:48:15] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[23:48:15] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[23:48:15] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[23:48:15] ========= drm_test_connector_hdmi_init_type_valid =========
[23:48:15] [PASSED] HDMI-A
[23:48:15] [PASSED] HDMI-B
[23:48:15] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[23:48:15] ======== drm_test_connector_hdmi_init_type_invalid ========
[23:48:15] [PASSED] Unknown
[23:48:15] [PASSED] VGA
[23:48:15] [PASSED] DVI-I
[23:48:15] [PASSED] DVI-D
[23:48:15] [PASSED] DVI-A
[23:48:15] [PASSED] Composite
[23:48:15] [PASSED] SVIDEO
[23:48:15] [PASSED] LVDS
[23:48:15] [PASSED] Component
[23:48:15] [PASSED] DIN
[23:48:15] [PASSED] DP
[23:48:15] [PASSED] TV
[23:48:15] [PASSED] eDP
[23:48:15] [PASSED] Virtual
[23:48:15] [PASSED] DSI
[23:48:15] [PASSED] DPI
[23:48:15] [PASSED] Writeback
[23:48:15] [PASSED] SPI
[23:48:15] [PASSED] USB
[23:48:15] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[23:48:15] ============ [PASSED] drmm_connector_hdmi_init =============
[23:48:15] ============= drmm_connector_init (3 subtests) =============
[23:48:15] [PASSED] drm_test_drmm_connector_init
[23:48:15] [PASSED] drm_test_drmm_connector_init_null_ddc
[23:48:15] ========= drm_test_drmm_connector_init_type_valid =========
[23:48:15] [PASSED] Unknown
[23:48:15] [PASSED] VGA
[23:48:15] [PASSED] DVI-I
[23:48:15] [PASSED] DVI-D
[23:48:15] [PASSED] DVI-A
[23:48:15] [PASSED] Composite
[23:48:15] [PASSED] SVIDEO
[23:48:15] [PASSED] LVDS
[23:48:15] [PASSED] Component
[23:48:15] [PASSED] DIN
[23:48:15] [PASSED] DP
[23:48:15] [PASSED] HDMI-A
[23:48:15] [PASSED] HDMI-B
[23:48:15] [PASSED] TV
[23:48:15] [PASSED] eDP
[23:48:15] [PASSED] Virtual
[23:48:15] [PASSED] DSI
[23:48:15] [PASSED] DPI
[23:48:15] [PASSED] Writeback
[23:48:15] [PASSED] SPI
[23:48:15] [PASSED] USB
[23:48:15] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[23:48:15] =============== [PASSED] drmm_connector_init ===============
[23:48:15] ========= drm_connector_dynamic_init (6 subtests) ==========
[23:48:15] [PASSED] drm_test_drm_connector_dynamic_init
[23:48:15] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[23:48:15] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[23:48:15] [PASSED] drm_test_drm_connector_dynamic_init_properties
[23:48:15] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[23:48:15] [PASSED] Unknown
[23:48:15] [PASSED] VGA
[23:48:15] [PASSED] DVI-I
[23:48:15] [PASSED] DVI-D
[23:48:15] [PASSED] DVI-A
[23:48:15] [PASSED] Composite
[23:48:15] [PASSED] SVIDEO
[23:48:15] [PASSED] LVDS
[23:48:15] [PASSED] Component
[23:48:15] [PASSED] DIN
[23:48:15] [PASSED] DP
[23:48:15] [PASSED] HDMI-A
[23:48:15] [PASSED] HDMI-B
[23:48:15] [PASSED] TV
[23:48:15] [PASSED] eDP
[23:48:15] [PASSED] Virtual
[23:48:15] [PASSED] DSI
[23:48:15] [PASSED] DPI
[23:48:15] [PASSED] Writeback
[23:48:15] [PASSED] SPI
[23:48:15] [PASSED] USB
[23:48:15] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[23:48:15] ======== drm_test_drm_connector_dynamic_init_name =========
[23:48:15] [PASSED] Unknown
[23:48:15] [PASSED] VGA
[23:48:15] [PASSED] DVI-I
[23:48:15] [PASSED] DVI-D
[23:48:15] [PASSED] DVI-A
[23:48:15] [PASSED] Composite
[23:48:15] [PASSED] SVIDEO
[23:48:15] [PASSED] LVDS
[23:48:15] [PASSED] Component
[23:48:15] [PASSED] DIN
[23:48:15] [PASSED] DP
[23:48:15] [PASSED] HDMI-A
[23:48:15] [PASSED] HDMI-B
[23:48:15] [PASSED] TV
[23:48:15] [PASSED] eDP
[23:48:15] [PASSED] Virtual
[23:48:15] [PASSED] DSI
[23:48:15] [PASSED] DPI
[23:48:15] [PASSED] Writeback
[23:48:15] [PASSED] SPI
[23:48:15] [PASSED] USB
[23:48:15] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[23:48:15] =========== [PASSED] drm_connector_dynamic_init ============
[23:48:15] ==== drm_connector_dynamic_register_early (4 subtests) =====
[23:48:15] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[23:48:15] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[23:48:15] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[23:48:15] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[23:48:15] ====== [PASSED] drm_connector_dynamic_register_early =======
[23:48:15] ======= drm_connector_dynamic_register (7 subtests) ========
[23:48:15] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[23:48:15] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[23:48:15] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[23:48:15] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[23:48:15] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[23:48:15] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[23:48:15] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[23:48:15] ========= [PASSED] drm_connector_dynamic_register ==========
[23:48:15] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[23:48:15] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[23:48:15] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[23:48:15] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[23:48:15] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[23:48:15] ========== drm_test_get_tv_mode_from_name_valid ===========
[23:48:15] [PASSED] NTSC
[23:48:15] [PASSED] NTSC-443
[23:48:15] [PASSED] NTSC-J
[23:48:15] [PASSED] PAL
[23:48:15] [PASSED] PAL-M
[23:48:15] [PASSED] PAL-N
[23:48:15] [PASSED] SECAM
[23:48:15] [PASSED] Mono
[23:48:15] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[23:48:15] [PASSED] drm_test_get_tv_mode_from_name_truncated
[23:48:15] ============ [PASSED] drm_get_tv_mode_from_name ============
[23:48:15] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[23:48:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[23:48:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[23:48:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[23:48:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[23:48:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[23:48:15] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[23:48:15] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[23:48:15] [PASSED] VIC 96
[23:48:15] [PASSED] VIC 97
[23:48:15] [PASSED] VIC 101
[23:48:15] [PASSED] VIC 102
[23:48:15] [PASSED] VIC 106
[23:48:15] [PASSED] VIC 107
[23:48:15] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[23:48:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[23:48:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[23:48:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[23:48:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[23:48:15] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[23:48:15] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[23:48:15] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[23:48:15] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[23:48:15] [PASSED] Automatic
[23:48:15] [PASSED] Full
[23:48:15] [PASSED] Limited 16:235
[23:48:15] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[23:48:15] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[23:48:15] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[23:48:15] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[23:48:15] === drm_test_drm_hdmi_connector_get_output_format_name ====
[23:48:15] [PASSED] RGB
[23:48:15] [PASSED] YUV 4:2:0
[23:48:15] [PASSED] YUV 4:2:2
[23:48:15] [PASSED] YUV 4:4:4
[23:48:15] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[23:48:15] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[23:48:15] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[23:48:15] ============= drm_damage_helper (21 subtests) ==============
[23:48:15] [PASSED] drm_test_damage_iter_no_damage
[23:48:15] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[23:48:15] [PASSED] drm_test_damage_iter_no_damage_src_moved
[23:48:15] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[23:48:15] [PASSED] drm_test_damage_iter_no_damage_not_visible
[23:48:15] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[23:48:15] [PASSED] drm_test_damage_iter_no_damage_no_fb
[23:48:15] [PASSED] drm_test_damage_iter_simple_damage
[23:48:15] [PASSED] drm_test_damage_iter_single_damage
[23:48:15] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[23:48:15] [PASSED] drm_test_damage_iter_single_damage_outside_src
[23:48:15] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[23:48:15] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[23:48:15] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[23:48:15] [PASSED] drm_test_damage_iter_single_damage_src_moved
[23:48:15] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[23:48:15] [PASSED] drm_test_damage_iter_damage
[23:48:15] [PASSED] drm_test_damage_iter_damage_one_intersect
[23:48:15] [PASSED] drm_test_damage_iter_damage_one_outside
[23:48:15] [PASSED] drm_test_damage_iter_damage_src_moved
[23:48:15] [PASSED] drm_test_damage_iter_damage_not_visible
[23:48:15] ================ [PASSED] drm_damage_helper ================
[23:48:15] ============== drm_dp_mst_helper (3 subtests) ==============
[23:48:15] ============== drm_test_dp_mst_calc_pbn_mode ==============
[23:48:15] [PASSED] Clock 154000 BPP 30 DSC disabled
[23:48:15] [PASSED] Clock 234000 BPP 30 DSC disabled
[23:48:15] [PASSED] Clock 297000 BPP 24 DSC disabled
[23:48:15] [PASSED] Clock 332880 BPP 24 DSC enabled
[23:48:15] [PASSED] Clock 324540 BPP 24 DSC enabled
[23:48:15] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[23:48:15] ============== drm_test_dp_mst_calc_pbn_div ===============
[23:48:15] [PASSED] Link rate 2000000 lane count 4
[23:48:15] [PASSED] Link rate 2000000 lane count 2
[23:48:15] [PASSED] Link rate 2000000 lane count 1
[23:48:15] [PASSED] Link rate 1350000 lane count 4
[23:48:15] [PASSED] Link rate 1350000 lane count 2
[23:48:15] [PASSED] Link rate 1350000 lane count 1
[23:48:15] [PASSED] Link rate 1000000 lane count 4
[23:48:15] [PASSED] Link rate 1000000 lane count 2
[23:48:15] [PASSED] Link rate 1000000 lane count 1
[23:48:15] [PASSED] Link rate 810000 lane count 4
[23:48:15] [PASSED] Link rate 810000 lane count 2
[23:48:15] [PASSED] Link rate 810000 lane count 1
[23:48:15] [PASSED] Link rate 540000 lane count 4
[23:48:15] [PASSED] Link rate 540000 lane count 2
[23:48:15] [PASSED] Link rate 540000 lane count 1
[23:48:15] [PASSED] Link rate 270000 lane count 4
[23:48:15] [PASSED] Link rate 270000 lane count 2
[23:48:15] [PASSED] Link rate 270000 lane count 1
[23:48:15] [PASSED] Link rate 162000 lane count 4
[23:48:15] [PASSED] Link rate 162000 lane count 2
[23:48:15] [PASSED] Link rate 162000 lane count 1
[23:48:15] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[23:48:15] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[23:48:15] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[23:48:15] [PASSED] DP_POWER_UP_PHY with port number
[23:48:15] [PASSED] DP_POWER_DOWN_PHY with port number
[23:48:15] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[23:48:15] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[23:48:15] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[23:48:15] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[23:48:15] [PASSED] DP_QUERY_PAYLOAD with port number
[23:48:15] [PASSED] DP_QUERY_PAYLOAD with VCPI
[23:48:15] [PASSED] DP_REMOTE_DPCD_READ with port number
[23:48:15] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[23:48:15] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[23:48:15] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[23:48:15] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[23:48:15] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[23:48:15] [PASSED] DP_REMOTE_I2C_READ with port number
[23:48:15] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[23:48:15] [PASSED] DP_REMOTE_I2C_READ with transactions array
[23:48:15] [PASSED] DP_REMOTE_I2C_WRITE with port number
[23:48:15] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[23:48:15] [PASSED] DP_REMOTE_I2C_WRITE with data array
[23:48:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[23:48:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[23:48:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[23:48:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[23:48:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[23:48:15] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[23:48:15] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[23:48:15] ================ [PASSED] drm_dp_mst_helper ================
[23:48:15] ================== drm_exec (7 subtests) ===================
[23:48:15] [PASSED] sanitycheck
[23:48:15] [PASSED] test_lock
[23:48:15] [PASSED] test_lock_unlock
[23:48:15] [PASSED] test_duplicates
[23:48:15] [PASSED] test_prepare
[23:48:15] [PASSED] test_prepare_array
[23:48:15] [PASSED] test_multiple_loops
[23:48:15] ==================== [PASSED] drm_exec =====================
[23:48:15] =========== drm_format_helper_test (17 subtests) ===========
[23:48:15] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[23:48:15] [PASSED] single_pixel_source_buffer
[23:48:15] [PASSED] single_pixel_clip_rectangle
[23:48:15] [PASSED] well_known_colors
[23:48:15] [PASSED] destination_pitch
[23:48:15] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[23:48:15] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[23:48:15] [PASSED] single_pixel_source_buffer
[23:48:15] [PASSED] single_pixel_clip_rectangle
[23:48:15] [PASSED] well_known_colors
[23:48:15] [PASSED] destination_pitch
[23:48:15] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[23:48:15] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[23:48:15] [PASSED] single_pixel_source_buffer
[23:48:15] [PASSED] single_pixel_clip_rectangle
[23:48:15] [PASSED] well_known_colors
[23:48:15] [PASSED] destination_pitch
[23:48:15] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[23:48:15] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[23:48:15] [PASSED] single_pixel_source_buffer
[23:48:15] [PASSED] single_pixel_clip_rectangle
[23:48:15] [PASSED] well_known_colors
[23:48:15] [PASSED] destination_pitch
[23:48:15] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[23:48:15] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[23:48:15] [PASSED] single_pixel_source_buffer
[23:48:15] [PASSED] single_pixel_clip_rectangle
[23:48:15] [PASSED] well_known_colors
[23:48:15] [PASSED] destination_pitch
[23:48:15] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[23:48:15] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[23:48:15] [PASSED] single_pixel_source_buffer
[23:48:15] [PASSED] single_pixel_clip_rectangle
[23:48:15] [PASSED] well_known_colors
[23:48:15] [PASSED] destination_pitch
[23:48:15] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[23:48:15] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[23:48:15] [PASSED] single_pixel_source_buffer
[23:48:15] [PASSED] single_pixel_clip_rectangle
[23:48:15] [PASSED] well_known_colors
[23:48:15] [PASSED] destination_pitch
[23:48:15] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[23:48:15] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[23:48:15] [PASSED] single_pixel_source_buffer
[23:48:15] [PASSED] single_pixel_clip_rectangle
[23:48:15] [PASSED] well_known_colors
[23:48:15] [PASSED] destination_pitch
[23:48:15] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[23:48:15] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[23:48:15] [PASSED] single_pixel_source_buffer
[23:48:15] [PASSED] single_pixel_clip_rectangle
[23:48:15] [PASSED] well_known_colors
[23:48:15] [PASSED] destination_pitch
[23:48:15] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[23:48:15] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[23:48:15] [PASSED] single_pixel_source_buffer
[23:48:15] [PASSED] single_pixel_clip_rectangle
[23:48:15] [PASSED] well_known_colors
[23:48:15] [PASSED] destination_pitch
[23:48:15] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[23:48:15] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[23:48:15] [PASSED] single_pixel_source_buffer
[23:48:15] [PASSED] single_pixel_clip_rectangle
[23:48:15] [PASSED] well_known_colors
[23:48:15] [PASSED] destination_pitch
[23:48:15] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[23:48:15] ============== drm_test_fb_xrgb8888_to_mono ===============
[23:48:15] [PASSED] single_pixel_source_buffer
[23:48:15] [PASSED] single_pixel_clip_rectangle
[23:48:15] [PASSED] well_known_colors
[23:48:15] [PASSED] destination_pitch
[23:48:15] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[23:48:15] ==================== drm_test_fb_swab =====================
[23:48:15] [PASSED] single_pixel_source_buffer
[23:48:15] [PASSED] single_pixel_clip_rectangle
[23:48:15] [PASSED] well_known_colors
[23:48:15] [PASSED] destination_pitch
[23:48:15] ================ [PASSED] drm_test_fb_swab =================
[23:48:15] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[23:48:15] [PASSED] single_pixel_source_buffer
[23:48:15] [PASSED] single_pixel_clip_rectangle
[23:48:15] [PASSED] well_known_colors
[23:48:15] [PASSED] destination_pitch
[23:48:15] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[23:48:15] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[23:48:15] [PASSED] single_pixel_source_buffer
[23:48:15] [PASSED] single_pixel_clip_rectangle
[23:48:15] [PASSED] well_known_colors
[23:48:15] [PASSED] destination_pitch
[23:48:15] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[23:48:15] ================= drm_test_fb_clip_offset =================
[23:48:15] [PASSED] pass through
[23:48:15] [PASSED] horizontal offset
[23:48:15] [PASSED] vertical offset
[23:48:15] [PASSED] horizontal and vertical offset
[23:48:15] [PASSED] horizontal offset (custom pitch)
[23:48:15] [PASSED] vertical offset (custom pitch)
[23:48:15] [PASSED] horizontal and vertical offset (custom pitch)
[23:48:15] ============= [PASSED] drm_test_fb_clip_offset =============
[23:48:15] =================== drm_test_fb_memcpy ====================
[23:48:15] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[23:48:15] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[23:48:15] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[23:48:15] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[23:48:15] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[23:48:15] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[23:48:15] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[23:48:15] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[23:48:15] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[23:48:15] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[23:48:15] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[23:48:15] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[23:48:15] =============== [PASSED] drm_test_fb_memcpy ================
[23:48:15] ============= [PASSED] drm_format_helper_test ==============
[23:48:15] ================= drm_format (18 subtests) =================
[23:48:15] [PASSED] drm_test_format_block_width_invalid
[23:48:15] [PASSED] drm_test_format_block_width_one_plane
[23:48:15] [PASSED] drm_test_format_block_width_two_plane
[23:48:15] [PASSED] drm_test_format_block_width_three_plane
[23:48:15] [PASSED] drm_test_format_block_width_tiled
[23:48:15] [PASSED] drm_test_format_block_height_invalid
[23:48:15] [PASSED] drm_test_format_block_height_one_plane
[23:48:15] [PASSED] drm_test_format_block_height_two_plane
[23:48:15] [PASSED] drm_test_format_block_height_three_plane
[23:48:15] [PASSED] drm_test_format_block_height_tiled
[23:48:15] [PASSED] drm_test_format_min_pitch_invalid
[23:48:15] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[23:48:15] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[23:48:15] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[23:48:15] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[23:48:15] [PASSED] drm_test_format_min_pitch_two_plane
[23:48:15] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[23:48:15] [PASSED] drm_test_format_min_pitch_tiled
[23:48:15] =================== [PASSED] drm_format ====================
[23:48:15] ============== drm_framebuffer (10 subtests) ===============
[23:48:15] ========== drm_test_framebuffer_check_src_coords ==========
[23:48:15] [PASSED] Success: source fits into fb
[23:48:15] [PASSED] Fail: overflowing fb with x-axis coordinate
[23:48:15] [PASSED] Fail: overflowing fb with y-axis coordinate
[23:48:15] [PASSED] Fail: overflowing fb with source width
[23:48:15] [PASSED] Fail: overflowing fb with source height
[23:48:15] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[23:48:15] [PASSED] drm_test_framebuffer_cleanup
[23:48:15] =============== drm_test_framebuffer_create ===============
[23:48:15] [PASSED] ABGR8888 normal sizes
[23:48:15] [PASSED] ABGR8888 max sizes
[23:48:15] [PASSED] ABGR8888 pitch greater than min required
[23:48:15] [PASSED] ABGR8888 pitch less than min required
[23:48:15] [PASSED] ABGR8888 Invalid width
[23:48:15] [PASSED] ABGR8888 Invalid buffer handle
[23:48:15] [PASSED] No pixel format
[23:48:15] [PASSED] ABGR8888 Width 0
[23:48:15] [PASSED] ABGR8888 Height 0
[23:48:15] [PASSED] ABGR8888 Out of bound height * pitch combination
[23:48:15] [PASSED] ABGR8888 Large buffer offset
[23:48:15] [PASSED] ABGR8888 Buffer offset for inexistent plane
[23:48:15] [PASSED] ABGR8888 Invalid flag
[23:48:15] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[23:48:15] [PASSED] ABGR8888 Valid buffer modifier
[23:48:15] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[23:48:15] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[23:48:15] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[23:48:15] [PASSED] NV12 Normal sizes
[23:48:15] [PASSED] NV12 Max sizes
[23:48:15] [PASSED] NV12 Invalid pitch
[23:48:15] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[23:48:15] [PASSED] NV12 different modifier per-plane
[23:48:15] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[23:48:15] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[23:48:15] [PASSED] NV12 Modifier for inexistent plane
[23:48:15] [PASSED] NV12 Handle for inexistent plane
[23:48:15] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[23:48:15] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[23:48:15] [PASSED] YVU420 Normal sizes
[23:48:15] [PASSED] YVU420 Max sizes
[23:48:15] [PASSED] YVU420 Invalid pitch
[23:48:15] [PASSED] YVU420 Different pitches
[23:48:15] [PASSED] YVU420 Different buffer offsets/pitches
[23:48:15] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[23:48:15] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[23:48:15] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[23:48:15] [PASSED] YVU420 Valid modifier
[23:48:15] [PASSED] YVU420 Different modifiers per plane
[23:48:15] [PASSED] YVU420 Modifier for inexistent plane
[23:48:15] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[23:48:15] [PASSED] X0L2 Normal sizes
[23:48:15] [PASSED] X0L2 Max sizes
[23:48:15] [PASSED] X0L2 Invalid pitch
[23:48:15] [PASSED] X0L2 Pitch greater than minimum required
[23:48:15] [PASSED] X0L2 Handle for inexistent plane
[23:48:15] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[23:48:15] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[23:48:15] [PASSED] X0L2 Valid modifier
[23:48:15] [PASSED] X0L2 Modifier for inexistent plane
[23:48:15] =========== [PASSED] drm_test_framebuffer_create ===========
[23:48:15] [PASSED] drm_test_framebuffer_free
[23:48:15] [PASSED] drm_test_framebuffer_init
[23:48:15] [PASSED] drm_test_framebuffer_init_bad_format
[23:48:15] [PASSED] drm_test_framebuffer_init_dev_mismatch
[23:48:15] [PASSED] drm_test_framebuffer_lookup
[23:48:15] [PASSED] drm_test_framebuffer_lookup_inexistent
[23:48:15] [PASSED] drm_test_framebuffer_modifiers_not_supported
[23:48:15] ================= [PASSED] drm_framebuffer =================
[23:48:15] ================ drm_gem_shmem (8 subtests) ================
[23:48:15] [PASSED] drm_gem_shmem_test_obj_create
[23:48:15] [PASSED] drm_gem_shmem_test_obj_create_private
[23:48:15] [PASSED] drm_gem_shmem_test_pin_pages
[23:48:15] [PASSED] drm_gem_shmem_test_vmap
[23:48:15] [PASSED] drm_gem_shmem_test_get_sg_table
[23:48:15] [PASSED] drm_gem_shmem_test_get_pages_sgt
[23:48:15] [PASSED] drm_gem_shmem_test_madvise
[23:48:15] [PASSED] drm_gem_shmem_test_purge
[23:48:15] ================== [PASSED] drm_gem_shmem ==================
[23:48:15] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[23:48:15] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[23:48:15] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[23:48:15] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[23:48:15] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[23:48:15] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[23:48:15] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[23:48:15] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[23:48:15] [PASSED] Automatic
[23:48:15] [PASSED] Full
[23:48:15] [PASSED] Limited 16:235
[23:48:15] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[23:48:15] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[23:48:15] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[23:48:15] [PASSED] drm_test_check_disable_connector
[23:48:15] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[23:48:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[23:48:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[23:48:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[23:48:15] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[23:48:15] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[23:48:15] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[23:48:15] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[23:48:15] [PASSED] drm_test_check_output_bpc_dvi
[23:48:15] [PASSED] drm_test_check_output_bpc_format_vic_1
[23:48:15] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[23:48:15] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[23:48:15] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[23:48:15] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[23:48:15] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[23:48:15] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[23:48:15] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[23:48:15] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[23:48:15] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[23:48:15] [PASSED] drm_test_check_broadcast_rgb_value
[23:48:15] [PASSED] drm_test_check_bpc_8_value
[23:48:15] [PASSED] drm_test_check_bpc_10_value
[23:48:15] [PASSED] drm_test_check_bpc_12_value
[23:48:15] [PASSED] drm_test_check_format_value
[23:48:15] [PASSED] drm_test_check_tmds_char_value
[23:48:15] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[23:48:15] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[23:48:15] [PASSED] drm_test_check_mode_valid
[23:48:15] [PASSED] drm_test_check_mode_valid_reject
[23:48:15] [PASSED] drm_test_check_mode_valid_reject_rate
[23:48:15] [PASSED] drm_test_check_mode_valid_reject_max_clock
[23:48:15] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[23:48:15] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[23:48:15] [PASSED] drm_test_check_infoframes
[23:48:15] [PASSED] drm_test_check_reject_avi_infoframe
[23:48:15] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[23:48:15] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[23:48:15] [PASSED] drm_test_check_reject_audio_infoframe
[23:48:15] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[23:48:15] ================= drm_managed (2 subtests) =================
[23:48:15] [PASSED] drm_test_managed_release_action
[23:48:15] [PASSED] drm_test_managed_run_action
[23:48:15] =================== [PASSED] drm_managed ===================
[23:48:15] =================== drm_mm (6 subtests) ====================
[23:48:15] [PASSED] drm_test_mm_init
[23:48:15] [PASSED] drm_test_mm_debug
[23:48:15] [PASSED] drm_test_mm_align32
[23:48:15] [PASSED] drm_test_mm_align64
[23:48:15] [PASSED] drm_test_mm_lowest
[23:48:15] [PASSED] drm_test_mm_highest
[23:48:15] ===================== [PASSED] drm_mm ======================
[23:48:15] ============= drm_modes_analog_tv (5 subtests) =============
[23:48:15] [PASSED] drm_test_modes_analog_tv_mono_576i
[23:48:15] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[23:48:15] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[23:48:15] [PASSED] drm_test_modes_analog_tv_pal_576i
[23:48:15] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[23:48:15] =============== [PASSED] drm_modes_analog_tv ===============
[23:48:15] ============== drm_plane_helper (2 subtests) ===============
[23:48:15] =============== drm_test_check_plane_state ================
[23:48:15] [PASSED] clipping_simple
[23:48:15] [PASSED] clipping_rotate_reflect
[23:48:15] [PASSED] positioning_simple
[23:48:15] [PASSED] upscaling
[23:48:15] [PASSED] downscaling
[23:48:15] [PASSED] rounding1
[23:48:15] [PASSED] rounding2
[23:48:15] [PASSED] rounding3
[23:48:15] [PASSED] rounding4
[23:48:15] =========== [PASSED] drm_test_check_plane_state ============
[23:48:15] =========== drm_test_check_invalid_plane_state ============
[23:48:15] [PASSED] positioning_invalid
[23:48:15] [PASSED] upscaling_invalid
[23:48:15] [PASSED] downscaling_invalid
[23:48:15] ======= [PASSED] drm_test_check_invalid_plane_state ========
[23:48:15] ================ [PASSED] drm_plane_helper =================
[23:48:15] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[23:48:15] ====== drm_test_connector_helper_tv_get_modes_check =======
[23:48:15] [PASSED] None
[23:48:15] [PASSED] PAL
[23:48:15] [PASSED] NTSC
[23:48:15] [PASSED] Both, NTSC Default
[23:48:15] [PASSED] Both, PAL Default
[23:48:15] [PASSED] Both, NTSC Default, with PAL on command-line
[23:48:15] [PASSED] Both, PAL Default, with NTSC on command-line
[23:48:15] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[23:48:15] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[23:48:15] ================== drm_rect (9 subtests) ===================
[23:48:15] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[23:48:15] [PASSED] drm_test_rect_clip_scaled_not_clipped
[23:48:15] [PASSED] drm_test_rect_clip_scaled_clipped
[23:48:15] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[23:48:15] ================= drm_test_rect_intersect =================
[23:48:15] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[23:48:15] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[23:48:15] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[23:48:15] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[23:48:15] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[23:48:15] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[23:48:15] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[23:48:15] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[23:48:15] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[23:48:15] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[23:48:15] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[23:48:15] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[23:48:15] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[23:48:15] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[23:48:15] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
stty: 'standard input': Inappropriate ioctl for device
[23:48:15] ============= [PASSED] drm_test_rect_intersect =============
[23:48:15] ================ drm_test_rect_calc_hscale ================
[23:48:15] [PASSED] normal use
[23:48:15] [PASSED] out of max range
[23:48:15] [PASSED] out of min range
[23:48:15] [PASSED] zero dst
[23:48:15] [PASSED] negative src
[23:48:15] [PASSED] negative dst
[23:48:15] ============ [PASSED] drm_test_rect_calc_hscale ============
[23:48:15] ================ drm_test_rect_calc_vscale ================
[23:48:15] [PASSED] normal use
[23:48:15] [PASSED] out of max range
[23:48:15] [PASSED] out of min range
[23:48:15] [PASSED] zero dst
[23:48:15] [PASSED] negative src
[23:48:15] [PASSED] negative dst
[23:48:15] ============ [PASSED] drm_test_rect_calc_vscale ============
[23:48:15] ================== drm_test_rect_rotate ===================
[23:48:15] [PASSED] reflect-x
[23:48:15] [PASSED] reflect-y
[23:48:15] [PASSED] rotate-0
[23:48:15] [PASSED] rotate-90
[23:48:15] [PASSED] rotate-180
[23:48:15] [PASSED] rotate-270
[23:48:15] ============== [PASSED] drm_test_rect_rotate ===============
[23:48:15] ================ drm_test_rect_rotate_inv =================
[23:48:15] [PASSED] reflect-x
[23:48:15] [PASSED] reflect-y
[23:48:15] [PASSED] rotate-0
[23:48:15] [PASSED] rotate-90
[23:48:15] [PASSED] rotate-180
[23:48:15] [PASSED] rotate-270
[23:48:15] ============ [PASSED] drm_test_rect_rotate_inv =============
[23:48:15] ==================== [PASSED] drm_rect =====================
[23:48:15] ============ drm_sysfb_modeset_test (1 subtest) ============
[23:48:15] ============ drm_test_sysfb_build_fourcc_list =============
[23:48:15] [PASSED] no native formats
[23:48:15] [PASSED] XRGB8888 as native format
[23:48:15] [PASSED] remove duplicates
[23:48:15] [PASSED] convert alpha formats
[23:48:15] [PASSED] random formats
[23:48:15] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[23:48:15] ============= [PASSED] drm_sysfb_modeset_test ==============
[23:48:15] ================== drm_fixp (2 subtests) ===================
[23:48:15] [PASSED] drm_test_int2fixp
[23:48:15] [PASSED] drm_test_sm2fixp
[23:48:15] ==================== [PASSED] drm_fixp =====================
[23:48:15] ============================================================
[23:48:15] Testing complete. Ran 630 tests: passed: 630
[23:48:15] Elapsed time: 28.119s total, 1.672s configuring, 26.029s building, 0.386s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[23:48:15] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:48:17] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:48:27] Starting KUnit Kernel (1/1)...
[23:48:27] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:48:27] ================= ttm_device (5 subtests) ==================
[23:48:27] [PASSED] ttm_device_init_basic
[23:48:27] [PASSED] ttm_device_init_multiple
[23:48:27] [PASSED] ttm_device_fini_basic
[23:48:27] [PASSED] ttm_device_init_no_vma_man
[23:48:27] ================== ttm_device_init_pools ==================
[23:48:27] [PASSED] No DMA allocations, no DMA32 required
[23:48:27] [PASSED] DMA allocations, DMA32 required
[23:48:27] [PASSED] No DMA allocations, DMA32 required
[23:48:27] [PASSED] DMA allocations, no DMA32 required
[23:48:27] ============== [PASSED] ttm_device_init_pools ==============
[23:48:27] =================== [PASSED] ttm_device ====================
[23:48:27] ================== ttm_pool (8 subtests) ===================
[23:48:27] ================== ttm_pool_alloc_basic ===================
[23:48:27] [PASSED] One page
[23:48:27] [PASSED] More than one page
[23:48:27] [PASSED] Above the allocation limit
[23:48:27] [PASSED] One page, with coherent DMA mappings enabled
[23:48:27] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:48:27] ============== [PASSED] ttm_pool_alloc_basic ===============
[23:48:27] ============== ttm_pool_alloc_basic_dma_addr ==============
[23:48:27] [PASSED] One page
[23:48:27] [PASSED] More than one page
[23:48:27] [PASSED] Above the allocation limit
[23:48:27] [PASSED] One page, with coherent DMA mappings enabled
[23:48:27] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:48:27] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[23:48:27] [PASSED] ttm_pool_alloc_order_caching_match
[23:48:27] [PASSED] ttm_pool_alloc_caching_mismatch
[23:48:27] [PASSED] ttm_pool_alloc_order_mismatch
[23:48:27] [PASSED] ttm_pool_free_dma_alloc
[23:48:27] [PASSED] ttm_pool_free_no_dma_alloc
[23:48:27] [PASSED] ttm_pool_fini_basic
[23:48:27] ==================== [PASSED] ttm_pool =====================
[23:48:27] ================ ttm_resource (8 subtests) =================
[23:48:27] ================= ttm_resource_init_basic =================
[23:48:27] [PASSED] Init resource in TTM_PL_SYSTEM
[23:48:27] [PASSED] Init resource in TTM_PL_VRAM
[23:48:27] [PASSED] Init resource in a private placement
[23:48:27] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[23:48:27] ============= [PASSED] ttm_resource_init_basic =============
[23:48:27] [PASSED] ttm_resource_init_pinned
[23:48:27] [PASSED] ttm_resource_fini_basic
[23:48:27] [PASSED] ttm_resource_manager_init_basic
[23:48:27] [PASSED] ttm_resource_manager_usage_basic
[23:48:27] [PASSED] ttm_resource_manager_set_used_basic
[23:48:27] [PASSED] ttm_sys_man_alloc_basic
[23:48:27] [PASSED] ttm_sys_man_free_basic
[23:48:27] ================== [PASSED] ttm_resource ===================
[23:48:27] =================== ttm_tt (15 subtests) ===================
[23:48:27] ==================== ttm_tt_init_basic ====================
[23:48:27] [PASSED] Page-aligned size
[23:48:27] [PASSED] Extra pages requested
[23:48:27] ================ [PASSED] ttm_tt_init_basic ================
[23:48:27] [PASSED] ttm_tt_init_misaligned
[23:48:27] [PASSED] ttm_tt_fini_basic
[23:48:27] [PASSED] ttm_tt_fini_sg
[23:48:27] [PASSED] ttm_tt_fini_shmem
[23:48:27] [PASSED] ttm_tt_create_basic
[23:48:27] [PASSED] ttm_tt_create_invalid_bo_type
[23:48:27] [PASSED] ttm_tt_create_ttm_exists
[23:48:27] [PASSED] ttm_tt_create_failed
[23:48:27] [PASSED] ttm_tt_destroy_basic
[23:48:27] [PASSED] ttm_tt_populate_null_ttm
[23:48:27] [PASSED] ttm_tt_populate_populated_ttm
[23:48:27] [PASSED] ttm_tt_unpopulate_basic
[23:48:27] [PASSED] ttm_tt_unpopulate_empty_ttm
[23:48:27] [PASSED] ttm_tt_swapin_basic
[23:48:27] ===================== [PASSED] ttm_tt ======================
[23:48:27] =================== ttm_bo (14 subtests) ===================
[23:48:27] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[23:48:27] [PASSED] Cannot be interrupted and sleeps
[23:48:27] [PASSED] Cannot be interrupted, locks straight away
[23:48:27] [PASSED] Can be interrupted, sleeps
[23:48:27] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[23:48:27] [PASSED] ttm_bo_reserve_locked_no_sleep
[23:48:27] [PASSED] ttm_bo_reserve_no_wait_ticket
[23:48:27] [PASSED] ttm_bo_reserve_double_resv
[23:48:27] [PASSED] ttm_bo_reserve_interrupted
[23:48:27] [PASSED] ttm_bo_reserve_deadlock
[23:48:27] [PASSED] ttm_bo_unreserve_basic
[23:48:27] [PASSED] ttm_bo_unreserve_pinned
[23:48:27] [PASSED] ttm_bo_unreserve_bulk
[23:48:27] [PASSED] ttm_bo_fini_basic
[23:48:27] [PASSED] ttm_bo_fini_shared_resv
[23:48:27] [PASSED] ttm_bo_pin_basic
[23:48:27] [PASSED] ttm_bo_pin_unpin_resource
[23:48:27] [PASSED] ttm_bo_multiple_pin_one_unpin
[23:48:27] ===================== [PASSED] ttm_bo ======================
[23:48:27] ============== ttm_bo_validate (21 subtests) ===============
[23:48:27] ============== ttm_bo_init_reserved_sys_man ===============
[23:48:27] [PASSED] Buffer object for userspace
[23:48:27] [PASSED] Kernel buffer object
[23:48:27] [PASSED] Shared buffer object
[23:48:27] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[23:48:27] ============== ttm_bo_init_reserved_mock_man ==============
[23:48:27] [PASSED] Buffer object for userspace
[23:48:27] [PASSED] Kernel buffer object
[23:48:27] [PASSED] Shared buffer object
[23:48:27] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[23:48:27] [PASSED] ttm_bo_init_reserved_resv
[23:48:27] ================== ttm_bo_validate_basic ==================
[23:48:27] [PASSED] Buffer object for userspace
[23:48:27] [PASSED] Kernel buffer object
[23:48:27] [PASSED] Shared buffer object
[23:48:27] ============== [PASSED] ttm_bo_validate_basic ==============
[23:48:27] [PASSED] ttm_bo_validate_invalid_placement
[23:48:27] ============= ttm_bo_validate_same_placement ==============
[23:48:27] [PASSED] System manager
[23:48:27] [PASSED] VRAM manager
[23:48:27] ========= [PASSED] ttm_bo_validate_same_placement ==========
[23:48:27] [PASSED] ttm_bo_validate_failed_alloc
[23:48:27] [PASSED] ttm_bo_validate_pinned
[23:48:27] [PASSED] ttm_bo_validate_busy_placement
[23:48:27] ================ ttm_bo_validate_multihop =================
[23:48:27] [PASSED] Buffer object for userspace
[23:48:27] [PASSED] Kernel buffer object
[23:48:27] [PASSED] Shared buffer object
[23:48:27] ============ [PASSED] ttm_bo_validate_multihop =============
[23:48:27] ========== ttm_bo_validate_no_placement_signaled ==========
[23:48:27] [PASSED] Buffer object in system domain, no page vector
[23:48:27] [PASSED] Buffer object in system domain with an existing page vector
[23:48:27] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[23:48:27] ======== ttm_bo_validate_no_placement_not_signaled ========
[23:48:27] [PASSED] Buffer object for userspace
[23:48:27] [PASSED] Kernel buffer object
[23:48:27] [PASSED] Shared buffer object
[23:48:27] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[23:48:27] [PASSED] ttm_bo_validate_move_fence_signaled
[23:48:27] ========= ttm_bo_validate_move_fence_not_signaled =========
[23:48:27] [PASSED] Waits for GPU
[23:48:27] [PASSED] Tries to lock straight away
[23:48:27] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[23:48:27] [PASSED] ttm_bo_validate_happy_evict
[23:48:27] [PASSED] ttm_bo_validate_all_pinned_evict
[23:48:27] [PASSED] ttm_bo_validate_allowed_only_evict
[23:48:27] [PASSED] ttm_bo_validate_deleted_evict
[23:48:27] [PASSED] ttm_bo_validate_busy_domain_evict
[23:48:27] [PASSED] ttm_bo_validate_evict_gutting
[23:48:27] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[23:48:27] ================= [PASSED] ttm_bo_validate =================
[23:48:27] ============================================================
[23:48:27] Testing complete. Ran 101 tests: passed: 101
[23:48:27] Elapsed time: 11.782s total, 1.679s configuring, 9.886s building, 0.192s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 23+ messages in thread
* ✗ CI.checksparse: warning for Basic enabling patches for Xe3p_LPG and NVL-P (rev2)
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
` (16 preceding siblings ...)
2026-02-05 23:48 ` ✓ CI.KUnit: success " Patchwork
@ 2026-02-06 0:04 ` Patchwork
2026-02-06 0:47 ` ✓ Xe.CI.BAT: success " Patchwork
18 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2026-02-06 0:04 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-xe
== Series Details ==
Series: Basic enabling patches for Xe3p_LPG and NVL-P (rev2)
URL : https://patchwork.freedesktop.org/series/161037/
State : warning
== Summary ==
+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 75acb0a8b6f69c6429941e6845df2af94ed15939
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display_device.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+./include/linux/pwm.h:13:1: error: bad constant expression
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 23+ messages in thread
* ✓ Xe.CI.BAT: success for Basic enabling patches for Xe3p_LPG and NVL-P (rev2)
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
` (17 preceding siblings ...)
2026-02-06 0:04 ` ✗ CI.checksparse: warning " Patchwork
@ 2026-02-06 0:47 ` Patchwork
18 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2026-02-06 0:47 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 875 bytes --]
== Series Details ==
Series: Basic enabling patches for Xe3p_LPG and NVL-P (rev2)
URL : https://patchwork.freedesktop.org/series/161037/
State : success
== Summary ==
CI Bug Log - changes from xe-4513-75acb0a8b6f69c6429941e6845df2af94ed15939_BAT -> xe-pw-161037v2_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-4513-75acb0a8b6f69c6429941e6845df2af94ed15939 -> xe-pw-161037v2
IGT_8739: 8739
xe-4513-75acb0a8b6f69c6429941e6845df2af94ed15939: 75acb0a8b6f69c6429941e6845df2af94ed15939
xe-pw-161037v2: 161037v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161037v2/index.html
[-- Attachment #2: Type: text/html, Size: 1423 bytes --]
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 15/15] drm/xe/nvlp: Bump maximum WOPCM size
2026-02-05 23:39 ` [PATCH v2 15/15] drm/xe/nvlp: Bump maximum WOPCM size Gustavo Sousa
@ 2026-02-06 8:39 ` Bhadane, Dnyaneshwar
0 siblings, 0 replies; 23+ messages in thread
From: Bhadane, Dnyaneshwar @ 2026-02-06 8:39 UTC (permalink / raw)
To: Gustavo Sousa, intel-xe, intel-gfx
On 06-Feb-26 5:09 AM, Gustavo Sousa wrote:
> On NVL-P, the primary GT's WOPCM gained an extra 8MiB for the Memory
> URB. As such, we need to bump the maximum size in the driver so that
> the driver is able to load without erroring out thinking that the WOPCM
> is too small.
>
> FIXME: The wopcm code in xe driver is a bit confusing. For the case
> where the offsets for GUC WOPCM are already locked, it appears we are
> using the maximum overall WOPCM size instead of the sizes relative to
> each type of GT. The function __check_layout() should be checking
> against the latter.
>
> Bspec: 67090
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
LGTM,
Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> ---
> drivers/gpu/drm/xe/xe_wopcm.c | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_wopcm.c b/drivers/gpu/drm/xe/xe_wopcm.c
> index dde4f4967ca3..900daf1d1b1b 100644
> --- a/drivers/gpu/drm/xe/xe_wopcm.c
> +++ b/drivers/gpu/drm/xe/xe_wopcm.c
> @@ -55,8 +55,6 @@
> #define MTL_WOPCM_SIZE SZ_4M
> #define WOPCM_SIZE SZ_2M
>
> -#define MAX_WOPCM_SIZE SZ_8M
> -
> /* 16KB WOPCM (RSVD WOPCM) is reserved from HuC firmware top. */
> #define WOPCM_RESERVED_SIZE SZ_16K
>
> @@ -186,6 +184,14 @@ u32 xe_wopcm_size(struct xe_device *xe)
> WOPCM_SIZE;
> }
>
> +static u32 max_wopcm_size(struct xe_device *xe)
> +{
> + if (xe->info.platform == XE_NOVALAKE_P)
> + return SZ_16M;
> + else
> + return SZ_8M;
> +}
> +
> /**
> * xe_wopcm_init() - Initialize the WOPCM structure.
> * @wopcm: pointer to xe_wopcm.
> @@ -227,8 +233,11 @@ int xe_wopcm_init(struct xe_wopcm *wopcm)
> * When the GuC wopcm base and size are preprogrammed by
> * BIOS/IFWI, check against the max allowed wopcm size to
> * validate if the programmed values align to the wopcm layout.
> + *
> + * FIXME: This is giving the maximum overall WOPCM size and not
> + * the size relative to each GT.
> */
> - wopcm->size = MAX_WOPCM_SIZE;
> + wopcm->size = max_wopcm_size(xe);
>
> goto check;
> }
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 02/15] drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10
2026-02-05 23:39 ` [PATCH v2 02/15] drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10 Gustavo Sousa
@ 2026-02-06 15:25 ` Matt Roper
0 siblings, 0 replies; 23+ messages in thread
From: Matt Roper @ 2026-02-06 15:25 UTC (permalink / raw)
To: Gustavo Sousa
Cc: intel-xe, intel-gfx, Shekhar Chauhan, Nitin Gote,
Tangudu Tilak Tirumalesh, Mallesh Koujalagi
On Thu, Feb 05, 2026 at 08:39:30PM -0300, Gustavo Sousa wrote:
> From: Shekhar Chauhan <shekhar.chauhan@intel.com>
>
> Add the initial set of workarounds for Xe3p_LPG graphics version 35.10.
>
> v2:
> - Fix spacing style for field LOCALITYDIS. (Matt)
> - Drop unnecessary Wa_14025780377. (Matt)
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Co-developed-by: Nitin Gote <nitin.r.gote@intel.com>
> Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> Co-developed-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
> Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
> Co-developed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> Signed-off-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> Co-developed-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 16 +++++++++++++
> drivers/gpu/drm/xe/xe_reg_whitelist.c | 8 +++++++
> drivers/gpu/drm/xe/xe_wa.c | 43 +++++++++++++++++++++++++++++++++++
> 3 files changed, 67 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 24fc64fc832e..55f5be7283db 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -100,6 +100,9 @@
> #define VE1_AUX_INV XE_REG(0x42b8)
> #define AUX_INV REG_BIT(0)
>
> +#define GAMSTLB_CTRL2 XE_REG_MCR(0x4788)
> +#define STLB_SINGLE_BANK_MODE REG_BIT(11)
> +
> #define XE2_LMEM_CFG XE_REG(0x48b0)
>
> #define XE2_GAMWALK_CTRL 0x47e4
> @@ -107,6 +110,9 @@
> #define XE2_GAMWALK_CTRL_3D XE_REG_MCR(XE2_GAMWALK_CTRL)
> #define EN_CMP_1WCOH_GW REG_BIT(14)
>
> +#define MMIOATSREQLIMIT_GAM_WALK_3D XE_REG_MCR(0x47f8)
> +#define DIS_ATS_WRONLY_PG REG_BIT(18)
> +
> #define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910)
> #define XEHP_FLAT_CCS_PTR REG_GENMASK(31, 8)
>
> @@ -210,6 +216,9 @@
>
> #define GSCPSMI_BASE XE_REG(0x880c)
>
> +#define CCCHKNREG2 XE_REG_MCR(0x881c)
> +#define LOCALITYDIS REG_BIT(7)
> +
> #define CCCHKNREG1 XE_REG_MCR(0x8828)
> #define L3CMPCTRL REG_BIT(23)
> #define ENCOMPPERFFIX REG_BIT(18)
> @@ -420,6 +429,8 @@
> #define LSN_DIM_Z_WGT(value) REG_FIELD_PREP(LSN_DIM_Z_WGT_MASK, value)
>
> #define L3SQCREG2 XE_REG_MCR(0xb104)
> +#define L3_SQ_DISABLE_COAMA_2WAY_COH REG_BIT(30)
> +#define L3_SQ_DISABLE_COAMA REG_BIT(22)
> #define COMPMEMRD256BOVRFETCHEN REG_BIT(20)
>
> #define L3SQCREG3 XE_REG_MCR(0xb108)
> @@ -550,11 +561,16 @@
> #define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32)
> #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32)
> #define XE2_ALLOC_DPA_STARVE_FIX_DIS REG_BIT(47 - 32)
> +#define SAMPLER_LD_LSC_DISABLE REG_BIT(45 - 32)
> #define ENABLE_SMP_LD_RENDER_SURFACE_CONTROL REG_BIT(44 - 32)
> #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32)
> #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32)
> #define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32)
> #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32)
> +#define LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE REG_BIT(35 - 32)
> +
> +#define ROW_CHICKEN5 XE_REG_MCR(0xe7f0)
> +#define CPSS_AWARE_DIS REG_BIT(3)
>
> #define SARB_CHICKEN1 XE_REG_MCR(0xe90c)
> #define COMP_CKN_IN REG_GENMASK(30, 29)
> diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> index 1d36c09681aa..9c513778d370 100644
> --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> @@ -81,6 +81,14 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
> WHITELIST(VFLSKPD,
> RING_FORCE_TO_NONPRIV_ACCESS_RW))
> },
> + { XE_RTP_NAME("14024997852"),
> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
> + ENGINE_CLASS(RENDER)),
> + XE_RTP_ACTIONS(WHITELIST(FF_MODE,
> + RING_FORCE_TO_NONPRIV_ACCESS_RW),
> + WHITELIST(VFLSKPD,
> + RING_FORCE_TO_NONPRIV_ACCESS_RW))
> + },
>
> #define WHITELIST_OA_MMIO_TRG(trg, status, head) \
> WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 1e8d61ac581b..682865f1fc16 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -325,6 +325,31 @@ static const struct xe_rtp_entry_sr gt_was[] = {
> XE_RTP_RULES(MEDIA_VERSION(3500)),
> XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
> },
> +
> + /* Xe3P_LPG */
> +
> + { XE_RTP_NAME("14025160223"),
> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
> + XE_RTP_ACTIONS(SET(MMIOATSREQLIMIT_GAM_WALK_3D,
> + DIS_ATS_WRONLY_PG))
> + },
> + { XE_RTP_NAME("16028780921"),
> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
> + XE_RTP_ACTIONS(SET(CCCHKNREG2, LOCALITYDIS))
> + },
> + { XE_RTP_NAME("14026144927"),
> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
> + XE_RTP_ACTIONS(SET(L3SQCREG2, L3_SQ_DISABLE_COAMA_2WAY_COH |
> + L3_SQ_DISABLE_COAMA))
> + },
> + { XE_RTP_NAME("14025635424"),
> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
> + XE_RTP_ACTIONS(SET(GAMSTLB_CTRL2, STLB_SINGLE_BANK_MODE))
> + },
> + { XE_RTP_NAME("16028005424"),
> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
> + XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
> + },
> };
>
> static const struct xe_rtp_entry_sr engine_was[] = {
> @@ -699,6 +724,24 @@ static const struct xe_rtp_entry_sr engine_was[] = {
> FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
> XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
> },
> +
> + /* Xe3p_LPG*/
> +
> + { XE_RTP_NAME("22021149932"),
> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
> + FUNC(xe_rtp_match_first_render_or_compute)),
> + XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, SAMPLER_LD_LSC_DISABLE))
> + },
> + { XE_RTP_NAME("14025676848"),
> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
> + FUNC(xe_rtp_match_first_render_or_compute)),
> + XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE))
> + },
> + { XE_RTP_NAME("16028951944"),
> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
> + FUNC(xe_rtp_match_first_render_or_compute)),
> + XE_RTP_ACTIONS(SET(ROW_CHICKEN5, CPSS_AWARE_DIS))
> + },
> };
>
> static const struct xe_rtp_entry_sr lrc_was[] = {
>
> --
> 2.52.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 01/15] drm/xe/xe3p_lpg: Add support for graphics IP 35.10
2026-02-05 23:39 ` [PATCH v2 01/15] drm/xe/xe3p_lpg: Add support for graphics IP 35.10 Gustavo Sousa
@ 2026-02-06 15:26 ` Matt Roper
0 siblings, 0 replies; 23+ messages in thread
From: Matt Roper @ 2026-02-06 15:26 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-xe, intel-gfx, Shekhar Chauhan
On Thu, Feb 05, 2026 at 08:39:29PM -0300, Gustavo Sousa wrote:
> From: Shekhar Chauhan <shekhar.chauhan@intel.com>
>
> Add Xe3p_LPG graphics IP version 35.10. Xe3p_LPG supports all features
> described by XE2_GFX_FEATURES and also multi-queue feature on BCS and
> CCS engines. As such, create a new struct xe_graphics_desc named
> graphics_xe3p_lpg that inherits from XE2_GFX_FEATURES and also includes
> the necessary .multi_queue_engine_class_mask.
>
> Here is a list of fields and associated Bspec references for the members
> of the IP descriptor:
>
> .hw_engine_mask (Bspec 60149)
> .multi_queue_engine_class_mask (Bspec 74110)
> .has_asid (Bspec 71132)
> .has_atomic_enable_pte_bit (Bspec 59510, 74675)
> .has_indirect_ring_state (Bspec 67296)
> .has_range_tlb_inval (Bspec 71126)
> .has_usm (Bspec 59651)
> .has_64bit_timestamp (Bspec 60318)
>
> v2:
> - Drop non-existing fields from the list in the commit message. (Matt)
> - Squash patch adding .multi_queue_engine_class_mask here. (Matt)
> - Rename graphics_xe3p to graphics_xe3p_lpg. (Matt)
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_pci.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index b5e8935fff1d..08e0ff9f75e8 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -106,6 +106,11 @@ static const struct xe_graphics_desc graphics_xe2 = {
> XE2_GFX_FEATURES,
> };
>
> +static const struct xe_graphics_desc graphics_xe3p_lpg = {
> + XE2_GFX_FEATURES,
> + .multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | BIT(XE_ENGINE_CLASS_COMPUTE),
> +};
> +
> static const struct xe_graphics_desc graphics_xe3p_xpc = {
> XE2_GFX_FEATURES,
> .has_indirect_ring_state = 1,
> @@ -148,6 +153,7 @@ static const struct xe_ip graphics_ips[] = {
> { 3003, "Xe3_LPG", &graphics_xe2 },
> { 3004, "Xe3_LPG", &graphics_xe2 },
> { 3005, "Xe3_LPG", &graphics_xe2 },
> + { 3510, "Xe3p_LPG", &graphics_xe3p_lpg },
> { 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
> };
>
>
> --
> 2.52.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2026-02-06 15:26 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 01/15] drm/xe/xe3p_lpg: Add support for graphics IP 35.10 Gustavo Sousa
2026-02-06 15:26 ` Matt Roper
2026-02-05 23:39 ` [PATCH v2 02/15] drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10 Gustavo Sousa
2026-02-06 15:25 ` Matt Roper
2026-02-05 23:39 ` [PATCH v2 03/15] drm/xe/pat: Differentiate between primary and media for PTA Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 04/15] drm/xe/xe3p_lpg: Add new PAT table Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 05/15] drm/xe/xe3p_lpg: Add MCR steering Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 06/15] drm/xe/xe3p_lpg: Add LRC parsing for additional RCS engine state Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 07/15] drm/xe/xe3p_lpg: Disable reporting of context switch status to GHWSP Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 08/15] drm/xe/xe3p_lpg: Drop unnecessary tuning settings Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 09/15] drm/xe/xe3p_lpg: Extend 'group ID' mask size Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 10/15] drm/xe/xe3p_lpg: Update LRC sizes Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 11/15] drm/xe/xe3p_lpg: Set STLB bank hash mode to 4KB Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 12/15] drm/xe/nvlp: Add NVL-P platform definition Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 13/15] drm/xe/nvlp: Attach MOCS table for nvlp Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 14/15] drm/i915/nvlp: Hook up display support Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 15/15] drm/xe/nvlp: Bump maximum WOPCM size Gustavo Sousa
2026-02-06 8:39 ` Bhadane, Dnyaneshwar
2026-02-05 23:47 ` ✗ CI.checkpatch: warning for Basic enabling patches for Xe3p_LPG and NVL-P (rev2) Patchwork
2026-02-05 23:48 ` ✓ CI.KUnit: success " Patchwork
2026-02-06 0:04 ` ✗ CI.checksparse: warning " Patchwork
2026-02-06 0:47 ` ✓ Xe.CI.BAT: success " Patchwork
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox