[v2 00/19] Make Display free from i915_reg.h

[v2 00/19] Make Display free from i915_reg.h

[Uma Shankar]

Move the common register definition to a header to free up
display files from including i915_reg.h. This will help
avoid dupicate definitions and includes and can serve as
a common file for xe, i915 and display module.

v2:
- Moved display definitions needed for gvt and clock gating
  to display header (Jani)
- Fixed redundant includes

Uma Shankar (19):
  drm/{i915, xe}: Extract display registers from i915_reg.h to display
  drm/{i915, xe}: Extract South chicken registers from i915_reg.h to
    display
  drm/{i915, xe}: Extract display interrupt definitions
  drm/{i915, xe}: Extract DSPCLK_GATE_D from i915_reg to display
  drm/{i915, xe}: Extract pcode definitions to common header
  drm/{i915, xe}: Remove i915_reg.h from intel_display_device.c
  drm/{i915, xe}: Remove i915_reg.h from intel_dram.c
  drm/{i915, xe}: Removed i915_reg.h from intel_display.c
  drm/{i915, xe}: Remove i915_reg.h from intel_overlay.c
  drm/{i915, xe}: Remove i915_reg.h from g4x_dp.c
  drm/{i915, xe}: Remove i915_reg.h from i9xx_wm.c
  drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c
  drm/{i915, xe}: Remove i915_reg.h from intel_rom.c
  drm/{i915, xe}: Remove i915_reg.h from intel_psr.c
  drm/{i915, xe}: Remove i915_reg.h from intel_fifo_underrun.c
  drm/{i915, xe}: Remove i915_reg.h from intel_display_irq.c
  drm/{i915, xe}: Remove i915_reg.h from intel_display_power_well.c
  drm/{i915, xe}: Remove i915_reg.h from intel_modeset_setup.c
  drm/{i915, xe}: Remove i915_reg.h from display

 drivers/gpu/drm/i915/display/g4x_dp.c         |   2 +-
 drivers/gpu/drm/i915/display/g4x_hdmi.c       |   1 -
 drivers/gpu/drm/i915/display/hsw_ips.c        |   2 +-
 drivers/gpu/drm/i915/display/i9xx_plane.c     |   1 -
 drivers/gpu/drm/i915/display/i9xx_wm.c        |   2 +-
 drivers/gpu/drm/i915/display/icl_dsi.c        |   1 -
 .../gpu/drm/i915/display/intel_backlight.c    |   1 -
 drivers/gpu/drm/i915/display/intel_bw.c       |   2 +-
 drivers/gpu/drm/i915/display/intel_casf.c     |   1 -
 drivers/gpu/drm/i915/display/intel_cdclk.c    |   2 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |   2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |   1 -
 .../drm/i915/display/intel_display_debugfs.c  |   2 +-
 .../drm/i915/display/intel_display_device.c   |   2 +-
 .../gpu/drm/i915/display/intel_display_irq.c  |   2 +-
 .../drm/i915/display/intel_display_power.c    |   2 +-
 .../i915/display/intel_display_power_well.c   |   2 +-
 .../gpu/drm/i915/display/intel_display_regs.h | 257 +++++++++-
 .../gpu/drm/i915/display/intel_display_rps.c  |   2 +-
 .../gpu/drm/i915/display/intel_display_wa.c   |   1 -
 drivers/gpu/drm/i915/display/intel_dmc.c      |   1 -
 drivers/gpu/drm/i915/display/intel_dram.c     |   3 +-
 drivers/gpu/drm/i915/display/intel_fdi.c      |   1 -
 .../drm/i915/display/intel_fifo_underrun.c    |   2 +-
 drivers/gpu/drm/i915/display/intel_gmbus.c    |   1 -
 drivers/gpu/drm/i915/display/intel_hdcp.c     |   2 +-
 .../gpu/drm/i915/display/intel_hotplug_irq.c  |   1 -
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |   1 -
 .../drm/i915/display/intel_modeset_setup.c    |   1 -
 drivers/gpu/drm/i915/display/intel_overlay.c  |   2 +-
 .../gpu/drm/i915/display/intel_pch_display.c  |   1 -
 .../gpu/drm/i915/display/intel_pch_refclk.c   |   1 -
 drivers/gpu/drm/i915/display/intel_pps.c      |   1 -
 drivers/gpu/drm/i915/display/intel_psr.c      |   1 -
 drivers/gpu/drm/i915/display/intel_rom.c      |   3 +-
 drivers/gpu/drm/i915/display/intel_tc.c       |   2 +-
 drivers/gpu/drm/i915/display/skl_watermark.c  |   2 +-
 drivers/gpu/drm/i915/display/vlv_dsi.c        |   1 -
 drivers/gpu/drm/i915/i915_reg.h               | 465 +-----------------
 drivers/gpu/drm/i915/intel_clock_gating.c     |   2 +-
 include/drm/intel/intel_gmd_common_regs.h     | 249 ++++++++++
 41 files changed, 514 insertions(+), 517 deletions(-)
 create mode 100644 include/drm/intel/intel_gmd_common_regs.h

-- 
2.50.1

[v2 01/19] drm/{i915, xe}: Extract display registers from i915_reg.h to display

[Uma Shankar]

There are certain register definitions which are defined in i915_reg.h
which are exclusively needed by display. Move the same to display
headers to remove i915_reg.h includes from display. This is a step
towards making display independent of i915.

intel_clock_gating.c can include display header directly.

v2: Drop common header in include and use display_regs.h (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_regs.h | 10 ++++++++++
 drivers/gpu/drm/i915/display/intel_pch_display.c  |  1 -
 drivers/gpu/drm/i915/i915_reg.h                   | 10 ----------
 drivers/gpu/drm/i915/intel_clock_gating.c         |  2 +-
 4 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9e0d853f4b61..9f8fbfb2e115 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2021,6 +2021,16 @@
 #define  TRANS_BPC_6			REG_FIELD_PREP(TRANS_BPC_MASK, 2)
 #define  TRANS_BPC_12			REG_FIELD_PREP(TRANS_BPC_MASK, 3)
 
+#define _TRANSA_CHICKEN2	0xf0064
+#define _TRANSB_CHICKEN2	0xf1064
+#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
+#define   TRANS_CHICKEN2_TIMING_OVERRIDE		REG_BIT(31)
+#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED		REG_BIT(29)
+#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK		REG_GENMASK(28, 27)
+#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
+#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	REG_BIT(26)
+#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	REG_BIT(25)
+
 #define PCH_DP_B		_MMIO(0xe4100)
 #define PCH_DP_C		_MMIO(0xe4200)
 #define PCH_DP_D		_MMIO(0xe4300)
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 16619f7be5f8..69c7952a1413 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -6,7 +6,6 @@
 #include <drm/drm_print.h>
 
 #include "g4x_dp.h"
-#include "i915_reg.h"
 #include "intel_crt.h"
 #include "intel_crt_regs.h"
 #include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5bf3b4ab2baa..d247e107f42f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1022,16 +1022,6 @@
 #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
 #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
 
-#define _TRANSA_CHICKEN2	 0xf0064
-#define _TRANSB_CHICKEN2	 0xf1064
-#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
-#define   TRANS_CHICKEN2_TIMING_OVERRIDE		REG_BIT(31)
-#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED		REG_BIT(29)
-#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK		REG_GENMASK(28, 27)
-#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
-#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	REG_BIT(26)
-#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	REG_BIT(25)
-
 #define SOUTH_CHICKEN1		_MMIO(0xc2000)
 #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
 #define  FDIA_PHASE_SYNC_SHIFT_EN	18
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 7336934bb934..4e18d5a22112 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -30,7 +30,7 @@
 #include "display/i9xx_plane_regs.h"
 #include "display/intel_display.h"
 #include "display/intel_display_core.h"
-
+#include "display/intel_display_regs.h"
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_mcr.h"
-- 
2.50.1

[v2 02/19] drm/{i915, xe}: Extract South chicken registers from i915_reg.h to display

[Uma Shankar]

Extract South Chicken registers from i915_reg.h to display header.
This allows intel_pch_refclk.c not to include i915_reg.h

v2: Drop common header in include and use display_regs.h (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../gpu/drm/i915/display/intel_display_regs.h | 28 +++++++++++++++++++
 .../gpu/drm/i915/display/intel_pch_refclk.c   |  1 -
 drivers/gpu/drm/i915/i915_reg.h               | 27 ------------------
 3 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9f8fbfb2e115..4759a9600d3f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2864,6 +2864,34 @@ enum skl_power_gate {
 #define  SFUSE_STRAP_DDIC_DETECTED	(1 << 1)
 #define  SFUSE_STRAP_DDID_DETECTED	(1 << 0)
 
+#define SOUTH_CHICKEN1			_MMIO(0xc2000)
+#define  FDIA_PHASE_SYNC_SHIFT_OVR	19
+#define  FDIA_PHASE_SYNC_SHIFT_EN	18
+#define  INVERT_DDIE_HPD		REG_BIT(28)
+#define  INVERT_DDID_HPD_MTP		REG_BIT(27)
+#define  INVERT_TC4_HPD			REG_BIT(26)
+#define  INVERT_TC3_HPD			REG_BIT(25)
+#define  INVERT_TC2_HPD			REG_BIT(24)
+#define  INVERT_TC1_HPD			REG_BIT(23)
+#define  INVERT_DDID_HPD		(1 << 18)
+#define  INVERT_DDIC_HPD		(1 << 17)
+#define  INVERT_DDIB_HPD                (1 << 16)
+#define  INVERT_DDIA_HPD                (1 << 15)
+#define  FDI_PHASE_SYNC_OVR(pipe)	(1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
+#define  FDI_PHASE_SYNC_EN(pipe)	(1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
+#define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
+#define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
+#define  CHASSIS_CLK_REQ_DURATION(x)	((x) << 8)
+#define  SBCLK_RUN_REFCLK_DIS		(1 << 7)
+#define  ICP_SECOND_PPS_IO_SELECT	REG_BIT(2)
+#define  SPT_PWM_GRANULARITY		(1 << 0)
+
+#define SOUTH_CHICKEN2			_MMIO(0xc2004)
+#define  FDI_MPHY_IOSFSB_RESET_STATUS	(1 << 13)
+#define  FDI_MPHY_IOSFSB_RESET_CTL	(1 << 12)
+#define  LPT_PWM_GRANULARITY		(1 << 5)
+#define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
+
 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
 #define GEN4_TIMESTAMP		_MMIO(0x2358)
 #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 9a89bb6dcf65..5f88663ef5e8 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -5,7 +5,6 @@
 
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d247e107f42f..80ea0df40b1e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1022,33 +1022,6 @@
 #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
 #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
 
-#define SOUTH_CHICKEN1		_MMIO(0xc2000)
-#define  FDIA_PHASE_SYNC_SHIFT_OVR	19
-#define  FDIA_PHASE_SYNC_SHIFT_EN	18
-#define  INVERT_DDIE_HPD			REG_BIT(28)
-#define  INVERT_DDID_HPD_MTP			REG_BIT(27)
-#define  INVERT_TC4_HPD				REG_BIT(26)
-#define  INVERT_TC3_HPD				REG_BIT(25)
-#define  INVERT_TC2_HPD				REG_BIT(24)
-#define  INVERT_TC1_HPD				REG_BIT(23)
-#define  INVERT_DDID_HPD			(1 << 18)
-#define  INVERT_DDIC_HPD			(1 << 17)
-#define  INVERT_DDIB_HPD			(1 << 16)
-#define  INVERT_DDIA_HPD			(1 << 15)
-#define  FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
-#define  FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
-#define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
-#define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
-#define  CHASSIS_CLK_REQ_DURATION(x)	((x) << 8)
-#define  SBCLK_RUN_REFCLK_DIS		(1 << 7)
-#define  ICP_SECOND_PPS_IO_SELECT	REG_BIT(2)
-#define  SPT_PWM_GRANULARITY		(1 << 0)
-#define SOUTH_CHICKEN2		_MMIO(0xc2004)
-#define  FDI_MPHY_IOSFSB_RESET_STATUS	(1 << 13)
-#define  FDI_MPHY_IOSFSB_RESET_CTL	(1 << 12)
-#define  LPT_PWM_GRANULARITY		(1 << 5)
-#define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
-
 #define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
 #define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
 #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
-- 
2.50.1

[v2 03/19] drm/{i915, xe}: Extract display interrupt definitions

[Uma Shankar]

Move common registers to display to allow intel_display_rps.c
free of i915_reg.h dependency.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../gpu/drm/i915/display/intel_display_regs.h | 34 +++++++++++++++++++
 .../gpu/drm/i915/display/intel_display_rps.c  |  2 +-
 drivers/gpu/drm/i915/i915_reg.h               | 33 ------------------
 3 files changed, 35 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 4759a9600d3f..1f922d013cd3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1333,6 +1333,40 @@
 						      GEN8_DE_PORT_IER, \
 						      GEN8_DE_PORT_IIR)
 
+/* interrupts */
+#define DE_MASTER_IRQ_CONTROL   (1 << 31)
+#define DE_SPRITEB_FLIP_DONE    (1 << 29)
+#define DE_SPRITEA_FLIP_DONE    (1 << 28)
+#define DE_PLANEB_FLIP_DONE     (1 << 27)
+#define DE_PLANEA_FLIP_DONE     (1 << 26)
+#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
+#define DE_PCU_EVENT            (1 << 25)
+#define DE_GTT_FAULT            (1 << 24)
+#define DE_POISON               (1 << 23)
+#define DE_PERFORM_COUNTER      (1 << 22)
+#define DE_PCH_EVENT            (1 << 21)
+#define DE_AUX_CHANNEL_A        (1 << 20)
+#define DE_DP_A_HOTPLUG         (1 << 19)
+#define DE_GSE                  (1 << 18)
+#define DE_PIPEB_VBLANK         (1 << 15)
+#define DE_PIPEB_EVEN_FIELD     (1 << 14)
+#define DE_PIPEB_ODD_FIELD      (1 << 13)
+#define DE_PIPEB_LINE_COMPARE   (1 << 12)
+#define DE_PIPEB_VSYNC          (1 << 11)
+#define DE_PIPEB_CRC_DONE	(1 << 10)
+#define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
+#define DE_PIPEA_VBLANK         (1 << 7)
+#define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8 * (pipe)))
+#define DE_PIPEA_EVEN_FIELD     (1 << 6)
+#define DE_PIPEA_ODD_FIELD      (1 << 5)
+#define DE_PIPEA_LINE_COMPARE   (1 << 4)
+#define DE_PIPEA_VSYNC          (1 << 3)
+#define DE_PIPEA_CRC_DONE	(1 << 2)
+#define DE_PIPE_CRC_DONE(pipe)	(1 << (2 + 8 * (pipe)))
+#define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
+#define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8 * (pipe)))
+
+
 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
diff --git a/drivers/gpu/drm/i915/display/intel_display_rps.c b/drivers/gpu/drm/i915/display/intel_display_rps.c
index e77811396474..bf00266dae4b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_rps.c
+++ b/drivers/gpu/drm/i915/display/intel_display_rps.c
@@ -8,8 +8,8 @@
 #include <drm/drm_crtc.h>
 #include <drm/drm_vblank.h>
 
-#include "i915_reg.h"
 #include "intel_display_core.h"
+#include "intel_display_regs.h"
 #include "intel_display_irq.h"
 #include "intel_display_rps.h"
 #include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 80ea0df40b1e..5cd124083c17 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -804,39 +804,6 @@
 #define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
 #define  MMIO_TIMEOUT_US(us)	((us) << 0)
 
-/* interrupts */
-#define DE_MASTER_IRQ_CONTROL   (1 << 31)
-#define DE_SPRITEB_FLIP_DONE    (1 << 29)
-#define DE_SPRITEA_FLIP_DONE    (1 << 28)
-#define DE_PLANEB_FLIP_DONE     (1 << 27)
-#define DE_PLANEA_FLIP_DONE     (1 << 26)
-#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
-#define DE_PCU_EVENT            (1 << 25)
-#define DE_GTT_FAULT            (1 << 24)
-#define DE_POISON               (1 << 23)
-#define DE_PERFORM_COUNTER      (1 << 22)
-#define DE_PCH_EVENT            (1 << 21)
-#define DE_AUX_CHANNEL_A        (1 << 20)
-#define DE_DP_A_HOTPLUG         (1 << 19)
-#define DE_GSE                  (1 << 18)
-#define DE_PIPEB_VBLANK         (1 << 15)
-#define DE_PIPEB_EVEN_FIELD     (1 << 14)
-#define DE_PIPEB_ODD_FIELD      (1 << 13)
-#define DE_PIPEB_LINE_COMPARE   (1 << 12)
-#define DE_PIPEB_VSYNC          (1 << 11)
-#define DE_PIPEB_CRC_DONE	(1 << 10)
-#define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
-#define DE_PIPEA_VBLANK         (1 << 7)
-#define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8 * (pipe)))
-#define DE_PIPEA_EVEN_FIELD     (1 << 6)
-#define DE_PIPEA_ODD_FIELD      (1 << 5)
-#define DE_PIPEA_LINE_COMPARE   (1 << 4)
-#define DE_PIPEA_VSYNC          (1 << 3)
-#define DE_PIPEA_CRC_DONE	(1 << 2)
-#define DE_PIPE_CRC_DONE(pipe)	(1 << (2 + 8 * (pipe)))
-#define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
-#define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8 * (pipe)))
-
 #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
 #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
 
-- 
2.50.1

[v2 04/19] drm/{i915, xe}: Extract DSPCLK_GATE_D from i915_reg to display

[Uma Shankar]

Move DSPCLK_GATE_D register definition to display header.
This allows intel_gmbus.c free of i915_reg.h include.

v2: Drop common header in include and use display_regs.h (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../gpu/drm/i915/display/intel_display_regs.h | 50 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_gmbus.c    |  1 -
 drivers/gpu/drm/i915/i915_reg.h               | 50 -------------------
 3 files changed, 50 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 1f922d013cd3..5136b7166775 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -160,6 +160,47 @@
 
 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
 
+#define DSPCLK_GATE_D			_MMIO(0x6200)
+#define VLV_DSPCLK_GATE_D		_MMIO(VLV_DISPLAY_BASE + 0x6200)
+# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
+# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
+# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
+# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
+# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
+# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
+# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
+# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */
+# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
+# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
+# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
+# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
+# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
+# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
+# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
+# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
+# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
+# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
+# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
+# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
+# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
+# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
+# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
+# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
+# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
+# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
+# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
+# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
+# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
+/*
+ * This bit must be set on the 830 to prevent hangs when turning off the
+ * overlay scaler.
+ */
+# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
+# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
+# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
+# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
+# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
+
 /* Additional CHV pll/phy registers */
 #define DPIO_PHY_STATUS			_MMIO(VLV_DISPLAY_BASE + 0x6240)
 #define   DPLL_PORTD_READY_MASK		(0xf)
@@ -2926,6 +2967,15 @@ enum skl_power_gate {
 #define  LPT_PWM_GRANULARITY		(1 << 5)
 #define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
 
+#define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
+#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
+#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
+#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
+#define  PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
+#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
+#define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
+#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
+
 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
 #define GEN4_TIMESTAMP		_MMIO(0x2358)
 #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 2caff677600c..81b6c6991323 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -35,7 +35,6 @@
 #include <drm/drm_print.h>
 #include <drm/display/drm_hdcp_helper.h>
 
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5cd124083c17..dc13f9eb4cd7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -613,47 +613,6 @@
 #define  DSTATE_GFX_CLOCK_GATING		(1 << 1)
 #define  DSTATE_DOT_CLOCK_GATING		(1 << 0)
 
-#define DSPCLK_GATE_D			_MMIO(0x6200)
-#define VLV_DSPCLK_GATE_D		_MMIO(VLV_DISPLAY_BASE + 0x6200)
-# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
-# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
-# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
-# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
-# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
-# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
-# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
-# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */
-# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
-# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
-# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
-# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
-# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
-# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
-# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
-# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
-# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
-# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
-# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
-# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
-# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
-# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
-# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
-# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
-# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
-# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
-# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
-# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
-# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
-/*
- * This bit must be set on the 830 to prevent hangs when turning off the
- * overlay scaler.
- */
-# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
-# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
-# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
-# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
-# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
-
 #define RENCLK_GATE_D1		_MMIO(0x6204)
 # define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
 # define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
@@ -989,15 +948,6 @@
 #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
 #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
 
-#define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
-#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
-#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
-#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
-#define  PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
-#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
-#define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
-#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
-
 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
 
 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
-- 
2.50.1

[v2 05/19] drm/{i915, xe}: Extract pcode definitions to common header

[Uma Shankar]

There are certain register definitions which are commonly shared
by i915, xe and display. Extract the same to a common header to
avoid duplication.

Move GEN6_PCODE_MAILBOX to common header to make intel_cdclk.c
free from including i915_reg.h

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c |   2 +-
 drivers/gpu/drm/i915/i915_reg.h            | 101 +------------------
 include/drm/intel/intel_gmd_common_regs.h  | 108 +++++++++++++++++++++
 3 files changed, 110 insertions(+), 101 deletions(-)
 create mode 100644 include/drm/intel/intel_gmd_common_regs.h

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9bfbfbf34dc0..531db1b452d1 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -27,9 +27,9 @@
 
 #include <drm/drm_fixed.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include "hsw_ips.h"
-#include "i915_reg.h"
 #include "intel_atomic.h"
 #include "intel_audio.h"
 #include "intel_cdclk.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dc13f9eb4cd7..35122c997b8a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -25,6 +25,7 @@
 #ifndef _I915_REG_H_
 #define _I915_REG_H_
 
+#include <drm/intel/intel_gmd_common_regs.h>
 #include "i915_reg_defs.h"
 #include "display/intel_display_reg_defs.h"
 
@@ -956,106 +957,6 @@
 #define    EDRAM_WAYS_IDX(cap)			(((cap) >> 5) & 0x7)
 #define    EDRAM_SETS_IDX(cap)			(((cap) >> 8) & 0x3)
 
-#define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
-#define   GEN6_PCODE_READY			(1 << 31)
-#define   GEN6_PCODE_MB_PARAM2			REG_GENMASK(23, 16)
-#define   GEN6_PCODE_MB_PARAM1			REG_GENMASK(15, 8)
-#define   GEN6_PCODE_MB_COMMAND			REG_GENMASK(7, 0)
-#define   GEN6_PCODE_ERROR_MASK			0xFF
-#define     GEN6_PCODE_SUCCESS			0x0
-#define     GEN6_PCODE_ILLEGAL_CMD		0x1
-#define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
-#define     GEN6_PCODE_TIMEOUT			0x3
-#define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
-#define     GEN7_PCODE_TIMEOUT			0x2
-#define     GEN7_PCODE_ILLEGAL_DATA		0x3
-#define     GEN11_PCODE_ILLEGAL_SUBCOMMAND	0x4
-#define     GEN11_PCODE_LOCKED			0x6
-#define     GEN11_PCODE_REJECTED		0x11
-#define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
-#define   GEN6_PCODE_WRITE_RC6VIDS		0x4
-#define   GEN6_PCODE_READ_RC6VIDS		0x5
-#define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
-#define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
-#define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
-#define   GEN9_PCODE_READ_MEM_LATENCY		0x6
-#define     GEN9_MEM_LATENCY_LEVEL_3_7_MASK	REG_GENMASK(31, 24)
-#define     GEN9_MEM_LATENCY_LEVEL_2_6_MASK	REG_GENMASK(23, 16)
-#define     GEN9_MEM_LATENCY_LEVEL_1_5_MASK	REG_GENMASK(15, 8)
-#define     GEN9_MEM_LATENCY_LEVEL_0_4_MASK	REG_GENMASK(7, 0)
-#define   SKL_PCODE_LOAD_HDCP_KEYS		0x5
-#define   SKL_PCODE_CDCLK_CONTROL		0x7
-#define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
-#define     SKL_CDCLK_READY_FOR_CHANGE		0x1
-#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
-#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
-#define   GEN6_READ_OC_PARAMS			0xc
-#define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
-#define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
-#define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
-#define     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO	((0) | (0x2 << 8))
-#define   DISPLAY_TO_PCODE_CDCLK_MAX		0x28D
-#define   DISPLAY_TO_PCODE_VOLTAGE_MASK		REG_GENMASK(1, 0)
-#define	  DISPLAY_TO_PCODE_VOLTAGE_MAX		DISPLAY_TO_PCODE_VOLTAGE_MASK
-#define   DISPLAY_TO_PCODE_CDCLK_VALID		REG_BIT(27)
-#define   DISPLAY_TO_PCODE_PIPE_COUNT_VALID	REG_BIT(31)
-#define   DISPLAY_TO_PCODE_CDCLK_MASK		REG_GENMASK(25, 16)
-#define   DISPLAY_TO_PCODE_PIPE_COUNT_MASK	REG_GENMASK(30, 28)
-#define   DISPLAY_TO_PCODE_CDCLK(x)		REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
-#define   DISPLAY_TO_PCODE_PIPE_COUNT(x)	REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
-#define   DISPLAY_TO_PCODE_VOLTAGE(x)		REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
-#define   DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
-		((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
-		(DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
-		(DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
-#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
-#define     ICL_PCODE_REP_QGV_MASK		REG_GENMASK(1, 0)
-#define     ICL_PCODE_REP_QGV_SAFE		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
-#define     ICL_PCODE_REP_QGV_POLL		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
-#define     ICL_PCODE_REP_QGV_REJECTED		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
-#define     ADLS_PCODE_REP_PSF_MASK		REG_GENMASK(3, 2)
-#define     ADLS_PCODE_REP_PSF_SAFE		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
-#define     ADLS_PCODE_REP_PSF_POLL		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
-#define     ADLS_PCODE_REP_PSF_REJECTED		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
-#define     ICL_PCODE_REQ_QGV_PT_MASK		REG_GENMASK(7, 0)
-#define     ICL_PCODE_REQ_QGV_PT(x)		REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
-#define     ADLS_PCODE_REQ_PSF_PT_MASK		REG_GENMASK(10, 8)
-#define     ADLS_PCODE_REQ_PSF_PT(x)		REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
-#define   GEN6_PCODE_READ_D_COMP		0x10
-#define   GEN6_PCODE_WRITE_D_COMP		0x11
-#define   ICL_PCODE_EXIT_TCCOLD			0x12
-#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
-#define   DISPLAY_IPS_CONTROL			0x19
-#define   TGL_PCODE_TCCOLD			0x26
-#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED	REG_BIT(0)
-#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ	0
-#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ	REG_BIT(0)
-            /* See also IPS_CTL */
-#define     IPS_PCODE_CONTROL			(1 << 30)
-#define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
-#define   GEN9_PCODE_SAGV_CONTROL		0x21
-#define     GEN9_SAGV_DISABLE			0x0
-#define     GEN9_SAGV_IS_DISABLED		0x1
-#define     GEN9_SAGV_ENABLE			0x3
-#define   DG1_PCODE_STATUS			0x7E
-#define     DG1_UNCORE_GET_INIT_STATUS		0x0
-#define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
-#define   PCODE_POWER_SETUP			0x7C
-#define     POWER_SETUP_SUBCOMMAND_READ_I1	0x4
-#define     POWER_SETUP_SUBCOMMAND_WRITE_I1	0x5
-#define	    POWER_SETUP_I1_WATTS		REG_BIT(31)
-#define	    POWER_SETUP_I1_SHIFT		6	/* 10.6 fixed point format */
-#define	    POWER_SETUP_I1_DATA_MASK		REG_GENMASK(15, 0)
-#define     POWER_SETUP_SUBCOMMAND_G8_ENABLE	0x6
-#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
-#define   XEHP_PCODE_FREQUENCY_CONFIG		0x6e	/* pvc */
-/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
-#define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
-#define     PCODE_MBOX_FC_SC_READ_FUSED_PN	0x1
-/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
-/*   XEHP_PCODE_FREQUENCY_CONFIG param2 */
-#define     PCODE_MBOX_DOMAIN_NONE		0x0
-#define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
 #define GEN6_PCODE_DATA				_MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
new file mode 100644
index 000000000000..8e9a574c87d9
--- /dev/null
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2026 Intel Corporation */
+
+#ifndef _INTEL_GMD_COMMON_REG_H_
+#define _INTEL_GMD_COMMON_REG_H_
+
+#define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
+#define   GEN6_PCODE_READY			(1 << 31)
+#define   GEN6_PCODE_MB_PARAM2			REG_GENMASK(23, 16)
+#define   GEN6_PCODE_MB_PARAM1			REG_GENMASK(15, 8)
+#define   GEN6_PCODE_MB_COMMAND			REG_GENMASK(7, 0)
+#define   GEN6_PCODE_ERROR_MASK			0xFF
+#define     GEN6_PCODE_SUCCESS			0x0
+#define     GEN6_PCODE_ILLEGAL_CMD		0x1
+#define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
+#define     GEN6_PCODE_TIMEOUT			0x3
+#define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
+#define     GEN7_PCODE_TIMEOUT			0x2
+#define     GEN7_PCODE_ILLEGAL_DATA		0x3
+#define     GEN11_PCODE_ILLEGAL_SUBCOMMAND	0x4
+#define     GEN11_PCODE_LOCKED			0x6
+#define     GEN11_PCODE_REJECTED		0x11
+#define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
+#define   GEN6_PCODE_WRITE_RC6VIDS		0x4
+#define   GEN6_PCODE_READ_RC6VIDS		0x5
+#define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
+#define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
+#define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
+#define   GEN9_PCODE_READ_MEM_LATENCY		0x6
+#define     GEN9_MEM_LATENCY_LEVEL_3_7_MASK	REG_GENMASK(31, 24)
+#define     GEN9_MEM_LATENCY_LEVEL_2_6_MASK	REG_GENMASK(23, 16)
+#define     GEN9_MEM_LATENCY_LEVEL_1_5_MASK	REG_GENMASK(15, 8)
+#define     GEN9_MEM_LATENCY_LEVEL_0_4_MASK	REG_GENMASK(7, 0)
+#define   SKL_PCODE_LOAD_HDCP_KEYS		0x5
+#define   SKL_PCODE_CDCLK_CONTROL		0x7
+#define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
+#define     SKL_CDCLK_READY_FOR_CHANGE		0x1
+#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
+#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
+#define   GEN6_READ_OC_PARAMS			0xc
+#define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
+#define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
+#define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
+#define     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO	((0) | (0x2 << 8))
+#define   DISPLAY_TO_PCODE_CDCLK_MAX		0x28D
+#define   DISPLAY_TO_PCODE_VOLTAGE_MASK		REG_GENMASK(1, 0)
+#define	  DISPLAY_TO_PCODE_VOLTAGE_MAX		DISPLAY_TO_PCODE_VOLTAGE_MASK
+#define   DISPLAY_TO_PCODE_CDCLK_VALID		REG_BIT(27)
+#define   DISPLAY_TO_PCODE_PIPE_COUNT_VALID	REG_BIT(31)
+#define   DISPLAY_TO_PCODE_CDCLK_MASK		REG_GENMASK(25, 16)
+#define   DISPLAY_TO_PCODE_PIPE_COUNT_MASK	REG_GENMASK(30, 28)
+#define   DISPLAY_TO_PCODE_CDCLK(x)		REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
+#define   DISPLAY_TO_PCODE_PIPE_COUNT(x)	REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
+#define   DISPLAY_TO_PCODE_VOLTAGE(x)		REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
+#define   DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
+		((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
+		(DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
+		(DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
+#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
+#define     ICL_PCODE_REP_QGV_MASK		REG_GENMASK(1, 0)
+#define     ICL_PCODE_REP_QGV_SAFE		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
+#define     ICL_PCODE_REP_QGV_POLL		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
+#define     ICL_PCODE_REP_QGV_REJECTED		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
+#define     ADLS_PCODE_REP_PSF_MASK		REG_GENMASK(3, 2)
+#define     ADLS_PCODE_REP_PSF_SAFE		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
+#define     ADLS_PCODE_REP_PSF_POLL		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
+#define     ADLS_PCODE_REP_PSF_REJECTED		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
+#define     ICL_PCODE_REQ_QGV_PT_MASK		REG_GENMASK(7, 0)
+#define     ICL_PCODE_REQ_QGV_PT(x)		REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
+#define     ADLS_PCODE_REQ_PSF_PT_MASK		REG_GENMASK(10, 8)
+#define     ADLS_PCODE_REQ_PSF_PT(x)		REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
+#define   GEN6_PCODE_READ_D_COMP		0x10
+#define   GEN6_PCODE_WRITE_D_COMP		0x11
+#define   ICL_PCODE_EXIT_TCCOLD			0x12
+#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
+#define   DISPLAY_IPS_CONTROL			0x19
+#define   TGL_PCODE_TCCOLD			0x26
+#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED	REG_BIT(0)
+#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ	0
+#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ	REG_BIT(0)
+/* See also IPS_CTL */
+#define     IPS_PCODE_CONTROL			(1 << 30)
+#define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
+#define   GEN9_PCODE_SAGV_CONTROL		0x21
+#define     GEN9_SAGV_DISABLE			0x0
+#define     GEN9_SAGV_IS_DISABLED		0x1
+#define     GEN9_SAGV_ENABLE			0x3
+#define   DG1_PCODE_STATUS			0x7E
+#define     DG1_UNCORE_GET_INIT_STATUS		0x0
+#define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
+#define   PCODE_POWER_SETUP			0x7C
+#define     POWER_SETUP_SUBCOMMAND_READ_I1	0x4
+#define     POWER_SETUP_SUBCOMMAND_WRITE_I1	0x5
+#define	    POWER_SETUP_I1_WATTS		REG_BIT(31)
+#define	    POWER_SETUP_I1_SHIFT		6	/* 10.6 fixed point format */
+#define	    POWER_SETUP_I1_DATA_MASK		REG_GENMASK(15, 0)
+#define     POWER_SETUP_SUBCOMMAND_G8_ENABLE	0x6
+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
+#define   XEHP_PCODE_FREQUENCY_CONFIG		0x6e	/* pvc */
+/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
+#define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
+#define     PCODE_MBOX_FC_SC_READ_FUSED_PN	0x1
+/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
+/*   XEHP_PCODE_FREQUENCY_CONFIG param2 */
+#define     PCODE_MBOX_DOMAIN_NONE		0x0
+#define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
+
+#endif
-- 
2.50.1

[v2 06/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_device.c

[Uma Shankar]

Move GU_CNTL_PROTECTED to common header, this helps
intel_display_device.c free from i915_reg.h dependency.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
 drivers/gpu/drm/i915/display/intel_display_regs.h   | 3 +++
 drivers/gpu/drm/i915/i915_reg.h                     | 8 --------
 include/drm/intel/intel_gmd_common_regs.h           | 5 +++++
 4 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 471f236c9ddf..f7cc4198a870 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -9,8 +9,8 @@
 #include <drm/drm_drv.h>
 #include <drm/drm_print.h>
 #include <drm/intel/pciids.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_de.h"
 #include "intel_display.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 5136b7166775..3447ee229354 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -6,6 +6,9 @@
 
 #include "intel_display_reg_defs.h"
 
+#define GU_CNTL_PROTECTED		_MMIO(0x10100C)
+#define   DEPRESENT			REG_BIT(9)
+
 #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
 #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 35122c997b8a..fac24a649d61 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -117,9 +117,6 @@
  *  #define GEN8_BAR                    _MMIO(0xb888)
  */
 
-#define GU_CNTL_PROTECTED		_MMIO(0x10100C)
-#define   DEPRESENT			REG_BIT(9)
-
 #define GU_CNTL				_MMIO(0x101010)
 #define   LMEM_INIT			REG_BIT(7)
 #define   DRIVERFLR			REG_BIT(31)
@@ -925,11 +922,6 @@
 #define   MASK_WAKEMEM				REG_BIT(13)
 #define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
 
-#define GMD_ID_DISPLAY				_MMIO(0x510a0)
-#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
-#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
-#define   GMD_ID_STEP				REG_GENMASK(5, 0)
-
 /* PCH */
 
 #define SDEISR  _MMIO(0xc4000)
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index 8e9a574c87d9..489d59379ab0 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -105,4 +105,9 @@
 #define     PCODE_MBOX_DOMAIN_NONE		0x0
 #define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
 
+#define GMD_ID_DISPLAY				_MMIO(0x510a0)
+#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
+#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
+#define   GMD_ID_STEP				REG_GENMASK(5, 0)
+
 #endif
-- 
2.50.1

[v2 07/19] drm/{i915, xe}: Remove i915_reg.h from intel_dram.c

[Uma Shankar]

Make intel_dram.c free from including i915_reg.h.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_regs.h | 6 +++++-
 drivers/gpu/drm/i915/display/intel_dram.c         | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h                   | 6 ------
 3 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 3447ee229354..f395b7d4d640 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -3075,6 +3075,10 @@ enum skl_power_gate {
 #define   MTL_TRAS_MASK			REG_GENMASK(16, 8)
 #define   MTL_TRDPRE_MASK		REG_GENMASK(7, 0)
 
-
+#define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
+#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
+#define   MTL_N_OF_ENABLED_QGV_POINTS_MASK	REG_GENMASK(11, 8)
+#define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
+#define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
 
 #endif /* __INTEL_DISPLAY_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c
index 170de304fe96..73a127dd6720 100644
--- a/drivers/gpu/drm/i915/display/intel_dram.c
+++ b/drivers/gpu/drm/i915/display/intel_dram.c
@@ -7,10 +7,11 @@
 
 #include <drm/drm_managed.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_display_core.h"
 #include "intel_display_utils.h"
+#include "intel_display_regs.h"
 #include "intel_dram.h"
 #include "intel_mchbar_regs.h"
 #include "intel_pcode.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fac24a649d61..c9fb9af1a35c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1005,12 +1005,6 @@
 #define OROM_OFFSET				_MMIO(0x1020c0)
 #define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
 
-#define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
-#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
-#define   MTL_N_OF_ENABLED_QGV_POINTS_MASK	REG_GENMASK(11, 8)
-#define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
-#define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
-
 #define MTL_MEDIA_GSI_BASE		0x380000
 
 #endif /* _I915_REG_H_ */
-- 
2.50.1

[v2 08/19] drm/{i915, xe}: Removed i915_reg.h from intel_display.c

[Uma Shankar]

Move CHICKEN_PIPESL_1 register definition to display header.
This allows intel_display.c free of i915_reg.h include.

v2: Drop common header in include and use display_regs.h (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |  1 -
 .../gpu/drm/i915/display/intel_display_regs.h | 23 +++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h               | 22 ------------------
 3 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7491e00e3858..b7d4ac7e5ff9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -50,7 +50,6 @@
 #include "g4x_hdmi.h"
 #include "hsw_ips.h"
 #include "i915_config.h"
-#include "i915_reg.h"
 #include "i9xx_plane.h"
 #include "i9xx_plane_regs.h"
 #include "i9xx_wm.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index f395b7d4d640..b26e6a4ee1c3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1544,6 +1544,29 @@
 #define   CHICKEN_FBC_STRIDE_MASK	REG_GENMASK(12, 0)
 #define   CHICKEN_FBC_STRIDE(x)		REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
 
+#define _CHICKEN_PIPESL_1_A	0x420b0
+#define _CHICKEN_PIPESL_1_B	0x420b4
+#define CHICKEN_PIPESL_1(pipe)	_MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+#define   HSW_PRI_STRETCH_MAX_MASK	REG_GENMASK(28, 27)
+#define   HSW_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
+#define   HSW_PRI_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
+#define   HSW_PRI_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
+#define   HSW_PRI_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
+#define   HSW_SPR_STRETCH_MAX_MASK	REG_GENMASK(26, 25)
+#define   HSW_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
+#define   HSW_SPR_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
+#define   HSW_SPR_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
+#define   HSW_SPR_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
+#define   HSW_FBCQ_DIS			REG_BIT(22)
+#define   HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
+#define   SKL_PSR_MASK_PLANE_FLIP	REG_BIT(11) /* skl+ */
+#define   SKL_PLANE1_STRETCH_MAX_MASK	REG_GENMASK(1, 0)
+#define   SKL_PLANE1_STRETCH_MAX_X8	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
+#define   SKL_PLANE1_STRETCH_MAX_X4	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
+#define   SKL_PLANE1_STRETCH_MAX_X2	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
+#define   SKL_PLANE1_STRETCH_MAX_X1	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
+#define   BDW_UNMASK_VBL_TO_REGS_IN_SRD	REG_BIT(0) /* bdw */
+
 #define _CHICKEN_TRANS_A	0x420c0
 #define _CHICKEN_TRANS_B	0x420c4
 #define _CHICKEN_TRANS_C	0x420c8
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c9fb9af1a35c..c1d141e9ca47 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -878,28 +878,6 @@
 #define CHICKEN_PAR2_1		_MMIO(0x42090)
 #define   KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	REG_BIT(14)
 
-#define _CHICKEN_PIPESL_1_A	0x420b0
-#define _CHICKEN_PIPESL_1_B	0x420b4
-#define CHICKEN_PIPESL_1(pipe)	_MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
-#define   HSW_PRI_STRETCH_MAX_MASK	REG_GENMASK(28, 27)
-#define   HSW_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
-#define   HSW_PRI_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
-#define   HSW_PRI_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
-#define   HSW_PRI_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
-#define   HSW_SPR_STRETCH_MAX_MASK	REG_GENMASK(26, 25)
-#define   HSW_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
-#define   HSW_SPR_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
-#define   HSW_SPR_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
-#define   HSW_SPR_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
-#define   HSW_FBCQ_DIS			REG_BIT(22)
-#define   HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
-#define   SKL_PSR_MASK_PLANE_FLIP	REG_BIT(11) /* skl+ */
-#define   SKL_PLANE1_STRETCH_MAX_MASK	REG_GENMASK(1, 0)
-#define   SKL_PLANE1_STRETCH_MAX_X8	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
-#define   SKL_PLANE1_STRETCH_MAX_X4	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
-#define   SKL_PLANE1_STRETCH_MAX_X2	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
-#define   SKL_PLANE1_STRETCH_MAX_X1	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
-#define   BDW_UNMASK_VBL_TO_REGS_IN_SRD	REG_BIT(0) /* bdw */
 
 #define DISP_ARB_CTL	_MMIO(0x45000)
 #define   DISP_FBC_MEMORY_WAKE		REG_BIT(31)
-- 
2.50.1

[v2 09/19] drm/{i915, xe}: Remove i915_reg.h from intel_overlay.c

[Uma Shankar]

Move GEN2_ISR and some interrupt definitions to common header.
This removes dependency of i915_reg.h from intel_overlay.c.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_overlay.c |  2 +-
 drivers/gpu/drm/i915/i915_reg.h              | 36 -------------------
 include/drm/intel/intel_gmd_common_regs.h    | 38 ++++++++++++++++++++
 3 files changed, 39 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 88eb7ae5765c..62026f7f71d3 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -28,6 +28,7 @@
 
 #include <drm/drm_fourcc.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include "gem/i915_gem_internal.h"
 #include "gem/i915_gem_object_frontbuffer.h"
@@ -37,7 +38,6 @@
 #include "gt/intel_ring.h"
 
 #include "i915_drv.h"
-#include "i915_reg.h"
 #include "intel_color_regs.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1d141e9ca47..504ba9b2fb5b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -522,42 +522,6 @@
 /* These are all the "old" interrupts */
 #define ILK_BSD_USER_INTERRUPT				(1 << 5)
 
-#define I915_PM_INTERRUPT				(1 << 31)
-#define I915_ISP_INTERRUPT				(1 << 22)
-#define I915_LPE_PIPE_B_INTERRUPT			(1 << 21)
-#define I915_LPE_PIPE_A_INTERRUPT			(1 << 20)
-#define I915_MIPIC_INTERRUPT				(1 << 19)
-#define I915_MIPIA_INTERRUPT				(1 << 18)
-#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1 << 18)
-#define I915_DISPLAY_PORT_INTERRUPT			(1 << 17)
-#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1 << 16)
-#define I915_MASTER_ERROR_INTERRUPT			(1 << 15)
-#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1 << 14)
-#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1 << 14) /* p-state */
-#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1 << 13)
-#define I915_HWB_OOM_INTERRUPT				(1 << 13)
-#define I915_LPE_PIPE_C_INTERRUPT			(1 << 12)
-#define I915_SYNC_STATUS_INTERRUPT			(1 << 12)
-#define I915_MISC_INTERRUPT				(1 << 11)
-#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1 << 11)
-#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1 << 10)
-#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1 << 10)
-#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1 << 9)
-#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1 << 9)
-#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1 << 8)
-#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1 << 8)
-#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1 << 7)
-#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1 << 6)
-#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1 << 5)
-#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1 << 4)
-#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1 << 3)
-#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1 << 2)
-#define I915_DEBUG_INTERRUPT				(1 << 2)
-#define I915_WINVALID_INTERRUPT				(1 << 1)
-#define I915_USER_INTERRUPT				(1 << 1)
-#define I915_ASLE_INTERRUPT				(1 << 0)
-#define I915_BSD_USER_INTERRUPT				(1 << 25)
-
 #define GEN6_BSD_RNCID			_MMIO(0x12198)
 
 #define GEN7_FF_THREAD_MODE		_MMIO(0x20a0)
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index 489d59379ab0..2214cee38cf7 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -110,4 +110,42 @@
 #define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
 #define   GMD_ID_STEP				REG_GENMASK(5, 0)
 
+#define GEN2_ISR       _MMIO(0x20ac)
+
+#define I915_PM_INTERRUPT				(1 << 31)
+#define I915_ISP_INTERRUPT				(1 << 22)
+#define I915_LPE_PIPE_B_INTERRUPT			(1 << 21)
+#define I915_LPE_PIPE_A_INTERRUPT			(1 << 20)
+#define I915_MIPIC_INTERRUPT				(1 << 19)
+#define I915_MIPIA_INTERRUPT				(1 << 18)
+#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1 << 18)
+#define I915_DISPLAY_PORT_INTERRUPT			(1 << 17)
+#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1 << 16)
+#define I915_MASTER_ERROR_INTERRUPT			(1 << 15)
+#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1 << 14)
+#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1 << 14) /* p-state */
+#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1 << 13)
+#define I915_HWB_OOM_INTERRUPT				(1 << 13)
+#define I915_LPE_PIPE_C_INTERRUPT			(1 << 12)
+#define I915_SYNC_STATUS_INTERRUPT			(1 << 12)
+#define I915_MISC_INTERRUPT				(1 << 11)
+#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1 << 11)
+#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1 << 10)
+#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1 << 10)
+#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1 << 9)
+#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1 << 9)
+#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1 << 8)
+#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1 << 8)
+#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1 << 7)
+#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1 << 6)
+#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1 << 5)
+#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1 << 4)
+#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1 << 3)
+#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1 << 2)
+#define I915_DEBUG_INTERRUPT				(1 << 2)
+#define I915_WINVALID_INTERRUPT				(1 << 1)
+#define I915_USER_INTERRUPT				(1 << 1)
+#define I915_ASLE_INTERRUPT				(1 << 0)
+#define I915_BSD_USER_INTERRUPT				(1 << 25)
+
 #endif
-- 
2.50.1

[v2 10/19] drm/{i915, xe}: Remove i915_reg.h from g4x_dp.c

[Uma Shankar]

Move DE_IRQ_REGS to common header to make g4x_dp.c
free from i915_reg.h dependency.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c            |  2 +-
 .../gpu/drm/i915/display/intel_display_regs.h    |  9 +++++++++
 drivers/gpu/drm/i915/i915_reg.h                  | 16 ----------------
 include/drm/intel/intel_gmd_common_regs.h        |  7 +++++++
 4 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 4cb753177fd8..b2b63e811776 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -8,9 +8,9 @@
 #include <linux/string_helpers.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include "g4x_dp.h"
-#include "i915_reg.h"
 #include "intel_audio.h"
 #include "intel_backlight.h"
 #include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index b26e6a4ee1c3..eabee5abc23b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -3104,4 +3104,13 @@ enum skl_power_gate {
 #define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
 #define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
 
+#define DEISR   _MMIO(0x44000)
+#define DEIMR   _MMIO(0x44004)
+#define DEIIR   _MMIO(0x44008)
+#define DEIER   _MMIO(0x4400c)
+
+#define DE_IRQ_REGS		I915_IRQ_REGS(DEIMR, \
+					      DEIER, \
+					      DEIIR)
+
 #endif /* __INTEL_DISPLAY_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 504ba9b2fb5b..c0c2fab99a47 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -728,15 +728,6 @@
 #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
 #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
 
-#define DEISR   _MMIO(0x44000)
-#define DEIMR   _MMIO(0x44004)
-#define DEIIR   _MMIO(0x44008)
-#define DEIER   _MMIO(0x4400c)
-
-#define DE_IRQ_REGS		I915_IRQ_REGS(DEIMR, \
-					      DEIER, \
-					      DEIIR)
-
 #define GTISR   _MMIO(0x44010)
 #define GTIMR   _MMIO(0x44014)
 #define GTIIR   _MMIO(0x44018)
@@ -864,13 +855,6 @@
 #define   MASK_WAKEMEM				REG_BIT(13)
 #define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
 
-/* PCH */
-
-#define SDEISR  _MMIO(0xc4000)
-#define SDEIMR  _MMIO(0xc4004)
-#define SDEIIR  _MMIO(0xc4008)
-#define SDEIER  _MMIO(0xc400c)
-
 /* Icelake PPS_DATA and _ECC DIP Registers.
  * These are available for transcoders B,C and eDP.
  * Adding the _A so as to reuse the _MMIO_TRANS2
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index 2214cee38cf7..c8b2b5b2739c 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -148,4 +148,11 @@
 #define I915_ASLE_INTERRUPT				(1 << 0)
 #define I915_BSD_USER_INTERRUPT				(1 << 25)
 
+/* PCH */
+
+#define SDEISR  _MMIO(0xc4000)
+#define SDEIMR  _MMIO(0xc4004)
+#define SDEIIR  _MMIO(0xc4008)
+#define SDEIER  _MMIO(0xc400c)
+
 #endif
-- 
2.50.1

[v2 11/19] drm/{i915, xe}: Remove i915_reg.h from i9xx_wm.c

[Uma Shankar]

Move FW_BLC_SELF to common header to make i9xx_wm.c
free from i915_reg.h include.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_wm.c        |  2 +-
 .../gpu/drm/i915/display/intel_display_regs.h |  7 +++++++
 drivers/gpu/drm/i915/i915_reg.h               | 19 -------------------
 include/drm/intel/intel_gmd_common_regs.h     | 14 ++++++++++++++
 4 files changed, 22 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 39dfceb438ae..fb579490d317 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -6,8 +6,8 @@
 #include <linux/iopoll.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "i9xx_wm.h"
 #include "i9xx_wm_regs.h"
 #include "intel_atomic.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index eabee5abc23b..477896faa79e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -3113,4 +3113,11 @@ enum skl_power_gate {
 					      DEIER, \
 					      DEIIR)
 
+#define FW_BLC		_MMIO(0x20d8)
+#define FW_BLC2		_MMIO(0x20dc)
+#define FW_BLC_SELF	_MMIO(0x20e0) /* 915+ only */
+#define   FW_BLC_SELF_EN_MASK      REG_BIT(31)
+#define   FW_BLC_SELF_FIFO_MASK    REG_BIT(16) /* 945 only */
+#define   FW_BLC_SELF_EN           REG_BIT(15) /* 945 only */
+
 #endif /* __INTEL_DISPLAY_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c0c2fab99a47..bd3871f458d6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -395,24 +395,10 @@
 
 #define GEN2_ERROR_REGS		I915_ERROR_REGS(EMR, EIR)
 
-#define INSTPM	        _MMIO(0x20c0)
-#define   INSTPM_SELF_EN (1 << 12) /* 915GM only */
-#define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
-					will not assert AGPBUSY# and will only
-					be delivered when out of C3. */
-#define   INSTPM_FORCE_ORDERING				(1 << 7) /* GEN6+ */
-#define   INSTPM_TLB_INVALIDATE	(1 << 9)
-#define   INSTPM_SYNC_FLUSH	(1 << 5)
 #define MEM_MODE	_MMIO(0x20cc)
 #define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
 #define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
 #define   MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
-#define FW_BLC		_MMIO(0x20d8)
-#define FW_BLC2		_MMIO(0x20dc)
-#define FW_BLC_SELF	_MMIO(0x20e0) /* 915+ only */
-#define   FW_BLC_SELF_EN_MASK      REG_BIT(31)
-#define   FW_BLC_SELF_FIFO_MASK    REG_BIT(16) /* 945 only */
-#define   FW_BLC_SELF_EN           REG_BIT(15) /* 945 only */
 #define MM_BURST_LENGTH     0x00700000
 #define MM_FIFO_WATERMARK   0x0001F000
 #define LM_BURST_LENGTH     0x00000700
@@ -834,11 +820,6 @@
 #define   KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	REG_BIT(14)
 
 
-#define DISP_ARB_CTL	_MMIO(0x45000)
-#define   DISP_FBC_MEMORY_WAKE		REG_BIT(31)
-#define   DISP_TILE_SURFACE_SWIZZLING	REG_BIT(13)
-#define   DISP_FBC_WM_DIS		REG_BIT(15)
-
 #define GEN8_CHICKEN_DCPR_1			_MMIO(0x46430)
 #define   _LATENCY_REPORTING_REMOVED_PIPE_D	REG_BIT(31)
 #define   SKL_SELECT_ALTERNATE_DC_EXIT		REG_BIT(30)
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index c8b2b5b2739c..049349c365e3 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -155,4 +155,18 @@
 #define SDEIIR  _MMIO(0xc4008)
 #define SDEIER  _MMIO(0xc400c)
 
+#define DISP_ARB_CTL	_MMIO(0x45000)
+#define   DISP_FBC_MEMORY_WAKE		REG_BIT(31)
+#define   DISP_TILE_SURFACE_SWIZZLING	REG_BIT(13)
+#define   DISP_FBC_WM_DIS		REG_BIT(15)
+
+#define INSTPM	        _MMIO(0x20c0)
+#define   INSTPM_SELF_EN (1 << 12) /* 915GM only */
+#define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
+					will not assert AGPBUSY# and will only
+					be delivered when out of C3. */
+#define   INSTPM_FORCE_ORDERING				(1 << 7) /* GEN6+ */
+#define   INSTPM_TLB_INVALIDATE	(1 << 9)
+#define   INSTPM_SYNC_FLUSH	(1 << 5)
+
 #endif
-- 
2.50.1

[v2 12/19] drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c

[Uma Shankar]

Move TRANS_CHICKEN1 reg to display header to make g4x_hdmi.c
free from i915_reg.h dependency.

v2: Remove from common header in include and use display_regs.h (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/g4x_hdmi.c           |  1 -
 drivers/gpu/drm/i915/display/intel_display_regs.h | 12 ++++++++++++
 drivers/gpu/drm/i915/i915_reg.h                   | 12 ------------
 3 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 8b22447e8e23..5fe5067c4237 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -8,7 +8,6 @@
 #include <drm/drm_print.h>
 
 #include "g4x_hdmi.h"
-#include "i915_reg.h"
 #include "intel_atomic.h"
 #include "intel_audio.h"
 #include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 477896faa79e..2c7cd9002da3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2122,6 +2122,18 @@
 #define  TRANS_BPC_6			REG_FIELD_PREP(TRANS_BPC_MASK, 2)
 #define  TRANS_BPC_12			REG_FIELD_PREP(TRANS_BPC_MASK, 3)
 
+/* Icelake PPS_DATA and _ECC DIP Registers.
+ * These are available for transcoders B,C and eDP.
+ * Adding the _A so as to reuse the _MMIO_TRANS2
+ * definition, with which it offsets to the right location.
+ */
+
+#define _TRANSA_CHICKEN1	 0xf0060
+#define _TRANSB_CHICKEN1	 0xf1060
+#define TRANS_CHICKEN1(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
+#define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
+#define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
+
 #define _TRANSA_CHICKEN2	0xf0064
 #define _TRANSB_CHICKEN2	0xf1064
 #define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bd3871f458d6..5d640f7cfc23 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -836,18 +836,6 @@
 #define   MASK_WAKEMEM				REG_BIT(13)
 #define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
 
-/* Icelake PPS_DATA and _ECC DIP Registers.
- * These are available for transcoders B,C and eDP.
- * Adding the _A so as to reuse the _MMIO_TRANS2
- * definition, with which it offsets to the right location.
- */
-
-#define _TRANSA_CHICKEN1	 0xf0060
-#define _TRANSB_CHICKEN1	 0xf1060
-#define TRANS_CHICKEN1(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
-#define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
-#define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
-
 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
 
 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
-- 
2.50.1

[v2 13/19] drm/{i915, xe}: Remove i915_reg.h from intel_rom.c

[Uma Shankar]

Make intel_rom.c free from including i915_reg.h.

v2: Use display header instead of gmd common include (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++++++
 drivers/gpu/drm/i915/display/intel_rom.c          | 3 +--
 drivers/gpu/drm/i915/i915_reg.h                   | 8 --------
 3 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 2c7cd9002da3..f468e0d20b92 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -9,6 +9,14 @@
 #define GU_CNTL_PROTECTED		_MMIO(0x10100C)
 #define   DEPRESENT			REG_BIT(9)
 
+#define PRIMARY_SPI_TRIGGER			_MMIO(0x102040)
+#define PRIMARY_SPI_ADDRESS			_MMIO(0x102080)
+#define PRIMARY_SPI_REGIONID			_MMIO(0x102084)
+#define SPI_STATIC_REGIONS			_MMIO(0x102090)
+#define   OPTIONROM_SPI_REGIONID_MASK		REG_GENMASK(7, 0)
+#define OROM_OFFSET				_MMIO(0x1020c0)
+#define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
+
 #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
 #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
diff --git a/drivers/gpu/drm/i915/display/intel_rom.c b/drivers/gpu/drm/i915/display/intel_rom.c
index c8f615315310..d7de53acaba9 100644
--- a/drivers/gpu/drm/i915/display/intel_rom.c
+++ b/drivers/gpu/drm/i915/display/intel_rom.c
@@ -7,10 +7,9 @@
 
 #include <drm/drm_device.h>
 
-#include "i915_reg.h"
-
 #include "intel_rom.h"
 #include "intel_uncore.h"
+#include "intel_display_regs.h"
 
 struct intel_rom {
 	/* for PCI ROM */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d640f7cfc23..d43c04e491e1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -892,14 +892,6 @@
 #define   SGGI_DIS			REG_BIT(15)
 #define   SGR_DIS			REG_BIT(13)
 
-#define PRIMARY_SPI_TRIGGER			_MMIO(0x102040)
-#define PRIMARY_SPI_ADDRESS			_MMIO(0x102080)
-#define PRIMARY_SPI_REGIONID			_MMIO(0x102084)
-#define SPI_STATIC_REGIONS			_MMIO(0x102090)
-#define   OPTIONROM_SPI_REGIONID_MASK		REG_GENMASK(7, 0)
-#define OROM_OFFSET				_MMIO(0x1020c0)
-#define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
-
 #define MTL_MEDIA_GSI_BASE		0x380000
 
 #endif /* _I915_REG_H_ */
-- 
2.50.1

[v2 14/19] drm/{i915, xe}: Remove i915_reg.h from intel_psr.c

[Uma Shankar]

Move some chicken registers to display header to make
intel_psr.c free from including i915_reg.h.

v2: Use display header instead of gmd common include (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../gpu/drm/i915/display/intel_display_regs.h | 26 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_psr.c      |  1 -
 drivers/gpu/drm/i915/i915_reg.h               | 26 -------------------
 3 files changed, 26 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index f468e0d20b92..aafe71a3b410 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -363,6 +363,32 @@
 #define OGAMC1			_MMIO(0x30020)
 #define OGAMC0			_MMIO(0x30024)
 
+#define GEN8_CHICKEN_DCPR_1			_MMIO(0x46430)
+#define   _LATENCY_REPORTING_REMOVED_PIPE_D	REG_BIT(31)
+#define   SKL_SELECT_ALTERNATE_DC_EXIT		REG_BIT(30)
+#define   _LATENCY_REPORTING_REMOVED_PIPE_C	REG_BIT(25)
+#define   _LATENCY_REPORTING_REMOVED_PIPE_B	REG_BIT(24)
+#define   _LATENCY_REPORTING_REMOVED_PIPE_A	REG_BIT(23)
+#define   LATENCY_REPORTING_REMOVED(pipe)	_PICK((pipe), \
+						      _LATENCY_REPORTING_REMOVED_PIPE_A, \
+						      _LATENCY_REPORTING_REMOVED_PIPE_B, \
+						      _LATENCY_REPORTING_REMOVED_PIPE_C, \
+						      _LATENCY_REPORTING_REMOVED_PIPE_D)
+#define   ICL_DELAY_PMRSP			REG_BIT(22)
+#define   DISABLE_FLR_SRC			REG_BIT(15)
+#define   MASK_WAKEMEM				REG_BIT(13)
+#define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
+
+#define CHICKEN_PAR1_1		_MMIO(0x42080)
+#define   IGNORE_KVMR_PIPE_A		REG_BIT(23)
+#define   KBL_ARB_FILL_SPARE_22		REG_BIT(22)
+#define   DIS_RAM_BYPASS_PSR2_MAN_TRACK	REG_BIT(16)
+#define   SKL_DE_COMPRESSED_HASH_MODE	REG_BIT(15)
+#define   HSW_MASK_VBL_TO_PIPE_IN_SRD	REG_BIT(15) /* hsw/bdw */
+#define   FORCE_ARB_IDLE_PLANES		REG_BIT(14)
+#define   SKL_EDP_PSR_FIX_RDWRAP	REG_BIT(3)
+#define   IGNORE_PSR2_HW_TRACKING	REG_BIT(1)
+
 #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
 #define   BXT_GMBUS_GATING_DIS		(1 << 14)
 #define   DG2_DPFC_GATING_DIS		REG_BIT(31)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 62208ffc5101..bde7dbfe15a8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -29,7 +29,6 @@
 #include <drm/drm_print.h>
 #include <drm/drm_vblank.h>
 
-#include "i915_reg.h"
 #include "intel_alpm.h"
 #include "intel_atomic.h"
 #include "intel_crtc.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d43c04e491e1..62d58d7cfa7a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -806,36 +806,10 @@
 #define   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	REG_BIT(5)
 #define   CHICKEN3_DGMG_DONE_FIX_DISABLE	REG_BIT(2)
 
-#define CHICKEN_PAR1_1		_MMIO(0x42080)
-#define   IGNORE_KVMR_PIPE_A		REG_BIT(23)
-#define   KBL_ARB_FILL_SPARE_22		REG_BIT(22)
-#define   DIS_RAM_BYPASS_PSR2_MAN_TRACK	REG_BIT(16)
-#define   SKL_DE_COMPRESSED_HASH_MODE	REG_BIT(15)
-#define   HSW_MASK_VBL_TO_PIPE_IN_SRD	REG_BIT(15) /* hsw/bdw */
-#define   FORCE_ARB_IDLE_PLANES		REG_BIT(14)
-#define   SKL_EDP_PSR_FIX_RDWRAP	REG_BIT(3)
-#define   IGNORE_PSR2_HW_TRACKING	REG_BIT(1)
-
 #define CHICKEN_PAR2_1		_MMIO(0x42090)
 #define   KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	REG_BIT(14)
 
 
-#define GEN8_CHICKEN_DCPR_1			_MMIO(0x46430)
-#define   _LATENCY_REPORTING_REMOVED_PIPE_D	REG_BIT(31)
-#define   SKL_SELECT_ALTERNATE_DC_EXIT		REG_BIT(30)
-#define   _LATENCY_REPORTING_REMOVED_PIPE_C	REG_BIT(25)
-#define   _LATENCY_REPORTING_REMOVED_PIPE_B	REG_BIT(24)
-#define   _LATENCY_REPORTING_REMOVED_PIPE_A	REG_BIT(23)
-#define   LATENCY_REPORTING_REMOVED(pipe)	_PICK((pipe), \
-						      _LATENCY_REPORTING_REMOVED_PIPE_A, \
-						      _LATENCY_REPORTING_REMOVED_PIPE_B, \
-						      _LATENCY_REPORTING_REMOVED_PIPE_C, \
-						      _LATENCY_REPORTING_REMOVED_PIPE_D)
-#define   ICL_DELAY_PMRSP			REG_BIT(22)
-#define   DISABLE_FLR_SRC			REG_BIT(15)
-#define   MASK_WAKEMEM				REG_BIT(13)
-#define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
-
 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
 
 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
-- 
2.50.1

[v2 15/19] drm/{i915, xe}: Remove i915_reg.h from intel_fifo_underrun.c

[Uma Shankar]

Move GEN7_ERR_INT reg to common header to make intel_fifo_underrun.c
free from including i915_reg.h.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../drm/i915/display/intel_fifo_underrun.c    |  2 +-
 drivers/gpu/drm/i915/i915_reg.h               | 23 -------------------
 include/drm/intel/intel_gmd_common_regs.h     | 23 +++++++++++++++++++
 3 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index b413b3e871d8..c834be759e40 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -28,8 +28,8 @@
 #include <linux/seq_buf.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_irq.h"
 #include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 62d58d7cfa7a..0af2c9c8dc0f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -326,29 +326,6 @@
 #define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
 #define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)
 
-#define GEN7_ERR_INT	_MMIO(0x44040)
-#define   ERR_INT_POISON		(1 << 31)
-#define   ERR_INT_INVALID_GTT_PTE	(1 << 29)
-#define   ERR_INT_INVALID_PTE_DATA	(1 << 28)
-#define   ERR_INT_SPRITE_C_FAULT	(1 << 23)
-#define   ERR_INT_PRIMARY_C_FAULT	(1 << 22)
-#define   ERR_INT_CURSOR_C_FAULT	(1 << 21)
-#define   ERR_INT_SPRITE_B_FAULT	(1 << 20)
-#define   ERR_INT_PRIMARY_B_FAULT	(1 << 19)
-#define   ERR_INT_CURSOR_B_FAULT	(1 << 18)
-#define   ERR_INT_SPRITE_A_FAULT	(1 << 17)
-#define   ERR_INT_PRIMARY_A_FAULT	(1 << 16)
-#define   ERR_INT_CURSOR_A_FAULT	(1 << 15)
-#define   ERR_INT_MMIO_UNCLAIMED	(1 << 13)
-#define   ERR_INT_PIPE_CRC_DONE_C	(1 << 8)
-#define   ERR_INT_FIFO_UNDERRUN_C	(1 << 6)
-#define   ERR_INT_PIPE_CRC_DONE_B	(1 << 5)
-#define   ERR_INT_FIFO_UNDERRUN_B	(1 << 3)
-#define   ERR_INT_PIPE_CRC_DONE_A	(1 << 2)
-#define   ERR_INT_PIPE_CRC_DONE(pipe)	(1 << (2 + (pipe) * 3))
-#define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
-#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
-
 #define FPGA_DBG		_MMIO(0x42300)
 #define   FPGA_DBG_RM_NOCLAIM	REG_BIT(31)
 
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index 049349c365e3..2b2a7f21529a 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -169,4 +169,27 @@
 #define   INSTPM_TLB_INVALIDATE	(1 << 9)
 #define   INSTPM_SYNC_FLUSH	(1 << 5)
 
+#define GEN7_ERR_INT	_MMIO(0x44040)
+#define   ERR_INT_POISON		(1 << 31)
+#define   ERR_INT_INVALID_GTT_PTE	(1 << 29)
+#define   ERR_INT_INVALID_PTE_DATA	(1 << 28)
+#define   ERR_INT_SPRITE_C_FAULT	(1 << 23)
+#define   ERR_INT_PRIMARY_C_FAULT	(1 << 22)
+#define   ERR_INT_CURSOR_C_FAULT	(1 << 21)
+#define   ERR_INT_SPRITE_B_FAULT	(1 << 20)
+#define   ERR_INT_PRIMARY_B_FAULT	(1 << 19)
+#define   ERR_INT_CURSOR_B_FAULT	(1 << 18)
+#define   ERR_INT_SPRITE_A_FAULT	(1 << 17)
+#define   ERR_INT_PRIMARY_A_FAULT	(1 << 16)
+#define   ERR_INT_CURSOR_A_FAULT	(1 << 15)
+#define   ERR_INT_MMIO_UNCLAIMED	(1 << 13)
+#define   ERR_INT_PIPE_CRC_DONE_C	(1 << 8)
+#define   ERR_INT_FIFO_UNDERRUN_C	(1 << 6)
+#define   ERR_INT_PIPE_CRC_DONE_B	(1 << 5)
+#define   ERR_INT_FIFO_UNDERRUN_B	(1 << 3)
+#define   ERR_INT_PIPE_CRC_DONE_A	(1 << 2)
+#define   ERR_INT_PIPE_CRC_DONE(pipe)	(1 << (2 + (pipe) * 3))
+#define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
+#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
+
 #endif
-- 
2.50.1

[v2 16/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_irq.c

[Uma Shankar]

Move VLV_IRQ_REGS to common header to make intel_display_irq.c
free from including i915_reg.h.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../gpu/drm/i915/display/intel_display_irq.c  |  2 +-
 .../gpu/drm/i915/display/intel_display_regs.h | 28 +++++-----
 drivers/gpu/drm/i915/i915_reg.h               | 52 ------------------
 include/drm/intel/intel_gmd_common_regs.h     | 54 +++++++++++++++++++
 4 files changed, 69 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 9adeebb376b1..206c0d004646 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -5,8 +5,8 @@
 
 #include <drm/drm_print.h>
 #include <drm/drm_vblank.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "icl_dsi_regs.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index aafe71a3b410..fb21b1cf6124 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -90,20 +90,6 @@
 #define   DERRMR_PIPEC_VBLANK		(1 << 21)
 #define   DERRMR_PIPEC_HBLANK		(1 << 22)
 
-#define VLV_IRQ_REGS		I915_IRQ_REGS(VLV_IMR, \
-					      VLV_IER, \
-					      VLV_IIR)
-
-#define VLV_EIR		_MMIO(VLV_DISPLAY_BASE + 0x20b0)
-#define VLV_EMR		_MMIO(VLV_DISPLAY_BASE + 0x20b4)
-#define VLV_ESR		_MMIO(VLV_DISPLAY_BASE + 0x20b8)
-#define   VLV_ERROR_GUNIT_TLB_DATA			(1 << 6)
-#define   VLV_ERROR_GUNIT_TLB_PTE			(1 << 5)
-#define   VLV_ERROR_PAGE_TABLE				(1 << 4)
-#define   VLV_ERROR_CLAIM				(1 << 0)
-
-#define VLV_ERROR_REGS		I915_ERROR_REGS(VLV_EMR, VLV_EIR)
-
 #define _MBUS_ABOX0_CTL			0x45038
 #define _MBUS_ABOX1_CTL			0x45048
 #define _MBUS_ABOX2_CTL			0x4504C
@@ -3166,4 +3152,18 @@ enum skl_power_gate {
 #define   FW_BLC_SELF_FIFO_MASK    REG_BIT(16) /* 945 only */
 #define   FW_BLC_SELF_EN           REG_BIT(15) /* 945 only */
 
+#define VLV_IRQ_REGS		I915_IRQ_REGS(VLV_IMR, \
+					      VLV_IER, \
+					      VLV_IIR)
+
+#define VLV_EIR		_MMIO(VLV_DISPLAY_BASE + 0x20b0)
+#define VLV_EMR		_MMIO(VLV_DISPLAY_BASE + 0x20b4)
+#define VLV_ESR		_MMIO(VLV_DISPLAY_BASE + 0x20b8)
+#define   VLV_ERROR_GUNIT_TLB_DATA			(1 << 6)
+#define   VLV_ERROR_GUNIT_TLB_PTE			(1 << 5)
+#define   VLV_ERROR_PAGE_TABLE				(1 << 4)
+#define   VLV_ERROR_CLAIM				(1 << 0)
+
+#define VLV_ERROR_REGS		I915_ERROR_REGS(VLV_EMR, VLV_EIR)
+
 #endif /* __INTEL_DISPLAY_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0af2c9c8dc0f..a85e2d9ab561 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -336,9 +336,6 @@
 
 #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
 #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
-#define SCPD0		_MMIO(0x209c) /* 915+ only */
-#define  SCPD_FBC_IGNORE_3D			(1 << 6)
-#define  CSTATE_RENDER_CLOCK_GATE_DISABLE	(1 << 5)
 #define GEN2_IER	_MMIO(0x20a0)
 #define GEN2_IIR	_MMIO(0x20a4)
 #define GEN2_IMR	_MMIO(0x20a8)
@@ -352,13 +349,6 @@
 #define   GINT_DIS		(1 << 22)
 #define   GCFG_DIS		(1 << 8)
 #define VLV_GUNIT_CLOCK_GATE2	_MMIO(VLV_DISPLAY_BASE + 0x2064)
-#define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
-#define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
-#define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
-#define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
-#define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
-#define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
-#define VLV_PCBR_ADDR_SHIFT	12
 
 #define EIR		_MMIO(0x20b0)
 #define EMR		_MMIO(0x20b4)
@@ -683,11 +673,6 @@
 #define PCH_3DCGDIS1		_MMIO(0x46024)
 # define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
 
-/* Display Internal Timeout Register */
-#define RM_TIMEOUT		_MMIO(0x42060)
-#define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
-#define  MMIO_TIMEOUT_US(us)	((us) << 0)
-
 #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
 #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
 
@@ -700,24 +685,6 @@
 					      GTIER, \
 					      GTIIR)
 
-#define GEN8_MASTER_IRQ			_MMIO(0x44200)
-#define  GEN8_MASTER_IRQ_CONTROL	(1 << 31)
-#define  GEN8_PCU_IRQ			(1 << 30)
-#define  GEN8_DE_PCH_IRQ		(1 << 23)
-#define  GEN8_DE_MISC_IRQ		(1 << 22)
-#define  GEN8_DE_PORT_IRQ		(1 << 20)
-#define  GEN8_DE_PIPE_C_IRQ		(1 << 18)
-#define  GEN8_DE_PIPE_B_IRQ		(1 << 17)
-#define  GEN8_DE_PIPE_A_IRQ		(1 << 16)
-#define  GEN8_DE_PIPE_IRQ(pipe)		(1 << (16 + (pipe)))
-#define  GEN8_GT_VECS_IRQ		(1 << 6)
-#define  GEN8_GT_GUC_IRQ		(1 << 5)
-#define  GEN8_GT_PM_IRQ			(1 << 4)
-#define  GEN8_GT_VCS1_IRQ		(1 << 3) /* NB: VCS2 in bspec! */
-#define  GEN8_GT_VCS0_IRQ		(1 << 2) /* NB: VCS1 in bpsec! */
-#define  GEN8_GT_BCS_IRQ		(1 << 1)
-#define  GEN8_GT_RCS_IRQ		(1 << 0)
-
 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
@@ -743,25 +710,6 @@
 						      GEN8_PCU_IER, \
 						      GEN8_PCU_IIR)
 
-#define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
-#define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
-#define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
-#define GEN11_GU_MISC_IER	_MMIO(0x444fc)
-#define  GEN11_GU_MISC_GSE	(1 << 27)
-
-#define GEN11_GU_MISC_IRQ_REGS		I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
-						      GEN11_GU_MISC_IER, \
-						      GEN11_GU_MISC_IIR)
-
-#define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
-#define  GEN11_MASTER_IRQ		(1 << 31)
-#define  GEN11_PCU_IRQ			(1 << 30)
-#define  GEN11_GU_MISC_IRQ		(1 << 29)
-#define  GEN11_DISPLAY_IRQ		(1 << 16)
-#define  GEN11_GT_DW_IRQ(x)		(1 << (x))
-#define  GEN11_GT_DW1_IRQ		(1 << 1)
-#define  GEN11_GT_DW0_IRQ		(1 << 0)
-
 #define DG1_MSTR_TILE_INTR		_MMIO(0x190008)
 #define   DG1_MSTR_IRQ			REG_BIT(31)
 #define   DG1_MSTR_TILE(t)		REG_BIT(t)
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index 2b2a7f21529a..9bc234135454 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -111,6 +111,9 @@
 #define   GMD_ID_STEP				REG_GENMASK(5, 0)
 
 #define GEN2_ISR       _MMIO(0x20ac)
+#define SCPD0		_MMIO(0x209c) /* 915+ only */
+#define  SCPD_FBC_IGNORE_3D			(1 << 6)
+#define  CSTATE_RENDER_CLOCK_GATE_DISABLE	(1 << 5)
 
 #define I915_PM_INTERRUPT				(1 << 31)
 #define I915_ISP_INTERRUPT				(1 << 22)
@@ -192,4 +195,55 @@
 #define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
 #define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
 
+#define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
+#define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
+#define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
+#define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
+#define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
+#define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
+#define VLV_PCBR_ADDR_SHIFT	12
+
+#define GEN8_MASTER_IRQ			_MMIO(0x44200)
+#define  GEN8_MASTER_IRQ_CONTROL	(1 << 31)
+#define  GEN8_PCU_IRQ			(1 << 30)
+#define  GEN8_DE_PCH_IRQ		(1 << 23)
+#define  GEN8_DE_MISC_IRQ		(1 << 22)
+#define  GEN8_DE_PORT_IRQ		(1 << 20)
+#define  GEN8_DE_PIPE_C_IRQ		(1 << 18)
+#define  GEN8_DE_PIPE_B_IRQ		(1 << 17)
+#define  GEN8_DE_PIPE_A_IRQ		(1 << 16)
+#define  GEN8_DE_PIPE_IRQ(pipe)		(1 << (16 + (pipe)))
+#define  GEN8_GT_VECS_IRQ		(1 << 6)
+#define  GEN8_GT_GUC_IRQ		(1 << 5)
+#define  GEN8_GT_PM_IRQ			(1 << 4)
+#define  GEN8_GT_VCS1_IRQ		(1 << 3) /* NB: VCS2 in bspec! */
+#define  GEN8_GT_VCS0_IRQ		(1 << 2) /* NB: VCS1 in bpsec! */
+#define  GEN8_GT_BCS_IRQ		(1 << 1)
+#define  GEN8_GT_RCS_IRQ		(1 << 0)
+
+
+#define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
+#define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
+#define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
+#define GEN11_GU_MISC_IER	_MMIO(0x444fc)
+#define  GEN11_GU_MISC_GSE	(1 << 27)
+
+#define GEN11_GU_MISC_IRQ_REGS		I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
+						      GEN11_GU_MISC_IER, \
+						      GEN11_GU_MISC_IIR)
+
+/* Display Internal Timeout Register */
+#define RM_TIMEOUT		_MMIO(0x42060)
+#define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
+#define  MMIO_TIMEOUT_US(us)	((us) << 0)
+
+#define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
+#define  GEN11_MASTER_IRQ		(1 << 31)
+#define  GEN11_PCU_IRQ			(1 << 30)
+#define  GEN11_GU_MISC_IRQ		(1 << 29)
+#define  GEN11_DISPLAY_IRQ		(1 << 16)
+#define  GEN11_GT_DW_IRQ(x)		(1 << (x))
+#define  GEN11_GT_DW1_IRQ		(1 << 1)
+#define  GEN11_GT_DW0_IRQ		(1 << 0)
+
 #endif
-- 
2.50.1

[v2 17/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_power_well.c

[Uma Shankar]

Make intel_display_power_well.c free from including i915_reg.h.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
 drivers/gpu/drm/i915/display/intel_display_regs.h       | 2 ++
 drivers/gpu/drm/i915/i915_reg.h                         | 3 ---
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index db185a859133..8a1f1c61c6da 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -6,8 +6,8 @@
 #include <linux/iopoll.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_backlight_regs.h"
 #include "intel_combo_phy.h"
 #include "intel_combo_phy_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index fb21b1cf6124..1def3dccdf61 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -319,6 +319,8 @@
 #define  FW_CSPWRDWNEN		(1 << 15)
 
 #define MI_ARB_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6504)
+/* Disable display A/B trickle feed */
+#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
 
 #define CZCLK_CDCLK_FREQ_RATIO	_MMIO(VLV_DISPLAY_BASE + 0x6508)
 #define   CDCLK_FREQ_SHIFT	4
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a85e2d9ab561..c68a64bc7646 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -428,9 +428,6 @@
 #define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
 #define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)
 
-/* Disable display A/B trickle feed */
-#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
-
 /* Set display plane priority */
 #define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
 #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
-- 
2.50.1

[v2 18/19] drm/{i915, xe}: Remove i915_reg.h from intel_modeset_setup.c

[Uma Shankar]

Move GEN9_CLKGATE_DIS_0 reg to display header to make
intel_modeset_setup.c free from i915_reg.h include.

v2: Remove from gmd common header and use display_regs.h (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_regs.h  | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_modeset_setup.c |  1 -
 drivers/gpu/drm/i915/i915_reg.h                    | 13 -------------
 3 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 1def3dccdf61..ec18ad9a262c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -377,6 +377,19 @@
 #define   SKL_EDP_PSR_FIX_RDWRAP	REG_BIT(3)
 #define   IGNORE_PSR2_HW_TRACKING	REG_BIT(1)
 
+/*
+ * GEN9 clock gating regs
+ */
+#define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
+#define   DARBF_GATING_DIS		REG_BIT(27)
+#define   MTL_PIPEDMC_GATING_DIS(pipe)	REG_BIT(15 - (pipe))
+#define   PWM2_GATING_DIS		REG_BIT(14)
+#define   PWM1_GATING_DIS		REG_BIT(13)
+
+#define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)
+#define   TGL_VRH_GATING_DIS		REG_BIT(31)
+#define   DPT_GATING_DIS		REG_BIT(22)
+
 #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
 #define   BXT_GMBUS_GATING_DIS		(1 << 14)
 #define   DG2_DPFC_GATING_DIS		REG_BIT(31)
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index d10cbf69a5f8..9b0becee221c 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -11,7 +11,6 @@
 #include <drm/drm_print.h>
 #include <drm/drm_vblank.h>
 
-#include "i915_reg.h"
 #include "i9xx_wm.h"
 #include "intel_atomic.h"
 #include "intel_bw.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c68a64bc7646..86035f54ae7a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -629,19 +629,6 @@
 #define VLV_CLK_CTL2			_MMIO(0x101104)
 #define   CLK_CTL2_CZCOUNT_30NS_SHIFT	28
 
-/*
- * GEN9 clock gating regs
- */
-#define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
-#define   DARBF_GATING_DIS		REG_BIT(27)
-#define   MTL_PIPEDMC_GATING_DIS(pipe)	REG_BIT(15 - (pipe))
-#define   PWM2_GATING_DIS		REG_BIT(14)
-#define   PWM1_GATING_DIS		REG_BIT(13)
-
-#define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)
-#define   TGL_VRH_GATING_DIS		REG_BIT(31)
-#define   DPT_GATING_DIS		REG_BIT(22)
-
 #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
 #define   PIPEB_LINE_COMPARE_INT_EN			REG_BIT(29)
 #define   PIPEB_HLINE_INT_EN			REG_BIT(28)
-- 
2.50.1

[v2 19/19] drm/{i915, xe}: Remove i915_reg.h from display

[Uma Shankar]

Make display files free from including i915_reg.h.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/hsw_ips.c               | 2 +-
 drivers/gpu/drm/i915/display/i9xx_plane.c            | 1 -
 drivers/gpu/drm/i915/display/icl_dsi.c               | 1 -
 drivers/gpu/drm/i915/display/intel_backlight.c       | 1 -
 drivers/gpu/drm/i915/display/intel_bw.c              | 2 +-
 drivers/gpu/drm/i915/display/intel_casf.c            | 1 -
 drivers/gpu/drm/i915/display/intel_ddi.c             | 2 +-
 drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
 drivers/gpu/drm/i915/display/intel_display_power.c   | 2 +-
 drivers/gpu/drm/i915/display/intel_display_wa.c      | 1 -
 drivers/gpu/drm/i915/display/intel_dmc.c             | 1 -
 drivers/gpu/drm/i915/display/intel_fdi.c             | 1 -
 drivers/gpu/drm/i915/display/intel_hdcp.c            | 2 +-
 drivers/gpu/drm/i915/display/intel_hotplug_irq.c     | 1 -
 drivers/gpu/drm/i915/display/intel_lt_phy.c          | 1 -
 drivers/gpu/drm/i915/display/intel_pps.c             | 1 -
 drivers/gpu/drm/i915/display/intel_tc.c              | 2 +-
 drivers/gpu/drm/i915/display/skl_watermark.c         | 2 +-
 drivers/gpu/drm/i915/display/vlv_dsi.c               | 1 -
 19 files changed, 8 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 008d339d5c21..290d54fe87e4 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -6,9 +6,9 @@
 #include <linux/debugfs.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include "hsw_ips.h"
-#include "i915_reg.h"
 #include "intel_color_regs.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index b1fecf178906..9c16753a1f3b 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -10,7 +10,6 @@
 #include <drm/drm_fourcc.h>
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "i9xx_plane.h"
 #include "i9xx_plane_regs.h"
 #include "intel_atomic.h"
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index c8e0333706c1..7cf511a6c0f9 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -34,7 +34,6 @@
 #include <drm/drm_print.h>
 #include <drm/drm_probe_helper.h>
 
-#include "i915_reg.h"
 #include "icl_dsi.h"
 #include "icl_dsi_regs.h"
 #include "intel_atomic.h"
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index a68fdbd2acb9..34e95f05936e 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -12,7 +12,6 @@
 #include <drm/drm_file.h>
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_backlight.h"
 #include "intel_backlight_regs.h"
 #include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 4ee3f5172f4e..372081d80aa8 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -5,8 +5,8 @@
 
 #include <drm/drm_atomic_state_helper.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_bw.h"
 #include "intel_crtc.h"
 #include "intel_display_core.h"
diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
index 0fe4398a1a4e..b167af31de5b 100644
--- a/drivers/gpu/drm/i915/display/intel_casf.c
+++ b/drivers/gpu/drm/i915/display/intel_casf.c
@@ -3,7 +3,6 @@
 
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_casf.h"
 #include "intel_casf_regs.h"
 #include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d8739e2bb004..4bec15352d0f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -33,8 +33,8 @@
 #include <drm/display/drm_scdc_helper.h>
 #include <drm/drm_print.h>
 #include <drm/drm_privacy_screen_consumer.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "icl_dsi.h"
 #include "intel_alpm.h"
 #include "intel_audio.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index aba13e8a9051..07cb56f80e88 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -13,9 +13,9 @@
 #include <drm/drm_file.h>
 #include <drm/drm_fourcc.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include "hsw_ips.h"
-#include "i915_reg.h"
 #include "i9xx_wm_regs.h"
 #include "intel_alpm.h"
 #include "intel_bo.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index d27397f43863..20dadabcd812 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -7,8 +7,8 @@
 #include <linux/string_helpers.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_backlight_regs.h"
 #include "intel_cdclk.h"
 #include "intel_clock_gating.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index 581d943b9bdc..518df619f5e5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -5,7 +5,6 @@
 
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_core.h"
 #include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 1182bc9a2e6d..8df06b993890 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -29,7 +29,6 @@
 #include <drm/drm_file.h>
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_power_well.h"
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 5bb0090dd5ed..24ce8a7842c7 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -8,7 +8,6 @@
 #include <drm/drm_fixed.h>
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_atomic.h"
 #include "intel_crtc.h"
 #include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 7114fc405c29..db15bf1980c0 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -17,8 +17,8 @@
 #include <drm/display/drm_hdcp_helper.h>
 #include <drm/drm_print.h>
 #include <drm/intel/i915_component.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_connector.h"
 #include "intel_de.h"
 #include "intel_display_jiffies.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index 82c39e4ffa37..8865cb2ac569 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -5,7 +5,6 @@
 
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_irq.h"
 #include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index b4b281ef258b..d17a9b013b67 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -5,7 +5,6 @@
 
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index b217ec7aa758..2d799af73bb7 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -9,7 +9,6 @@
 #include <drm/drm_print.h>
 
 #include "g4x_dp.h"
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_jiffies.h"
 #include "intel_display_power_well.h"
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 064f572bbc85..5784d5d5132d 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -6,8 +6,8 @@
 #include <linux/iopoll.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_atomic.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index a6aab79812e5..410289b3fadd 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -7,8 +7,8 @@
 
 #include <drm/drm_blend.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "i9xx_wm.h"
 #include "intel_atomic.h"
 #include "intel_bw.h"
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index d705af3bf8ba..67f0082d3a69 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -33,7 +33,6 @@
 #include <drm/drm_print.h>
 #include <drm/drm_probe_helper.h>
 
-#include "i915_reg.h"
 #include "intel_atomic.h"
 #include "intel_backlight.h"
 #include "intel_connector.h"
-- 
2.50.1

✗ CI.checkpatch: warning for Make Display free from i915_reg.h (rev2)

[Patchwork]

== Series Details ==

Series: Make Display free from i915_reg.h (rev2)
URL   : https://patchwork.freedesktop.org/series/159130/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 61042b4f7b8e895433d620cf513360872c08ecdc
Author: Uma Shankar <uma.shankar@intel.com>
Date:   Thu Jan 22 04:54:14 2026 +0530

    drm/{i915, xe}: Remove i915_reg.h from display
    
    Make display files free from including i915_reg.h.
    
    Signed-off-by: Uma Shankar <uma.shankar@intel.com>
+ /mt/dim checkpatch ad2a046603cba140214aed34015ed5027441e85a drm-intel
0675804ceab4 drm/{i915, xe}: Extract display registers from i915_reg.h to display
-:32: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#32: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2030:
+#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */

total: 0 errors, 1 warnings, 0 checks, 47 lines checked
e419f0f65808 drm/{i915, xe}: Extract South chicken registers from i915_reg.h to display
c800a061bf31 drm/{i915, xe}: Extract display interrupt definitions
-:52: CHECK:LINE_SPACING: Please don't use multiple blank lines
#52: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1369:
+
+

total: 0 errors, 0 warnings, 1 checks, 88 lines checked
9d06eb81fff4 drm/{i915, xe}: Extract DSPCLK_GATE_D from i915_reg to display
8cdf78ea11f5 drm/{i915, xe}: Extract pcode definitions to common header
-:150: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#150: 
new file mode 100644

-:207: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#207: FILE: include/drm/intel/intel_gmd_common_regs.h:53:
+#define   DISPLAY_TO_PCODE_PIPE_COUNT(x)	REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))

total: 0 errors, 2 warnings, 0 checks, 231 lines checked
34b6f3381439 drm/{i915, xe}: Remove i915_reg.h from intel_display_device.c
b450da3f4328 drm/{i915, xe}: Remove i915_reg.h from intel_dram.c
9959e6d10976 drm/{i915, xe}: Removed i915_reg.h from intel_display.c
5994ff8d2122 drm/{i915, xe}: Remove i915_reg.h from intel_overlay.c
596963c79c89 drm/{i915, xe}: Remove i915_reg.h from g4x_dp.c
a83d323eb3a8 drm/{i915, xe}: Remove i915_reg.h from i9xx_wm.c
-:98: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#98: FILE: include/drm/intel/intel_gmd_common_regs.h:166:
+#define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
+					will not assert AGPBUSY# and will only

-:99: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#99: FILE: include/drm/intel/intel_gmd_common_regs.h:167:
+					be delivered when out of C3. */

total: 0 errors, 2 warnings, 0 checks, 73 lines checked
021bba3cdf84 drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c
261ade0a4f2b drm/{i915, xe}: Remove i915_reg.h from intel_rom.c
216d06fda909 drm/{i915, xe}: Remove i915_reg.h from intel_psr.c
47ebbb5664f8 drm/{i915, xe}: Remove i915_reg.h from intel_fifo_underrun.c
a9f979136fc9 drm/{i915, xe}: Remove i915_reg.h from intel_display_irq.c
-:204: CHECK:LINE_SPACING: Please don't use multiple blank lines
#204: FILE: include/drm/intel/intel_gmd_common_regs.h:224:
+
+

total: 0 errors, 0 warnings, 1 checks, 193 lines checked
513c37c47cb3 drm/{i915, xe}: Remove i915_reg.h from intel_display_power_well.c
2c5ec47e0704 drm/{i915, xe}: Remove i915_reg.h from intel_modeset_setup.c
61042b4f7b8e drm/{i915, xe}: Remove i915_reg.h from display

✓ CI.KUnit: success for Make Display free from i915_reg.h (rev2)

[Patchwork]

== Series Details ==

Series: Make Display free from i915_reg.h (rev2)
URL   : https://patchwork.freedesktop.org/series/159130/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[23:56:53] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:56:57] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:57:29] Starting KUnit Kernel (1/1)...
[23:57:29] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:57:29] ================== guc_buf (11 subtests) ===================
[23:57:29] [PASSED] test_smallest
[23:57:29] [PASSED] test_largest
[23:57:29] [PASSED] test_granular
[23:57:29] [PASSED] test_unique
[23:57:29] [PASSED] test_overlap
[23:57:29] [PASSED] test_reusable
[23:57:29] [PASSED] test_too_big
[23:57:29] [PASSED] test_flush
[23:57:29] [PASSED] test_lookup
[23:57:29] [PASSED] test_data
[23:57:29] [PASSED] test_class
[23:57:29] ===================== [PASSED] guc_buf =====================
[23:57:29] =================== guc_dbm (7 subtests) ===================
[23:57:29] [PASSED] test_empty
[23:57:29] [PASSED] test_default
[23:57:29] ======================== test_size  ========================
[23:57:29] [PASSED] 4
[23:57:29] [PASSED] 8
[23:57:29] [PASSED] 32
[23:57:29] [PASSED] 256
[23:57:29] ==================== [PASSED] test_size ====================
[23:57:29] ======================= test_reuse  ========================
[23:57:29] [PASSED] 4
[23:57:29] [PASSED] 8
[23:57:29] [PASSED] 32
[23:57:29] [PASSED] 256
[23:57:29] =================== [PASSED] test_reuse ====================
[23:57:29] =================== test_range_overlap  ====================
[23:57:29] [PASSED] 4
[23:57:29] [PASSED] 8
[23:57:29] [PASSED] 32
[23:57:29] [PASSED] 256
[23:57:29] =============== [PASSED] test_range_overlap ================
[23:57:29] =================== test_range_compact  ====================
[23:57:29] [PASSED] 4
[23:57:29] [PASSED] 8
[23:57:29] [PASSED] 32
[23:57:29] [PASSED] 256
[23:57:29] =============== [PASSED] test_range_compact ================
[23:57:29] ==================== test_range_spare  =====================
[23:57:29] [PASSED] 4
[23:57:29] [PASSED] 8
[23:57:29] [PASSED] 32
[23:57:29] [PASSED] 256
[23:57:29] ================ [PASSED] test_range_spare =================
[23:57:29] ===================== [PASSED] guc_dbm =====================
[23:57:29] =================== guc_idm (6 subtests) ===================
[23:57:29] [PASSED] bad_init
[23:57:29] [PASSED] no_init
[23:57:29] [PASSED] init_fini
[23:57:29] [PASSED] check_used
[23:57:29] [PASSED] check_quota
[23:57:29] [PASSED] check_all
[23:57:29] ===================== [PASSED] guc_idm =====================
[23:57:29] ================== no_relay (3 subtests) ===================
[23:57:29] [PASSED] xe_drops_guc2pf_if_not_ready
[23:57:29] [PASSED] xe_drops_guc2vf_if_not_ready
[23:57:29] [PASSED] xe_rejects_send_if_not_ready
[23:57:29] ==================== [PASSED] no_relay =====================
[23:57:29] ================== pf_relay (14 subtests) ==================
[23:57:29] [PASSED] pf_rejects_guc2pf_too_short
[23:57:29] [PASSED] pf_rejects_guc2pf_too_long
[23:57:29] [PASSED] pf_rejects_guc2pf_no_payload
[23:57:29] [PASSED] pf_fails_no_payload
[23:57:29] [PASSED] pf_fails_bad_origin
[23:57:29] [PASSED] pf_fails_bad_type
[23:57:29] [PASSED] pf_txn_reports_error
[23:57:29] [PASSED] pf_txn_sends_pf2guc
[23:57:29] [PASSED] pf_sends_pf2guc
[23:57:29] [SKIPPED] pf_loopback_nop
[23:57:29] [SKIPPED] pf_loopback_echo
[23:57:29] [SKIPPED] pf_loopback_fail
[23:57:29] [SKIPPED] pf_loopback_busy
[23:57:29] [SKIPPED] pf_loopback_retry
[23:57:29] ==================== [PASSED] pf_relay =====================
[23:57:29] ================== vf_relay (3 subtests) ===================
[23:57:29] [PASSED] vf_rejects_guc2vf_too_short
[23:57:29] [PASSED] vf_rejects_guc2vf_too_long
[23:57:29] [PASSED] vf_rejects_guc2vf_no_payload
[23:57:29] ==================== [PASSED] vf_relay =====================
[23:57:29] ================ pf_gt_config (6 subtests) =================
[23:57:29] [PASSED] fair_contexts_1vf
[23:57:29] [PASSED] fair_doorbells_1vf
[23:57:29] [PASSED] fair_ggtt_1vf
[23:57:29] ====================== fair_contexts  ======================
[23:57:29] [PASSED] 1 VF
[23:57:29] [PASSED] 2 VFs
[23:57:29] [PASSED] 3 VFs
[23:57:29] [PASSED] 4 VFs
[23:57:29] [PASSED] 5 VFs
[23:57:29] [PASSED] 6 VFs
[23:57:29] [PASSED] 7 VFs
[23:57:29] [PASSED] 8 VFs
[23:57:29] [PASSED] 9 VFs
[23:57:29] [PASSED] 10 VFs
[23:57:29] [PASSED] 11 VFs
[23:57:29] [PASSED] 12 VFs
[23:57:29] [PASSED] 13 VFs
[23:57:29] [PASSED] 14 VFs
[23:57:29] [PASSED] 15 VFs
[23:57:29] [PASSED] 16 VFs
[23:57:29] [PASSED] 17 VFs
[23:57:29] [PASSED] 18 VFs
[23:57:29] [PASSED] 19 VFs
[23:57:29] [PASSED] 20 VFs
[23:57:29] [PASSED] 21 VFs
[23:57:29] [PASSED] 22 VFs
[23:57:29] [PASSED] 23 VFs
[23:57:29] [PASSED] 24 VFs
[23:57:29] [PASSED] 25 VFs
[23:57:29] [PASSED] 26 VFs
[23:57:29] [PASSED] 27 VFs
[23:57:29] [PASSED] 28 VFs
[23:57:29] [PASSED] 29 VFs
[23:57:29] [PASSED] 30 VFs
[23:57:29] [PASSED] 31 VFs
[23:57:29] [PASSED] 32 VFs
[23:57:29] [PASSED] 33 VFs
[23:57:29] [PASSED] 34 VFs
[23:57:29] [PASSED] 35 VFs
[23:57:29] [PASSED] 36 VFs
[23:57:29] [PASSED] 37 VFs
[23:57:29] [PASSED] 38 VFs
[23:57:29] [PASSED] 39 VFs
[23:57:29] [PASSED] 40 VFs
[23:57:29] [PASSED] 41 VFs
[23:57:29] [PASSED] 42 VFs
[23:57:29] [PASSED] 43 VFs
[23:57:29] [PASSED] 44 VFs
[23:57:29] [PASSED] 45 VFs
[23:57:29] [PASSED] 46 VFs
[23:57:29] [PASSED] 47 VFs
[23:57:29] [PASSED] 48 VFs
[23:57:29] [PASSED] 49 VFs
[23:57:29] [PASSED] 50 VFs
[23:57:29] [PASSED] 51 VFs
[23:57:29] [PASSED] 52 VFs
[23:57:29] [PASSED] 53 VFs
[23:57:29] [PASSED] 54 VFs
[23:57:29] [PASSED] 55 VFs
[23:57:29] [PASSED] 56 VFs
[23:57:29] [PASSED] 57 VFs
[23:57:29] [PASSED] 58 VFs
[23:57:29] [PASSED] 59 VFs
[23:57:29] [PASSED] 60 VFs
[23:57:29] [PASSED] 61 VFs
[23:57:29] [PASSED] 62 VFs
[23:57:29] [PASSED] 63 VFs
[23:57:29] ================== [PASSED] fair_contexts ==================
[23:57:29] ===================== fair_doorbells  ======================
[23:57:29] [PASSED] 1 VF
[23:57:29] [PASSED] 2 VFs
[23:57:29] [PASSED] 3 VFs
[23:57:29] [PASSED] 4 VFs
[23:57:29] [PASSED] 5 VFs
[23:57:29] [PASSED] 6 VFs
[23:57:29] [PASSED] 7 VFs
[23:57:29] [PASSED] 8 VFs
[23:57:29] [PASSED] 9 VFs
[23:57:29] [PASSED] 10 VFs
[23:57:29] [PASSED] 11 VFs
[23:57:29] [PASSED] 12 VFs
[23:57:29] [PASSED] 13 VFs
[23:57:29] [PASSED] 14 VFs
[23:57:29] [PASSED] 15 VFs
[23:57:29] [PASSED] 16 VFs
[23:57:29] [PASSED] 17 VFs
[23:57:29] [PASSED] 18 VFs
[23:57:29] [PASSED] 19 VFs
[23:57:29] [PASSED] 20 VFs
[23:57:29] [PASSED] 21 VFs
[23:57:29] [PASSED] 22 VFs
[23:57:29] [PASSED] 23 VFs
[23:57:29] [PASSED] 24 VFs
[23:57:29] [PASSED] 25 VFs
[23:57:29] [PASSED] 26 VFs
[23:57:29] [PASSED] 27 VFs
[23:57:29] [PASSED] 28 VFs
[23:57:29] [PASSED] 29 VFs
[23:57:29] [PASSED] 30 VFs
[23:57:29] [PASSED] 31 VFs
[23:57:29] [PASSED] 32 VFs
[23:57:29] [PASSED] 33 VFs
[23:57:29] [PASSED] 34 VFs
[23:57:29] [PASSED] 35 VFs
[23:57:29] [PASSED] 36 VFs
[23:57:29] [PASSED] 37 VFs
[23:57:29] [PASSED] 38 VFs
[23:57:29] [PASSED] 39 VFs
[23:57:29] [PASSED] 40 VFs
[23:57:29] [PASSED] 41 VFs
[23:57:29] [PASSED] 42 VFs
[23:57:29] [PASSED] 43 VFs
[23:57:29] [PASSED] 44 VFs
[23:57:29] [PASSED] 45 VFs
[23:57:29] [PASSED] 46 VFs
[23:57:29] [PASSED] 47 VFs
[23:57:29] [PASSED] 48 VFs
[23:57:29] [PASSED] 49 VFs
[23:57:29] [PASSED] 50 VFs
[23:57:29] [PASSED] 51 VFs
[23:57:29] [PASSED] 52 VFs
[23:57:29] [PASSED] 53 VFs
[23:57:29] [PASSED] 54 VFs
[23:57:29] [PASSED] 55 VFs
[23:57:29] [PASSED] 56 VFs
[23:57:29] [PASSED] 57 VFs
[23:57:29] [PASSED] 58 VFs
[23:57:29] [PASSED] 59 VFs
[23:57:29] [PASSED] 60 VFs
[23:57:29] [PASSED] 61 VFs
[23:57:29] [PASSED] 62 VFs
[23:57:29] [PASSED] 63 VFs
[23:57:29] ================= [PASSED] fair_doorbells ==================
[23:57:29] ======================== fair_ggtt  ========================
[23:57:29] [PASSED] 1 VF
[23:57:29] [PASSED] 2 VFs
[23:57:29] [PASSED] 3 VFs
[23:57:29] [PASSED] 4 VFs
[23:57:29] [PASSED] 5 VFs
[23:57:29] [PASSED] 6 VFs
[23:57:29] [PASSED] 7 VFs
[23:57:29] [PASSED] 8 VFs
[23:57:29] [PASSED] 9 VFs
[23:57:29] [PASSED] 10 VFs
[23:57:29] [PASSED] 11 VFs
[23:57:29] [PASSED] 12 VFs
[23:57:29] [PASSED] 13 VFs
[23:57:29] [PASSED] 14 VFs
[23:57:29] [PASSED] 15 VFs
[23:57:29] [PASSED] 16 VFs
[23:57:29] [PASSED] 17 VFs
[23:57:29] [PASSED] 18 VFs
[23:57:29] [PASSED] 19 VFs
[23:57:29] [PASSED] 20 VFs
[23:57:29] [PASSED] 21 VFs
[23:57:29] [PASSED] 22 VFs
[23:57:29] [PASSED] 23 VFs
[23:57:29] [PASSED] 24 VFs
[23:57:29] [PASSED] 25 VFs
[23:57:29] [PASSED] 26 VFs
[23:57:29] [PASSED] 27 VFs
[23:57:29] [PASSED] 28 VFs
[23:57:29] [PASSED] 29 VFs
[23:57:29] [PASSED] 30 VFs
[23:57:29] [PASSED] 31 VFs
[23:57:29] [PASSED] 32 VFs
[23:57:29] [PASSED] 33 VFs
[23:57:29] [PASSED] 34 VFs
[23:57:29] [PASSED] 35 VFs
[23:57:29] [PASSED] 36 VFs
[23:57:29] [PASSED] 37 VFs
[23:57:29] [PASSED] 38 VFs
[23:57:29] [PASSED] 39 VFs
[23:57:29] [PASSED] 40 VFs
[23:57:29] [PASSED] 41 VFs
[23:57:29] [PASSED] 42 VFs
[23:57:29] [PASSED] 43 VFs
[23:57:29] [PASSED] 44 VFs
[23:57:29] [PASSED] 45 VFs
[23:57:29] [PASSED] 46 VFs
[23:57:29] [PASSED] 47 VFs
[23:57:29] [PASSED] 48 VFs
[23:57:29] [PASSED] 49 VFs
[23:57:29] [PASSED] 50 VFs
[23:57:29] [PASSED] 51 VFs
[23:57:29] [PASSED] 52 VFs
[23:57:29] [PASSED] 53 VFs
[23:57:29] [PASSED] 54 VFs
[23:57:29] [PASSED] 55 VFs
[23:57:29] [PASSED] 56 VFs
[23:57:29] [PASSED] 57 VFs
[23:57:29] [PASSED] 58 VFs
[23:57:29] [PASSED] 59 VFs
[23:57:29] [PASSED] 60 VFs
[23:57:29] [PASSED] 61 VFs
[23:57:29] [PASSED] 62 VFs
[23:57:29] [PASSED] 63 VFs
[23:57:29] ==================== [PASSED] fair_ggtt ====================
[23:57:29] ================== [PASSED] pf_gt_config ===================
[23:57:29] ===================== lmtt (1 subtest) =====================
[23:57:29] ======================== test_ops  =========================
[23:57:29] [PASSED] 2-level
[23:57:29] [PASSED] multi-level
[23:57:29] ==================== [PASSED] test_ops =====================
[23:57:29] ====================== [PASSED] lmtt =======================
[23:57:29] ================= pf_service (11 subtests) =================
[23:57:29] [PASSED] pf_negotiate_any
[23:57:29] [PASSED] pf_negotiate_base_match
[23:57:29] [PASSED] pf_negotiate_base_newer
[23:57:29] [PASSED] pf_negotiate_base_next
[23:57:29] [SKIPPED] pf_negotiate_base_older
[23:57:29] [PASSED] pf_negotiate_base_prev
[23:57:29] [PASSED] pf_negotiate_latest_match
[23:57:29] [PASSED] pf_negotiate_latest_newer
[23:57:29] [PASSED] pf_negotiate_latest_next
[23:57:29] [SKIPPED] pf_negotiate_latest_older
[23:57:29] [SKIPPED] pf_negotiate_latest_prev
[23:57:29] =================== [PASSED] pf_service ====================
[23:57:29] ================= xe_guc_g2g (2 subtests) ==================
[23:57:29] ============== xe_live_guc_g2g_kunit_default  ==============
[23:57:29] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[23:57:29] ============== xe_live_guc_g2g_kunit_allmem  ===============
[23:57:29] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[23:57:29] =================== [SKIPPED] xe_guc_g2g ===================
[23:57:29] =================== xe_mocs (2 subtests) ===================
[23:57:29] ================ xe_live_mocs_kernel_kunit  ================
[23:57:29] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[23:57:29] ================ xe_live_mocs_reset_kunit  =================
[23:57:29] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[23:57:29] ==================== [SKIPPED] xe_mocs =====================
[23:57:29] ================= xe_migrate (2 subtests) ==================
[23:57:29] ================= xe_migrate_sanity_kunit  =================
[23:57:29] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[23:57:29] ================== xe_validate_ccs_kunit  ==================
[23:57:29] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[23:57:29] =================== [SKIPPED] xe_migrate ===================
[23:57:29] ================== xe_dma_buf (1 subtest) ==================
[23:57:29] ==================== xe_dma_buf_kunit  =====================
[23:57:29] ================ [SKIPPED] xe_dma_buf_kunit ================
[23:57:29] =================== [SKIPPED] xe_dma_buf ===================
[23:57:29] ================= xe_bo_shrink (1 subtest) =================
[23:57:29] =================== xe_bo_shrink_kunit  ====================
[23:57:29] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[23:57:29] ================== [SKIPPED] xe_bo_shrink ==================
[23:57:29] ==================== xe_bo (2 subtests) ====================
[23:57:29] ================== xe_ccs_migrate_kunit  ===================
[23:57:29] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[23:57:29] ==================== xe_bo_evict_kunit  ====================
[23:57:29] =============== [SKIPPED] xe_bo_evict_kunit ================
[23:57:29] ===================== [SKIPPED] xe_bo ======================
[23:57:29] ==================== args (13 subtests) ====================
[23:57:29] [PASSED] count_args_test
[23:57:29] [PASSED] call_args_example
[23:57:29] [PASSED] call_args_test
[23:57:29] [PASSED] drop_first_arg_example
[23:57:29] [PASSED] drop_first_arg_test
[23:57:29] [PASSED] first_arg_example
[23:57:29] [PASSED] first_arg_test
[23:57:29] [PASSED] last_arg_example
[23:57:29] [PASSED] last_arg_test
[23:57:29] [PASSED] pick_arg_example
[23:57:29] [PASSED] if_args_example
[23:57:29] [PASSED] if_args_test
[23:57:29] [PASSED] sep_comma_example
[23:57:29] ====================== [PASSED] args =======================
[23:57:29] =================== xe_pci (3 subtests) ====================
[23:57:29] ==================== check_graphics_ip  ====================
[23:57:29] [PASSED] 12.00 Xe_LP
[23:57:29] [PASSED] 12.10 Xe_LP+
[23:57:29] [PASSED] 12.55 Xe_HPG
[23:57:29] [PASSED] 12.60 Xe_HPC
[23:57:29] [PASSED] 12.70 Xe_LPG
[23:57:29] [PASSED] 12.71 Xe_LPG
[23:57:29] [PASSED] 12.74 Xe_LPG+
[23:57:29] [PASSED] 20.01 Xe2_HPG
[23:57:29] [PASSED] 20.02 Xe2_HPG
[23:57:29] [PASSED] 20.04 Xe2_LPG
[23:57:29] [PASSED] 30.00 Xe3_LPG
[23:57:29] [PASSED] 30.01 Xe3_LPG
[23:57:29] [PASSED] 30.03 Xe3_LPG
[23:57:29] [PASSED] 30.04 Xe3_LPG
[23:57:29] [PASSED] 30.05 Xe3_LPG
[23:57:29] [PASSED] 35.11 Xe3p_XPC
[23:57:29] ================ [PASSED] check_graphics_ip ================
[23:57:29] ===================== check_media_ip  ======================
[23:57:29] [PASSED] 12.00 Xe_M
[23:57:29] [PASSED] 12.55 Xe_HPM
[23:57:29] [PASSED] 13.00 Xe_LPM+
[23:57:29] [PASSED] 13.01 Xe2_HPM
[23:57:29] [PASSED] 20.00 Xe2_LPM
[23:57:29] [PASSED] 30.00 Xe3_LPM
[23:57:29] [PASSED] 30.02 Xe3_LPM
[23:57:29] [PASSED] 35.00 Xe3p_LPM
[23:57:29] [PASSED] 35.03 Xe3p_HPM
[23:57:29] ================= [PASSED] check_media_ip ==================
[23:57:29] =================== check_platform_desc  ===================
[23:57:29] [PASSED] 0x9A60 (TIGERLAKE)
[23:57:29] [PASSED] 0x9A68 (TIGERLAKE)
[23:57:29] [PASSED] 0x9A70 (TIGERLAKE)
[23:57:29] [PASSED] 0x9A40 (TIGERLAKE)
[23:57:29] [PASSED] 0x9A49 (TIGERLAKE)
[23:57:29] [PASSED] 0x9A59 (TIGERLAKE)
[23:57:29] [PASSED] 0x9A78 (TIGERLAKE)
[23:57:29] [PASSED] 0x9AC0 (TIGERLAKE)
[23:57:29] [PASSED] 0x9AC9 (TIGERLAKE)
[23:57:29] [PASSED] 0x9AD9 (TIGERLAKE)
[23:57:29] [PASSED] 0x9AF8 (TIGERLAKE)
[23:57:29] [PASSED] 0x4C80 (ROCKETLAKE)
[23:57:29] [PASSED] 0x4C8A (ROCKETLAKE)
[23:57:29] [PASSED] 0x4C8B (ROCKETLAKE)
[23:57:29] [PASSED] 0x4C8C (ROCKETLAKE)
[23:57:29] [PASSED] 0x4C90 (ROCKETLAKE)
[23:57:29] [PASSED] 0x4C9A (ROCKETLAKE)
[23:57:29] [PASSED] 0x4680 (ALDERLAKE_S)
[23:57:29] [PASSED] 0x4682 (ALDERLAKE_S)
[23:57:29] [PASSED] 0x4688 (ALDERLAKE_S)
[23:57:29] [PASSED] 0x468A (ALDERLAKE_S)
[23:57:29] [PASSED] 0x468B (ALDERLAKE_S)
[23:57:29] [PASSED] 0x4690 (ALDERLAKE_S)
[23:57:29] [PASSED] 0x4692 (ALDERLAKE_S)
[23:57:29] [PASSED] 0x4693 (ALDERLAKE_S)
[23:57:29] [PASSED] 0x46A0 (ALDERLAKE_P)
[23:57:29] [PASSED] 0x46A1 (ALDERLAKE_P)
[23:57:29] [PASSED] 0x46A2 (ALDERLAKE_P)
[23:57:29] [PASSED] 0x46A3 (ALDERLAKE_P)
[23:57:29] [PASSED] 0x46A6 (ALDERLAKE_P)
[23:57:29] [PASSED] 0x46A8 (ALDERLAKE_P)
[23:57:29] [PASSED] 0x46AA (ALDERLAKE_P)
[23:57:29] [PASSED] 0x462A (ALDERLAKE_P)
[23:57:29] [PASSED] 0x4626 (ALDERLAKE_P)
[23:57:29] [PASSED] 0x4628 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[23:57:29] [PASSED] 0x46B0 (ALDERLAKE_P)
[23:57:29] [PASSED] 0x46B1 (ALDERLAKE_P)
[23:57:29] [PASSED] 0x46B2 (ALDERLAKE_P)
[23:57:29] [PASSED] 0x46B3 (ALDERLAKE_P)
[23:57:29] [PASSED] 0x46C0 (ALDERLAKE_P)
[23:57:29] [PASSED] 0x46C1 (ALDERLAKE_P)
[23:57:29] [PASSED] 0x46C2 (ALDERLAKE_P)
[23:57:29] [PASSED] 0x46C3 (ALDERLAKE_P)
[23:57:29] [PASSED] 0x46D0 (ALDERLAKE_N)
[23:57:29] [PASSED] 0x46D1 (ALDERLAKE_N)
[23:57:29] [PASSED] 0x46D2 (ALDERLAKE_N)
[23:57:29] [PASSED] 0x46D3 (ALDERLAKE_N)
[23:57:29] [PASSED] 0x46D4 (ALDERLAKE_N)
[23:57:29] [PASSED] 0xA721 (ALDERLAKE_P)
[23:57:29] [PASSED] 0xA7A1 (ALDERLAKE_P)
[23:57:29] [PASSED] 0xA7A9 (ALDERLAKE_P)
[23:57:29] [PASSED] 0xA7AC (ALDERLAKE_P)
[23:57:29] [PASSED] 0xA7AD (ALDERLAKE_P)
[23:57:29] [PASSED] 0xA720 (ALDERLAKE_P)
[23:57:29] [PASSED] 0xA7A0 (ALDERLAKE_P)
[23:57:29] [PASSED] 0xA7A8 (ALDERLAKE_P)
[23:57:29] [PASSED] 0xA7AA (ALDERLAKE_P)
[23:57:29] [PASSED] 0xA7AB (ALDERLAKE_P)
[23:57:29] [PASSED] 0xA780 (ALDERLAKE_S)
[23:57:29] [PASSED] 0xA781 (ALDERLAKE_S)
[23:57:29] [PASSED] 0xA782 (ALDERLAKE_S)
[23:57:29] [PASSED] 0xA783 (ALDERLAKE_S)
[23:57:29] [PASSED] 0xA788 (ALDERLAKE_S)
[23:57:29] [PASSED] 0xA789 (ALDERLAKE_S)
[23:57:29] [PASSED] 0xA78A (ALDERLAKE_S)
[23:57:29] [PASSED] 0xA78B (ALDERLAKE_S)
[23:57:29] [PASSED] 0x4905 (DG1)
[23:57:29] [PASSED] 0x4906 (DG1)
[23:57:29] [PASSED] 0x4907 (DG1)
[23:57:29] [PASSED] 0x4908 (DG1)
[23:57:29] [PASSED] 0x4909 (DG1)
[23:57:29] [PASSED] 0x56C0 (DG2)
[23:57:29] [PASSED] 0x56C2 (DG2)
[23:57:29] [PASSED] 0x56C1 (DG2)
[23:57:29] [PASSED] 0x7D51 (METEORLAKE)
[23:57:29] [PASSED] 0x7DD1 (METEORLAKE)
[23:57:29] [PASSED] 0x7D41 (METEORLAKE)
[23:57:29] [PASSED] 0x7D67 (METEORLAKE)
[23:57:29] [PASSED] 0xB640 (METEORLAKE)
[23:57:29] [PASSED] 0x56A0 (DG2)
[23:57:29] [PASSED] 0x56A1 (DG2)
[23:57:29] [PASSED] 0x56A2 (DG2)
[23:57:29] [PASSED] 0x56BE (DG2)
[23:57:29] [PASSED] 0x56BF (DG2)
[23:57:29] [PASSED] 0x5690 (DG2)
[23:57:29] [PASSED] 0x5691 (DG2)
[23:57:29] [PASSED] 0x5692 (DG2)
[23:57:29] [PASSED] 0x56A5 (DG2)
[23:57:29] [PASSED] 0x56A6 (DG2)
[23:57:29] [PASSED] 0x56B0 (DG2)
[23:57:29] [PASSED] 0x56B1 (DG2)
[23:57:29] [PASSED] 0x56BA (DG2)
[23:57:29] [PASSED] 0x56BB (DG2)
[23:57:29] [PASSED] 0x56BC (DG2)
[23:57:29] [PASSED] 0x56BD (DG2)
[23:57:29] [PASSED] 0x5693 (DG2)
[23:57:29] [PASSED] 0x5694 (DG2)
[23:57:29] [PASSED] 0x5695 (DG2)
[23:57:29] [PASSED] 0x56A3 (DG2)
[23:57:29] [PASSED] 0x56A4 (DG2)
[23:57:29] [PASSED] 0x56B2 (DG2)
[23:57:29] [PASSED] 0x56B3 (DG2)
[23:57:29] [PASSED] 0x5696 (DG2)
[23:57:29] [PASSED] 0x5697 (DG2)
[23:57:29] [PASSED] 0xB69 (PVC)
[23:57:29] [PASSED] 0xB6E (PVC)
[23:57:29] [PASSED] 0xBD4 (PVC)
[23:57:29] [PASSED] 0xBD5 (PVC)
[23:57:29] [PASSED] 0xBD6 (PVC)
[23:57:29] [PASSED] 0xBD7 (PVC)
[23:57:29] [PASSED] 0xBD8 (PVC)
[23:57:29] [PASSED] 0xBD9 (PVC)
[23:57:29] [PASSED] 0xBDA (PVC)
[23:57:29] [PASSED] 0xBDB (PVC)
[23:57:29] [PASSED] 0xBE0 (PVC)
[23:57:29] [PASSED] 0xBE1 (PVC)
[23:57:29] [PASSED] 0xBE5 (PVC)
[23:57:29] [PASSED] 0x7D40 (METEORLAKE)
[23:57:29] [PASSED] 0x7D45 (METEORLAKE)
[23:57:29] [PASSED] 0x7D55 (METEORLAKE)
[23:57:29] [PASSED] 0x7D60 (METEORLAKE)
[23:57:29] [PASSED] 0x7DD5 (METEORLAKE)
[23:57:29] [PASSED] 0x6420 (LUNARLAKE)
[23:57:29] [PASSED] 0x64A0 (LUNARLAKE)
[23:57:29] [PASSED] 0x64B0 (LUNARLAKE)
[23:57:29] [PASSED] 0xE202 (BATTLEMAGE)
[23:57:29] [PASSED] 0xE209 (BATTLEMAGE)
[23:57:29] [PASSED] 0xE20B (BATTLEMAGE)
[23:57:29] [PASSED] 0xE20C (BATTLEMAGE)
[23:57:29] [PASSED] 0xE20D (BATTLEMAGE)
[23:57:29] [PASSED] 0xE210 (BATTLEMAGE)
[23:57:29] [PASSED] 0xE211 (BATTLEMAGE)
[23:57:29] [PASSED] 0xE212 (BATTLEMAGE)
[23:57:29] [PASSED] 0xE216 (BATTLEMAGE)
[23:57:29] [PASSED] 0xE220 (BATTLEMAGE)
[23:57:29] [PASSED] 0xE221 (BATTLEMAGE)
[23:57:29] [PASSED] 0xE222 (BATTLEMAGE)
[23:57:29] [PASSED] 0xE223 (BATTLEMAGE)
[23:57:29] [PASSED] 0xB080 (PANTHERLAKE)
[23:57:29] [PASSED] 0xB081 (PANTHERLAKE)
[23:57:29] [PASSED] 0xB082 (PANTHERLAKE)
[23:57:29] [PASSED] 0xB083 (PANTHERLAKE)
[23:57:29] [PASSED] 0xB084 (PANTHERLAKE)
[23:57:29] [PASSED] 0xB085 (PANTHERLAKE)
[23:57:29] [PASSED] 0xB086 (PANTHERLAKE)
[23:57:29] [PASSED] 0xB087 (PANTHERLAKE)
[23:57:29] [PASSED] 0xB08F (PANTHERLAKE)
[23:57:29] [PASSED] 0xB090 (PANTHERLAKE)
[23:57:29] [PASSED] 0xB0A0 (PANTHERLAKE)
[23:57:29] [PASSED] 0xB0B0 (PANTHERLAKE)
[23:57:29] [PASSED] 0xFD80 (PANTHERLAKE)
[23:57:29] [PASSED] 0xFD81 (PANTHERLAKE)
[23:57:29] [PASSED] 0xD740 (NOVALAKE_S)
[23:57:29] [PASSED] 0xD741 (NOVALAKE_S)
[23:57:29] [PASSED] 0xD742 (NOVALAKE_S)
[23:57:29] [PASSED] 0xD743 (NOVALAKE_S)
[23:57:29] [PASSED] 0xD744 (NOVALAKE_S)
[23:57:29] [PASSED] 0xD745 (NOVALAKE_S)
[23:57:29] [PASSED] 0x674C (CRESCENTISLAND)
[23:57:29] =============== [PASSED] check_platform_desc ===============
[23:57:29] ===================== [PASSED] xe_pci ======================
[23:57:29] =================== xe_rtp (2 subtests) ====================
[23:57:29] =============== xe_rtp_process_to_sr_tests  ================
[23:57:29] [PASSED] coalesce-same-reg
[23:57:29] [PASSED] no-match-no-add
[23:57:29] [PASSED] match-or
[23:57:29] [PASSED] match-or-xfail
[23:57:29] [PASSED] no-match-no-add-multiple-rules
[23:57:29] [PASSED] two-regs-two-entries
[23:57:29] [PASSED] clr-one-set-other
[23:57:29] [PASSED] set-field
[23:57:29] [PASSED] conflict-duplicate
[23:57:29] [PASSED] conflict-not-disjoint
[23:57:29] [PASSED] conflict-reg-type
[23:57:29] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[23:57:29] ================== xe_rtp_process_tests  ===================
[23:57:29] [PASSED] active1
[23:57:29] [PASSED] active2
[23:57:29] [PASSED] active-inactive
[23:57:29] [PASSED] inactive-active
[23:57:29] [PASSED] inactive-1st_or_active-inactive
[23:57:29] [PASSED] inactive-2nd_or_active-inactive
[23:57:29] [PASSED] inactive-last_or_active-inactive
[23:57:29] [PASSED] inactive-no_or_active-inactive
[23:57:29] ============== [PASSED] xe_rtp_process_tests ===============
[23:57:29] ===================== [PASSED] xe_rtp ======================
[23:57:29] ==================== xe_wa (1 subtest) =====================
[23:57:29] ======================== xe_wa_gt  =========================
[23:57:29] [PASSED] TIGERLAKE B0
[23:57:29] [PASSED] DG1 A0
[23:57:29] [PASSED] DG1 B0
[23:57:29] [PASSED] ALDERLAKE_S A0
[23:57:29] [PASSED] ALDERLAKE_S B0
[23:57:29] [PASSED] ALDERLAKE_S C0
[23:57:29] [PASSED] ALDERLAKE_S D0
[23:57:29] [PASSED] ALDERLAKE_P A0
[23:57:29] [PASSED] ALDERLAKE_P B0
[23:57:29] [PASSED] ALDERLAKE_P C0
[23:57:29] [PASSED] ALDERLAKE_S RPLS D0
[23:57:29] [PASSED] ALDERLAKE_P RPLU E0
[23:57:29] [PASSED] DG2 G10 C0
[23:57:29] [PASSED] DG2 G11 B1
[23:57:29] [PASSED] DG2 G12 A1
[23:57:29] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:57:29] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:57:29] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[23:57:29] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[23:57:29] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[23:57:29] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[23:57:29] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[23:57:29] ==================== [PASSED] xe_wa_gt =====================
[23:57:29] ====================== [PASSED] xe_wa ======================
[23:57:29] ============================================================
[23:57:29] Testing complete. Ran 512 tests: passed: 494, skipped: 18
[23:57:29] Elapsed time: 36.240s total, 4.202s configuring, 31.521s building, 0.470s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[23:57:29] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:57:31] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:57:56] Starting KUnit Kernel (1/1)...
[23:57:56] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:57:56] ============ drm_test_pick_cmdline (2 subtests) ============
[23:57:56] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[23:57:56] =============== drm_test_pick_cmdline_named  ===============
[23:57:56] [PASSED] NTSC
[23:57:56] [PASSED] NTSC-J
[23:57:56] [PASSED] PAL
[23:57:56] [PASSED] PAL-M
[23:57:56] =========== [PASSED] drm_test_pick_cmdline_named ===========
[23:57:56] ============== [PASSED] drm_test_pick_cmdline ==============
[23:57:57] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[23:57:57] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[23:57:57] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[23:57:57] =========== drm_validate_clone_mode (2 subtests) ===========
[23:57:57] ============== drm_test_check_in_clone_mode  ===============
[23:57:57] [PASSED] in_clone_mode
[23:57:57] [PASSED] not_in_clone_mode
[23:57:57] ========== [PASSED] drm_test_check_in_clone_mode ===========
[23:57:57] =============== drm_test_check_valid_clones  ===============
[23:57:57] [PASSED] not_in_clone_mode
[23:57:57] [PASSED] valid_clone
[23:57:57] [PASSED] invalid_clone
[23:57:57] =========== [PASSED] drm_test_check_valid_clones ===========
[23:57:57] ============= [PASSED] drm_validate_clone_mode =============
[23:57:57] ============= drm_validate_modeset (1 subtest) =============
[23:57:57] [PASSED] drm_test_check_connector_changed_modeset
[23:57:57] ============== [PASSED] drm_validate_modeset ===============
[23:57:57] ====== drm_test_bridge_get_current_state (2 subtests) ======
[23:57:57] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[23:57:57] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[23:57:57] ======== [PASSED] drm_test_bridge_get_current_state ========
[23:57:57] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[23:57:57] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[23:57:57] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[23:57:57] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[23:57:57] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[23:57:57] ============== drm_bridge_alloc (2 subtests) ===============
[23:57:57] [PASSED] drm_test_drm_bridge_alloc_basic
[23:57:57] [PASSED] drm_test_drm_bridge_alloc_get_put
[23:57:57] ================ [PASSED] drm_bridge_alloc =================
[23:57:57] ================== drm_buddy (9 subtests) ==================
[23:57:57] [PASSED] drm_test_buddy_alloc_limit
[23:57:57] [PASSED] drm_test_buddy_alloc_optimistic
[23:57:57] [PASSED] drm_test_buddy_alloc_pessimistic
[23:57:57] [PASSED] drm_test_buddy_alloc_pathological
[23:57:57] [PASSED] drm_test_buddy_alloc_contiguous
[23:57:57] [PASSED] drm_test_buddy_alloc_clear
[23:57:57] [PASSED] drm_test_buddy_alloc_range_bias
[23:57:57] [PASSED] drm_test_buddy_fragmentation_performance
[23:57:57] [PASSED] drm_test_buddy_alloc_exceeds_max_order
[23:57:57] ==================== [PASSED] drm_buddy ====================
[23:57:57] ============= drm_cmdline_parser (40 subtests) =============
[23:57:57] [PASSED] drm_test_cmdline_force_d_only
[23:57:57] [PASSED] drm_test_cmdline_force_D_only_dvi
[23:57:57] [PASSED] drm_test_cmdline_force_D_only_hdmi
[23:57:57] [PASSED] drm_test_cmdline_force_D_only_not_digital
[23:57:57] [PASSED] drm_test_cmdline_force_e_only
[23:57:57] [PASSED] drm_test_cmdline_res
[23:57:57] [PASSED] drm_test_cmdline_res_vesa
[23:57:57] [PASSED] drm_test_cmdline_res_vesa_rblank
[23:57:57] [PASSED] drm_test_cmdline_res_rblank
[23:57:57] [PASSED] drm_test_cmdline_res_bpp
[23:57:57] [PASSED] drm_test_cmdline_res_refresh
[23:57:57] [PASSED] drm_test_cmdline_res_bpp_refresh
[23:57:57] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[23:57:57] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[23:57:57] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[23:57:57] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[23:57:57] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[23:57:57] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[23:57:57] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[23:57:57] [PASSED] drm_test_cmdline_res_margins_force_on
[23:57:57] [PASSED] drm_test_cmdline_res_vesa_margins
[23:57:57] [PASSED] drm_test_cmdline_name
[23:57:57] [PASSED] drm_test_cmdline_name_bpp
[23:57:57] [PASSED] drm_test_cmdline_name_option
[23:57:57] [PASSED] drm_test_cmdline_name_bpp_option
[23:57:57] [PASSED] drm_test_cmdline_rotate_0
[23:57:57] [PASSED] drm_test_cmdline_rotate_90
[23:57:57] [PASSED] drm_test_cmdline_rotate_180
[23:57:57] [PASSED] drm_test_cmdline_rotate_270
[23:57:57] [PASSED] drm_test_cmdline_hmirror
[23:57:57] [PASSED] drm_test_cmdline_vmirror
[23:57:57] [PASSED] drm_test_cmdline_margin_options
[23:57:57] [PASSED] drm_test_cmdline_multiple_options
[23:57:57] [PASSED] drm_test_cmdline_bpp_extra_and_option
[23:57:57] [PASSED] drm_test_cmdline_extra_and_option
[23:57:57] [PASSED] drm_test_cmdline_freestanding_options
[23:57:57] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[23:57:57] [PASSED] drm_test_cmdline_panel_orientation
[23:57:57] ================ drm_test_cmdline_invalid  =================
[23:57:57] [PASSED] margin_only
[23:57:57] [PASSED] interlace_only
[23:57:57] [PASSED] res_missing_x
[23:57:57] [PASSED] res_missing_y
[23:57:57] [PASSED] res_bad_y
[23:57:57] [PASSED] res_missing_y_bpp
[23:57:57] [PASSED] res_bad_bpp
[23:57:57] [PASSED] res_bad_refresh
[23:57:57] [PASSED] res_bpp_refresh_force_on_off
[23:57:57] [PASSED] res_invalid_mode
[23:57:57] [PASSED] res_bpp_wrong_place_mode
[23:57:57] [PASSED] name_bpp_refresh
[23:57:57] [PASSED] name_refresh
[23:57:57] [PASSED] name_refresh_wrong_mode
[23:57:57] [PASSED] name_refresh_invalid_mode
[23:57:57] [PASSED] rotate_multiple
[23:57:57] [PASSED] rotate_invalid_val
[23:57:57] [PASSED] rotate_truncated
[23:57:57] [PASSED] invalid_option
[23:57:57] [PASSED] invalid_tv_option
[23:57:57] [PASSED] truncated_tv_option
[23:57:57] ============ [PASSED] drm_test_cmdline_invalid =============
[23:57:57] =============== drm_test_cmdline_tv_options  ===============
[23:57:57] [PASSED] NTSC
[23:57:57] [PASSED] NTSC_443
[23:57:57] [PASSED] NTSC_J
[23:57:57] [PASSED] PAL
[23:57:57] [PASSED] PAL_M
[23:57:57] [PASSED] PAL_N
[23:57:57] [PASSED] SECAM
[23:57:57] [PASSED] MONO_525
[23:57:57] [PASSED] MONO_625
[23:57:57] =========== [PASSED] drm_test_cmdline_tv_options ===========
[23:57:57] =============== [PASSED] drm_cmdline_parser ================
[23:57:57] ========== drmm_connector_hdmi_init (20 subtests) ==========
[23:57:57] [PASSED] drm_test_connector_hdmi_init_valid
[23:57:57] [PASSED] drm_test_connector_hdmi_init_bpc_8
[23:57:57] [PASSED] drm_test_connector_hdmi_init_bpc_10
[23:57:57] [PASSED] drm_test_connector_hdmi_init_bpc_12
[23:57:57] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[23:57:57] [PASSED] drm_test_connector_hdmi_init_bpc_null
[23:57:57] [PASSED] drm_test_connector_hdmi_init_formats_empty
[23:57:57] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[23:57:57] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[23:57:57] [PASSED] supported_formats=0x9 yuv420_allowed=1
[23:57:57] [PASSED] supported_formats=0x9 yuv420_allowed=0
[23:57:57] [PASSED] supported_formats=0x3 yuv420_allowed=1
[23:57:57] [PASSED] supported_formats=0x3 yuv420_allowed=0
[23:57:57] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[23:57:57] [PASSED] drm_test_connector_hdmi_init_null_ddc
[23:57:57] [PASSED] drm_test_connector_hdmi_init_null_product
[23:57:57] [PASSED] drm_test_connector_hdmi_init_null_vendor
[23:57:57] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[23:57:57] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[23:57:57] [PASSED] drm_test_connector_hdmi_init_product_valid
[23:57:57] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[23:57:57] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[23:57:57] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[23:57:57] ========= drm_test_connector_hdmi_init_type_valid  =========
[23:57:57] [PASSED] HDMI-A
[23:57:57] [PASSED] HDMI-B
[23:57:57] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[23:57:57] ======== drm_test_connector_hdmi_init_type_invalid  ========
[23:57:57] [PASSED] Unknown
[23:57:57] [PASSED] VGA
[23:57:57] [PASSED] DVI-I
[23:57:57] [PASSED] DVI-D
[23:57:57] [PASSED] DVI-A
[23:57:57] [PASSED] Composite
[23:57:57] [PASSED] SVIDEO
[23:57:57] [PASSED] LVDS
[23:57:57] [PASSED] Component
[23:57:57] [PASSED] DIN
[23:57:57] [PASSED] DP
[23:57:57] [PASSED] TV
[23:57:57] [PASSED] eDP
[23:57:57] [PASSED] Virtual
[23:57:57] [PASSED] DSI
[23:57:57] [PASSED] DPI
[23:57:57] [PASSED] Writeback
[23:57:57] [PASSED] SPI
[23:57:57] [PASSED] USB
[23:57:57] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[23:57:57] ============ [PASSED] drmm_connector_hdmi_init =============
[23:57:57] ============= drmm_connector_init (3 subtests) =============
[23:57:57] [PASSED] drm_test_drmm_connector_init
[23:57:57] [PASSED] drm_test_drmm_connector_init_null_ddc
[23:57:57] ========= drm_test_drmm_connector_init_type_valid  =========
[23:57:57] [PASSED] Unknown
[23:57:57] [PASSED] VGA
[23:57:57] [PASSED] DVI-I
[23:57:57] [PASSED] DVI-D
[23:57:57] [PASSED] DVI-A
[23:57:57] [PASSED] Composite
[23:57:57] [PASSED] SVIDEO
[23:57:57] [PASSED] LVDS
[23:57:57] [PASSED] Component
[23:57:57] [PASSED] DIN
[23:57:57] [PASSED] DP
[23:57:57] [PASSED] HDMI-A
[23:57:57] [PASSED] HDMI-B
[23:57:57] [PASSED] TV
[23:57:57] [PASSED] eDP
[23:57:57] [PASSED] Virtual
[23:57:57] [PASSED] DSI
[23:57:57] [PASSED] DPI
[23:57:57] [PASSED] Writeback
[23:57:57] [PASSED] SPI
[23:57:57] [PASSED] USB
[23:57:57] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[23:57:57] =============== [PASSED] drmm_connector_init ===============
[23:57:57] ========= drm_connector_dynamic_init (6 subtests) ==========
[23:57:57] [PASSED] drm_test_drm_connector_dynamic_init
[23:57:57] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[23:57:57] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[23:57:57] [PASSED] drm_test_drm_connector_dynamic_init_properties
[23:57:57] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[23:57:57] [PASSED] Unknown
[23:57:57] [PASSED] VGA
[23:57:57] [PASSED] DVI-I
[23:57:57] [PASSED] DVI-D
[23:57:57] [PASSED] DVI-A
[23:57:57] [PASSED] Composite
[23:57:57] [PASSED] SVIDEO
[23:57:57] [PASSED] LVDS
[23:57:57] [PASSED] Component
[23:57:57] [PASSED] DIN
[23:57:57] [PASSED] DP
[23:57:57] [PASSED] HDMI-A
[23:57:57] [PASSED] HDMI-B
[23:57:57] [PASSED] TV
[23:57:57] [PASSED] eDP
[23:57:57] [PASSED] Virtual
[23:57:57] [PASSED] DSI
[23:57:57] [PASSED] DPI
[23:57:57] [PASSED] Writeback
[23:57:57] [PASSED] SPI
[23:57:57] [PASSED] USB
[23:57:57] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[23:57:57] ======== drm_test_drm_connector_dynamic_init_name  =========
[23:57:57] [PASSED] Unknown
[23:57:57] [PASSED] VGA
[23:57:57] [PASSED] DVI-I
[23:57:57] [PASSED] DVI-D
[23:57:57] [PASSED] DVI-A
[23:57:57] [PASSED] Composite
[23:57:57] [PASSED] SVIDEO
[23:57:57] [PASSED] LVDS
[23:57:57] [PASSED] Component
[23:57:57] [PASSED] DIN
[23:57:57] [PASSED] DP
[23:57:57] [PASSED] HDMI-A
[23:57:57] [PASSED] HDMI-B
[23:57:57] [PASSED] TV
[23:57:57] [PASSED] eDP
[23:57:57] [PASSED] Virtual
[23:57:57] [PASSED] DSI
[23:57:57] [PASSED] DPI
[23:57:57] [PASSED] Writeback
[23:57:57] [PASSED] SPI
[23:57:57] [PASSED] USB
[23:57:57] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[23:57:57] =========== [PASSED] drm_connector_dynamic_init ============
[23:57:57] ==== drm_connector_dynamic_register_early (4 subtests) =====
[23:57:57] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[23:57:57] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[23:57:57] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[23:57:57] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[23:57:57] ====== [PASSED] drm_connector_dynamic_register_early =======
[23:57:57] ======= drm_connector_dynamic_register (7 subtests) ========
[23:57:57] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[23:57:57] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[23:57:57] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[23:57:57] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[23:57:57] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[23:57:57] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[23:57:57] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[23:57:57] ========= [PASSED] drm_connector_dynamic_register ==========
[23:57:57] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[23:57:57] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[23:57:57] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[23:57:57] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[23:57:57] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[23:57:57] ========== drm_test_get_tv_mode_from_name_valid  ===========
[23:57:57] [PASSED] NTSC
[23:57:57] [PASSED] NTSC-443
[23:57:57] [PASSED] NTSC-J
[23:57:57] [PASSED] PAL
[23:57:57] [PASSED] PAL-M
[23:57:57] [PASSED] PAL-N
[23:57:57] [PASSED] SECAM
[23:57:57] [PASSED] Mono
[23:57:57] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[23:57:57] [PASSED] drm_test_get_tv_mode_from_name_truncated
[23:57:57] ============ [PASSED] drm_get_tv_mode_from_name ============
[23:57:57] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[23:57:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[23:57:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[23:57:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[23:57:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[23:57:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[23:57:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[23:57:57] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[23:57:57] [PASSED] VIC 96
[23:57:57] [PASSED] VIC 97
[23:57:57] [PASSED] VIC 101
[23:57:57] [PASSED] VIC 102
[23:57:57] [PASSED] VIC 106
[23:57:57] [PASSED] VIC 107
[23:57:57] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[23:57:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[23:57:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[23:57:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[23:57:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[23:57:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[23:57:57] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[23:57:57] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[23:57:57] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[23:57:57] [PASSED] Automatic
[23:57:57] [PASSED] Full
[23:57:57] [PASSED] Limited 16:235
[23:57:57] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[23:57:57] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[23:57:57] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[23:57:57] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[23:57:57] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[23:57:57] [PASSED] RGB
[23:57:57] [PASSED] YUV 4:2:0
[23:57:57] [PASSED] YUV 4:2:2
[23:57:57] [PASSED] YUV 4:4:4
[23:57:57] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[23:57:57] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[23:57:57] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[23:57:57] ============= drm_damage_helper (21 subtests) ==============
[23:57:57] [PASSED] drm_test_damage_iter_no_damage
[23:57:57] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[23:57:57] [PASSED] drm_test_damage_iter_no_damage_src_moved
[23:57:57] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[23:57:57] [PASSED] drm_test_damage_iter_no_damage_not_visible
[23:57:57] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[23:57:57] [PASSED] drm_test_damage_iter_no_damage_no_fb
[23:57:57] [PASSED] drm_test_damage_iter_simple_damage
[23:57:57] [PASSED] drm_test_damage_iter_single_damage
[23:57:57] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[23:57:57] [PASSED] drm_test_damage_iter_single_damage_outside_src
[23:57:57] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[23:57:57] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[23:57:57] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[23:57:57] [PASSED] drm_test_damage_iter_single_damage_src_moved
[23:57:57] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[23:57:57] [PASSED] drm_test_damage_iter_damage
[23:57:57] [PASSED] drm_test_damage_iter_damage_one_intersect
[23:57:57] [PASSED] drm_test_damage_iter_damage_one_outside
[23:57:57] [PASSED] drm_test_damage_iter_damage_src_moved
[23:57:57] [PASSED] drm_test_damage_iter_damage_not_visible
[23:57:57] ================ [PASSED] drm_damage_helper ================
[23:57:57] ============== drm_dp_mst_helper (3 subtests) ==============
[23:57:57] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[23:57:57] [PASSED] Clock 154000 BPP 30 DSC disabled
[23:57:57] [PASSED] Clock 234000 BPP 30 DSC disabled
[23:57:57] [PASSED] Clock 297000 BPP 24 DSC disabled
[23:57:57] [PASSED] Clock 332880 BPP 24 DSC enabled
[23:57:57] [PASSED] Clock 324540 BPP 24 DSC enabled
[23:57:57] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[23:57:57] ============== drm_test_dp_mst_calc_pbn_div  ===============
[23:57:57] [PASSED] Link rate 2000000 lane count 4
[23:57:57] [PASSED] Link rate 2000000 lane count 2
[23:57:57] [PASSED] Link rate 2000000 lane count 1
[23:57:57] [PASSED] Link rate 1350000 lane count 4
[23:57:57] [PASSED] Link rate 1350000 lane count 2
[23:57:57] [PASSED] Link rate 1350000 lane count 1
[23:57:57] [PASSED] Link rate 1000000 lane count 4
[23:57:57] [PASSED] Link rate 1000000 lane count 2
[23:57:57] [PASSED] Link rate 1000000 lane count 1
[23:57:57] [PASSED] Link rate 810000 lane count 4
[23:57:57] [PASSED] Link rate 810000 lane count 2
[23:57:57] [PASSED] Link rate 810000 lane count 1
[23:57:57] [PASSED] Link rate 540000 lane count 4
[23:57:57] [PASSED] Link rate 540000 lane count 2
[23:57:57] [PASSED] Link rate 540000 lane count 1
[23:57:57] [PASSED] Link rate 270000 lane count 4
[23:57:57] [PASSED] Link rate 270000 lane count 2
[23:57:57] [PASSED] Link rate 270000 lane count 1
[23:57:57] [PASSED] Link rate 162000 lane count 4
[23:57:57] [PASSED] Link rate 162000 lane count 2
[23:57:57] [PASSED] Link rate 162000 lane count 1
[23:57:57] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[23:57:57] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[23:57:57] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[23:57:57] [PASSED] DP_POWER_UP_PHY with port number
[23:57:57] [PASSED] DP_POWER_DOWN_PHY with port number
[23:57:57] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[23:57:57] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[23:57:57] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[23:57:57] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[23:57:57] [PASSED] DP_QUERY_PAYLOAD with port number
[23:57:57] [PASSED] DP_QUERY_PAYLOAD with VCPI
[23:57:57] [PASSED] DP_REMOTE_DPCD_READ with port number
[23:57:57] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[23:57:57] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[23:57:57] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[23:57:57] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[23:57:57] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[23:57:57] [PASSED] DP_REMOTE_I2C_READ with port number
[23:57:57] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[23:57:57] [PASSED] DP_REMOTE_I2C_READ with transactions array
[23:57:57] [PASSED] DP_REMOTE_I2C_WRITE with port number
[23:57:57] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[23:57:57] [PASSED] DP_REMOTE_I2C_WRITE with data array
[23:57:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[23:57:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[23:57:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[23:57:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[23:57:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[23:57:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[23:57:57] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[23:57:57] ================ [PASSED] drm_dp_mst_helper ================
[23:57:57] ================== drm_exec (7 subtests) ===================
[23:57:57] [PASSED] sanitycheck
[23:57:57] [PASSED] test_lock
[23:57:57] [PASSED] test_lock_unlock
[23:57:57] [PASSED] test_duplicates
[23:57:57] [PASSED] test_prepare
[23:57:57] [PASSED] test_prepare_array
[23:57:57] [PASSED] test_multiple_loops
[23:57:57] ==================== [PASSED] drm_exec =====================
[23:57:57] =========== drm_format_helper_test (17 subtests) ===========
[23:57:57] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[23:57:57] [PASSED] single_pixel_source_buffer
[23:57:57] [PASSED] single_pixel_clip_rectangle
[23:57:57] [PASSED] well_known_colors
[23:57:57] [PASSED] destination_pitch
[23:57:57] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[23:57:57] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[23:57:57] [PASSED] single_pixel_source_buffer
[23:57:57] [PASSED] single_pixel_clip_rectangle
[23:57:57] [PASSED] well_known_colors
[23:57:57] [PASSED] destination_pitch
[23:57:57] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[23:57:57] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[23:57:57] [PASSED] single_pixel_source_buffer
[23:57:57] [PASSED] single_pixel_clip_rectangle
[23:57:57] [PASSED] well_known_colors
[23:57:57] [PASSED] destination_pitch
[23:57:57] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[23:57:57] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[23:57:57] [PASSED] single_pixel_source_buffer
[23:57:57] [PASSED] single_pixel_clip_rectangle
[23:57:57] [PASSED] well_known_colors
[23:57:57] [PASSED] destination_pitch
[23:57:57] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[23:57:57] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[23:57:57] [PASSED] single_pixel_source_buffer
[23:57:57] [PASSED] single_pixel_clip_rectangle
[23:57:57] [PASSED] well_known_colors
[23:57:57] [PASSED] destination_pitch
[23:57:57] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[23:57:57] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[23:57:57] [PASSED] single_pixel_source_buffer
[23:57:57] [PASSED] single_pixel_clip_rectangle
[23:57:57] [PASSED] well_known_colors
[23:57:57] [PASSED] destination_pitch
[23:57:57] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[23:57:57] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[23:57:57] [PASSED] single_pixel_source_buffer
[23:57:57] [PASSED] single_pixel_clip_rectangle
[23:57:57] [PASSED] well_known_colors
[23:57:57] [PASSED] destination_pitch
[23:57:57] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[23:57:57] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[23:57:57] [PASSED] single_pixel_source_buffer
[23:57:57] [PASSED] single_pixel_clip_rectangle
[23:57:57] [PASSED] well_known_colors
[23:57:57] [PASSED] destination_pitch
[23:57:57] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[23:57:57] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[23:57:57] [PASSED] single_pixel_source_buffer
[23:57:57] [PASSED] single_pixel_clip_rectangle
[23:57:57] [PASSED] well_known_colors
[23:57:57] [PASSED] destination_pitch
[23:57:57] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[23:57:57] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[23:57:57] [PASSED] single_pixel_source_buffer
[23:57:57] [PASSED] single_pixel_clip_rectangle
[23:57:57] [PASSED] well_known_colors
[23:57:57] [PASSED] destination_pitch
[23:57:57] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[23:57:57] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[23:57:57] [PASSED] single_pixel_source_buffer
[23:57:57] [PASSED] single_pixel_clip_rectangle
[23:57:57] [PASSED] well_known_colors
[23:57:57] [PASSED] destination_pitch
[23:57:57] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[23:57:57] ============== drm_test_fb_xrgb8888_to_mono  ===============
[23:57:57] [PASSED] single_pixel_source_buffer
[23:57:57] [PASSED] single_pixel_clip_rectangle
[23:57:57] [PASSED] well_known_colors
[23:57:57] [PASSED] destination_pitch
[23:57:57] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[23:57:57] ==================== drm_test_fb_swab  =====================
[23:57:57] [PASSED] single_pixel_source_buffer
[23:57:57] [PASSED] single_pixel_clip_rectangle
[23:57:57] [PASSED] well_known_colors
[23:57:57] [PASSED] destination_pitch
[23:57:57] ================ [PASSED] drm_test_fb_swab =================
[23:57:57] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[23:57:57] [PASSED] single_pixel_source_buffer
[23:57:57] [PASSED] single_pixel_clip_rectangle
[23:57:57] [PASSED] well_known_colors
[23:57:57] [PASSED] destination_pitch
[23:57:57] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[23:57:57] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[23:57:57] [PASSED] single_pixel_source_buffer
[23:57:57] [PASSED] single_pixel_clip_rectangle
[23:57:57] [PASSED] well_known_colors
[23:57:57] [PASSED] destination_pitch
[23:57:57] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[23:57:57] ================= drm_test_fb_clip_offset  =================
[23:57:57] [PASSED] pass through
[23:57:57] [PASSED] horizontal offset
[23:57:57] [PASSED] vertical offset
[23:57:57] [PASSED] horizontal and vertical offset
[23:57:57] [PASSED] horizontal offset (custom pitch)
[23:57:57] [PASSED] vertical offset (custom pitch)
[23:57:57] [PASSED] horizontal and vertical offset (custom pitch)
[23:57:57] ============= [PASSED] drm_test_fb_clip_offset =============
[23:57:57] =================== drm_test_fb_memcpy  ====================
[23:57:57] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[23:57:57] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[23:57:57] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[23:57:57] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[23:57:57] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[23:57:57] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[23:57:57] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[23:57:57] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[23:57:57] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[23:57:57] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[23:57:57] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[23:57:57] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[23:57:57] =============== [PASSED] drm_test_fb_memcpy ================
[23:57:57] ============= [PASSED] drm_format_helper_test ==============
[23:57:57] ================= drm_format (18 subtests) =================
[23:57:57] [PASSED] drm_test_format_block_width_invalid
[23:57:57] [PASSED] drm_test_format_block_width_one_plane
[23:57:57] [PASSED] drm_test_format_block_width_two_plane
[23:57:57] [PASSED] drm_test_format_block_width_three_plane
[23:57:57] [PASSED] drm_test_format_block_width_tiled
[23:57:57] [PASSED] drm_test_format_block_height_invalid
[23:57:57] [PASSED] drm_test_format_block_height_one_plane
[23:57:57] [PASSED] drm_test_format_block_height_two_plane
[23:57:57] [PASSED] drm_test_format_block_height_three_plane
[23:57:57] [PASSED] drm_test_format_block_height_tiled
[23:57:57] [PASSED] drm_test_format_min_pitch_invalid
[23:57:57] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[23:57:57] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[23:57:57] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[23:57:57] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[23:57:57] [PASSED] drm_test_format_min_pitch_two_plane
[23:57:57] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[23:57:57] [PASSED] drm_test_format_min_pitch_tiled
[23:57:57] =================== [PASSED] drm_format ====================
[23:57:57] ============== drm_framebuffer (10 subtests) ===============
[23:57:57] ========== drm_test_framebuffer_check_src_coords  ==========
[23:57:57] [PASSED] Success: source fits into fb
[23:57:57] [PASSED] Fail: overflowing fb with x-axis coordinate
[23:57:57] [PASSED] Fail: overflowing fb with y-axis coordinate
[23:57:57] [PASSED] Fail: overflowing fb with source width
[23:57:57] [PASSED] Fail: overflowing fb with source height
[23:57:57] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[23:57:57] [PASSED] drm_test_framebuffer_cleanup
[23:57:57] =============== drm_test_framebuffer_create  ===============
[23:57:57] [PASSED] ABGR8888 normal sizes
[23:57:57] [PASSED] ABGR8888 max sizes
[23:57:57] [PASSED] ABGR8888 pitch greater than min required
[23:57:57] [PASSED] ABGR8888 pitch less than min required
[23:57:57] [PASSED] ABGR8888 Invalid width
[23:57:57] [PASSED] ABGR8888 Invalid buffer handle
[23:57:57] [PASSED] No pixel format
[23:57:57] [PASSED] ABGR8888 Width 0
[23:57:57] [PASSED] ABGR8888 Height 0
[23:57:57] [PASSED] ABGR8888 Out of bound height * pitch combination
[23:57:57] [PASSED] ABGR8888 Large buffer offset
[23:57:57] [PASSED] ABGR8888 Buffer offset for inexistent plane
[23:57:57] [PASSED] ABGR8888 Invalid flag
[23:57:57] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[23:57:57] [PASSED] ABGR8888 Valid buffer modifier
[23:57:57] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[23:57:57] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[23:57:57] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[23:57:57] [PASSED] NV12 Normal sizes
[23:57:57] [PASSED] NV12 Max sizes
[23:57:57] [PASSED] NV12 Invalid pitch
[23:57:57] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[23:57:57] [PASSED] NV12 different  modifier per-plane
[23:57:57] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[23:57:57] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[23:57:57] [PASSED] NV12 Modifier for inexistent plane
[23:57:57] [PASSED] NV12 Handle for inexistent plane
[23:57:57] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[23:57:57] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[23:57:57] [PASSED] YVU420 Normal sizes
[23:57:57] [PASSED] YVU420 Max sizes
[23:57:57] [PASSED] YVU420 Invalid pitch
[23:57:57] [PASSED] YVU420 Different pitches
[23:57:57] [PASSED] YVU420 Different buffer offsets/pitches
[23:57:57] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[23:57:57] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[23:57:57] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[23:57:57] [PASSED] YVU420 Valid modifier
[23:57:57] [PASSED] YVU420 Different modifiers per plane
[23:57:57] [PASSED] YVU420 Modifier for inexistent plane
[23:57:57] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[23:57:57] [PASSED] X0L2 Normal sizes
[23:57:57] [PASSED] X0L2 Max sizes
[23:57:57] [PASSED] X0L2 Invalid pitch
[23:57:57] [PASSED] X0L2 Pitch greater than minimum required
[23:57:57] [PASSED] X0L2 Handle for inexistent plane
[23:57:57] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[23:57:57] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[23:57:57] [PASSED] X0L2 Valid modifier
[23:57:57] [PASSED] X0L2 Modifier for inexistent plane
[23:57:57] =========== [PASSED] drm_test_framebuffer_create ===========
[23:57:57] [PASSED] drm_test_framebuffer_free
[23:57:57] [PASSED] drm_test_framebuffer_init
[23:57:57] [PASSED] drm_test_framebuffer_init_bad_format
[23:57:57] [PASSED] drm_test_framebuffer_init_dev_mismatch
[23:57:57] [PASSED] drm_test_framebuffer_lookup
[23:57:57] [PASSED] drm_test_framebuffer_lookup_inexistent
[23:57:57] [PASSED] drm_test_framebuffer_modifiers_not_supported
[23:57:57] ================= [PASSED] drm_framebuffer =================
[23:57:57] ================ drm_gem_shmem (8 subtests) ================
[23:57:57] [PASSED] drm_gem_shmem_test_obj_create
[23:57:57] [PASSED] drm_gem_shmem_test_obj_create_private
[23:57:57] [PASSED] drm_gem_shmem_test_pin_pages
[23:57:57] [PASSED] drm_gem_shmem_test_vmap
[23:57:57] [PASSED] drm_gem_shmem_test_get_sg_table
[23:57:57] [PASSED] drm_gem_shmem_test_get_pages_sgt
[23:57:57] [PASSED] drm_gem_shmem_test_madvise
[23:57:57] [PASSED] drm_gem_shmem_test_purge
[23:57:57] ================== [PASSED] drm_gem_shmem ==================
[23:57:57] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[23:57:57] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[23:57:57] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[23:57:57] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[23:57:57] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[23:57:57] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[23:57:57] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[23:57:57] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[23:57:57] [PASSED] Automatic
[23:57:57] [PASSED] Full
[23:57:57] [PASSED] Limited 16:235
[23:57:57] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[23:57:57] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[23:57:57] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[23:57:57] [PASSED] drm_test_check_disable_connector
[23:57:57] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[23:57:57] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[23:57:57] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[23:57:57] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[23:57:57] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[23:57:57] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[23:57:57] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[23:57:57] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[23:57:57] [PASSED] drm_test_check_output_bpc_dvi
[23:57:57] [PASSED] drm_test_check_output_bpc_format_vic_1
[23:57:57] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[23:57:57] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[23:57:57] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[23:57:57] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[23:57:57] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[23:57:57] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[23:57:57] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[23:57:57] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[23:57:57] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[23:57:57] [PASSED] drm_test_check_broadcast_rgb_value
[23:57:57] [PASSED] drm_test_check_bpc_8_value
[23:57:57] [PASSED] drm_test_check_bpc_10_value
[23:57:57] [PASSED] drm_test_check_bpc_12_value
[23:57:57] [PASSED] drm_test_check_format_value
[23:57:57] [PASSED] drm_test_check_tmds_char_value
[23:57:57] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[23:57:57] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[23:57:57] [PASSED] drm_test_check_mode_valid
[23:57:57] [PASSED] drm_test_check_mode_valid_reject
[23:57:57] [PASSED] drm_test_check_mode_valid_reject_rate
[23:57:57] [PASSED] drm_test_check_mode_valid_reject_max_clock
[23:57:57] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[23:57:57] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[23:57:57] [PASSED] drm_test_check_infoframes
[23:57:57] [PASSED] drm_test_check_reject_avi_infoframe
[23:57:57] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[23:57:57] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[23:57:57] [PASSED] drm_test_check_reject_audio_infoframe
[23:57:57] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[23:57:57] ================= drm_managed (2 subtests) =================
[23:57:57] [PASSED] drm_test_managed_release_action
[23:57:57] [PASSED] drm_test_managed_run_action
[23:57:57] =================== [PASSED] drm_managed ===================
[23:57:57] =================== drm_mm (6 subtests) ====================
[23:57:57] [PASSED] drm_test_mm_init
[23:57:57] [PASSED] drm_test_mm_debug
[23:57:57] [PASSED] drm_test_mm_align32
[23:57:57] [PASSED] drm_test_mm_align64
[23:57:57] [PASSED] drm_test_mm_lowest
[23:57:57] [PASSED] drm_test_mm_highest
[23:57:57] ===================== [PASSED] drm_mm ======================
[23:57:57] ============= drm_modes_analog_tv (5 subtests) =============
[23:57:57] [PASSED] drm_test_modes_analog_tv_mono_576i
[23:57:57] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[23:57:57] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[23:57:57] [PASSED] drm_test_modes_analog_tv_pal_576i
[23:57:57] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[23:57:57] =============== [PASSED] drm_modes_analog_tv ===============
[23:57:57] ============== drm_plane_helper (2 subtests) ===============
[23:57:57] =============== drm_test_check_plane_state  ================
[23:57:57] [PASSED] clipping_simple
[23:57:57] [PASSED] clipping_rotate_reflect
[23:57:57] [PASSED] positioning_simple
[23:57:57] [PASSED] upscaling
[23:57:57] [PASSED] downscaling
[23:57:57] [PASSED] rounding1
[23:57:57] [PASSED] rounding2
[23:57:57] [PASSED] rounding3
[23:57:57] [PASSED] rounding4
[23:57:57] =========== [PASSED] drm_test_check_plane_state ============
[23:57:57] =========== drm_test_check_invalid_plane_state  ============
[23:57:57] [PASSED] positioning_invalid
[23:57:57] [PASSED] upscaling_invalid
[23:57:57] [PASSED] downscaling_invalid
[23:57:57] ======= [PASSED] drm_test_check_invalid_plane_state ========
[23:57:57] ================ [PASSED] drm_plane_helper =================
[23:57:57] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[23:57:57] ====== drm_test_connector_helper_tv_get_modes_check  =======
[23:57:57] [PASSED] None
[23:57:57] [PASSED] PAL
[23:57:57] [PASSED] NTSC
[23:57:57] [PASSED] Both, NTSC Default
[23:57:57] [PASSED] Both, PAL Default
[23:57:57] [PASSED] Both, NTSC Default, with PAL on command-line
[23:57:57] [PASSED] Both, PAL Default, with NTSC on command-line
[23:57:57] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[23:57:57] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[23:57:57] ================== drm_rect (9 subtests) ===================
[23:57:57] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[23:57:57] [PASSED] drm_test_rect_clip_scaled_not_clipped
[23:57:57] [PASSED] drm_test_rect_clip_scaled_clipped
[23:57:57] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[23:57:57] ================= drm_test_rect_intersect  =================
[23:57:57] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[23:57:57] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[23:57:57] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[23:57:57] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[23:57:57] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[23:57:57] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[23:57:57] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[23:57:57] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[23:57:57] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[23:57:57] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[23:57:57] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[23:57:57] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[23:57:57] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[23:57:57] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[23:57:57] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
stty: 'standard input': Inappropriate ioctl for device
[23:57:57] ============= [PASSED] drm_test_rect_intersect =============
[23:57:57] ================ drm_test_rect_calc_hscale  ================
[23:57:57] [PASSED] normal use
[23:57:57] [PASSED] out of max range
[23:57:57] [PASSED] out of min range
[23:57:57] [PASSED] zero dst
[23:57:57] [PASSED] negative src
[23:57:57] [PASSED] negative dst
[23:57:57] ============ [PASSED] drm_test_rect_calc_hscale ============
[23:57:57] ================ drm_test_rect_calc_vscale  ================
[23:57:57] [PASSED] normal use
[23:57:57] [PASSED] out of max range
[23:57:57] [PASSED] out of min range
[23:57:57] [PASSED] zero dst
[23:57:57] [PASSED] negative src
[23:57:57] [PASSED] negative dst
[23:57:57] ============ [PASSED] drm_test_rect_calc_vscale ============
[23:57:57] ================== drm_test_rect_rotate  ===================
[23:57:57] [PASSED] reflect-x
[23:57:57] [PASSED] reflect-y
[23:57:57] [PASSED] rotate-0
[23:57:57] [PASSED] rotate-90
[23:57:57] [PASSED] rotate-180
[23:57:57] [PASSED] rotate-270
[23:57:57] ============== [PASSED] drm_test_rect_rotate ===============
[23:57:57] ================ drm_test_rect_rotate_inv  =================
[23:57:57] [PASSED] reflect-x
[23:57:57] [PASSED] reflect-y
[23:57:57] [PASSED] rotate-0
[23:57:57] [PASSED] rotate-90
[23:57:57] [PASSED] rotate-180
[23:57:57] [PASSED] rotate-270
[23:57:57] ============ [PASSED] drm_test_rect_rotate_inv =============
[23:57:57] ==================== [PASSED] drm_rect =====================
[23:57:57] ============ drm_sysfb_modeset_test (1 subtest) ============
[23:57:57] ============ drm_test_sysfb_build_fourcc_list  =============
[23:57:57] [PASSED] no native formats
[23:57:57] [PASSED] XRGB8888 as native format
[23:57:57] [PASSED] remove duplicates
[23:57:57] [PASSED] convert alpha formats
[23:57:57] [PASSED] random formats
[23:57:57] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[23:57:57] ============= [PASSED] drm_sysfb_modeset_test ==============
[23:57:57] ================== drm_fixp (2 subtests) ===================
[23:57:57] [PASSED] drm_test_int2fixp
[23:57:57] [PASSED] drm_test_sm2fixp
[23:57:57] ==================== [PASSED] drm_fixp =====================
[23:57:57] ============================================================
[23:57:57] Testing complete. Ran 630 tests: passed: 630
[23:57:57] Elapsed time: 27.611s total, 1.692s configuring, 25.502s building, 0.382s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[23:57:57] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:57:59] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:58:08] Starting KUnit Kernel (1/1)...
[23:58:08] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:58:08] ================= ttm_device (5 subtests) ==================
[23:58:08] [PASSED] ttm_device_init_basic
[23:58:08] [PASSED] ttm_device_init_multiple
[23:58:08] [PASSED] ttm_device_fini_basic
[23:58:08] [PASSED] ttm_device_init_no_vma_man
[23:58:08] ================== ttm_device_init_pools  ==================
[23:58:08] [PASSED] No DMA allocations, no DMA32 required
[23:58:08] [PASSED] DMA allocations, DMA32 required
[23:58:08] [PASSED] No DMA allocations, DMA32 required
[23:58:08] [PASSED] DMA allocations, no DMA32 required
[23:58:08] ============== [PASSED] ttm_device_init_pools ==============
[23:58:08] =================== [PASSED] ttm_device ====================
[23:58:08] ================== ttm_pool (8 subtests) ===================
[23:58:08] ================== ttm_pool_alloc_basic  ===================
[23:58:08] [PASSED] One page
[23:58:08] [PASSED] More than one page
[23:58:08] [PASSED] Above the allocation limit
[23:58:08] [PASSED] One page, with coherent DMA mappings enabled
[23:58:08] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:58:08] ============== [PASSED] ttm_pool_alloc_basic ===============
[23:58:08] ============== ttm_pool_alloc_basic_dma_addr  ==============
[23:58:08] [PASSED] One page
[23:58:08] [PASSED] More than one page
[23:58:08] [PASSED] Above the allocation limit
[23:58:08] [PASSED] One page, with coherent DMA mappings enabled
[23:58:08] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:58:08] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[23:58:08] [PASSED] ttm_pool_alloc_order_caching_match
[23:58:08] [PASSED] ttm_pool_alloc_caching_mismatch
[23:58:08] [PASSED] ttm_pool_alloc_order_mismatch
[23:58:08] [PASSED] ttm_pool_free_dma_alloc
[23:58:08] [PASSED] ttm_pool_free_no_dma_alloc
[23:58:08] [PASSED] ttm_pool_fini_basic
[23:58:08] ==================== [PASSED] ttm_pool =====================
[23:58:08] ================ ttm_resource (8 subtests) =================
[23:58:08] ================= ttm_resource_init_basic  =================
[23:58:08] [PASSED] Init resource in TTM_PL_SYSTEM
[23:58:08] [PASSED] Init resource in TTM_PL_VRAM
[23:58:08] [PASSED] Init resource in a private placement
[23:58:08] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[23:58:08] ============= [PASSED] ttm_resource_init_basic =============
[23:58:08] [PASSED] ttm_resource_init_pinned
[23:58:08] [PASSED] ttm_resource_fini_basic
[23:58:08] [PASSED] ttm_resource_manager_init_basic
[23:58:08] [PASSED] ttm_resource_manager_usage_basic
[23:58:08] [PASSED] ttm_resource_manager_set_used_basic
[23:58:08] [PASSED] ttm_sys_man_alloc_basic
[23:58:08] [PASSED] ttm_sys_man_free_basic
[23:58:08] ================== [PASSED] ttm_resource ===================
[23:58:08] =================== ttm_tt (15 subtests) ===================
[23:58:08] ==================== ttm_tt_init_basic  ====================
[23:58:08] [PASSED] Page-aligned size
[23:58:08] [PASSED] Extra pages requested
[23:58:08] ================ [PASSED] ttm_tt_init_basic ================
[23:58:08] [PASSED] ttm_tt_init_misaligned
[23:58:08] [PASSED] ttm_tt_fini_basic
[23:58:08] [PASSED] ttm_tt_fini_sg
[23:58:08] [PASSED] ttm_tt_fini_shmem
[23:58:08] [PASSED] ttm_tt_create_basic
[23:58:08] [PASSED] ttm_tt_create_invalid_bo_type
[23:58:08] [PASSED] ttm_tt_create_ttm_exists
[23:58:08] [PASSED] ttm_tt_create_failed
[23:58:08] [PASSED] ttm_tt_destroy_basic
[23:58:08] [PASSED] ttm_tt_populate_null_ttm
[23:58:08] [PASSED] ttm_tt_populate_populated_ttm
[23:58:08] [PASSED] ttm_tt_unpopulate_basic
[23:58:08] [PASSED] ttm_tt_unpopulate_empty_ttm
[23:58:08] [PASSED] ttm_tt_swapin_basic
[23:58:08] ===================== [PASSED] ttm_tt ======================
[23:58:08] =================== ttm_bo (14 subtests) ===================
[23:58:08] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[23:58:08] [PASSED] Cannot be interrupted and sleeps
[23:58:08] [PASSED] Cannot be interrupted, locks straight away
[23:58:08] [PASSED] Can be interrupted, sleeps
[23:58:08] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[23:58:08] [PASSED] ttm_bo_reserve_locked_no_sleep
[23:58:08] [PASSED] ttm_bo_reserve_no_wait_ticket
[23:58:08] [PASSED] ttm_bo_reserve_double_resv
[23:58:08] [PASSED] ttm_bo_reserve_interrupted
[23:58:08] [PASSED] ttm_bo_reserve_deadlock
[23:58:08] [PASSED] ttm_bo_unreserve_basic
[23:58:08] [PASSED] ttm_bo_unreserve_pinned
[23:58:08] [PASSED] ttm_bo_unreserve_bulk
[23:58:08] [PASSED] ttm_bo_fini_basic
[23:58:08] [PASSED] ttm_bo_fini_shared_resv
[23:58:08] [PASSED] ttm_bo_pin_basic
[23:58:08] [PASSED] ttm_bo_pin_unpin_resource
[23:58:08] [PASSED] ttm_bo_multiple_pin_one_unpin
[23:58:08] ===================== [PASSED] ttm_bo ======================
[23:58:08] ============== ttm_bo_validate (21 subtests) ===============
[23:58:08] ============== ttm_bo_init_reserved_sys_man  ===============
[23:58:08] [PASSED] Buffer object for userspace
[23:58:08] [PASSED] Kernel buffer object
[23:58:08] [PASSED] Shared buffer object
[23:58:08] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[23:58:08] ============== ttm_bo_init_reserved_mock_man  ==============
[23:58:08] [PASSED] Buffer object for userspace
[23:58:08] [PASSED] Kernel buffer object
[23:58:08] [PASSED] Shared buffer object
[23:58:08] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[23:58:08] [PASSED] ttm_bo_init_reserved_resv
[23:58:08] ================== ttm_bo_validate_basic  ==================
[23:58:08] [PASSED] Buffer object for userspace
[23:58:08] [PASSED] Kernel buffer object
[23:58:08] [PASSED] Shared buffer object
[23:58:08] ============== [PASSED] ttm_bo_validate_basic ==============
[23:58:08] [PASSED] ttm_bo_validate_invalid_placement
[23:58:08] ============= ttm_bo_validate_same_placement  ==============
[23:58:08] [PASSED] System manager
[23:58:08] [PASSED] VRAM manager
[23:58:08] ========= [PASSED] ttm_bo_validate_same_placement ==========
[23:58:08] [PASSED] ttm_bo_validate_failed_alloc
[23:58:08] [PASSED] ttm_bo_validate_pinned
[23:58:08] [PASSED] ttm_bo_validate_busy_placement
[23:58:08] ================ ttm_bo_validate_multihop  =================
[23:58:08] [PASSED] Buffer object for userspace
[23:58:08] [PASSED] Kernel buffer object
[23:58:08] [PASSED] Shared buffer object
[23:58:08] ============ [PASSED] ttm_bo_validate_multihop =============
[23:58:08] ========== ttm_bo_validate_no_placement_signaled  ==========
[23:58:08] [PASSED] Buffer object in system domain, no page vector
[23:58:08] [PASSED] Buffer object in system domain with an existing page vector
[23:58:08] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[23:58:08] ======== ttm_bo_validate_no_placement_not_signaled  ========
[23:58:08] [PASSED] Buffer object for userspace
[23:58:08] [PASSED] Kernel buffer object
[23:58:08] [PASSED] Shared buffer object
[23:58:08] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[23:58:08] [PASSED] ttm_bo_validate_move_fence_signaled
[23:58:08] ========= ttm_bo_validate_move_fence_not_signaled  =========
[23:58:08] [PASSED] Waits for GPU
[23:58:08] [PASSED] Tries to lock straight away
[23:58:08] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[23:58:08] [PASSED] ttm_bo_validate_happy_evict
[23:58:08] [PASSED] ttm_bo_validate_all_pinned_evict
[23:58:08] [PASSED] ttm_bo_validate_allowed_only_evict
[23:58:08] [PASSED] ttm_bo_validate_deleted_evict
[23:58:08] [PASSED] ttm_bo_validate_busy_domain_evict
[23:58:08] [PASSED] ttm_bo_validate_evict_gutting
[23:58:08] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[23:58:08] ================= [PASSED] ttm_bo_validate =================
[23:58:08] ============================================================
[23:58:08] Testing complete. Ran 101 tests: passed: 101
[23:58:08] Elapsed time: 11.424s total, 1.679s configuring, 9.478s building, 0.218s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for Make Display free from i915_reg.h (rev2)

[Patchwork]

== Series Details ==

Series: Make Display free from i915_reg.h (rev2)
URL   : https://patchwork.freedesktop.org/series/159130/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast ad2a046603cba140214aed34015ed5027441e85a
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/g4x_dp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/g4x_hdmi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/i9xx_wm.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_combo_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_crt.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_cx0_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_device.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_irq.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_display_power_map.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_power_well.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_rps.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_hdcp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpio_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpll.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpll_mgr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_mst.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpt_common.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_test.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_drrs.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dsb.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dsi_vbt.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dvo.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fbc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_fifo_underrun.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_gmbus.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hdmi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_lspcon.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_modeset_setup.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_overlay.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pch_display.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pch_refclk.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pfit.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pipe_crc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pmdemand.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_sdvo.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_snps_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_tv.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vblank.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vrr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/skl_scaler.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/skl_universal_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/gt/intel_reset.c:1569:12: warning: context imbalance in '_intel_gt_reset_lock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:193:1: error: bad constant expression
+drivers/gpu/drm/i915/i915_irq.c:467:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:467:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:475:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:475:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:480:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:480:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:480:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:518:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:518:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:526:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:526:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:531:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:531:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:531:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:575:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:575:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:578:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:578:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:582:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:582:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:589:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:589:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:589:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:589:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1932:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1933:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1999:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2000:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2021:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2022:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Make Display free from i915_reg.h (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1001 bytes --]

== Series Details ==

Series: Make Display free from i915_reg.h (rev2)
URL   : https://patchwork.freedesktop.org/series/159130/
State : success

== Summary ==

CI Bug Log - changes from xe-4432-ad2a046603cba140214aed34015ed5027441e85a_BAT -> xe-pw-159130v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_8709 -> IGT_8710
  * Linux: xe-4432-ad2a046603cba140214aed34015ed5027441e85a -> xe-pw-159130v2

  IGT_8709: 16ce286cac6acc9669a1c758572ae9fceb483c46 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8710: 8710
  xe-4432-ad2a046603cba140214aed34015ed5027441e85a: ad2a046603cba140214aed34015ed5027441e85a
  xe-pw-159130v2: 159130v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/index.html

[-- Attachment #2: Type: text/html, Size: 1563 bytes --]

✓ Xe.CI.Full: success for Make Display free from i915_reg.h (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 45117 bytes --]

== Series Details ==

Series: Make Display free from i915_reg.h (rev2)
URL   : https://patchwork.freedesktop.org/series/159130/
State : success

== Summary ==

CI Bug Log - changes from xe-4432-ad2a046603cba140214aed34015ed5027441e85a_FULL -> xe-pw-159130v2_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-159130v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-write:
    - shard-bmg:          [PASS][1] -> [FAIL][2] ([Intel XE#4665])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-1/igt@intel_hwmon@hwmon-write.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-7/igt@intel_hwmon@hwmon-write.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][3] ([Intel XE#3658])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#2327]) +2 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-1/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-lnl:          NOTRUN -> [SKIP][5] ([Intel XE#1407]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-7/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-0:
    - shard-lnl:          NOTRUN -> [SKIP][6] ([Intel XE#1124]) +5 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-1/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#1124]) +6 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-4/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html

  * igt@kms_bw@linear-tiling-2-displays-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#367])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-4/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2887]) +3 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-4/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][10] ([Intel XE#2669]) +3 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs@pipe-b-edp-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [PASS][11] -> [INCOMPLETE][12] ([Intel XE#7084]) +1 other test incomplete
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#3432])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-10/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][14] ([Intel XE#2887]) +3 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-3/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2724])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-1/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_chamelium_color@ctm-0-25:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#306])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-8/igt@kms_chamelium_color@ctm-0-25.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2325])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-4/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_hpd@hdmi-hpd-after-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2252]) +6 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-1/igt@kms_chamelium_hpd@hdmi-hpd-after-suspend.html

  * igt@kms_chamelium_hpd@vga-hpd-fast:
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#373]) +4 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-4/igt@kms_chamelium_hpd@vga-hpd-fast.html

  * igt@kms_color_pipeline@plane-ctm3x4-lut1d@pipe-c-edp-1:
    - shard-lnl:          NOTRUN -> [FAIL][20] ([Intel XE#6968]) +3 other tests fail
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-2/igt@kms_color_pipeline@plane-ctm3x4-lut1d@pipe-c-edp-1.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2390] / [Intel XE#6974])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-9/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@type1:
    - shard-lnl:          NOTRUN -> [SKIP][22] ([Intel XE#3278])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-1/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2320]) +2 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-8/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x32:
    - shard-lnl:          NOTRUN -> [SKIP][24] ([Intel XE#1424])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-3/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#309]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-3/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#323])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2286])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#1508])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-5/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#4294])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-8/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#2244])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-9/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_feature_discovery@display-2x:
    - shard-lnl:          NOTRUN -> [SKIP][31] ([Intel XE#702])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-5/igt@kms_feature_discovery@display-2x.html

  * igt@kms_flip@2x-busy-flip:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#1421])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-4/igt@kms_flip@2x-busy-flip.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-bmg:          [PASS][33] -> [INCOMPLETE][34] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-8/igt@kms_flip@flip-vs-suspend-interruptible.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-9/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#2293] / [Intel XE#2380]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#2293]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#1401] / [Intel XE#1745]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#1401]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#1397] / [Intel XE#1745])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#1397])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#7064] / [Intel XE#7081])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-10/igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x.html

  * igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#7064])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-10/igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#2311]) +13 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#651]) +2 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-4/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#4141]) +7 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-shrfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#6312])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][47] ([Intel XE#7061]) +2 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-4/igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][48] ([Intel XE#656]) +12 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#2313]) +14 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#7061])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-10/igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-render.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-lnl:          NOTRUN -> [SKIP][51] ([Intel XE#1470] / [Intel XE#2853])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-2/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][52] -> [SKIP][53] ([Intel XE#1503])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-8/igt@kms_hdr@invalid-hdr.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-4/igt@kms_hdr@invalid-hdr.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#6912])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-1/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#4329] / [Intel XE#6912])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-10/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling:
    - shard-lnl:          NOTRUN -> [SKIP][56] ([Intel XE#6886]) +3 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-2/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling.html

  * igt@kms_pm_dc@dc5-dpms:
    - shard-lnl:          [PASS][57] -> [FAIL][58] ([Intel XE#718])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-lnl-2/igt@kms_pm_dc@dc5-dpms.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-4/igt@kms_pm_dc@dc5-dpms.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-lnl:          NOTRUN -> [SKIP][59] ([Intel XE#1439] / [Intel XE#3141])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-8/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-9/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-8/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html
    - shard-lnl:          NOTRUN -> [SKIP][62] ([Intel XE#1406] / [Intel XE#2893] / [Intel XE#4608])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][63] ([Intel XE#1406] / [Intel XE#4608]) +1 other test skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area@pipe-b-edp-1.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-lnl:          NOTRUN -> [SKIP][64] ([Intel XE#1406] / [Intel XE#2893]) +1 other test skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-8/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-lnl:          NOTRUN -> [SKIP][65] ([Intel XE#1128] / [Intel XE#1406])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-3/igt@kms_psr2_su@frontbuffer-xrgb8888.html
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#1406] / [Intel XE#2387])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-7/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@fbc-psr-basic:
    - shard-bmg:          NOTRUN -> [SKIP][67] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-9/igt@kms_psr@fbc-psr-basic.html

  * igt@kms_psr@pr-sprite-render:
    - shard-lnl:          NOTRUN -> [SKIP][68] ([Intel XE#1406]) +1 other test skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-7/igt@kms_psr@pr-sprite-render.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#3414] / [Intel XE#3904])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-1/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_sharpness_filter@filter-rotations:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#6503])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-4/igt@kms_sharpness_filter@filter-rotations.html

  * igt@kms_vblank@query-forked-busy-hang@pipe-a-edp-1:
    - shard-lnl:          [PASS][71] -> [DMESG-WARN][72] ([Intel XE#4537] / [Intel XE#7063]) +1 other test dmesg-warn
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-lnl-7/igt@kms_vblank@query-forked-busy-hang@pipe-a-edp-1.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-2/igt@kms_vblank@query-forked-busy-hang@pipe-a-edp-1.html

  * igt@xe_configfs@survivability-mode:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#6010])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-7/igt@xe_configfs@survivability-mode.html

  * igt@xe_eudebug@discovery-empty-clients:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#4837]) +2 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-3/igt@xe_eudebug@discovery-empty-clients.html

  * igt@xe_eudebug@vma-ufence:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#4837]) +3 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-7/igt@xe_eudebug@vma-ufence.html

  * igt@xe_eudebug_online@interrupt-other:
    - shard-lnl:          NOTRUN -> [SKIP][76] ([Intel XE#4837] / [Intel XE#6665])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-5/igt@xe_eudebug_online@interrupt-other.html

  * igt@xe_eudebug_online@pagefault-one-of-many:
    - shard-bmg:          NOTRUN -> [SKIP][77] ([Intel XE#6665])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-7/igt@xe_eudebug_online@pagefault-one-of-many.html

  * igt@xe_eudebug_online@set-breakpoint:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#4837] / [Intel XE#6665])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-8/igt@xe_eudebug_online@set-breakpoint.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [PASS][79] -> [INCOMPLETE][80] ([Intel XE#6321])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-9/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-4/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_evict@evict-beng-mixed-threads-small-multi-vm:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#688]) +5 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-5/igt@xe_evict@evict-beng-mixed-threads-small-multi-vm.html

  * igt@xe_exec_basic@multigpu-once-null-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][82] ([Intel XE#2322]) +3 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-2/igt@xe_exec_basic@multigpu-once-null-rebind.html

  * igt@xe_exec_basic@multigpu-once-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][83] ([Intel XE#1392]) +1 other test skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-7/igt@xe_exec_basic@multigpu-once-userptr.html

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-dyn-priority-smem:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#6874]) +16 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-8/igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-dyn-priority-smem.html

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][85] ([Intel XE#6874]) +11 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-4/igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-userptr.html

  * igt@xe_exec_system_allocator@many-64k-mmap-huge:
    - shard-lnl:          NOTRUN -> [SKIP][86] ([Intel XE#5007])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-1/igt@xe_exec_system_allocator@many-64k-mmap-huge.html

  * igt@xe_exec_system_allocator@many-64k-mmap-new-huge:
    - shard-bmg:          NOTRUN -> [SKIP][87] ([Intel XE#5007])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-9/igt@xe_exec_system_allocator@many-64k-mmap-new-huge.html

  * igt@xe_exec_system_allocator@process-many-execqueues-mmap-free-huge:
    - shard-bmg:          NOTRUN -> [SKIP][88] ([Intel XE#4943]) +13 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-8/igt@xe_exec_system_allocator@process-many-execqueues-mmap-free-huge.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-free-huge:
    - shard-lnl:          NOTRUN -> [SKIP][89] ([Intel XE#4943]) +11 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-1/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-free-huge.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-remap-ro-dontunmap:
    - shard-lnl:          [PASS][90] -> [DMESG-WARN][91] ([Intel XE#7063]) +1 other test dmesg-warn
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-lnl-5/igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-remap-ro-dontunmap.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-2/igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-remap-ro-dontunmap.html

  * igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit:
    - shard-lnl:          NOTRUN -> [SKIP][92] ([Intel XE#2229])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-3/igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit.html

  * igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
    - shard-bmg:          NOTRUN -> [SKIP][93] ([Intel XE#2229])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-1/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html

  * igt@xe_mmap@pci-membarrier:
    - shard-lnl:          NOTRUN -> [SKIP][94] ([Intel XE#5100])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-1/igt@xe_mmap@pci-membarrier.html

  * igt@xe_pat@pat-index-xelp:
    - shard-lnl:          NOTRUN -> [SKIP][95] ([Intel XE#977])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-3/igt@xe_pat@pat-index-xelp.html
    - shard-bmg:          NOTRUN -> [SKIP][96] ([Intel XE#2245])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-1/igt@xe_pat@pat-index-xelp.html

  * igt@xe_pm@d3cold-mmap-vram:
    - shard-bmg:          NOTRUN -> [SKIP][97] ([Intel XE#2284])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-9/igt@xe_pm@d3cold-mmap-vram.html

  * igt@xe_pm@s3-vm-bind-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][98] ([Intel XE#584])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-5/igt@xe_pm@s3-vm-bind-userptr.html

  * igt@xe_query@multigpu-query-uc-fw-version-huc:
    - shard-bmg:          NOTRUN -> [SKIP][99] ([Intel XE#944])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-2/igt@xe_query@multigpu-query-uc-fw-version-huc.html

  * igt@xe_sriov_auto_provisioning@exclusive-ranges:
    - shard-lnl:          NOTRUN -> [SKIP][100] ([Intel XE#4130])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-8/igt@xe_sriov_auto_provisioning@exclusive-ranges.html

  
#### Possible fixes ####

  * igt@kms_async_flips@test-cursor:
    - shard-bmg:          [INCOMPLETE][101] ([Intel XE#4912] / [Intel XE#6819]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-3/igt@kms_async_flips@test-cursor.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-10/igt@kms_async_flips@test-cursor.html

  * igt@kms_async_flips@test-cursor@pipe-b-hdmi-a-3:
    - shard-bmg:          [DMESG-WARN][103] ([Intel XE#6819]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-3/igt@kms_async_flips@test-cursor@pipe-b-hdmi-a-3.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-10/igt@kms_async_flips@test-cursor@pipe-b-hdmi-a-3.html

  * igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw:
    - shard-lnl:          [DMESG-WARN][105] ([Intel XE#7063]) -> [PASS][106] +2 other tests pass
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-lnl-1/igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-3/igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-lnl:          [SKIP][107] ([Intel XE#1406] / [Intel XE#4692]) -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-lnl-8/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-lnl-4/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [SKIP][131], [PASS][132], [PASS][133], [PASS][134]) ([Intel XE#2457]) -> ([PASS][135], [PASS][136], [PASS][137], [PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143], [PASS][144], [PASS][145], [PASS][146], [PASS][147], [PASS][148], [PASS][149], [PASS][150], [PASS][151], [PASS][152], [PASS][153], [PASS][154], [PASS][155], [PASS][156], [PASS][157], [PASS][158], [PASS][159])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-3/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-3/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-8/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-8/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-2/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-2/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-4/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-4/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-3/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-10/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-10/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-4/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-2/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-2/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-9/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-9/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-9/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-1/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-9/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-1/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-1/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-1/igt@xe_module_load@load.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-1/igt@xe_module_load@load.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-7/igt@xe_module_load@load.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-7/igt@xe_module_load@load.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-7/igt@xe_module_load@load.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-3/igt@xe_module_load@load.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-2/igt@xe_module_load@load.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-8/igt@xe_module_load@load.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-7/igt@xe_module_load@load.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-3/igt@xe_module_load@load.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-3/igt@xe_module_load@load.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-10/igt@xe_module_load@load.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-7/igt@xe_module_load@load.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-2/igt@xe_module_load@load.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-4/igt@xe_module_load@load.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-9/igt@xe_module_load@load.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-2/igt@xe_module_load@load.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-8/igt@xe_module_load@load.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-8/igt@xe_module_load@load.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-9/igt@xe_module_load@load.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-7/igt@xe_module_load@load.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-9/igt@xe_module_load@load.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-1/igt@xe_module_load@load.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-1/igt@xe_module_load@load.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-4/igt@xe_module_load@load.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-4/igt@xe_module_load@load.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-4/igt@xe_module_load@load.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-1/igt@xe_module_load@load.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-10/igt@xe_module_load@load.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-10/igt@xe_module_load@load.html

  * igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling@numvfs-random:
    - shard-bmg:          [FAIL][160] ([Intel XE#5937]) -> [PASS][161] +1 other test pass
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-2/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling@numvfs-random.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-9/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling@numvfs-random.html

  * igt@xe_sriov_flr@flr-twice:
    - shard-bmg:          [FAIL][162] ([Intel XE#6569]) -> [PASS][163]
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-2/igt@xe_sriov_flr@flr-twice.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-2/igt@xe_sriov_flr@flr-twice.html

  
#### Warnings ####

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [FAIL][164] ([Intel XE#5299]) -> [FAIL][165] ([Intel XE#4633])
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-10/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-10/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][166] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][167] ([Intel XE#3544])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-1/igt@kms_hdr@brightness-with-hdr.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][168] ([Intel XE#2426]) -> [FAIL][169] ([Intel XE#1729])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4432-ad2a046603cba140214aed34015ed5027441e85a/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2853]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2853
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3278]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3278
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4294
  [Intel XE#4329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4329
  [Intel XE#4537]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4537
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
  [Intel XE#4665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4665
  [Intel XE#4692]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4692
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4912
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#5937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5937
  [Intel XE#6010]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6010
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6819
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6912
  [Intel XE#6968]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6968
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#702]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/702
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7063]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7063
  [Intel XE#7064]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7064
  [Intel XE#7081]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7081
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977


Build changes
-------------

  * IGT: IGT_8709 -> IGT_8710
  * Linux: xe-4432-ad2a046603cba140214aed34015ed5027441e85a -> xe-pw-159130v2

  IGT_8709: 16ce286cac6acc9669a1c758572ae9fceb483c46 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8710: 8710
  xe-4432-ad2a046603cba140214aed34015ed5027441e85a: ad2a046603cba140214aed34015ed5027441e85a
  xe-pw-159130v2: 159130v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v2/index.html

[-- Attachment #2: Type: text/html, Size: 50685 bytes --]

Re: [v2 01/19] drm/{i915, xe}: Extract display registers from i915_reg.h to display

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> There are certain register definitions which are defined in i915_reg.h
> which are exclusively needed by display. Move the same to display
> headers to remove i915_reg.h includes from display. This is a step
> towards making display independent of i915.
>
> intel_clock_gating.c can include display header directly.

...because its usage should be refactored and moved inside display.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> v2: Drop common header in include and use display_regs.h (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_regs.h | 10 ++++++++++
>  drivers/gpu/drm/i915/display/intel_pch_display.c  |  1 -
>  drivers/gpu/drm/i915/i915_reg.h                   | 10 ----------
>  drivers/gpu/drm/i915/intel_clock_gating.c         |  2 +-
>  4 files changed, 11 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 9e0d853f4b61..9f8fbfb2e115 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -2021,6 +2021,16 @@
>  #define  TRANS_BPC_6			REG_FIELD_PREP(TRANS_BPC_MASK, 2)
>  #define  TRANS_BPC_12			REG_FIELD_PREP(TRANS_BPC_MASK, 3)
>  
> +#define _TRANSA_CHICKEN2	0xf0064
> +#define _TRANSB_CHICKEN2	0xf1064
> +#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> +#define   TRANS_CHICKEN2_TIMING_OVERRIDE		REG_BIT(31)
> +#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED		REG_BIT(29)
> +#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK		REG_GENMASK(28, 27)
> +#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
> +#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	REG_BIT(26)
> +#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	REG_BIT(25)
> +
>  #define PCH_DP_B		_MMIO(0xe4100)
>  #define PCH_DP_C		_MMIO(0xe4200)
>  #define PCH_DP_D		_MMIO(0xe4300)
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 16619f7be5f8..69c7952a1413 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -6,7 +6,6 @@
>  #include <drm/drm_print.h>
>  
>  #include "g4x_dp.h"
> -#include "i915_reg.h"
>  #include "intel_crt.h"
>  #include "intel_crt_regs.h"
>  #include "intel_de.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5bf3b4ab2baa..d247e107f42f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1022,16 +1022,6 @@
>  #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
>  #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
>  
> -#define _TRANSA_CHICKEN2	 0xf0064
> -#define _TRANSB_CHICKEN2	 0xf1064
> -#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> -#define   TRANS_CHICKEN2_TIMING_OVERRIDE		REG_BIT(31)
> -#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED		REG_BIT(29)
> -#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK		REG_GENMASK(28, 27)
> -#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
> -#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	REG_BIT(26)
> -#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	REG_BIT(25)
> -
>  #define SOUTH_CHICKEN1		_MMIO(0xc2000)
>  #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
>  #define  FDIA_PHASE_SYNC_SHIFT_EN	18
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> index 7336934bb934..4e18d5a22112 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -30,7 +30,7 @@
>  #include "display/i9xx_plane_regs.h"
>  #include "display/intel_display.h"
>  #include "display/intel_display_core.h"
> -
> +#include "display/intel_display_regs.h"
>  #include "gt/intel_engine_regs.h"
>  #include "gt/intel_gt.h"
>  #include "gt/intel_gt_mcr.h"

-- 
Jani Nikula, Intel

Re: [v2 01/19] drm/{i915, xe}: Extract display registers from i915_reg.h to display

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> There are certain register definitions which are defined in i915_reg.h
> which are exclusively needed by display. Move the same to display
> headers to remove i915_reg.h includes from display. This is a step
> towards making display independent of i915.
>
> intel_clock_gating.c can include display header directly.
>
> v2: Drop common header in include and use display_regs.h (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Oh, the Subject should just be drm/i915, this isn't directly related to
xe.

> ---
>  drivers/gpu/drm/i915/display/intel_display_regs.h | 10 ++++++++++
>  drivers/gpu/drm/i915/display/intel_pch_display.c  |  1 -
>  drivers/gpu/drm/i915/i915_reg.h                   | 10 ----------
>  drivers/gpu/drm/i915/intel_clock_gating.c         |  2 +-
>  4 files changed, 11 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 9e0d853f4b61..9f8fbfb2e115 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -2021,6 +2021,16 @@
>  #define  TRANS_BPC_6			REG_FIELD_PREP(TRANS_BPC_MASK, 2)
>  #define  TRANS_BPC_12			REG_FIELD_PREP(TRANS_BPC_MASK, 3)
>  
> +#define _TRANSA_CHICKEN2	0xf0064
> +#define _TRANSB_CHICKEN2	0xf1064
> +#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> +#define   TRANS_CHICKEN2_TIMING_OVERRIDE		REG_BIT(31)
> +#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED		REG_BIT(29)
> +#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK		REG_GENMASK(28, 27)
> +#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
> +#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	REG_BIT(26)
> +#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	REG_BIT(25)
> +
>  #define PCH_DP_B		_MMIO(0xe4100)
>  #define PCH_DP_C		_MMIO(0xe4200)
>  #define PCH_DP_D		_MMIO(0xe4300)
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 16619f7be5f8..69c7952a1413 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -6,7 +6,6 @@
>  #include <drm/drm_print.h>
>  
>  #include "g4x_dp.h"
> -#include "i915_reg.h"
>  #include "intel_crt.h"
>  #include "intel_crt_regs.h"
>  #include "intel_de.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5bf3b4ab2baa..d247e107f42f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1022,16 +1022,6 @@
>  #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
>  #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
>  
> -#define _TRANSA_CHICKEN2	 0xf0064
> -#define _TRANSB_CHICKEN2	 0xf1064
> -#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> -#define   TRANS_CHICKEN2_TIMING_OVERRIDE		REG_BIT(31)
> -#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED		REG_BIT(29)
> -#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK		REG_GENMASK(28, 27)
> -#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
> -#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	REG_BIT(26)
> -#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	REG_BIT(25)
> -
>  #define SOUTH_CHICKEN1		_MMIO(0xc2000)
>  #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
>  #define  FDIA_PHASE_SYNC_SHIFT_EN	18
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> index 7336934bb934..4e18d5a22112 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -30,7 +30,7 @@
>  #include "display/i9xx_plane_regs.h"
>  #include "display/intel_display.h"
>  #include "display/intel_display_core.h"
> -
> +#include "display/intel_display_regs.h"
>  #include "gt/intel_engine_regs.h"
>  #include "gt/intel_gt.h"
>  #include "gt/intel_gt_mcr.h"

-- 
Jani Nikula, Intel

Re: [v2 02/19] drm/{i915, xe}: Extract South chicken registers from i915_reg.h to display

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Extract South Chicken registers from i915_reg.h to display header.
> This allows intel_pch_refclk.c not to include i915_reg.h
>
> v2: Drop common header in include and use display_regs.h (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Just drm/i915 is sufficient as subject prefix.

It's mildly annoying that there's a bunch of whitespace changes bundled
in here. They should be kept separate, if only to speed up review by 10x
with 'git show --color-moved' which works wonders for pure code
movement. Subsequent separate whitespace changes, in turn, are a breeze
to review with 'git show -w'.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_display_regs.h | 28 +++++++++++++++++++
>  .../gpu/drm/i915/display/intel_pch_refclk.c   |  1 -
>  drivers/gpu/drm/i915/i915_reg.h               | 27 ------------------
>  3 files changed, 28 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 9f8fbfb2e115..4759a9600d3f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -2864,6 +2864,34 @@ enum skl_power_gate {
>  #define  SFUSE_STRAP_DDIC_DETECTED	(1 << 1)
>  #define  SFUSE_STRAP_DDID_DETECTED	(1 << 0)
>  
> +#define SOUTH_CHICKEN1			_MMIO(0xc2000)
> +#define  FDIA_PHASE_SYNC_SHIFT_OVR	19
> +#define  FDIA_PHASE_SYNC_SHIFT_EN	18
> +#define  INVERT_DDIE_HPD		REG_BIT(28)
> +#define  INVERT_DDID_HPD_MTP		REG_BIT(27)
> +#define  INVERT_TC4_HPD			REG_BIT(26)
> +#define  INVERT_TC3_HPD			REG_BIT(25)
> +#define  INVERT_TC2_HPD			REG_BIT(24)
> +#define  INVERT_TC1_HPD			REG_BIT(23)
> +#define  INVERT_DDID_HPD		(1 << 18)
> +#define  INVERT_DDIC_HPD		(1 << 17)
> +#define  INVERT_DDIB_HPD                (1 << 16)
> +#define  INVERT_DDIA_HPD                (1 << 15)
> +#define  FDI_PHASE_SYNC_OVR(pipe)	(1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
> +#define  FDI_PHASE_SYNC_EN(pipe)	(1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
> +#define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
> +#define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
> +#define  CHASSIS_CLK_REQ_DURATION(x)	((x) << 8)
> +#define  SBCLK_RUN_REFCLK_DIS		(1 << 7)
> +#define  ICP_SECOND_PPS_IO_SELECT	REG_BIT(2)
> +#define  SPT_PWM_GRANULARITY		(1 << 0)
> +
> +#define SOUTH_CHICKEN2			_MMIO(0xc2004)
> +#define  FDI_MPHY_IOSFSB_RESET_STATUS	(1 << 13)
> +#define  FDI_MPHY_IOSFSB_RESET_CTL	(1 << 12)
> +#define  LPT_PWM_GRANULARITY		(1 << 5)
> +#define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
> +
>  /* Gen4+ Timestamp and Pipe Frame time stamp registers */
>  #define GEN4_TIMESTAMP		_MMIO(0x2358)
>  #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> index 9a89bb6dcf65..5f88663ef5e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> @@ -5,7 +5,6 @@
>  
>  #include <drm/drm_print.h>
>  
> -#include "i915_reg.h"
>  #include "intel_de.h"
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d247e107f42f..80ea0df40b1e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1022,33 +1022,6 @@
>  #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
>  #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
>  
> -#define SOUTH_CHICKEN1		_MMIO(0xc2000)
> -#define  FDIA_PHASE_SYNC_SHIFT_OVR	19
> -#define  FDIA_PHASE_SYNC_SHIFT_EN	18
> -#define  INVERT_DDIE_HPD			REG_BIT(28)
> -#define  INVERT_DDID_HPD_MTP			REG_BIT(27)
> -#define  INVERT_TC4_HPD				REG_BIT(26)
> -#define  INVERT_TC3_HPD				REG_BIT(25)
> -#define  INVERT_TC2_HPD				REG_BIT(24)
> -#define  INVERT_TC1_HPD				REG_BIT(23)
> -#define  INVERT_DDID_HPD			(1 << 18)
> -#define  INVERT_DDIC_HPD			(1 << 17)
> -#define  INVERT_DDIB_HPD			(1 << 16)
> -#define  INVERT_DDIA_HPD			(1 << 15)
> -#define  FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
> -#define  FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
> -#define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
> -#define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
> -#define  CHASSIS_CLK_REQ_DURATION(x)	((x) << 8)
> -#define  SBCLK_RUN_REFCLK_DIS		(1 << 7)
> -#define  ICP_SECOND_PPS_IO_SELECT	REG_BIT(2)
> -#define  SPT_PWM_GRANULARITY		(1 << 0)
> -#define SOUTH_CHICKEN2		_MMIO(0xc2004)
> -#define  FDI_MPHY_IOSFSB_RESET_STATUS	(1 << 13)
> -#define  FDI_MPHY_IOSFSB_RESET_CTL	(1 << 12)
> -#define  LPT_PWM_GRANULARITY		(1 << 5)
> -#define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
> -
>  #define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
>  #define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
>  #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)

-- 
Jani Nikula, Intel

Re: [v2 03/19] drm/{i915, xe}: Extract display interrupt definitions

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move common registers to display to allow intel_display_rps.c
> free of i915_reg.h dependency.

The grammar's not quite right there.

> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_regs.h | 34 +++++++++++++++++++
>  .../gpu/drm/i915/display/intel_display_rps.c  |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h               | 33 ------------------
>  3 files changed, 35 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 4759a9600d3f..1f922d013cd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -1333,6 +1333,40 @@
>  						      GEN8_DE_PORT_IER, \
>  						      GEN8_DE_PORT_IIR)
>  
> +/* interrupts */
> +#define DE_MASTER_IRQ_CONTROL   (1 << 31)
> +#define DE_SPRITEB_FLIP_DONE    (1 << 29)
> +#define DE_SPRITEA_FLIP_DONE    (1 << 28)
> +#define DE_PLANEB_FLIP_DONE     (1 << 27)
> +#define DE_PLANEA_FLIP_DONE     (1 << 26)
> +#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
> +#define DE_PCU_EVENT            (1 << 25)
> +#define DE_GTT_FAULT            (1 << 24)
> +#define DE_POISON               (1 << 23)
> +#define DE_PERFORM_COUNTER      (1 << 22)
> +#define DE_PCH_EVENT            (1 << 21)
> +#define DE_AUX_CHANNEL_A        (1 << 20)
> +#define DE_DP_A_HOTPLUG         (1 << 19)
> +#define DE_GSE                  (1 << 18)
> +#define DE_PIPEB_VBLANK         (1 << 15)
> +#define DE_PIPEB_EVEN_FIELD     (1 << 14)
> +#define DE_PIPEB_ODD_FIELD      (1 << 13)
> +#define DE_PIPEB_LINE_COMPARE   (1 << 12)
> +#define DE_PIPEB_VSYNC          (1 << 11)
> +#define DE_PIPEB_CRC_DONE	(1 << 10)
> +#define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
> +#define DE_PIPEA_VBLANK         (1 << 7)
> +#define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8 * (pipe)))
> +#define DE_PIPEA_EVEN_FIELD     (1 << 6)
> +#define DE_PIPEA_ODD_FIELD      (1 << 5)
> +#define DE_PIPEA_LINE_COMPARE   (1 << 4)
> +#define DE_PIPEA_VSYNC          (1 << 3)
> +#define DE_PIPEA_CRC_DONE	(1 << 2)
> +#define DE_PIPE_CRC_DONE(pipe)	(1 << (2 + 8 * (pipe)))
> +#define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
> +#define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8 * (pipe)))
> +
> +

Superfluous newline.

Other than that,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

PS. This one took like 5 seconds to review with 'git show
--color-moved'.


>  #define GEN8_DE_MISC_ISR _MMIO(0x44460)
>  #define GEN8_DE_MISC_IMR _MMIO(0x44464)
>  #define GEN8_DE_MISC_IIR _MMIO(0x44468)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_rps.c b/drivers/gpu/drm/i915/display/intel_display_rps.c
> index e77811396474..bf00266dae4b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_rps.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_rps.c
> @@ -8,8 +8,8 @@
>  #include <drm/drm_crtc.h>
>  #include <drm/drm_vblank.h>
>  
> -#include "i915_reg.h"
>  #include "intel_display_core.h"
> +#include "intel_display_regs.h"
>  #include "intel_display_irq.h"
>  #include "intel_display_rps.h"
>  #include "intel_display_types.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 80ea0df40b1e..5cd124083c17 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -804,39 +804,6 @@
>  #define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
>  #define  MMIO_TIMEOUT_US(us)	((us) << 0)
>  
> -/* interrupts */
> -#define DE_MASTER_IRQ_CONTROL   (1 << 31)
> -#define DE_SPRITEB_FLIP_DONE    (1 << 29)
> -#define DE_SPRITEA_FLIP_DONE    (1 << 28)
> -#define DE_PLANEB_FLIP_DONE     (1 << 27)
> -#define DE_PLANEA_FLIP_DONE     (1 << 26)
> -#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
> -#define DE_PCU_EVENT            (1 << 25)
> -#define DE_GTT_FAULT            (1 << 24)
> -#define DE_POISON               (1 << 23)
> -#define DE_PERFORM_COUNTER      (1 << 22)
> -#define DE_PCH_EVENT            (1 << 21)
> -#define DE_AUX_CHANNEL_A        (1 << 20)
> -#define DE_DP_A_HOTPLUG         (1 << 19)
> -#define DE_GSE                  (1 << 18)
> -#define DE_PIPEB_VBLANK         (1 << 15)
> -#define DE_PIPEB_EVEN_FIELD     (1 << 14)
> -#define DE_PIPEB_ODD_FIELD      (1 << 13)
> -#define DE_PIPEB_LINE_COMPARE   (1 << 12)
> -#define DE_PIPEB_VSYNC          (1 << 11)
> -#define DE_PIPEB_CRC_DONE	(1 << 10)
> -#define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
> -#define DE_PIPEA_VBLANK         (1 << 7)
> -#define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8 * (pipe)))
> -#define DE_PIPEA_EVEN_FIELD     (1 << 6)
> -#define DE_PIPEA_ODD_FIELD      (1 << 5)
> -#define DE_PIPEA_LINE_COMPARE   (1 << 4)
> -#define DE_PIPEA_VSYNC          (1 << 3)
> -#define DE_PIPEA_CRC_DONE	(1 << 2)
> -#define DE_PIPE_CRC_DONE(pipe)	(1 << (2 + 8 * (pipe)))
> -#define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
> -#define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8 * (pipe)))
> -
>  #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
>  #define   MASTER_INTERRUPT_ENABLE	(1 << 31)

-- 
Jani Nikula, Intel

Re: [v2 04/19] drm/{i915, xe}: Extract DSPCLK_GATE_D from i915_reg to display

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move DSPCLK_GATE_D register definition to display header.
> This allows intel_gmbus.c free of i915_reg.h include.

Grammar, I think.

>
> v2: Drop common header in include and use display_regs.h (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Subject prefix, drm/i915. 

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_display_regs.h | 50 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_gmbus.c    |  1 -
>  drivers/gpu/drm/i915/i915_reg.h               | 50 -------------------
>  3 files changed, 50 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 1f922d013cd3..5136b7166775 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -160,6 +160,47 @@
>  
>  #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
>  
> +#define DSPCLK_GATE_D			_MMIO(0x6200)
> +#define VLV_DSPCLK_GATE_D		_MMIO(VLV_DISPLAY_BASE + 0x6200)
> +# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
> +# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
> +# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
> +# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
> +# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
> +# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
> +# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
> +# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */
> +# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
> +# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
> +# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
> +# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
> +# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
> +# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
> +# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
> +# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
> +# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
> +# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
> +# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
> +# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
> +# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
> +# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
> +# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
> +# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
> +# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
> +# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
> +# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
> +# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
> +# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
> +/*
> + * This bit must be set on the 830 to prevent hangs when turning off the
> + * overlay scaler.
> + */
> +# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
> +# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
> +# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
> +# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
> +# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
> +
>  /* Additional CHV pll/phy registers */
>  #define DPIO_PHY_STATUS			_MMIO(VLV_DISPLAY_BASE + 0x6240)
>  #define   DPLL_PORTD_READY_MASK		(0xf)
> @@ -2926,6 +2967,15 @@ enum skl_power_gate {
>  #define  LPT_PWM_GRANULARITY		(1 << 5)
>  #define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
>  
> +#define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
> +#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
> +#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
> +#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
> +#define  PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
> +#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
> +#define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
> +#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
> +
>  /* Gen4+ Timestamp and Pipe Frame time stamp registers */
>  #define GEN4_TIMESTAMP		_MMIO(0x2358)
>  #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index 2caff677600c..81b6c6991323 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -35,7 +35,6 @@
>  #include <drm/drm_print.h>
>  #include <drm/display/drm_hdcp_helper.h>
>  
> -#include "i915_reg.h"
>  #include "intel_de.h"
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5cd124083c17..dc13f9eb4cd7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -613,47 +613,6 @@
>  #define  DSTATE_GFX_CLOCK_GATING		(1 << 1)
>  #define  DSTATE_DOT_CLOCK_GATING		(1 << 0)
>  
> -#define DSPCLK_GATE_D			_MMIO(0x6200)
> -#define VLV_DSPCLK_GATE_D		_MMIO(VLV_DISPLAY_BASE + 0x6200)
> -# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
> -# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
> -# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
> -# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
> -# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
> -# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
> -# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
> -# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */
> -# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
> -# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
> -# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
> -# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
> -# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
> -# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
> -# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
> -# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
> -# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
> -# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
> -# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
> -# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
> -# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
> -# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
> -# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
> -# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
> -# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
> -# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
> -# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
> -# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
> -# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
> -/*
> - * This bit must be set on the 830 to prevent hangs when turning off the
> - * overlay scaler.
> - */
> -# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
> -# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
> -# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
> -# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
> -# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
> -
>  #define RENCLK_GATE_D1		_MMIO(0x6204)
>  # define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
>  # define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
> @@ -989,15 +948,6 @@
>  #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
>  #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
>  
> -#define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
> -#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
> -#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
> -#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
> -#define  PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
> -#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
> -#define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
> -#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
> -
>  #define  VLV_PMWGICZ				_MMIO(0x1300a4)
>  
>  #define  HSW_EDRAM_CAP				_MMIO(0x120010)

-- 
Jani Nikula, Intel

Re: [v2 06/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_device.c

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move GU_CNTL_PROTECTED to common header, this helps
> intel_display_device.c free from i915_reg.h dependency.

This doesn't mention the GMD ID stuff.

>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
>  drivers/gpu/drm/i915/display/intel_display_regs.h   | 3 +++
>  drivers/gpu/drm/i915/i915_reg.h                     | 8 --------
>  include/drm/intel/intel_gmd_common_regs.h           | 5 +++++
>  4 files changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 471f236c9ddf..f7cc4198a870 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -9,8 +9,8 @@
>  #include <drm/drm_drv.h>
>  #include <drm/drm_print.h>
>  #include <drm/intel/pciids.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
> -#include "i915_reg.h"
>  #include "intel_cx0_phy_regs.h"
>  #include "intel_de.h"
>  #include "intel_display.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 5136b7166775..3447ee229354 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -6,6 +6,9 @@
>  
>  #include "intel_display_reg_defs.h"
>  
> +#define GU_CNTL_PROTECTED		_MMIO(0x10100C)
> +#define   DEPRESENT			REG_BIT(9)
> +
>  #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
>  #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
>  #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 35122c997b8a..fac24a649d61 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -117,9 +117,6 @@
>   *  #define GEN8_BAR                    _MMIO(0xb888)
>   */
>  
> -#define GU_CNTL_PROTECTED		_MMIO(0x10100C)
> -#define   DEPRESENT			REG_BIT(9)
> -
>  #define GU_CNTL				_MMIO(0x101010)
>  #define   LMEM_INIT			REG_BIT(7)
>  #define   DRIVERFLR			REG_BIT(31)
> @@ -925,11 +922,6 @@
>  #define   MASK_WAKEMEM				REG_BIT(13)
>  #define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
>  
> -#define GMD_ID_DISPLAY				_MMIO(0x510a0)
> -#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
> -#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
> -#define   GMD_ID_STEP				REG_GENMASK(5, 0)
> -
>  /* PCH */
>  
>  #define SDEISR  _MMIO(0xc4000)
> diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
> index 8e9a574c87d9..489d59379ab0 100644
> --- a/include/drm/intel/intel_gmd_common_regs.h
> +++ b/include/drm/intel/intel_gmd_common_regs.h
> @@ -105,4 +105,9 @@
>  #define     PCODE_MBOX_DOMAIN_NONE		0x0
>  #define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
>  
> +#define GMD_ID_DISPLAY				_MMIO(0x510a0)
> +#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
> +#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
> +#define   GMD_ID_STEP				REG_GENMASK(5, 0)

Only display uses GMD_ID_DISPLAY register. I'd put this in display regs,
and define the register contents with GMD_ID_DISPLAY_* even if the
register contents are identical for display and non-display GMD
registers.

Main point is, we should use the common regs file as little as possible.

BR,
Jani.

> +
>  #endif

-- 
Jani Nikula, Intel

Re: [v2 05/19] drm/{i915, xe}: Extract pcode definitions to common header

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> There are certain register definitions which are commonly shared
> by i915, xe and display. Extract the same to a common header to
> avoid duplication.

I think starting a big new catch-all file for common registers is the
wrong direction. If we're adding new files, they should be per feature.

In this case, it's pcode registers, and the name should reflect that.

Later in the series more stuff gets added, and more files include it,
but it's not at all clear what they need from there. It would be so much
more obvious if it was per feature.

BR,
Jani.


>
> Move GEN6_PCODE_MAILBOX to common header to make intel_cdclk.c
> free from including i915_reg.h
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c |   2 +-
>  drivers/gpu/drm/i915/i915_reg.h            | 101 +------------------
>  include/drm/intel/intel_gmd_common_regs.h  | 108 +++++++++++++++++++++
>  3 files changed, 110 insertions(+), 101 deletions(-)
>  create mode 100644 include/drm/intel/intel_gmd_common_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 9bfbfbf34dc0..531db1b452d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -27,9 +27,9 @@
>  
>  #include <drm/drm_fixed.h>
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
>  #include "hsw_ips.h"
> -#include "i915_reg.h"
>  #include "intel_atomic.h"
>  #include "intel_audio.h"
>  #include "intel_cdclk.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dc13f9eb4cd7..35122c997b8a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -25,6 +25,7 @@
>  #ifndef _I915_REG_H_
>  #define _I915_REG_H_
>  
> +#include <drm/intel/intel_gmd_common_regs.h>
>  #include "i915_reg_defs.h"
>  #include "display/intel_display_reg_defs.h"
>  
> @@ -956,106 +957,6 @@
>  #define    EDRAM_WAYS_IDX(cap)			(((cap) >> 5) & 0x7)
>  #define    EDRAM_SETS_IDX(cap)			(((cap) >> 8) & 0x3)
>  
> -#define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
> -#define   GEN6_PCODE_READY			(1 << 31)
> -#define   GEN6_PCODE_MB_PARAM2			REG_GENMASK(23, 16)
> -#define   GEN6_PCODE_MB_PARAM1			REG_GENMASK(15, 8)
> -#define   GEN6_PCODE_MB_COMMAND			REG_GENMASK(7, 0)
> -#define   GEN6_PCODE_ERROR_MASK			0xFF
> -#define     GEN6_PCODE_SUCCESS			0x0
> -#define     GEN6_PCODE_ILLEGAL_CMD		0x1
> -#define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
> -#define     GEN6_PCODE_TIMEOUT			0x3
> -#define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
> -#define     GEN7_PCODE_TIMEOUT			0x2
> -#define     GEN7_PCODE_ILLEGAL_DATA		0x3
> -#define     GEN11_PCODE_ILLEGAL_SUBCOMMAND	0x4
> -#define     GEN11_PCODE_LOCKED			0x6
> -#define     GEN11_PCODE_REJECTED		0x11
> -#define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
> -#define   GEN6_PCODE_WRITE_RC6VIDS		0x4
> -#define   GEN6_PCODE_READ_RC6VIDS		0x5
> -#define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
> -#define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
> -#define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
> -#define   GEN9_PCODE_READ_MEM_LATENCY		0x6
> -#define     GEN9_MEM_LATENCY_LEVEL_3_7_MASK	REG_GENMASK(31, 24)
> -#define     GEN9_MEM_LATENCY_LEVEL_2_6_MASK	REG_GENMASK(23, 16)
> -#define     GEN9_MEM_LATENCY_LEVEL_1_5_MASK	REG_GENMASK(15, 8)
> -#define     GEN9_MEM_LATENCY_LEVEL_0_4_MASK	REG_GENMASK(7, 0)
> -#define   SKL_PCODE_LOAD_HDCP_KEYS		0x5
> -#define   SKL_PCODE_CDCLK_CONTROL		0x7
> -#define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
> -#define     SKL_CDCLK_READY_FOR_CHANGE		0x1
> -#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
> -#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
> -#define   GEN6_READ_OC_PARAMS			0xc
> -#define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
> -#define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
> -#define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
> -#define     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO	((0) | (0x2 << 8))
> -#define   DISPLAY_TO_PCODE_CDCLK_MAX		0x28D
> -#define   DISPLAY_TO_PCODE_VOLTAGE_MASK		REG_GENMASK(1, 0)
> -#define	  DISPLAY_TO_PCODE_VOLTAGE_MAX		DISPLAY_TO_PCODE_VOLTAGE_MASK
> -#define   DISPLAY_TO_PCODE_CDCLK_VALID		REG_BIT(27)
> -#define   DISPLAY_TO_PCODE_PIPE_COUNT_VALID	REG_BIT(31)
> -#define   DISPLAY_TO_PCODE_CDCLK_MASK		REG_GENMASK(25, 16)
> -#define   DISPLAY_TO_PCODE_PIPE_COUNT_MASK	REG_GENMASK(30, 28)
> -#define   DISPLAY_TO_PCODE_CDCLK(x)		REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
> -#define   DISPLAY_TO_PCODE_PIPE_COUNT(x)	REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
> -#define   DISPLAY_TO_PCODE_VOLTAGE(x)		REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
> -#define   DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
> -		((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
> -		(DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
> -		(DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
> -#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
> -#define     ICL_PCODE_REP_QGV_MASK		REG_GENMASK(1, 0)
> -#define     ICL_PCODE_REP_QGV_SAFE		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
> -#define     ICL_PCODE_REP_QGV_POLL		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
> -#define     ICL_PCODE_REP_QGV_REJECTED		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
> -#define     ADLS_PCODE_REP_PSF_MASK		REG_GENMASK(3, 2)
> -#define     ADLS_PCODE_REP_PSF_SAFE		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
> -#define     ADLS_PCODE_REP_PSF_POLL		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
> -#define     ADLS_PCODE_REP_PSF_REJECTED		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
> -#define     ICL_PCODE_REQ_QGV_PT_MASK		REG_GENMASK(7, 0)
> -#define     ICL_PCODE_REQ_QGV_PT(x)		REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
> -#define     ADLS_PCODE_REQ_PSF_PT_MASK		REG_GENMASK(10, 8)
> -#define     ADLS_PCODE_REQ_PSF_PT(x)		REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
> -#define   GEN6_PCODE_READ_D_COMP		0x10
> -#define   GEN6_PCODE_WRITE_D_COMP		0x11
> -#define   ICL_PCODE_EXIT_TCCOLD			0x12
> -#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
> -#define   DISPLAY_IPS_CONTROL			0x19
> -#define   TGL_PCODE_TCCOLD			0x26
> -#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED	REG_BIT(0)
> -#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ	0
> -#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ	REG_BIT(0)
> -            /* See also IPS_CTL */
> -#define     IPS_PCODE_CONTROL			(1 << 30)
> -#define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
> -#define   GEN9_PCODE_SAGV_CONTROL		0x21
> -#define     GEN9_SAGV_DISABLE			0x0
> -#define     GEN9_SAGV_IS_DISABLED		0x1
> -#define     GEN9_SAGV_ENABLE			0x3
> -#define   DG1_PCODE_STATUS			0x7E
> -#define     DG1_UNCORE_GET_INIT_STATUS		0x0
> -#define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
> -#define   PCODE_POWER_SETUP			0x7C
> -#define     POWER_SETUP_SUBCOMMAND_READ_I1	0x4
> -#define     POWER_SETUP_SUBCOMMAND_WRITE_I1	0x5
> -#define	    POWER_SETUP_I1_WATTS		REG_BIT(31)
> -#define	    POWER_SETUP_I1_SHIFT		6	/* 10.6 fixed point format */
> -#define	    POWER_SETUP_I1_DATA_MASK		REG_GENMASK(15, 0)
> -#define     POWER_SETUP_SUBCOMMAND_G8_ENABLE	0x6
> -#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
> -#define   XEHP_PCODE_FREQUENCY_CONFIG		0x6e	/* pvc */
> -/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
> -#define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
> -#define     PCODE_MBOX_FC_SC_READ_FUSED_PN	0x1
> -/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
> -/*   XEHP_PCODE_FREQUENCY_CONFIG param2 */
> -#define     PCODE_MBOX_DOMAIN_NONE		0x0
> -#define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
>  #define GEN6_PCODE_DATA				_MMIO(0x138128)
>  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
>  #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
> diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
> new file mode 100644
> index 000000000000..8e9a574c87d9
> --- /dev/null
> +++ b/include/drm/intel/intel_gmd_common_regs.h
> @@ -0,0 +1,108 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2026 Intel Corporation */
> +
> +#ifndef _INTEL_GMD_COMMON_REG_H_
> +#define _INTEL_GMD_COMMON_REG_H_
> +
> +#define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
> +#define   GEN6_PCODE_READY			(1 << 31)
> +#define   GEN6_PCODE_MB_PARAM2			REG_GENMASK(23, 16)
> +#define   GEN6_PCODE_MB_PARAM1			REG_GENMASK(15, 8)
> +#define   GEN6_PCODE_MB_COMMAND			REG_GENMASK(7, 0)
> +#define   GEN6_PCODE_ERROR_MASK			0xFF
> +#define     GEN6_PCODE_SUCCESS			0x0
> +#define     GEN6_PCODE_ILLEGAL_CMD		0x1
> +#define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
> +#define     GEN6_PCODE_TIMEOUT			0x3
> +#define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
> +#define     GEN7_PCODE_TIMEOUT			0x2
> +#define     GEN7_PCODE_ILLEGAL_DATA		0x3
> +#define     GEN11_PCODE_ILLEGAL_SUBCOMMAND	0x4
> +#define     GEN11_PCODE_LOCKED			0x6
> +#define     GEN11_PCODE_REJECTED		0x11
> +#define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
> +#define   GEN6_PCODE_WRITE_RC6VIDS		0x4
> +#define   GEN6_PCODE_READ_RC6VIDS		0x5
> +#define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
> +#define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
> +#define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
> +#define   GEN9_PCODE_READ_MEM_LATENCY		0x6
> +#define     GEN9_MEM_LATENCY_LEVEL_3_7_MASK	REG_GENMASK(31, 24)
> +#define     GEN9_MEM_LATENCY_LEVEL_2_6_MASK	REG_GENMASK(23, 16)
> +#define     GEN9_MEM_LATENCY_LEVEL_1_5_MASK	REG_GENMASK(15, 8)
> +#define     GEN9_MEM_LATENCY_LEVEL_0_4_MASK	REG_GENMASK(7, 0)
> +#define   SKL_PCODE_LOAD_HDCP_KEYS		0x5
> +#define   SKL_PCODE_CDCLK_CONTROL		0x7
> +#define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
> +#define     SKL_CDCLK_READY_FOR_CHANGE		0x1
> +#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
> +#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
> +#define   GEN6_READ_OC_PARAMS			0xc
> +#define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
> +#define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
> +#define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
> +#define     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO	((0) | (0x2 << 8))
> +#define   DISPLAY_TO_PCODE_CDCLK_MAX		0x28D
> +#define   DISPLAY_TO_PCODE_VOLTAGE_MASK		REG_GENMASK(1, 0)
> +#define	  DISPLAY_TO_PCODE_VOLTAGE_MAX		DISPLAY_TO_PCODE_VOLTAGE_MASK
> +#define   DISPLAY_TO_PCODE_CDCLK_VALID		REG_BIT(27)
> +#define   DISPLAY_TO_PCODE_PIPE_COUNT_VALID	REG_BIT(31)
> +#define   DISPLAY_TO_PCODE_CDCLK_MASK		REG_GENMASK(25, 16)
> +#define   DISPLAY_TO_PCODE_PIPE_COUNT_MASK	REG_GENMASK(30, 28)
> +#define   DISPLAY_TO_PCODE_CDCLK(x)		REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
> +#define   DISPLAY_TO_PCODE_PIPE_COUNT(x)	REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
> +#define   DISPLAY_TO_PCODE_VOLTAGE(x)		REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
> +#define   DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
> +		((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
> +		(DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
> +		(DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
> +#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
> +#define     ICL_PCODE_REP_QGV_MASK		REG_GENMASK(1, 0)
> +#define     ICL_PCODE_REP_QGV_SAFE		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
> +#define     ICL_PCODE_REP_QGV_POLL		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
> +#define     ICL_PCODE_REP_QGV_REJECTED		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
> +#define     ADLS_PCODE_REP_PSF_MASK		REG_GENMASK(3, 2)
> +#define     ADLS_PCODE_REP_PSF_SAFE		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
> +#define     ADLS_PCODE_REP_PSF_POLL		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
> +#define     ADLS_PCODE_REP_PSF_REJECTED		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
> +#define     ICL_PCODE_REQ_QGV_PT_MASK		REG_GENMASK(7, 0)
> +#define     ICL_PCODE_REQ_QGV_PT(x)		REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
> +#define     ADLS_PCODE_REQ_PSF_PT_MASK		REG_GENMASK(10, 8)
> +#define     ADLS_PCODE_REQ_PSF_PT(x)		REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
> +#define   GEN6_PCODE_READ_D_COMP		0x10
> +#define   GEN6_PCODE_WRITE_D_COMP		0x11
> +#define   ICL_PCODE_EXIT_TCCOLD			0x12
> +#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
> +#define   DISPLAY_IPS_CONTROL			0x19
> +#define   TGL_PCODE_TCCOLD			0x26
> +#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED	REG_BIT(0)
> +#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ	0
> +#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ	REG_BIT(0)
> +/* See also IPS_CTL */
> +#define     IPS_PCODE_CONTROL			(1 << 30)
> +#define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
> +#define   GEN9_PCODE_SAGV_CONTROL		0x21
> +#define     GEN9_SAGV_DISABLE			0x0
> +#define     GEN9_SAGV_IS_DISABLED		0x1
> +#define     GEN9_SAGV_ENABLE			0x3
> +#define   DG1_PCODE_STATUS			0x7E
> +#define     DG1_UNCORE_GET_INIT_STATUS		0x0
> +#define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
> +#define   PCODE_POWER_SETUP			0x7C
> +#define     POWER_SETUP_SUBCOMMAND_READ_I1	0x4
> +#define     POWER_SETUP_SUBCOMMAND_WRITE_I1	0x5
> +#define	    POWER_SETUP_I1_WATTS		REG_BIT(31)
> +#define	    POWER_SETUP_I1_SHIFT		6	/* 10.6 fixed point format */
> +#define	    POWER_SETUP_I1_DATA_MASK		REG_GENMASK(15, 0)
> +#define     POWER_SETUP_SUBCOMMAND_G8_ENABLE	0x6
> +#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
> +#define   XEHP_PCODE_FREQUENCY_CONFIG		0x6e	/* pvc */
> +/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
> +#define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
> +#define     PCODE_MBOX_FC_SC_READ_FUSED_PN	0x1
> +/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
> +/*   XEHP_PCODE_FREQUENCY_CONFIG param2 */
> +#define     PCODE_MBOX_DOMAIN_NONE		0x0
> +#define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
> +
> +#endif

-- 
Jani Nikula, Intel

Re: [v2 07/19] drm/{i915, xe}: Remove i915_reg.h from intel_dram.c

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Make intel_dram.c free from including i915_reg.h.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_regs.h | 6 +++++-
>  drivers/gpu/drm/i915/display/intel_dram.c         | 3 ++-
>  drivers/gpu/drm/i915/i915_reg.h                   | 6 ------
>  3 files changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 3447ee229354..f395b7d4d640 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -3075,6 +3075,10 @@ enum skl_power_gate {
>  #define   MTL_TRAS_MASK			REG_GENMASK(16, 8)
>  #define   MTL_TRDPRE_MASK		REG_GENMASK(7, 0)
>  
> -
> +#define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
> +#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
> +#define   MTL_N_OF_ENABLED_QGV_POINTS_MASK	REG_GENMASK(11, 8)
> +#define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
> +#define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
>  
>  #endif /* __INTEL_DISPLAY_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c
> index 170de304fe96..73a127dd6720 100644
> --- a/drivers/gpu/drm/i915/display/intel_dram.c
> +++ b/drivers/gpu/drm/i915/display/intel_dram.c
> @@ -7,10 +7,11 @@
>  
>  #include <drm/drm_managed.h>
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_common_regs.h>

dram only needs a few pcode things, so I'd prefer having a file for
pcode regs and only including that here.

>  
> -#include "i915_reg.h"
>  #include "intel_display_core.h"
>  #include "intel_display_utils.h"
> +#include "intel_display_regs.h"
>  #include "intel_dram.h"
>  #include "intel_mchbar_regs.h"
>  #include "intel_pcode.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fac24a649d61..c9fb9af1a35c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1005,12 +1005,6 @@
>  #define OROM_OFFSET				_MMIO(0x1020c0)
>  #define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
>  
> -#define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
> -#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
> -#define   MTL_N_OF_ENABLED_QGV_POINTS_MASK	REG_GENMASK(11, 8)
> -#define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
> -#define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
> -
>  #define MTL_MEDIA_GSI_BASE		0x380000
>  
>  #endif /* _I915_REG_H_ */

-- 
Jani Nikula, Intel

Re: [v2 08/19] drm/{i915, xe}: Removed i915_reg.h from intel_display.c

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move CHICKEN_PIPESL_1 register definition to display header.
> This allows intel_display.c free of i915_reg.h include.
>
> v2: Drop common header in include and use display_regs.h (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

*Remove in subject, also drm/i915 prefix only.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c  |  1 -
>  .../gpu/drm/i915/display/intel_display_regs.h | 23 +++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h               | 22 ------------------
>  3 files changed, 23 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7491e00e3858..b7d4ac7e5ff9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -50,7 +50,6 @@
>  #include "g4x_hdmi.h"
>  #include "hsw_ips.h"
>  #include "i915_config.h"
> -#include "i915_reg.h"
>  #include "i9xx_plane.h"
>  #include "i9xx_plane_regs.h"
>  #include "i9xx_wm.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index f395b7d4d640..b26e6a4ee1c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -1544,6 +1544,29 @@
>  #define   CHICKEN_FBC_STRIDE_MASK	REG_GENMASK(12, 0)
>  #define   CHICKEN_FBC_STRIDE(x)		REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
>  
> +#define _CHICKEN_PIPESL_1_A	0x420b0
> +#define _CHICKEN_PIPESL_1_B	0x420b4
> +#define CHICKEN_PIPESL_1(pipe)	_MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
> +#define   HSW_PRI_STRETCH_MAX_MASK	REG_GENMASK(28, 27)
> +#define   HSW_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
> +#define   HSW_PRI_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
> +#define   HSW_PRI_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
> +#define   HSW_PRI_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
> +#define   HSW_SPR_STRETCH_MAX_MASK	REG_GENMASK(26, 25)
> +#define   HSW_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
> +#define   HSW_SPR_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
> +#define   HSW_SPR_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
> +#define   HSW_SPR_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
> +#define   HSW_FBCQ_DIS			REG_BIT(22)
> +#define   HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
> +#define   SKL_PSR_MASK_PLANE_FLIP	REG_BIT(11) /* skl+ */
> +#define   SKL_PLANE1_STRETCH_MAX_MASK	REG_GENMASK(1, 0)
> +#define   SKL_PLANE1_STRETCH_MAX_X8	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
> +#define   SKL_PLANE1_STRETCH_MAX_X4	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
> +#define   SKL_PLANE1_STRETCH_MAX_X2	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
> +#define   SKL_PLANE1_STRETCH_MAX_X1	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
> +#define   BDW_UNMASK_VBL_TO_REGS_IN_SRD	REG_BIT(0) /* bdw */
> +
>  #define _CHICKEN_TRANS_A	0x420c0
>  #define _CHICKEN_TRANS_B	0x420c4
>  #define _CHICKEN_TRANS_C	0x420c8
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c9fb9af1a35c..c1d141e9ca47 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -878,28 +878,6 @@
>  #define CHICKEN_PAR2_1		_MMIO(0x42090)
>  #define   KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	REG_BIT(14)
>  
> -#define _CHICKEN_PIPESL_1_A	0x420b0
> -#define _CHICKEN_PIPESL_1_B	0x420b4
> -#define CHICKEN_PIPESL_1(pipe)	_MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
> -#define   HSW_PRI_STRETCH_MAX_MASK	REG_GENMASK(28, 27)
> -#define   HSW_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
> -#define   HSW_PRI_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
> -#define   HSW_PRI_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
> -#define   HSW_PRI_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
> -#define   HSW_SPR_STRETCH_MAX_MASK	REG_GENMASK(26, 25)
> -#define   HSW_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
> -#define   HSW_SPR_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
> -#define   HSW_SPR_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
> -#define   HSW_SPR_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
> -#define   HSW_FBCQ_DIS			REG_BIT(22)
> -#define   HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
> -#define   SKL_PSR_MASK_PLANE_FLIP	REG_BIT(11) /* skl+ */
> -#define   SKL_PLANE1_STRETCH_MAX_MASK	REG_GENMASK(1, 0)
> -#define   SKL_PLANE1_STRETCH_MAX_X8	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
> -#define   SKL_PLANE1_STRETCH_MAX_X4	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
> -#define   SKL_PLANE1_STRETCH_MAX_X2	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
> -#define   SKL_PLANE1_STRETCH_MAX_X1	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
> -#define   BDW_UNMASK_VBL_TO_REGS_IN_SRD	REG_BIT(0) /* bdw */
>  
>  #define DISP_ARB_CTL	_MMIO(0x45000)
>  #define   DISP_FBC_MEMORY_WAKE		REG_BIT(31)

-- 
Jani Nikula, Intel

Re: [v2 05/19] drm/{i915, xe}: Extract pcode definitions to common header

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> There are certain register definitions which are commonly shared
> by i915, xe and display. Extract the same to a common header to
> avoid duplication.
>
> Move GEN6_PCODE_MAILBOX to common header to make intel_cdclk.c
> free from including i915_reg.h
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c |   2 +-
>  drivers/gpu/drm/i915/i915_reg.h            | 101 +------------------
>  include/drm/intel/intel_gmd_common_regs.h  | 108 +++++++++++++++++++++
>  3 files changed, 110 insertions(+), 101 deletions(-)
>  create mode 100644 include/drm/intel/intel_gmd_common_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 9bfbfbf34dc0..531db1b452d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -27,9 +27,9 @@
>  
>  #include <drm/drm_fixed.h>
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
>  #include "hsw_ips.h"
> -#include "i915_reg.h"
>  #include "intel_atomic.h"
>  #include "intel_audio.h"
>  #include "intel_cdclk.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dc13f9eb4cd7..35122c997b8a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -25,6 +25,7 @@
>  #ifndef _I915_REG_H_
>  #define _I915_REG_H_
>  
> +#include <drm/intel/intel_gmd_common_regs.h>

Oh, I also dislike this, because it becomes unclear what needs them. The
benefit from more granular headers is that only the places that need
them can include them, and we can actually quickly check what includes
what instead of these indirect dependencies.

BR,
Jani.


-- 
Jani Nikula, Intel

Re: [v2 09/19] drm/{i915, xe}: Remove i915_reg.h from intel_overlay.c

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move GEN2_ISR and some interrupt definitions to common header.
> This removes dependency of i915_reg.h from intel_overlay.c.

Subject: drm/i915.

Here too I think this should be a dedicated file for the feture.

I actually think we might be able to refactor this away, but for the
time being a header in include/drm/intel is probably fine. But at least
you can just git grep who includes it (provided it's not included in
i915_reg.h!) and see what to do about it.

BR,
Jani.

>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_overlay.c |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h              | 36 -------------------
>  include/drm/intel/intel_gmd_common_regs.h    | 38 ++++++++++++++++++++
>  3 files changed, 39 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
> index 88eb7ae5765c..62026f7f71d3 100644
> --- a/drivers/gpu/drm/i915/display/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/display/intel_overlay.c
> @@ -28,6 +28,7 @@
>  
>  #include <drm/drm_fourcc.h>
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
>  #include "gem/i915_gem_internal.h"
>  #include "gem/i915_gem_object_frontbuffer.h"
> @@ -37,7 +38,6 @@
>  #include "gt/intel_ring.h"
>  
>  #include "i915_drv.h"
> -#include "i915_reg.h"
>  #include "intel_color_regs.h"
>  #include "intel_de.h"
>  #include "intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c1d141e9ca47..504ba9b2fb5b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -522,42 +522,6 @@
>  /* These are all the "old" interrupts */
>  #define ILK_BSD_USER_INTERRUPT				(1 << 5)
>  
> -#define I915_PM_INTERRUPT				(1 << 31)
> -#define I915_ISP_INTERRUPT				(1 << 22)
> -#define I915_LPE_PIPE_B_INTERRUPT			(1 << 21)
> -#define I915_LPE_PIPE_A_INTERRUPT			(1 << 20)
> -#define I915_MIPIC_INTERRUPT				(1 << 19)
> -#define I915_MIPIA_INTERRUPT				(1 << 18)
> -#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1 << 18)
> -#define I915_DISPLAY_PORT_INTERRUPT			(1 << 17)
> -#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1 << 16)
> -#define I915_MASTER_ERROR_INTERRUPT			(1 << 15)
> -#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1 << 14)
> -#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1 << 14) /* p-state */
> -#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1 << 13)
> -#define I915_HWB_OOM_INTERRUPT				(1 << 13)
> -#define I915_LPE_PIPE_C_INTERRUPT			(1 << 12)
> -#define I915_SYNC_STATUS_INTERRUPT			(1 << 12)
> -#define I915_MISC_INTERRUPT				(1 << 11)
> -#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1 << 11)
> -#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1 << 10)
> -#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1 << 10)
> -#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1 << 9)
> -#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1 << 9)
> -#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1 << 8)
> -#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1 << 8)
> -#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1 << 7)
> -#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1 << 6)
> -#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1 << 5)
> -#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1 << 4)
> -#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1 << 3)
> -#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1 << 2)
> -#define I915_DEBUG_INTERRUPT				(1 << 2)
> -#define I915_WINVALID_INTERRUPT				(1 << 1)
> -#define I915_USER_INTERRUPT				(1 << 1)
> -#define I915_ASLE_INTERRUPT				(1 << 0)
> -#define I915_BSD_USER_INTERRUPT				(1 << 25)
> -
>  #define GEN6_BSD_RNCID			_MMIO(0x12198)
>  
>  #define GEN7_FF_THREAD_MODE		_MMIO(0x20a0)
> diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
> index 489d59379ab0..2214cee38cf7 100644
> --- a/include/drm/intel/intel_gmd_common_regs.h
> +++ b/include/drm/intel/intel_gmd_common_regs.h
> @@ -110,4 +110,42 @@
>  #define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
>  #define   GMD_ID_STEP				REG_GENMASK(5, 0)
>  
> +#define GEN2_ISR       _MMIO(0x20ac)

This is duplication, and only used in display.

> +
> +#define I915_PM_INTERRUPT				(1 << 31)
> +#define I915_ISP_INTERRUPT				(1 << 22)
> +#define I915_LPE_PIPE_B_INTERRUPT			(1 << 21)
> +#define I915_LPE_PIPE_A_INTERRUPT			(1 << 20)
> +#define I915_MIPIC_INTERRUPT				(1 << 19)
> +#define I915_MIPIA_INTERRUPT				(1 << 18)
> +#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1 << 18)
> +#define I915_DISPLAY_PORT_INTERRUPT			(1 << 17)
> +#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1 << 16)
> +#define I915_MASTER_ERROR_INTERRUPT			(1 << 15)
> +#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1 << 14)
> +#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1 << 14) /* p-state */
> +#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1 << 13)
> +#define I915_HWB_OOM_INTERRUPT				(1 << 13)
> +#define I915_LPE_PIPE_C_INTERRUPT			(1 << 12)
> +#define I915_SYNC_STATUS_INTERRUPT			(1 << 12)
> +#define I915_MISC_INTERRUPT				(1 << 11)
> +#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1 << 11)
> +#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1 << 10)
> +#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1 << 10)
> +#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1 << 9)
> +#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1 << 9)
> +#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1 << 8)
> +#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1 << 8)
> +#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1 << 7)
> +#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1 << 6)
> +#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1 << 5)
> +#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1 << 4)
> +#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1 << 3)
> +#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1 << 2)
> +#define I915_DEBUG_INTERRUPT				(1 << 2)
> +#define I915_WINVALID_INTERRUPT				(1 << 1)
> +#define I915_USER_INTERRUPT				(1 << 1)
> +#define I915_ASLE_INTERRUPT				(1 << 0)
> +#define I915_BSD_USER_INTERRUPT				(1 << 25)
> +
>  #endif

-- 
Jani Nikula, Intel

Re: [v2 10/19] drm/{i915, xe}: Remove i915_reg.h from g4x_dp.c

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move DE_IRQ_REGS to common header to make g4x_dp.c
> free from i915_reg.h dependency.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/g4x_dp.c            |  2 +-
>  .../gpu/drm/i915/display/intel_display_regs.h    |  9 +++++++++
>  drivers/gpu/drm/i915/i915_reg.h                  | 16 ----------------
>  include/drm/intel/intel_gmd_common_regs.h        |  7 +++++++
>  4 files changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> index 4cb753177fd8..b2b63e811776 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -8,9 +8,9 @@
>  #include <linux/string_helpers.h>
>  
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
>  #include "g4x_dp.h"
> -#include "i915_reg.h"
>  #include "intel_audio.h"
>  #include "intel_backlight.h"
>  #include "intel_connector.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index b26e6a4ee1c3..eabee5abc23b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -3104,4 +3104,13 @@ enum skl_power_gate {
>  #define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
>  #define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
>  
> +#define DEISR   _MMIO(0x44000)
> +#define DEIMR   _MMIO(0x44004)
> +#define DEIIR   _MMIO(0x44008)
> +#define DEIER   _MMIO(0x4400c)
> +
> +#define DE_IRQ_REGS		I915_IRQ_REGS(DEIMR, \
> +					      DEIER, \
> +					      DEIIR)
> +
>  #endif /* __INTEL_DISPLAY_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 504ba9b2fb5b..c0c2fab99a47 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -728,15 +728,6 @@
>  #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
>  #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
>  
> -#define DEISR   _MMIO(0x44000)
> -#define DEIMR   _MMIO(0x44004)
> -#define DEIIR   _MMIO(0x44008)
> -#define DEIER   _MMIO(0x4400c)
> -
> -#define DE_IRQ_REGS		I915_IRQ_REGS(DEIMR, \
> -					      DEIER, \
> -					      DEIIR)
> -
>  #define GTISR   _MMIO(0x44010)
>  #define GTIMR   _MMIO(0x44014)
>  #define GTIIR   _MMIO(0x44018)
> @@ -864,13 +855,6 @@
>  #define   MASK_WAKEMEM				REG_BIT(13)
>  #define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
>  
> -/* PCH */
> -
> -#define SDEISR  _MMIO(0xc4000)
> -#define SDEIMR  _MMIO(0xc4004)
> -#define SDEIIR  _MMIO(0xc4008)
> -#define SDEIER  _MMIO(0xc400c)
> -
>  /* Icelake PPS_DATA and _ECC DIP Registers.
>   * These are available for transcoders B,C and eDP.
>   * Adding the _A so as to reuse the _MMIO_TRANS2
> diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
> index 2214cee38cf7..c8b2b5b2739c 100644
> --- a/include/drm/intel/intel_gmd_common_regs.h
> +++ b/include/drm/intel/intel_gmd_common_regs.h
> @@ -148,4 +148,11 @@
>  #define I915_ASLE_INTERRUPT				(1 << 0)
>  #define I915_BSD_USER_INTERRUPT				(1 << 25)
>  
> +/* PCH */
> +
> +#define SDEISR  _MMIO(0xc4000)
> +#define SDEIMR  _MMIO(0xc4004)
> +#define SDEIIR  _MMIO(0xc4008)
> +#define SDEIER  _MMIO(0xc400c)

These are only used by display and gvt. I don't know what we're going to
do about gvt in the long run, but at this point I'd be prepared to just
include the necessary display register headers directly. This is what we
do with all the other registers. There are no other users for these, and
IMO shouldn't be in the common header.

BR,
Jani.

> +
>  #endif

-- 
Jani Nikula, Intel

Re: [v2 12/19] drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move TRANS_CHICKEN1 reg to display header to make g4x_hdmi.c
> free from i915_reg.h dependency.
>
> v2: Remove from common header in include and use display_regs.h (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/g4x_hdmi.c           |  1 -
>  drivers/gpu/drm/i915/display/intel_display_regs.h | 12 ++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h                   | 12 ------------
>  3 files changed, 12 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> index 8b22447e8e23..5fe5067c4237 100644
> --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> @@ -8,7 +8,6 @@
>  #include <drm/drm_print.h>
>  
>  #include "g4x_hdmi.h"
> -#include "i915_reg.h"
>  #include "intel_atomic.h"
>  #include "intel_audio.h"
>  #include "intel_connector.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 477896faa79e..2c7cd9002da3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -2122,6 +2122,18 @@
>  #define  TRANS_BPC_6			REG_FIELD_PREP(TRANS_BPC_MASK, 2)
>  #define  TRANS_BPC_12			REG_FIELD_PREP(TRANS_BPC_MASK, 3)
>  
> +/* Icelake PPS_DATA and _ECC DIP Registers.
> + * These are available for transcoders B,C and eDP.
> + * Adding the _A so as to reuse the _MMIO_TRANS2
> + * definition, with which it offsets to the right location.
> + */
> +
> +#define _TRANSA_CHICKEN1	 0xf0060
> +#define _TRANSB_CHICKEN1	 0xf1060
> +#define TRANS_CHICKEN1(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
> +#define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
> +#define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
> +
>  #define _TRANSA_CHICKEN2	0xf0064
>  #define _TRANSB_CHICKEN2	0xf1064
>  #define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bd3871f458d6..5d640f7cfc23 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -836,18 +836,6 @@
>  #define   MASK_WAKEMEM				REG_BIT(13)
>  #define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
>  
> -/* Icelake PPS_DATA and _ECC DIP Registers.
> - * These are available for transcoders B,C and eDP.
> - * Adding the _A so as to reuse the _MMIO_TRANS2
> - * definition, with which it offsets to the right location.
> - */
> -
> -#define _TRANSA_CHICKEN1	 0xf0060
> -#define _TRANSB_CHICKEN1	 0xf1060
> -#define TRANS_CHICKEN1(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
> -#define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
> -#define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
> -
>  #define  VLV_PMWGICZ				_MMIO(0x1300a4)
>  
>  #define  HSW_EDRAM_CAP				_MMIO(0x120010)

-- 
Jani Nikula, Intel

Re: [v2 13/19] drm/{i915, xe}: Remove i915_reg.h from intel_rom.c

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Make intel_rom.c free from including i915_reg.h.
>
> v2: Use display header instead of gmd common include (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++++++
>  drivers/gpu/drm/i915/display/intel_rom.c          | 3 +--
>  drivers/gpu/drm/i915/i915_reg.h                   | 8 --------
>  3 files changed, 9 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 2c7cd9002da3..f468e0d20b92 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -9,6 +9,14 @@
>  #define GU_CNTL_PROTECTED		_MMIO(0x10100C)
>  #define   DEPRESENT			REG_BIT(9)
>  
> +#define PRIMARY_SPI_TRIGGER			_MMIO(0x102040)
> +#define PRIMARY_SPI_ADDRESS			_MMIO(0x102080)
> +#define PRIMARY_SPI_REGIONID			_MMIO(0x102084)
> +#define SPI_STATIC_REGIONS			_MMIO(0x102090)
> +#define   OPTIONROM_SPI_REGIONID_MASK		REG_GENMASK(7, 0)
> +#define OROM_OFFSET				_MMIO(0x1020c0)
> +#define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
> +
>  #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
>  #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
>  #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
> diff --git a/drivers/gpu/drm/i915/display/intel_rom.c b/drivers/gpu/drm/i915/display/intel_rom.c
> index c8f615315310..d7de53acaba9 100644
> --- a/drivers/gpu/drm/i915/display/intel_rom.c
> +++ b/drivers/gpu/drm/i915/display/intel_rom.c
> @@ -7,10 +7,9 @@
>  
>  #include <drm/drm_device.h>
>  
> -#include "i915_reg.h"
> -
>  #include "intel_rom.h"
>  #include "intel_uncore.h"
> +#include "intel_display_regs.h"
>  
>  struct intel_rom {
>  	/* for PCI ROM */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5d640f7cfc23..d43c04e491e1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -892,14 +892,6 @@
>  #define   SGGI_DIS			REG_BIT(15)
>  #define   SGR_DIS			REG_BIT(13)
>  
> -#define PRIMARY_SPI_TRIGGER			_MMIO(0x102040)
> -#define PRIMARY_SPI_ADDRESS			_MMIO(0x102080)
> -#define PRIMARY_SPI_REGIONID			_MMIO(0x102084)
> -#define SPI_STATIC_REGIONS			_MMIO(0x102090)
> -#define   OPTIONROM_SPI_REGIONID_MASK		REG_GENMASK(7, 0)
> -#define OROM_OFFSET				_MMIO(0x1020c0)
> -#define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
> -
>  #define MTL_MEDIA_GSI_BASE		0x380000
>  
>  #endif /* _I915_REG_H_ */

-- 
Jani Nikula, Intel

Re: [v2 14/19] drm/{i915, xe}: Remove i915_reg.h from intel_psr.c

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move some chicken registers to display header to make
> intel_psr.c free from including i915_reg.h.
>
> v2: Use display header instead of gmd common include (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_display_regs.h | 26 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_psr.c      |  1 -
>  drivers/gpu/drm/i915/i915_reg.h               | 26 -------------------
>  3 files changed, 26 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index f468e0d20b92..aafe71a3b410 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -363,6 +363,32 @@
>  #define OGAMC1			_MMIO(0x30020)
>  #define OGAMC0			_MMIO(0x30024)
>  
> +#define GEN8_CHICKEN_DCPR_1			_MMIO(0x46430)
> +#define   _LATENCY_REPORTING_REMOVED_PIPE_D	REG_BIT(31)
> +#define   SKL_SELECT_ALTERNATE_DC_EXIT		REG_BIT(30)
> +#define   _LATENCY_REPORTING_REMOVED_PIPE_C	REG_BIT(25)
> +#define   _LATENCY_REPORTING_REMOVED_PIPE_B	REG_BIT(24)
> +#define   _LATENCY_REPORTING_REMOVED_PIPE_A	REG_BIT(23)
> +#define   LATENCY_REPORTING_REMOVED(pipe)	_PICK((pipe), \
> +						      _LATENCY_REPORTING_REMOVED_PIPE_A, \
> +						      _LATENCY_REPORTING_REMOVED_PIPE_B, \
> +						      _LATENCY_REPORTING_REMOVED_PIPE_C, \
> +						      _LATENCY_REPORTING_REMOVED_PIPE_D)
> +#define   ICL_DELAY_PMRSP			REG_BIT(22)
> +#define   DISABLE_FLR_SRC			REG_BIT(15)
> +#define   MASK_WAKEMEM				REG_BIT(13)
> +#define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
> +
> +#define CHICKEN_PAR1_1		_MMIO(0x42080)
> +#define   IGNORE_KVMR_PIPE_A		REG_BIT(23)
> +#define   KBL_ARB_FILL_SPARE_22		REG_BIT(22)
> +#define   DIS_RAM_BYPASS_PSR2_MAN_TRACK	REG_BIT(16)
> +#define   SKL_DE_COMPRESSED_HASH_MODE	REG_BIT(15)
> +#define   HSW_MASK_VBL_TO_PIPE_IN_SRD	REG_BIT(15) /* hsw/bdw */
> +#define   FORCE_ARB_IDLE_PLANES		REG_BIT(14)
> +#define   SKL_EDP_PSR_FIX_RDWRAP	REG_BIT(3)
> +#define   IGNORE_PSR2_HW_TRACKING	REG_BIT(1)
> +
>  #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
>  #define   BXT_GMBUS_GATING_DIS		(1 << 14)
>  #define   DG2_DPFC_GATING_DIS		REG_BIT(31)
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 62208ffc5101..bde7dbfe15a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -29,7 +29,6 @@
>  #include <drm/drm_print.h>
>  #include <drm/drm_vblank.h>
>  
> -#include "i915_reg.h"
>  #include "intel_alpm.h"
>  #include "intel_atomic.h"
>  #include "intel_crtc.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d43c04e491e1..62d58d7cfa7a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -806,36 +806,10 @@
>  #define   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	REG_BIT(5)
>  #define   CHICKEN3_DGMG_DONE_FIX_DISABLE	REG_BIT(2)
>  
> -#define CHICKEN_PAR1_1		_MMIO(0x42080)
> -#define   IGNORE_KVMR_PIPE_A		REG_BIT(23)
> -#define   KBL_ARB_FILL_SPARE_22		REG_BIT(22)
> -#define   DIS_RAM_BYPASS_PSR2_MAN_TRACK	REG_BIT(16)
> -#define   SKL_DE_COMPRESSED_HASH_MODE	REG_BIT(15)
> -#define   HSW_MASK_VBL_TO_PIPE_IN_SRD	REG_BIT(15) /* hsw/bdw */
> -#define   FORCE_ARB_IDLE_PLANES		REG_BIT(14)
> -#define   SKL_EDP_PSR_FIX_RDWRAP	REG_BIT(3)
> -#define   IGNORE_PSR2_HW_TRACKING	REG_BIT(1)
> -
>  #define CHICKEN_PAR2_1		_MMIO(0x42090)
>  #define   KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	REG_BIT(14)
>  
>  
> -#define GEN8_CHICKEN_DCPR_1			_MMIO(0x46430)
> -#define   _LATENCY_REPORTING_REMOVED_PIPE_D	REG_BIT(31)
> -#define   SKL_SELECT_ALTERNATE_DC_EXIT		REG_BIT(30)
> -#define   _LATENCY_REPORTING_REMOVED_PIPE_C	REG_BIT(25)
> -#define   _LATENCY_REPORTING_REMOVED_PIPE_B	REG_BIT(24)
> -#define   _LATENCY_REPORTING_REMOVED_PIPE_A	REG_BIT(23)
> -#define   LATENCY_REPORTING_REMOVED(pipe)	_PICK((pipe), \
> -						      _LATENCY_REPORTING_REMOVED_PIPE_A, \
> -						      _LATENCY_REPORTING_REMOVED_PIPE_B, \
> -						      _LATENCY_REPORTING_REMOVED_PIPE_C, \
> -						      _LATENCY_REPORTING_REMOVED_PIPE_D)
> -#define   ICL_DELAY_PMRSP			REG_BIT(22)
> -#define   DISABLE_FLR_SRC			REG_BIT(15)
> -#define   MASK_WAKEMEM				REG_BIT(13)
> -#define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
> -
>  #define  VLV_PMWGICZ				_MMIO(0x1300a4)
>  
>  #define  HSW_EDRAM_CAP				_MMIO(0x120010)

-- 
Jani Nikula, Intel

Re: [v2 15/19] drm/{i915, xe}: Remove i915_reg.h from intel_fifo_underrun.c

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move GEN7_ERR_INT reg to common header to make intel_fifo_underrun.c
> free from including i915_reg.h.

I think these should be in a display register header, not the common
one. The users are display and gvt, apart from a single use in
gt_record_global_regs() which should be moved to display. I can send a
patch for that.

BR,
Jani.



>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  .../drm/i915/display/intel_fifo_underrun.c    |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h               | 23 -------------------
>  include/drm/intel/intel_gmd_common_regs.h     | 23 +++++++++++++++++++
>  3 files changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> index b413b3e871d8..c834be759e40 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> @@ -28,8 +28,8 @@
>  #include <linux/seq_buf.h>
>  
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
> -#include "i915_reg.h"
>  #include "intel_de.h"
>  #include "intel_display_irq.h"
>  #include "intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 62d58d7cfa7a..0af2c9c8dc0f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -326,29 +326,6 @@
>  #define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
>  #define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)
>  
> -#define GEN7_ERR_INT	_MMIO(0x44040)
> -#define   ERR_INT_POISON		(1 << 31)
> -#define   ERR_INT_INVALID_GTT_PTE	(1 << 29)
> -#define   ERR_INT_INVALID_PTE_DATA	(1 << 28)
> -#define   ERR_INT_SPRITE_C_FAULT	(1 << 23)
> -#define   ERR_INT_PRIMARY_C_FAULT	(1 << 22)
> -#define   ERR_INT_CURSOR_C_FAULT	(1 << 21)
> -#define   ERR_INT_SPRITE_B_FAULT	(1 << 20)
> -#define   ERR_INT_PRIMARY_B_FAULT	(1 << 19)
> -#define   ERR_INT_CURSOR_B_FAULT	(1 << 18)
> -#define   ERR_INT_SPRITE_A_FAULT	(1 << 17)
> -#define   ERR_INT_PRIMARY_A_FAULT	(1 << 16)
> -#define   ERR_INT_CURSOR_A_FAULT	(1 << 15)
> -#define   ERR_INT_MMIO_UNCLAIMED	(1 << 13)
> -#define   ERR_INT_PIPE_CRC_DONE_C	(1 << 8)
> -#define   ERR_INT_FIFO_UNDERRUN_C	(1 << 6)
> -#define   ERR_INT_PIPE_CRC_DONE_B	(1 << 5)
> -#define   ERR_INT_FIFO_UNDERRUN_B	(1 << 3)
> -#define   ERR_INT_PIPE_CRC_DONE_A	(1 << 2)
> -#define   ERR_INT_PIPE_CRC_DONE(pipe)	(1 << (2 + (pipe) * 3))
> -#define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
> -#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
> -
>  #define FPGA_DBG		_MMIO(0x42300)
>  #define   FPGA_DBG_RM_NOCLAIM	REG_BIT(31)
>  
> diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
> index 049349c365e3..2b2a7f21529a 100644
> --- a/include/drm/intel/intel_gmd_common_regs.h
> +++ b/include/drm/intel/intel_gmd_common_regs.h
> @@ -169,4 +169,27 @@
>  #define   INSTPM_TLB_INVALIDATE	(1 << 9)
>  #define   INSTPM_SYNC_FLUSH	(1 << 5)
>  
> +#define GEN7_ERR_INT	_MMIO(0x44040)
> +#define   ERR_INT_POISON		(1 << 31)
> +#define   ERR_INT_INVALID_GTT_PTE	(1 << 29)
> +#define   ERR_INT_INVALID_PTE_DATA	(1 << 28)
> +#define   ERR_INT_SPRITE_C_FAULT	(1 << 23)
> +#define   ERR_INT_PRIMARY_C_FAULT	(1 << 22)
> +#define   ERR_INT_CURSOR_C_FAULT	(1 << 21)
> +#define   ERR_INT_SPRITE_B_FAULT	(1 << 20)
> +#define   ERR_INT_PRIMARY_B_FAULT	(1 << 19)
> +#define   ERR_INT_CURSOR_B_FAULT	(1 << 18)
> +#define   ERR_INT_SPRITE_A_FAULT	(1 << 17)
> +#define   ERR_INT_PRIMARY_A_FAULT	(1 << 16)
> +#define   ERR_INT_CURSOR_A_FAULT	(1 << 15)
> +#define   ERR_INT_MMIO_UNCLAIMED	(1 << 13)
> +#define   ERR_INT_PIPE_CRC_DONE_C	(1 << 8)
> +#define   ERR_INT_FIFO_UNDERRUN_C	(1 << 6)
> +#define   ERR_INT_PIPE_CRC_DONE_B	(1 << 5)
> +#define   ERR_INT_FIFO_UNDERRUN_B	(1 << 3)
> +#define   ERR_INT_PIPE_CRC_DONE_A	(1 << 2)
> +#define   ERR_INT_PIPE_CRC_DONE(pipe)	(1 << (2 + (pipe) * 3))
> +#define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
> +#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
> +
>  #endif

-- 
Jani Nikula, Intel

Re: [v2 16/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_irq.c

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move VLV_IRQ_REGS to common header to make intel_display_irq.c
> free from including i915_reg.h.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_irq.c  |  2 +-
>  .../gpu/drm/i915/display/intel_display_regs.h | 28 +++++-----
>  drivers/gpu/drm/i915/i915_reg.h               | 52 ------------------
>  include/drm/intel/intel_gmd_common_regs.h     | 54 +++++++++++++++++++
>  4 files changed, 69 insertions(+), 67 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 9adeebb376b1..206c0d004646 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -5,8 +5,8 @@
>  
>  #include <drm/drm_print.h>
>  #include <drm/drm_vblank.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
> -#include "i915_reg.h"
>  #include "icl_dsi_regs.h"
>  #include "intel_crtc.h"
>  #include "intel_de.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index aafe71a3b410..fb21b1cf6124 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -90,20 +90,6 @@
>  #define   DERRMR_PIPEC_VBLANK		(1 << 21)
>  #define   DERRMR_PIPEC_HBLANK		(1 << 22)
>  
> -#define VLV_IRQ_REGS		I915_IRQ_REGS(VLV_IMR, \
> -					      VLV_IER, \
> -					      VLV_IIR)
> -
> -#define VLV_EIR		_MMIO(VLV_DISPLAY_BASE + 0x20b0)
> -#define VLV_EMR		_MMIO(VLV_DISPLAY_BASE + 0x20b4)
> -#define VLV_ESR		_MMIO(VLV_DISPLAY_BASE + 0x20b8)
> -#define   VLV_ERROR_GUNIT_TLB_DATA			(1 << 6)
> -#define   VLV_ERROR_GUNIT_TLB_PTE			(1 << 5)
> -#define   VLV_ERROR_PAGE_TABLE				(1 << 4)
> -#define   VLV_ERROR_CLAIM				(1 << 0)
> -
> -#define VLV_ERROR_REGS		I915_ERROR_REGS(VLV_EMR, VLV_EIR)
> -
>  #define _MBUS_ABOX0_CTL			0x45038
>  #define _MBUS_ABOX1_CTL			0x45048
>  #define _MBUS_ABOX2_CTL			0x4504C
> @@ -3166,4 +3152,18 @@ enum skl_power_gate {
>  #define   FW_BLC_SELF_FIFO_MASK    REG_BIT(16) /* 945 only */
>  #define   FW_BLC_SELF_EN           REG_BIT(15) /* 945 only */
>  
> +#define VLV_IRQ_REGS		I915_IRQ_REGS(VLV_IMR, \
> +					      VLV_IER, \
> +					      VLV_IIR)
> +
> +#define VLV_EIR		_MMIO(VLV_DISPLAY_BASE + 0x20b0)
> +#define VLV_EMR		_MMIO(VLV_DISPLAY_BASE + 0x20b4)
> +#define VLV_ESR		_MMIO(VLV_DISPLAY_BASE + 0x20b8)
> +#define   VLV_ERROR_GUNIT_TLB_DATA			(1 << 6)
> +#define   VLV_ERROR_GUNIT_TLB_PTE			(1 << 5)
> +#define   VLV_ERROR_PAGE_TABLE				(1 << 4)
> +#define   VLV_ERROR_CLAIM				(1 << 0)
> +
> +#define VLV_ERROR_REGS		I915_ERROR_REGS(VLV_EMR, VLV_EIR)
> +
>  #endif /* __INTEL_DISPLAY_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0af2c9c8dc0f..a85e2d9ab561 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -336,9 +336,6 @@
>  
>  #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
>  #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
> -#define SCPD0		_MMIO(0x209c) /* 915+ only */
> -#define  SCPD_FBC_IGNORE_3D			(1 << 6)
> -#define  CSTATE_RENDER_CLOCK_GATE_DISABLE	(1 << 5)
>  #define GEN2_IER	_MMIO(0x20a0)
>  #define GEN2_IIR	_MMIO(0x20a4)
>  #define GEN2_IMR	_MMIO(0x20a8)
> @@ -352,13 +349,6 @@
>  #define   GINT_DIS		(1 << 22)
>  #define   GCFG_DIS		(1 << 8)
>  #define VLV_GUNIT_CLOCK_GATE2	_MMIO(VLV_DISPLAY_BASE + 0x2064)
> -#define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
> -#define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
> -#define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
> -#define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
> -#define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
> -#define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
> -#define VLV_PCBR_ADDR_SHIFT	12
>  
>  #define EIR		_MMIO(0x20b0)
>  #define EMR		_MMIO(0x20b4)
> @@ -683,11 +673,6 @@
>  #define PCH_3DCGDIS1		_MMIO(0x46024)
>  # define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
>  
> -/* Display Internal Timeout Register */
> -#define RM_TIMEOUT		_MMIO(0x42060)
> -#define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
> -#define  MMIO_TIMEOUT_US(us)	((us) << 0)
> -
>  #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
>  #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
>  
> @@ -700,24 +685,6 @@
>  					      GTIER, \
>  					      GTIIR)
>  
> -#define GEN8_MASTER_IRQ			_MMIO(0x44200)
> -#define  GEN8_MASTER_IRQ_CONTROL	(1 << 31)
> -#define  GEN8_PCU_IRQ			(1 << 30)
> -#define  GEN8_DE_PCH_IRQ		(1 << 23)
> -#define  GEN8_DE_MISC_IRQ		(1 << 22)
> -#define  GEN8_DE_PORT_IRQ		(1 << 20)
> -#define  GEN8_DE_PIPE_C_IRQ		(1 << 18)
> -#define  GEN8_DE_PIPE_B_IRQ		(1 << 17)
> -#define  GEN8_DE_PIPE_A_IRQ		(1 << 16)
> -#define  GEN8_DE_PIPE_IRQ(pipe)		(1 << (16 + (pipe)))
> -#define  GEN8_GT_VECS_IRQ		(1 << 6)
> -#define  GEN8_GT_GUC_IRQ		(1 << 5)
> -#define  GEN8_GT_PM_IRQ			(1 << 4)
> -#define  GEN8_GT_VCS1_IRQ		(1 << 3) /* NB: VCS2 in bspec! */
> -#define  GEN8_GT_VCS0_IRQ		(1 << 2) /* NB: VCS1 in bpsec! */
> -#define  GEN8_GT_BCS_IRQ		(1 << 1)
> -#define  GEN8_GT_RCS_IRQ		(1 << 0)
> -
>  #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
>  #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
>  #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
> @@ -743,25 +710,6 @@
>  						      GEN8_PCU_IER, \
>  						      GEN8_PCU_IIR)
>  
> -#define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
> -#define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
> -#define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
> -#define GEN11_GU_MISC_IER	_MMIO(0x444fc)
> -#define  GEN11_GU_MISC_GSE	(1 << 27)
> -
> -#define GEN11_GU_MISC_IRQ_REGS		I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
> -						      GEN11_GU_MISC_IER, \
> -						      GEN11_GU_MISC_IIR)
> -
> -#define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
> -#define  GEN11_MASTER_IRQ		(1 << 31)
> -#define  GEN11_PCU_IRQ			(1 << 30)
> -#define  GEN11_GU_MISC_IRQ		(1 << 29)
> -#define  GEN11_DISPLAY_IRQ		(1 << 16)
> -#define  GEN11_GT_DW_IRQ(x)		(1 << (x))
> -#define  GEN11_GT_DW1_IRQ		(1 << 1)
> -#define  GEN11_GT_DW0_IRQ		(1 << 0)
> -
>  #define DG1_MSTR_TILE_INTR		_MMIO(0x190008)
>  #define   DG1_MSTR_IRQ			REG_BIT(31)
>  #define   DG1_MSTR_TILE(t)		REG_BIT(t)
> diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
> index 2b2a7f21529a..9bc234135454 100644
> --- a/include/drm/intel/intel_gmd_common_regs.h
> +++ b/include/drm/intel/intel_gmd_common_regs.h
> @@ -111,6 +111,9 @@
>  #define   GMD_ID_STEP				REG_GENMASK(5, 0)
>  
>  #define GEN2_ISR       _MMIO(0x20ac)
> +#define SCPD0		_MMIO(0x209c) /* 915+ only */
> +#define  SCPD_FBC_IGNORE_3D			(1 << 6)
> +#define  CSTATE_RENDER_CLOCK_GATE_DISABLE	(1 << 5)
>  
>  #define I915_PM_INTERRUPT				(1 << 31)
>  #define I915_ISP_INTERRUPT				(1 << 22)
> @@ -192,4 +195,55 @@
>  #define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
>  #define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
>  
> +#define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
> +#define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
> +#define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
> +#define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
> +#define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
> +#define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
> +#define VLV_PCBR_ADDR_SHIFT	12
> +
> +#define GEN8_MASTER_IRQ			_MMIO(0x44200)
> +#define  GEN8_MASTER_IRQ_CONTROL	(1 << 31)
> +#define  GEN8_PCU_IRQ			(1 << 30)
> +#define  GEN8_DE_PCH_IRQ		(1 << 23)
> +#define  GEN8_DE_MISC_IRQ		(1 << 22)
> +#define  GEN8_DE_PORT_IRQ		(1 << 20)
> +#define  GEN8_DE_PIPE_C_IRQ		(1 << 18)
> +#define  GEN8_DE_PIPE_B_IRQ		(1 << 17)
> +#define  GEN8_DE_PIPE_A_IRQ		(1 << 16)
> +#define  GEN8_DE_PIPE_IRQ(pipe)		(1 << (16 + (pipe)))
> +#define  GEN8_GT_VECS_IRQ		(1 << 6)
> +#define  GEN8_GT_GUC_IRQ		(1 << 5)
> +#define  GEN8_GT_PM_IRQ			(1 << 4)
> +#define  GEN8_GT_VCS1_IRQ		(1 << 3) /* NB: VCS2 in bspec! */
> +#define  GEN8_GT_VCS0_IRQ		(1 << 2) /* NB: VCS1 in bpsec! */
> +#define  GEN8_GT_BCS_IRQ		(1 << 1)
> +#define  GEN8_GT_RCS_IRQ		(1 << 0)
> +
> +
> +#define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
> +#define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
> +#define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
> +#define GEN11_GU_MISC_IER	_MMIO(0x444fc)
> +#define  GEN11_GU_MISC_GSE	(1 << 27)
> +
> +#define GEN11_GU_MISC_IRQ_REGS		I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
> +						      GEN11_GU_MISC_IER, \
> +						      GEN11_GU_MISC_IIR)
> +
> +/* Display Internal Timeout Register */
> +#define RM_TIMEOUT		_MMIO(0x42060)
> +#define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
> +#define  MMIO_TIMEOUT_US(us)	((us) << 0)

These should be in display.

> +
> +#define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
> +#define  GEN11_MASTER_IRQ		(1 << 31)
> +#define  GEN11_PCU_IRQ			(1 << 30)
> +#define  GEN11_GU_MISC_IRQ		(1 << 29)
> +#define  GEN11_DISPLAY_IRQ		(1 << 16)
> +#define  GEN11_GT_DW_IRQ(x)		(1 << (x))
> +#define  GEN11_GT_DW1_IRQ		(1 << 1)
> +#define  GEN11_GT_DW0_IRQ		(1 << 0)

All the irq registers should be a file of their own.

> +
>  #endif

-- 
Jani Nikula, Intel

Re: [v2 17/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_power_well.c

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Make intel_display_power_well.c free from including i915_reg.h.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
>  drivers/gpu/drm/i915/display/intel_display_regs.h       | 2 ++
>  drivers/gpu/drm/i915/i915_reg.h                         | 3 ---
>  3 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index db185a859133..8a1f1c61c6da 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -6,8 +6,8 @@
>  #include <linux/iopoll.h>
>  
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_common_regs.h>

Again, I dislike the catch-all header, because I have no idea why this
is included. More granular is better.

BR,
Jani.

>  
> -#include "i915_reg.h"
>  #include "intel_backlight_regs.h"
>  #include "intel_combo_phy.h"
>  #include "intel_combo_phy_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index fb21b1cf6124..1def3dccdf61 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -319,6 +319,8 @@
>  #define  FW_CSPWRDWNEN		(1 << 15)
>  
>  #define MI_ARB_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6504)
> +/* Disable display A/B trickle feed */
> +#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
>  
>  #define CZCLK_CDCLK_FREQ_RATIO	_MMIO(VLV_DISPLAY_BASE + 0x6508)
>  #define   CDCLK_FREQ_SHIFT	4
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a85e2d9ab561..c68a64bc7646 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -428,9 +428,6 @@
>  #define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
>  #define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)
>  
> -/* Disable display A/B trickle feed */
> -#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
> -
>  /* Set display plane priority */
>  #define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
>  #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */

-- 
Jani Nikula, Intel

Re: [v2 19/19] drm/{i915, xe}: Remove i915_reg.h from display

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Make display files free from including i915_reg.h.

Yeah, I'd like this with more granular headers, please.

>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/hsw_ips.c               | 2 +-
>  drivers/gpu/drm/i915/display/i9xx_plane.c            | 1 -
>  drivers/gpu/drm/i915/display/icl_dsi.c               | 1 -
>  drivers/gpu/drm/i915/display/intel_backlight.c       | 1 -
>  drivers/gpu/drm/i915/display/intel_bw.c              | 2 +-
>  drivers/gpu/drm/i915/display/intel_casf.c            | 1 -
>  drivers/gpu/drm/i915/display/intel_ddi.c             | 2 +-
>  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
>  drivers/gpu/drm/i915/display/intel_display_power.c   | 2 +-
>  drivers/gpu/drm/i915/display/intel_display_wa.c      | 1 -
>  drivers/gpu/drm/i915/display/intel_dmc.c             | 1 -
>  drivers/gpu/drm/i915/display/intel_fdi.c             | 1 -
>  drivers/gpu/drm/i915/display/intel_hdcp.c            | 2 +-
>  drivers/gpu/drm/i915/display/intel_hotplug_irq.c     | 1 -
>  drivers/gpu/drm/i915/display/intel_lt_phy.c          | 1 -
>  drivers/gpu/drm/i915/display/intel_pps.c             | 1 -
>  drivers/gpu/drm/i915/display/intel_tc.c              | 2 +-
>  drivers/gpu/drm/i915/display/skl_watermark.c         | 2 +-
>  drivers/gpu/drm/i915/display/vlv_dsi.c               | 1 -
>  19 files changed, 8 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
> index 008d339d5c21..290d54fe87e4 100644
> --- a/drivers/gpu/drm/i915/display/hsw_ips.c
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> @@ -6,9 +6,9 @@
>  #include <linux/debugfs.h>
>  
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
>  #include "hsw_ips.h"
> -#include "i915_reg.h"
>  #include "intel_color_regs.h"
>  #include "intel_de.h"
>  #include "intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index b1fecf178906..9c16753a1f3b 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -10,7 +10,6 @@
>  #include <drm/drm_fourcc.h>
>  #include <drm/drm_print.h>
>  
> -#include "i915_reg.h"
>  #include "i9xx_plane.h"
>  #include "i9xx_plane_regs.h"
>  #include "intel_atomic.h"
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index c8e0333706c1..7cf511a6c0f9 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -34,7 +34,6 @@
>  #include <drm/drm_print.h>
>  #include <drm/drm_probe_helper.h>
>  
> -#include "i915_reg.h"
>  #include "icl_dsi.h"
>  #include "icl_dsi_regs.h"
>  #include "intel_atomic.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
> index a68fdbd2acb9..34e95f05936e 100644
> --- a/drivers/gpu/drm/i915/display/intel_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_backlight.c
> @@ -12,7 +12,6 @@
>  #include <drm/drm_file.h>
>  #include <drm/drm_print.h>
>  
> -#include "i915_reg.h"
>  #include "intel_backlight.h"
>  #include "intel_backlight_regs.h"
>  #include "intel_connector.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 4ee3f5172f4e..372081d80aa8 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -5,8 +5,8 @@
>  
>  #include <drm/drm_atomic_state_helper.h>
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
> -#include "i915_reg.h"
>  #include "intel_bw.h"
>  #include "intel_crtc.h"
>  #include "intel_display_core.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
> index 0fe4398a1a4e..b167af31de5b 100644
> --- a/drivers/gpu/drm/i915/display/intel_casf.c
> +++ b/drivers/gpu/drm/i915/display/intel_casf.c
> @@ -3,7 +3,6 @@
>  
>  #include <drm/drm_print.h>
>  
> -#include "i915_reg.h"
>  #include "intel_casf.h"
>  #include "intel_casf_regs.h"
>  #include "intel_de.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index d8739e2bb004..4bec15352d0f 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -33,8 +33,8 @@
>  #include <drm/display/drm_scdc_helper.h>
>  #include <drm/drm_print.h>
>  #include <drm/drm_privacy_screen_consumer.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
> -#include "i915_reg.h"
>  #include "icl_dsi.h"
>  #include "intel_alpm.h"
>  #include "intel_audio.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index aba13e8a9051..07cb56f80e88 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -13,9 +13,9 @@
>  #include <drm/drm_file.h>
>  #include <drm/drm_fourcc.h>
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
>  #include "hsw_ips.h"
> -#include "i915_reg.h"
>  #include "i9xx_wm_regs.h"
>  #include "intel_alpm.h"
>  #include "intel_bo.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index d27397f43863..20dadabcd812 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -7,8 +7,8 @@
>  #include <linux/string_helpers.h>
>  
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
> -#include "i915_reg.h"
>  #include "intel_backlight_regs.h"
>  #include "intel_cdclk.h"
>  #include "intel_clock_gating.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
> index 581d943b9bdc..518df619f5e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> @@ -5,7 +5,6 @@
>  
>  #include <drm/drm_print.h>
>  
> -#include "i915_reg.h"
>  #include "intel_de.h"
>  #include "intel_display_core.h"
>  #include "intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 1182bc9a2e6d..8df06b993890 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -29,7 +29,6 @@
>  #include <drm/drm_file.h>
>  #include <drm/drm_print.h>
>  
> -#include "i915_reg.h"
>  #include "intel_crtc.h"
>  #include "intel_de.h"
>  #include "intel_display_power_well.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index 5bb0090dd5ed..24ce8a7842c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -8,7 +8,6 @@
>  #include <drm/drm_fixed.h>
>  #include <drm/drm_print.h>
>  
> -#include "i915_reg.h"
>  #include "intel_atomic.h"
>  #include "intel_crtc.h"
>  #include "intel_ddi.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 7114fc405c29..db15bf1980c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -17,8 +17,8 @@
>  #include <drm/display/drm_hdcp_helper.h>
>  #include <drm/drm_print.h>
>  #include <drm/intel/i915_component.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
> -#include "i915_reg.h"
>  #include "intel_connector.h"
>  #include "intel_de.h"
>  #include "intel_display_jiffies.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index 82c39e4ffa37..8865cb2ac569 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -5,7 +5,6 @@
>  
>  #include <drm/drm_print.h>
>  
> -#include "i915_reg.h"
>  #include "intel_de.h"
>  #include "intel_display_irq.h"
>  #include "intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index b4b281ef258b..d17a9b013b67 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -5,7 +5,6 @@
>  
>  #include <drm/drm_print.h>
>  
> -#include "i915_reg.h"
>  #include "intel_cx0_phy.h"
>  #include "intel_cx0_phy_regs.h"
>  #include "intel_ddi.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index b217ec7aa758..2d799af73bb7 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -9,7 +9,6 @@
>  #include <drm/drm_print.h>
>  
>  #include "g4x_dp.h"
> -#include "i915_reg.h"
>  #include "intel_de.h"
>  #include "intel_display_jiffies.h"
>  #include "intel_display_power_well.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 064f572bbc85..5784d5d5132d 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -6,8 +6,8 @@
>  #include <linux/iopoll.h>
>  
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
> -#include "i915_reg.h"
>  #include "intel_atomic.h"
>  #include "intel_cx0_phy_regs.h"
>  #include "intel_ddi.h"
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index a6aab79812e5..410289b3fadd 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -7,8 +7,8 @@
>  
>  #include <drm/drm_blend.h>
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
> -#include "i915_reg.h"
>  #include "i9xx_wm.h"
>  #include "intel_atomic.h"
>  #include "intel_bw.h"
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index d705af3bf8ba..67f0082d3a69 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -33,7 +33,6 @@
>  #include <drm/drm_print.h>
>  #include <drm/drm_probe_helper.h>
>  
> -#include "i915_reg.h"
>  #include "intel_atomic.h"
>  #include "intel_backlight.h"
>  #include "intel_connector.h"

-- 
Jani Nikula, Intel

Re: [v2 18/19] drm/{i915, xe}: Remove i915_reg.h from intel_modeset_setup.c

[Jani Nikula]

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move GEN9_CLKGATE_DIS_0 reg to display header to make
> intel_modeset_setup.c free from i915_reg.h include.
>
> v2: Remove from gmd common header and use display_regs.h (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_regs.h  | 13 +++++++++++++
>  drivers/gpu/drm/i915/display/intel_modeset_setup.c |  1 -
>  drivers/gpu/drm/i915/i915_reg.h                    | 13 -------------
>  3 files changed, 13 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 1def3dccdf61..ec18ad9a262c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -377,6 +377,19 @@
>  #define   SKL_EDP_PSR_FIX_RDWRAP	REG_BIT(3)
>  #define   IGNORE_PSR2_HW_TRACKING	REG_BIT(1)
>  
> +/*
> + * GEN9 clock gating regs
> + */
> +#define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
> +#define   DARBF_GATING_DIS		REG_BIT(27)
> +#define   MTL_PIPEDMC_GATING_DIS(pipe)	REG_BIT(15 - (pipe))
> +#define   PWM2_GATING_DIS		REG_BIT(14)
> +#define   PWM1_GATING_DIS		REG_BIT(13)
> +
> +#define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)
> +#define   TGL_VRH_GATING_DIS		REG_BIT(31)
> +#define   DPT_GATING_DIS		REG_BIT(22)
> +
>  #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
>  #define   BXT_GMBUS_GATING_DIS		(1 << 14)
>  #define   DG2_DPFC_GATING_DIS		REG_BIT(31)
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index d10cbf69a5f8..9b0becee221c 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -11,7 +11,6 @@
>  #include <drm/drm_print.h>
>  #include <drm/drm_vblank.h>
>  
> -#include "i915_reg.h"
>  #include "i9xx_wm.h"
>  #include "intel_atomic.h"
>  #include "intel_bw.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c68a64bc7646..86035f54ae7a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -629,19 +629,6 @@
>  #define VLV_CLK_CTL2			_MMIO(0x101104)
>  #define   CLK_CTL2_CZCOUNT_30NS_SHIFT	28
>  
> -/*
> - * GEN9 clock gating regs
> - */
> -#define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
> -#define   DARBF_GATING_DIS		REG_BIT(27)
> -#define   MTL_PIPEDMC_GATING_DIS(pipe)	REG_BIT(15 - (pipe))
> -#define   PWM2_GATING_DIS		REG_BIT(14)
> -#define   PWM1_GATING_DIS		REG_BIT(13)
> -
> -#define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)
> -#define   TGL_VRH_GATING_DIS		REG_BIT(31)
> -#define   DPT_GATING_DIS		REG_BIT(22)
> -
>  #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
>  #define   PIPEB_LINE_COMPARE_INT_EN			REG_BIT(29)
>  #define   PIPEB_HLINE_INT_EN			REG_BIT(28)

-- 
Jani Nikula, Intel

RE: [v2 01/19] drm/{i915, xe}: Extract display registers from i915_reg.h to display

[Shankar, Uma]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, January 22, 2026 4:47 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v2 01/19] drm/{i915, xe}: Extract display registers from i915_reg.h to
> display
> 
> On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > There are certain register definitions which are defined in i915_reg.h
> > which are exclusively needed by display. Move the same to display
> > headers to remove i915_reg.h includes from display. This is a step
> > towards making display independent of i915.
> >
> > intel_clock_gating.c can include display header directly.
> >
> > v2: Drop common header in include and use display_regs.h (Jani)
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> 
> Oh, the Subject should just be drm/i915, this isn't directly related to xe.

Sure, will fix it.

Regards,
Uma Shankar

> > ---
> >  drivers/gpu/drm/i915/display/intel_display_regs.h | 10 ++++++++++
> > drivers/gpu/drm/i915/display/intel_pch_display.c  |  1 -
> >  drivers/gpu/drm/i915/i915_reg.h                   | 10 ----------
> >  drivers/gpu/drm/i915/intel_clock_gating.c         |  2 +-
> >  4 files changed, 11 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 9e0d853f4b61..9f8fbfb2e115 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -2021,6 +2021,16 @@
> >  #define  TRANS_BPC_6
> 	REG_FIELD_PREP(TRANS_BPC_MASK, 2)
> >  #define  TRANS_BPC_12
> 	REG_FIELD_PREP(TRANS_BPC_MASK, 3)
> >
> > +#define _TRANSA_CHICKEN2	0xf0064
> > +#define _TRANSB_CHICKEN2	0xf1064
> > +#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe,
> _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> > +#define   TRANS_CHICKEN2_TIMING_OVERRIDE		REG_BIT(31)
> > +#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED
> 	REG_BIT(29)
> > +#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK
> 	REG_GENMASK(28, 27)
> > +#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)
> 	REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK,
> (x)) /* 0-3 */
> > +#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
> 	REG_BIT(26)
> > +#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
> 	REG_BIT(25)
> > +
> >  #define PCH_DP_B		_MMIO(0xe4100)
> >  #define PCH_DP_C		_MMIO(0xe4200)
> >  #define PCH_DP_D		_MMIO(0xe4300)
> > diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
> > b/drivers/gpu/drm/i915/display/intel_pch_display.c
> > index 16619f7be5f8..69c7952a1413 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> > @@ -6,7 +6,6 @@
> >  #include <drm/drm_print.h>
> >
> >  #include "g4x_dp.h"
> > -#include "i915_reg.h"
> >  #include "intel_crt.h"
> >  #include "intel_crt_regs.h"
> >  #include "intel_de.h"
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 5bf3b4ab2baa..d247e107f42f
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1022,16 +1022,6 @@
> >  #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
> >  #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
> >
> > -#define _TRANSA_CHICKEN2	 0xf0064
> > -#define _TRANSB_CHICKEN2	 0xf1064
> > -#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe,
> _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> > -#define   TRANS_CHICKEN2_TIMING_OVERRIDE		REG_BIT(31)
> > -#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED
> 	REG_BIT(29)
> > -#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK
> 	REG_GENMASK(28, 27)
> > -#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)
> 	REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK,
> (x)) /* 0-3 */
> > -#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
> 	REG_BIT(26)
> > -#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
> 	REG_BIT(25)
> > -
> >  #define SOUTH_CHICKEN1		_MMIO(0xc2000)
> >  #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
> >  #define  FDIA_PHASE_SYNC_SHIFT_EN	18
> > diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c
> > b/drivers/gpu/drm/i915/intel_clock_gating.c
> > index 7336934bb934..4e18d5a22112 100644
> > --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> > +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> > @@ -30,7 +30,7 @@
> >  #include "display/i9xx_plane_regs.h"
> >  #include "display/intel_display.h"
> >  #include "display/intel_display_core.h"
> > -
> > +#include "display/intel_display_regs.h"
> >  #include "gt/intel_engine_regs.h"
> >  #include "gt/intel_gt.h"
> >  #include "gt/intel_gt_mcr.h"
> 
> --
> Jani Nikula, Intel

RE: [v2 02/19] drm/{i915, xe}: Extract South chicken registers from i915_reg.h to display

[Shankar, Uma]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, January 22, 2026 4:56 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v2 02/19] drm/{i915, xe}: Extract South chicken registers from
> i915_reg.h to display
> 
> On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Extract South Chicken registers from i915_reg.h to display header.
> > This allows intel_pch_refclk.c not to include i915_reg.h
> >
> > v2: Drop common header in include and use display_regs.h (Jani)
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> 
> Just drm/i915 is sufficient as subject prefix.
> 
> It's mildly annoying that there's a bunch of whitespace changes bundled in here.
> They should be kept separate, if only to speed up review by 10x with 'git show --
> color-moved' which works wonders for pure code movement. Subsequent separate
> whitespace changes, in turn, are a breeze to review with 'git show -w'.

Noted Jani, will take care of it next time.

Regards,
Uma Shankar

> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> > ---
> >  .../gpu/drm/i915/display/intel_display_regs.h | 28 +++++++++++++++++++
> >  .../gpu/drm/i915/display/intel_pch_refclk.c   |  1 -
> >  drivers/gpu/drm/i915/i915_reg.h               | 27 ------------------
> >  3 files changed, 28 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 9f8fbfb2e115..4759a9600d3f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -2864,6 +2864,34 @@ enum skl_power_gate {
> >  #define  SFUSE_STRAP_DDIC_DETECTED	(1 << 1)
> >  #define  SFUSE_STRAP_DDID_DETECTED	(1 << 0)
> >
> > +#define SOUTH_CHICKEN1			_MMIO(0xc2000)
> > +#define  FDIA_PHASE_SYNC_SHIFT_OVR	19
> > +#define  FDIA_PHASE_SYNC_SHIFT_EN	18
> > +#define  INVERT_DDIE_HPD		REG_BIT(28)
> > +#define  INVERT_DDID_HPD_MTP		REG_BIT(27)
> > +#define  INVERT_TC4_HPD			REG_BIT(26)
> > +#define  INVERT_TC3_HPD			REG_BIT(25)
> > +#define  INVERT_TC2_HPD			REG_BIT(24)
> > +#define  INVERT_TC1_HPD			REG_BIT(23)
> > +#define  INVERT_DDID_HPD		(1 << 18)
> > +#define  INVERT_DDIC_HPD		(1 << 17)
> > +#define  INVERT_DDIB_HPD                (1 << 16)
> > +#define  INVERT_DDIA_HPD                (1 << 15)
> > +#define  FDI_PHASE_SYNC_OVR(pipe)	(1 <<
> (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
> > +#define  FDI_PHASE_SYNC_EN(pipe)	(1 <<
> (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
> > +#define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
> > +#define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
> > +#define  CHASSIS_CLK_REQ_DURATION(x)	((x) << 8)
> > +#define  SBCLK_RUN_REFCLK_DIS		(1 << 7)
> > +#define  ICP_SECOND_PPS_IO_SELECT	REG_BIT(2)
> > +#define  SPT_PWM_GRANULARITY		(1 << 0)
> > +
> > +#define SOUTH_CHICKEN2			_MMIO(0xc2004)
> > +#define  FDI_MPHY_IOSFSB_RESET_STATUS	(1 << 13)
> > +#define  FDI_MPHY_IOSFSB_RESET_CTL	(1 << 12)
> > +#define  LPT_PWM_GRANULARITY		(1 << 5)
> > +#define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
> > +
> >  /* Gen4+ Timestamp and Pipe Frame time stamp registers */
> >  #define GEN4_TIMESTAMP		_MMIO(0x2358)
> >  #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
> > diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> > b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> > index 9a89bb6dcf65..5f88663ef5e8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> > @@ -5,7 +5,6 @@
> >
> >  #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> >  #include "intel_de.h"
> >  #include "intel_display_regs.h"
> >  #include "intel_display_types.h"
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index d247e107f42f..80ea0df40b1e
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1022,33 +1022,6 @@
> >  #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
> >  #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
> >
> > -#define SOUTH_CHICKEN1		_MMIO(0xc2000)
> > -#define  FDIA_PHASE_SYNC_SHIFT_OVR	19
> > -#define  FDIA_PHASE_SYNC_SHIFT_EN	18
> > -#define  INVERT_DDIE_HPD			REG_BIT(28)
> > -#define  INVERT_DDID_HPD_MTP			REG_BIT(27)
> > -#define  INVERT_TC4_HPD				REG_BIT(26)
> > -#define  INVERT_TC3_HPD				REG_BIT(25)
> > -#define  INVERT_TC2_HPD				REG_BIT(24)
> > -#define  INVERT_TC1_HPD				REG_BIT(23)
> > -#define  INVERT_DDID_HPD			(1 << 18)
> > -#define  INVERT_DDIC_HPD			(1 << 17)
> > -#define  INVERT_DDIB_HPD			(1 << 16)
> > -#define  INVERT_DDIA_HPD			(1 << 15)
> > -#define  FDI_PHASE_SYNC_OVR(pipe) (1 <<
> (FDIA_PHASE_SYNC_SHIFT_OVR -
> > ((pipe) * 2))) -#define  FDI_PHASE_SYNC_EN(pipe) (1 <<
> (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
> > -#define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
> > -#define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
> > -#define  CHASSIS_CLK_REQ_DURATION(x)	((x) << 8)
> > -#define  SBCLK_RUN_REFCLK_DIS		(1 << 7)
> > -#define  ICP_SECOND_PPS_IO_SELECT	REG_BIT(2)
> > -#define  SPT_PWM_GRANULARITY		(1 << 0)
> > -#define SOUTH_CHICKEN2		_MMIO(0xc2004)
> > -#define  FDI_MPHY_IOSFSB_RESET_STATUS	(1 << 13)
> > -#define  FDI_MPHY_IOSFSB_RESET_CTL	(1 << 12)
> > -#define  LPT_PWM_GRANULARITY		(1 << 5)
> > -#define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
> > -
> >  #define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
> >  #define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)  #define
> > PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
> 
> --
> Jani Nikula, Intel

RE: [v2 03/19] drm/{i915, xe}: Extract display interrupt definitions

[Shankar, Uma]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, January 22, 2026 5:00 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v2 03/19] drm/{i915, xe}: Extract display interrupt definitions
> 
> On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Move common registers to display to allow intel_display_rps.c free of
> > i915_reg.h dependency.
> 
> The grammar's not quite right there.
> 
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> >  .../gpu/drm/i915/display/intel_display_regs.h | 34
> > +++++++++++++++++++  .../gpu/drm/i915/display/intel_display_rps.c  |  2 +-
> >  drivers/gpu/drm/i915/i915_reg.h               | 33 ------------------
> >  3 files changed, 35 insertions(+), 34 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 4759a9600d3f..1f922d013cd3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -1333,6 +1333,40 @@
> >  						      GEN8_DE_PORT_IER, \
> >  						      GEN8_DE_PORT_IIR)
> >
> > +/* interrupts */
> > +#define DE_MASTER_IRQ_CONTROL   (1 << 31)
> > +#define DE_SPRITEB_FLIP_DONE    (1 << 29)
> > +#define DE_SPRITEA_FLIP_DONE    (1 << 28)
> > +#define DE_PLANEB_FLIP_DONE     (1 << 27)
> > +#define DE_PLANEA_FLIP_DONE     (1 << 26)
> > +#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
> > +#define DE_PCU_EVENT            (1 << 25)
> > +#define DE_GTT_FAULT            (1 << 24)
> > +#define DE_POISON               (1 << 23)
> > +#define DE_PERFORM_COUNTER      (1 << 22)
> > +#define DE_PCH_EVENT            (1 << 21)
> > +#define DE_AUX_CHANNEL_A        (1 << 20)
> > +#define DE_DP_A_HOTPLUG         (1 << 19)
> > +#define DE_GSE                  (1 << 18)
> > +#define DE_PIPEB_VBLANK         (1 << 15)
> > +#define DE_PIPEB_EVEN_FIELD     (1 << 14)
> > +#define DE_PIPEB_ODD_FIELD      (1 << 13)
> > +#define DE_PIPEB_LINE_COMPARE   (1 << 12)
> > +#define DE_PIPEB_VSYNC          (1 << 11)
> > +#define DE_PIPEB_CRC_DONE	(1 << 10)
> > +#define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
> > +#define DE_PIPEA_VBLANK         (1 << 7)
> > +#define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8 * (pipe)))
> > +#define DE_PIPEA_EVEN_FIELD     (1 << 6)
> > +#define DE_PIPEA_ODD_FIELD      (1 << 5)
> > +#define DE_PIPEA_LINE_COMPARE   (1 << 4)
> > +#define DE_PIPEA_VSYNC          (1 << 3)
> > +#define DE_PIPEA_CRC_DONE	(1 << 2)
> > +#define DE_PIPE_CRC_DONE(pipe)	(1 << (2 + 8 * (pipe)))
> > +#define DE_PIPEA_FIFO_UNDERRUN  (1 << 0) #define
> > +DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8 * (pipe)))
> > +
> > +
> 
> Superfluous newline.
> 
> Other than that,
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> PS. This one took like 5 seconds to review with 'git show --color-moved'.

Got it Jani.

Regards,
Uma Shankar

> 
> >  #define GEN8_DE_MISC_ISR _MMIO(0x44460)  #define GEN8_DE_MISC_IMR
> > _MMIO(0x44464)  #define GEN8_DE_MISC_IIR _MMIO(0x44468) diff --git
> > a/drivers/gpu/drm/i915/display/intel_display_rps.c
> > b/drivers/gpu/drm/i915/display/intel_display_rps.c
> > index e77811396474..bf00266dae4b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_rps.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_rps.c
> > @@ -8,8 +8,8 @@
> >  #include <drm/drm_crtc.h>
> >  #include <drm/drm_vblank.h>
> >
> > -#include "i915_reg.h"
> >  #include "intel_display_core.h"
> > +#include "intel_display_regs.h"
> >  #include "intel_display_irq.h"
> >  #include "intel_display_rps.h"
> >  #include "intel_display_types.h"
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 80ea0df40b1e..5cd124083c17
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -804,39 +804,6 @@
> >  #define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
> >  #define  MMIO_TIMEOUT_US(us)	((us) << 0)
> >
> > -/* interrupts */
> > -#define DE_MASTER_IRQ_CONTROL   (1 << 31)
> > -#define DE_SPRITEB_FLIP_DONE    (1 << 29)
> > -#define DE_SPRITEA_FLIP_DONE    (1 << 28)
> > -#define DE_PLANEB_FLIP_DONE     (1 << 27)
> > -#define DE_PLANEA_FLIP_DONE     (1 << 26)
> > -#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
> > -#define DE_PCU_EVENT            (1 << 25)
> > -#define DE_GTT_FAULT            (1 << 24)
> > -#define DE_POISON               (1 << 23)
> > -#define DE_PERFORM_COUNTER      (1 << 22)
> > -#define DE_PCH_EVENT            (1 << 21)
> > -#define DE_AUX_CHANNEL_A        (1 << 20)
> > -#define DE_DP_A_HOTPLUG         (1 << 19)
> > -#define DE_GSE                  (1 << 18)
> > -#define DE_PIPEB_VBLANK         (1 << 15)
> > -#define DE_PIPEB_EVEN_FIELD     (1 << 14)
> > -#define DE_PIPEB_ODD_FIELD      (1 << 13)
> > -#define DE_PIPEB_LINE_COMPARE   (1 << 12)
> > -#define DE_PIPEB_VSYNC          (1 << 11)
> > -#define DE_PIPEB_CRC_DONE	(1 << 10)
> > -#define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
> > -#define DE_PIPEA_VBLANK         (1 << 7)
> > -#define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8 * (pipe)))
> > -#define DE_PIPEA_EVEN_FIELD     (1 << 6)
> > -#define DE_PIPEA_ODD_FIELD      (1 << 5)
> > -#define DE_PIPEA_LINE_COMPARE   (1 << 4)
> > -#define DE_PIPEA_VSYNC          (1 << 3)
> > -#define DE_PIPEA_CRC_DONE	(1 << 2)
> > -#define DE_PIPE_CRC_DONE(pipe)	(1 << (2 + 8 * (pipe)))
> > -#define DE_PIPEA_FIFO_UNDERRUN  (1 << 0) -#define
> > DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8 * (pipe)))
> > -
> >  #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master
> IER */
> >  #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
> 
> --
> Jani Nikula, Intel

RE: [v2 06/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_device.c

[Shankar, Uma]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, January 22, 2026 5:07 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v2 06/19] drm/{i915, xe}: Remove i915_reg.h from
> intel_display_device.c
> 
> On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Move GU_CNTL_PROTECTED to common header, this helps
> > intel_display_device.c free from i915_reg.h dependency.
> 
> This doesn't mention the GMD ID stuff.
> 
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
> >  drivers/gpu/drm/i915/display/intel_display_regs.h   | 3 +++
> >  drivers/gpu/drm/i915/i915_reg.h                     | 8 --------
> >  include/drm/intel/intel_gmd_common_regs.h           | 5 +++++
> >  4 files changed, 9 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> > b/drivers/gpu/drm/i915/display/intel_display_device.c
> > index 471f236c9ddf..f7cc4198a870 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> > @@ -9,8 +9,8 @@
> >  #include <drm/drm_drv.h>
> >  #include <drm/drm_print.h>
> >  #include <drm/intel/pciids.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >
> > -#include "i915_reg.h"
> >  #include "intel_cx0_phy_regs.h"
> >  #include "intel_de.h"
> >  #include "intel_display.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 5136b7166775..3447ee229354 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -6,6 +6,9 @@
> >
> >  #include "intel_display_reg_defs.h"
> >
> > +#define GU_CNTL_PROTECTED		_MMIO(0x10100C)
> > +#define   DEPRESENT			REG_BIT(9)
> > +
> >  #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
> >  #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
> >  #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe,
> > _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) diff --git
> > a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 35122c997b8a..fac24a649d61 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -117,9 +117,6 @@
> >   *  #define GEN8_BAR                    _MMIO(0xb888)
> >   */
> >
> > -#define GU_CNTL_PROTECTED		_MMIO(0x10100C)
> > -#define   DEPRESENT			REG_BIT(9)
> > -
> >  #define GU_CNTL				_MMIO(0x101010)
> >  #define   LMEM_INIT			REG_BIT(7)
> >  #define   DRIVERFLR			REG_BIT(31)
> > @@ -925,11 +922,6 @@
> >  #define   MASK_WAKEMEM				REG_BIT(13)
> >  #define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
> >
> > -#define GMD_ID_DISPLAY				_MMIO(0x510a0)
> > -#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
> > -#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
> > -#define   GMD_ID_STEP				REG_GENMASK(5, 0)
> > -
> >  /* PCH */
> >
> >  #define SDEISR  _MMIO(0xc4000)
> > diff --git a/include/drm/intel/intel_gmd_common_regs.h
> > b/include/drm/intel/intel_gmd_common_regs.h
> > index 8e9a574c87d9..489d59379ab0 100644
> > --- a/include/drm/intel/intel_gmd_common_regs.h
> > +++ b/include/drm/intel/intel_gmd_common_regs.h
> > @@ -105,4 +105,9 @@
> >  #define     PCODE_MBOX_DOMAIN_NONE		0x0
> >  #define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
> >
> > +#define GMD_ID_DISPLAY				_MMIO(0x510a0)
> > +#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
> > +#define   GMD_ID_RELEASE_MASK
> 	REG_GENMASK(21, 14)
> > +#define   GMD_ID_STEP				REG_GENMASK(5, 0)
> 
> Only display uses GMD_ID_DISPLAY register. I'd put this in display regs, and
> define the register contents with GMD_ID_DISPLAY_* even if the register
> contents are identical for display and non-display GMD registers.
> 
> Main point is, we should use the common regs file as little as possible.

Sure, will fix it.

Regards,
Uma Shankar

> BR,
> Jani.
> 
> > +
> >  #endif
> 
> --
> Jani Nikula, Intel

RE: [v2 05/19] drm/{i915, xe}: Extract pcode definitions to common header

[Shankar, Uma]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, January 22, 2026 5:11 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v2 05/19] drm/{i915, xe}: Extract pcode definitions to common
> header
> 
> On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > There are certain register definitions which are commonly shared by
> > i915, xe and display. Extract the same to a common header to avoid
> > duplication.
> 
> I think starting a big new catch-all file for common registers is the wrong direction.
> If we're adding new files, they should be per feature.
> 
> In this case, it's pcode registers, and the name should reflect that.
> 
> Later in the series more stuff gets added, and more files include it, but it's not at
> all clear what they need from there. It would be so much more obvious if it was per
> feature.

Yeah sounds good, will try to separate this out. I got inspired with this one big i915_reg for
all driver, but yeah a logical feature wise split will be good. 

I will fix and send next version.

Regards,
Uma Shankar

> BR,
> Jani.
> 
> 
> >
> > Move GEN6_PCODE_MAILBOX to common header to make intel_cdclk.c free
> > from including i915_reg.h
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c |   2 +-
> >  drivers/gpu/drm/i915/i915_reg.h            | 101 +------------------
> >  include/drm/intel/intel_gmd_common_regs.h  | 108
> > +++++++++++++++++++++
> >  3 files changed, 110 insertions(+), 101 deletions(-)  create mode
> > 100644 include/drm/intel/intel_gmd_common_regs.h
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 9bfbfbf34dc0..531db1b452d1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -27,9 +27,9 @@
> >
> >  #include <drm/drm_fixed.h>
> >  #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >
> >  #include "hsw_ips.h"
> > -#include "i915_reg.h"
> >  #include "intel_atomic.h"
> >  #include "intel_audio.h"
> >  #include "intel_cdclk.h"
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index dc13f9eb4cd7..35122c997b8a
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -25,6 +25,7 @@
> >  #ifndef _I915_REG_H_
> >  #define _I915_REG_H_
> >
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >  #include "i915_reg_defs.h"
> >  #include "display/intel_display_reg_defs.h"
> >
> > @@ -956,106 +957,6 @@
> >  #define    EDRAM_WAYS_IDX(cap)			(((cap) >> 5) & 0x7)
> >  #define    EDRAM_SETS_IDX(cap)			(((cap) >> 8) & 0x3)
> >
> > -#define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
> > -#define   GEN6_PCODE_READY			(1 << 31)
> > -#define   GEN6_PCODE_MB_PARAM2
> 	REG_GENMASK(23, 16)
> > -#define   GEN6_PCODE_MB_PARAM1
> 	REG_GENMASK(15, 8)
> > -#define   GEN6_PCODE_MB_COMMAND
> 	REG_GENMASK(7, 0)
> > -#define   GEN6_PCODE_ERROR_MASK			0xFF
> > -#define     GEN6_PCODE_SUCCESS			0x0
> > -#define     GEN6_PCODE_ILLEGAL_CMD		0x1
> > -#define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
> 0x2
> > -#define     GEN6_PCODE_TIMEOUT			0x3
> > -#define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
> > -#define     GEN7_PCODE_TIMEOUT			0x2
> > -#define     GEN7_PCODE_ILLEGAL_DATA		0x3
> > -#define     GEN11_PCODE_ILLEGAL_SUBCOMMAND	0x4
> > -#define     GEN11_PCODE_LOCKED			0x6
> > -#define     GEN11_PCODE_REJECTED		0x11
> > -#define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
> 0x10
> > -#define   GEN6_PCODE_WRITE_RC6VIDS		0x4
> > -#define   GEN6_PCODE_READ_RC6VIDS		0x5
> > -#define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
> > -#define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
> > -#define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
> > -#define   GEN9_PCODE_READ_MEM_LATENCY		0x6
> > -#define     GEN9_MEM_LATENCY_LEVEL_3_7_MASK
> 	REG_GENMASK(31, 24)
> > -#define     GEN9_MEM_LATENCY_LEVEL_2_6_MASK
> 	REG_GENMASK(23, 16)
> > -#define     GEN9_MEM_LATENCY_LEVEL_1_5_MASK
> 	REG_GENMASK(15, 8)
> > -#define     GEN9_MEM_LATENCY_LEVEL_0_4_MASK
> 	REG_GENMASK(7, 0)
> > -#define   SKL_PCODE_LOAD_HDCP_KEYS		0x5
> > -#define   SKL_PCODE_CDCLK_CONTROL		0x7
> > -#define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
> > -#define     SKL_CDCLK_READY_FOR_CHANGE		0x1
> > -#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
> > -#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
> > -#define   GEN6_READ_OC_PARAMS			0xc
> > -#define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
> > -#define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
> > -#define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point)
> << 16) | (0x1 << 8))
> > -#define     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO	((0) | (0x2 << 8))
> > -#define   DISPLAY_TO_PCODE_CDCLK_MAX		0x28D
> > -#define   DISPLAY_TO_PCODE_VOLTAGE_MASK
> 	REG_GENMASK(1, 0)
> > -#define	  DISPLAY_TO_PCODE_VOLTAGE_MAX
> 	DISPLAY_TO_PCODE_VOLTAGE_MASK
> > -#define   DISPLAY_TO_PCODE_CDCLK_VALID		REG_BIT(27)
> > -#define   DISPLAY_TO_PCODE_PIPE_COUNT_VALID	REG_BIT(31)
> > -#define   DISPLAY_TO_PCODE_CDCLK_MASK
> 	REG_GENMASK(25, 16)
> > -#define   DISPLAY_TO_PCODE_PIPE_COUNT_MASK
> 	REG_GENMASK(30, 28)
> > -#define   DISPLAY_TO_PCODE_CDCLK(x)
> 	REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
> > -#define   DISPLAY_TO_PCODE_PIPE_COUNT(x)
> 	REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
> > -#define   DISPLAY_TO_PCODE_VOLTAGE(x)
> 	REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
> > -#define   DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes,
> voltage_level) \
> > -		((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
> > -		(DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
> > -		(DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
> > -#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
> > -#define     ICL_PCODE_REP_QGV_MASK		REG_GENMASK(1, 0)
> > -#define     ICL_PCODE_REP_QGV_SAFE
> 	REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
> > -#define     ICL_PCODE_REP_QGV_POLL
> 	REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
> > -#define     ICL_PCODE_REP_QGV_REJECTED
> 	REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
> > -#define     ADLS_PCODE_REP_PSF_MASK		REG_GENMASK(3, 2)
> > -#define     ADLS_PCODE_REP_PSF_SAFE
> 	REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
> > -#define     ADLS_PCODE_REP_PSF_POLL
> 	REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
> > -#define     ADLS_PCODE_REP_PSF_REJECTED
> 	REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
> > -#define     ICL_PCODE_REQ_QGV_PT_MASK
> 	REG_GENMASK(7, 0)
> > -#define     ICL_PCODE_REQ_QGV_PT(x)
> 	REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
> > -#define     ADLS_PCODE_REQ_PSF_PT_MASK
> 	REG_GENMASK(10, 8)
> > -#define     ADLS_PCODE_REQ_PSF_PT(x)
> 	REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
> > -#define   GEN6_PCODE_READ_D_COMP		0x10
> > -#define   GEN6_PCODE_WRITE_D_COMP		0x11
> > -#define   ICL_PCODE_EXIT_TCCOLD			0x12
> > -#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
> > -#define   DISPLAY_IPS_CONTROL			0x19
> > -#define   TGL_PCODE_TCCOLD			0x26
> > -#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED
> 	REG_BIT(0)
> > -#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ	0
> > -#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ
> 	REG_BIT(0)
> > -            /* See also IPS_CTL */
> > -#define     IPS_PCODE_CONTROL			(1 << 30)
> > -#define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
> > -#define   GEN9_PCODE_SAGV_CONTROL		0x21
> > -#define     GEN9_SAGV_DISABLE			0x0
> > -#define     GEN9_SAGV_IS_DISABLED		0x1
> > -#define     GEN9_SAGV_ENABLE			0x3
> > -#define   DG1_PCODE_STATUS			0x7E
> > -#define     DG1_UNCORE_GET_INIT_STATUS		0x0
> > -#define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
> > -#define   PCODE_POWER_SETUP			0x7C
> > -#define     POWER_SETUP_SUBCOMMAND_READ_I1	0x4
> > -#define     POWER_SETUP_SUBCOMMAND_WRITE_I1	0x5
> > -#define	    POWER_SETUP_I1_WATTS		REG_BIT(31)
> > -#define	    POWER_SETUP_I1_SHIFT		6	/* 10.6 fixed point
> format */
> > -#define	    POWER_SETUP_I1_DATA_MASK
> 	REG_GENMASK(15, 0)
> > -#define     POWER_SETUP_SUBCOMMAND_G8_ENABLE	0x6
> > -#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
> > -#define   XEHP_PCODE_FREQUENCY_CONFIG		0x6e	/* pvc */
> > -/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
> > -#define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
> > -#define     PCODE_MBOX_FC_SC_READ_FUSED_PN	0x1
> > -/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
> > -/*   XEHP_PCODE_FREQUENCY_CONFIG param2 */
> > -#define     PCODE_MBOX_DOMAIN_NONE		0x0
> > -#define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
> >  #define GEN6_PCODE_DATA
> 	_MMIO(0x138128)
> >  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
> >  #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
> > diff --git a/include/drm/intel/intel_gmd_common_regs.h
> > b/include/drm/intel/intel_gmd_common_regs.h
> > new file mode 100644
> > index 000000000000..8e9a574c87d9
> > --- /dev/null
> > +++ b/include/drm/intel/intel_gmd_common_regs.h
> > @@ -0,0 +1,108 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/* Copyright © 2026 Intel Corporation */
> > +
> > +#ifndef _INTEL_GMD_COMMON_REG_H_
> > +#define _INTEL_GMD_COMMON_REG_H_
> > +
> > +#define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
> > +#define   GEN6_PCODE_READY			(1 << 31)
> > +#define   GEN6_PCODE_MB_PARAM2
> 	REG_GENMASK(23, 16)
> > +#define   GEN6_PCODE_MB_PARAM1
> 	REG_GENMASK(15, 8)
> > +#define   GEN6_PCODE_MB_COMMAND
> 	REG_GENMASK(7, 0)
> > +#define   GEN6_PCODE_ERROR_MASK			0xFF
> > +#define     GEN6_PCODE_SUCCESS			0x0
> > +#define     GEN6_PCODE_ILLEGAL_CMD		0x1
> > +#define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
> 0x2
> > +#define     GEN6_PCODE_TIMEOUT			0x3
> > +#define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
> > +#define     GEN7_PCODE_TIMEOUT			0x2
> > +#define     GEN7_PCODE_ILLEGAL_DATA		0x3
> > +#define     GEN11_PCODE_ILLEGAL_SUBCOMMAND	0x4
> > +#define     GEN11_PCODE_LOCKED			0x6
> > +#define     GEN11_PCODE_REJECTED		0x11
> > +#define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
> 0x10
> > +#define   GEN6_PCODE_WRITE_RC6VIDS		0x4
> > +#define   GEN6_PCODE_READ_RC6VIDS		0x5
> > +#define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
> > +#define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
> > +#define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
> > +#define   GEN9_PCODE_READ_MEM_LATENCY		0x6
> > +#define     GEN9_MEM_LATENCY_LEVEL_3_7_MASK
> 	REG_GENMASK(31, 24)
> > +#define     GEN9_MEM_LATENCY_LEVEL_2_6_MASK
> 	REG_GENMASK(23, 16)
> > +#define     GEN9_MEM_LATENCY_LEVEL_1_5_MASK
> 	REG_GENMASK(15, 8)
> > +#define     GEN9_MEM_LATENCY_LEVEL_0_4_MASK
> 	REG_GENMASK(7, 0)
> > +#define   SKL_PCODE_LOAD_HDCP_KEYS		0x5
> > +#define   SKL_PCODE_CDCLK_CONTROL		0x7
> > +#define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
> > +#define     SKL_CDCLK_READY_FOR_CHANGE		0x1
> > +#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
> > +#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
> > +#define   GEN6_READ_OC_PARAMS			0xc
> > +#define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
> > +#define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
> > +#define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point)
> << 16) | (0x1 << 8))
> > +#define     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO	((0) | (0x2 << 8))
> > +#define   DISPLAY_TO_PCODE_CDCLK_MAX		0x28D
> > +#define   DISPLAY_TO_PCODE_VOLTAGE_MASK
> 	REG_GENMASK(1, 0)
> > +#define	  DISPLAY_TO_PCODE_VOLTAGE_MAX
> 	DISPLAY_TO_PCODE_VOLTAGE_MASK
> > +#define   DISPLAY_TO_PCODE_CDCLK_VALID		REG_BIT(27)
> > +#define   DISPLAY_TO_PCODE_PIPE_COUNT_VALID	REG_BIT(31)
> > +#define   DISPLAY_TO_PCODE_CDCLK_MASK
> 	REG_GENMASK(25, 16)
> > +#define   DISPLAY_TO_PCODE_PIPE_COUNT_MASK
> 	REG_GENMASK(30, 28)
> > +#define   DISPLAY_TO_PCODE_CDCLK(x)
> 	REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
> > +#define   DISPLAY_TO_PCODE_PIPE_COUNT(x)
> 	REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
> > +#define   DISPLAY_TO_PCODE_VOLTAGE(x)
> 	REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
> > +#define   DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes,
> voltage_level) \
> > +		((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
> > +		(DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
> > +		(DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
> > +#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
> > +#define     ICL_PCODE_REP_QGV_MASK		REG_GENMASK(1, 0)
> > +#define     ICL_PCODE_REP_QGV_SAFE
> 	REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
> > +#define     ICL_PCODE_REP_QGV_POLL
> 	REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
> > +#define     ICL_PCODE_REP_QGV_REJECTED
> 	REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
> > +#define     ADLS_PCODE_REP_PSF_MASK		REG_GENMASK(3, 2)
> > +#define     ADLS_PCODE_REP_PSF_SAFE
> 	REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
> > +#define     ADLS_PCODE_REP_PSF_POLL
> 	REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
> > +#define     ADLS_PCODE_REP_PSF_REJECTED
> 	REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
> > +#define     ICL_PCODE_REQ_QGV_PT_MASK
> 	REG_GENMASK(7, 0)
> > +#define     ICL_PCODE_REQ_QGV_PT(x)
> 	REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
> > +#define     ADLS_PCODE_REQ_PSF_PT_MASK
> 	REG_GENMASK(10, 8)
> > +#define     ADLS_PCODE_REQ_PSF_PT(x)
> 	REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
> > +#define   GEN6_PCODE_READ_D_COMP		0x10
> > +#define   GEN6_PCODE_WRITE_D_COMP		0x11
> > +#define   ICL_PCODE_EXIT_TCCOLD			0x12
> > +#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
> > +#define   DISPLAY_IPS_CONTROL			0x19
> > +#define   TGL_PCODE_TCCOLD			0x26
> > +#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED
> 	REG_BIT(0)
> > +#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ	0
> > +#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ
> 	REG_BIT(0)
> > +/* See also IPS_CTL */
> > +#define     IPS_PCODE_CONTROL			(1 << 30)
> > +#define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
> > +#define   GEN9_PCODE_SAGV_CONTROL		0x21
> > +#define     GEN9_SAGV_DISABLE			0x0
> > +#define     GEN9_SAGV_IS_DISABLED		0x1
> > +#define     GEN9_SAGV_ENABLE			0x3
> > +#define   DG1_PCODE_STATUS			0x7E
> > +#define     DG1_UNCORE_GET_INIT_STATUS		0x0
> > +#define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
> > +#define   PCODE_POWER_SETUP			0x7C
> > +#define     POWER_SETUP_SUBCOMMAND_READ_I1	0x4
> > +#define     POWER_SETUP_SUBCOMMAND_WRITE_I1	0x5
> > +#define	    POWER_SETUP_I1_WATTS		REG_BIT(31)
> > +#define	    POWER_SETUP_I1_SHIFT		6	/* 10.6 fixed point
> format */
> > +#define	    POWER_SETUP_I1_DATA_MASK
> 	REG_GENMASK(15, 0)
> > +#define     POWER_SETUP_SUBCOMMAND_G8_ENABLE	0x6
> > +#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
> > +#define   XEHP_PCODE_FREQUENCY_CONFIG		0x6e	/* pvc */
> > +/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
> > +#define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
> > +#define     PCODE_MBOX_FC_SC_READ_FUSED_PN	0x1
> > +/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
> > +/*   XEHP_PCODE_FREQUENCY_CONFIG param2 */
> > +#define     PCODE_MBOX_DOMAIN_NONE		0x0
> > +#define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
> > +
> > +#endif
> 
> --
> Jani Nikula, Intel

RE: [v2 07/19] drm/{i915, xe}: Remove i915_reg.h from intel_dram.c

[Shankar, Uma]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, January 22, 2026 5:12 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v2 07/19] drm/{i915, xe}: Remove i915_reg.h from intel_dram.c
> 
> On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Make intel_dram.c free from including i915_reg.h.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_regs.h | 6 +++++-
> >  drivers/gpu/drm/i915/display/intel_dram.c         | 3 ++-
> >  drivers/gpu/drm/i915/i915_reg.h                   | 6 ------
> >  3 files changed, 7 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 3447ee229354..f395b7d4d640 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -3075,6 +3075,10 @@ enum skl_power_gate {
> >  #define   MTL_TRAS_MASK			REG_GENMASK(16, 8)
> >  #define   MTL_TRDPRE_MASK		REG_GENMASK(7, 0)
> >
> > -
> > +#define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
> > +#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
> > +#define   MTL_N_OF_ENABLED_QGV_POINTS_MASK
> 	REG_GENMASK(11, 8)
> > +#define   MTL_N_OF_POPULATED_CH_MASK
> 	REG_GENMASK(7, 4)
> > +#define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
> >
> >  #endif /* __INTEL_DISPLAY_REGS_H__ */ diff --git
> > a/drivers/gpu/drm/i915/display/intel_dram.c
> > b/drivers/gpu/drm/i915/display/intel_dram.c
> > index 170de304fe96..73a127dd6720 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dram.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dram.c
> > @@ -7,10 +7,11 @@
> >
> >  #include <drm/drm_managed.h>
> >  #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> 
> dram only needs a few pcode things, so I'd prefer having a file for pcode regs and
> only including that here.

Will fix it.

Regards,
Uma Shankar

> >
> > -#include "i915_reg.h"
> >  #include "intel_display_core.h"
> >  #include "intel_display_utils.h"
> > +#include "intel_display_regs.h"
> >  #include "intel_dram.h"
> >  #include "intel_mchbar_regs.h"
> >  #include "intel_pcode.h"
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index fac24a649d61..c9fb9af1a35c
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1005,12 +1005,6 @@
> >  #define OROM_OFFSET				_MMIO(0x1020c0)
> >  #define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
> >
> > -#define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
> > -#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
> > -#define   MTL_N_OF_ENABLED_QGV_POINTS_MASK
> 	REG_GENMASK(11, 8)
> > -#define   MTL_N_OF_POPULATED_CH_MASK
> 	REG_GENMASK(7, 4)
> > -#define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
> > -
> >  #define MTL_MEDIA_GSI_BASE		0x380000
> >
> >  #endif /* _I915_REG_H_ */
> 
> --
> Jani Nikula, Intel

RE: [v2 05/19] drm/{i915, xe}: Extract pcode definitions to common header

[Shankar, Uma]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, January 22, 2026 5:16 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v2 05/19] drm/{i915, xe}: Extract pcode definitions to common
> header
> 
> On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > There are certain register definitions which are commonly shared by
> > i915, xe and display. Extract the same to a common header to avoid
> > duplication.
> >
> > Move GEN6_PCODE_MAILBOX to common header to make intel_cdclk.c free
> > from including i915_reg.h
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c |   2 +-
> >  drivers/gpu/drm/i915/i915_reg.h            | 101 +------------------
> >  include/drm/intel/intel_gmd_common_regs.h  | 108
> > +++++++++++++++++++++
> >  3 files changed, 110 insertions(+), 101 deletions(-)  create mode
> > 100644 include/drm/intel/intel_gmd_common_regs.h
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 9bfbfbf34dc0..531db1b452d1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -27,9 +27,9 @@
> >
> >  #include <drm/drm_fixed.h>
> >  #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >
> >  #include "hsw_ips.h"
> > -#include "i915_reg.h"
> >  #include "intel_atomic.h"
> >  #include "intel_audio.h"
> >  #include "intel_cdclk.h"
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index dc13f9eb4cd7..35122c997b8a
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -25,6 +25,7 @@
> >  #ifndef _I915_REG_H_
> >  #define _I915_REG_H_
> >
> > +#include <drm/intel/intel_gmd_common_regs.h>
> 
> Oh, I also dislike this, because it becomes unclear what needs them. The benefit
> from more granular headers is that only the places that need them can include
> them, and we can actually quickly check what includes what instead of these
> indirect dependencies.

Noted, will fix it.

Regards,
Uma Shankar

> BR,
> Jani.
> 
> 
> --
> Jani Nikula, Intel

RE: [v2 09/19] drm/{i915, xe}: Remove i915_reg.h from intel_overlay.c

[Shankar, Uma]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, January 22, 2026 5:22 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v2 09/19] drm/{i915, xe}: Remove i915_reg.h from intel_overlay.c
> 
> On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Move GEN2_ISR and some interrupt definitions to common header.
> > This removes dependency of i915_reg.h from intel_overlay.c.
> 
> Subject: drm/i915.
> 
> Here too I think this should be a dedicated file for the feture.
> 
> I actually think we might be able to refactor this away, but for the time being a
> header in include/drm/intel is probably fine. But at least you can just git grep who
> includes it (provided it's not included in
> i915_reg.h!) and see what to do about it.

Sure, will fix it.

Regards,
Uma Shankar

> BR,
> Jani.
> 
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_overlay.c |  2 +-
> >  drivers/gpu/drm/i915/i915_reg.h              | 36 -------------------
> >  include/drm/intel/intel_gmd_common_regs.h    | 38 ++++++++++++++++++++
> >  3 files changed, 39 insertions(+), 37 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
> > b/drivers/gpu/drm/i915/display/intel_overlay.c
> > index 88eb7ae5765c..62026f7f71d3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_overlay.c
> > +++ b/drivers/gpu/drm/i915/display/intel_overlay.c
> > @@ -28,6 +28,7 @@
> >
> >  #include <drm/drm_fourcc.h>
> >  #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >
> >  #include "gem/i915_gem_internal.h"
> >  #include "gem/i915_gem_object_frontbuffer.h"
> > @@ -37,7 +38,6 @@
> >  #include "gt/intel_ring.h"
> >
> >  #include "i915_drv.h"
> > -#include "i915_reg.h"
> >  #include "intel_color_regs.h"
> >  #include "intel_de.h"
> >  #include "intel_display_regs.h"
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index c1d141e9ca47..504ba9b2fb5b
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -522,42 +522,6 @@
> >  /* These are all the "old" interrupts */
> >  #define ILK_BSD_USER_INTERRUPT				(1 << 5)
> >
> > -#define I915_PM_INTERRUPT				(1 << 31)
> > -#define I915_ISP_INTERRUPT				(1 << 22)
> > -#define I915_LPE_PIPE_B_INTERRUPT			(1 << 21)
> > -#define I915_LPE_PIPE_A_INTERRUPT			(1 << 20)
> > -#define I915_MIPIC_INTERRUPT				(1 << 19)
> > -#define I915_MIPIA_INTERRUPT				(1 << 18)
> > -#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1 << 18)
> > -#define I915_DISPLAY_PORT_INTERRUPT			(1 << 17)
> > -#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1 << 16)
> > -#define I915_MASTER_ERROR_INTERRUPT			(1 << 15)
> > -#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1 << 14)
> > -#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1 << 14)
> /* p-state */
> > -#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1 << 13)
> > -#define I915_HWB_OOM_INTERRUPT				(1 << 13)
> > -#define I915_LPE_PIPE_C_INTERRUPT			(1 << 12)
> > -#define I915_SYNC_STATUS_INTERRUPT			(1 << 12)
> > -#define I915_MISC_INTERRUPT				(1 << 11)
> > -#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1 << 11)
> > -#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1 << 10)
> > -#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1 << 10)
> > -#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1 << 9)
> > -#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1 << 9)
> > -#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1 << 8)
> > -#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1 << 8)
> > -#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1 << 7)
> > -#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1 << 6)
> > -#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1 << 5)
> > -#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1 << 4)
> > -#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1 << 3)
> > -#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1 << 2)
> > -#define I915_DEBUG_INTERRUPT				(1 << 2)
> > -#define I915_WINVALID_INTERRUPT				(1 << 1)
> > -#define I915_USER_INTERRUPT				(1 << 1)
> > -#define I915_ASLE_INTERRUPT				(1 << 0)
> > -#define I915_BSD_USER_INTERRUPT				(1 << 25)
> > -
> >  #define GEN6_BSD_RNCID			_MMIO(0x12198)
> >
> >  #define GEN7_FF_THREAD_MODE		_MMIO(0x20a0)
> > diff --git a/include/drm/intel/intel_gmd_common_regs.h
> > b/include/drm/intel/intel_gmd_common_regs.h
> > index 489d59379ab0..2214cee38cf7 100644
> > --- a/include/drm/intel/intel_gmd_common_regs.h
> > +++ b/include/drm/intel/intel_gmd_common_regs.h
> > @@ -110,4 +110,42 @@
> >  #define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
> >  #define   GMD_ID_STEP				REG_GENMASK(5, 0)
> >
> > +#define GEN2_ISR       _MMIO(0x20ac)
> 
> This is duplication, and only used in display.
> 
> > +
> > +#define I915_PM_INTERRUPT				(1 << 31)
> > +#define I915_ISP_INTERRUPT				(1 << 22)
> > +#define I915_LPE_PIPE_B_INTERRUPT			(1 << 21)
> > +#define I915_LPE_PIPE_A_INTERRUPT			(1 << 20)
> > +#define I915_MIPIC_INTERRUPT				(1 << 19)
> > +#define I915_MIPIA_INTERRUPT				(1 << 18)
> > +#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1 << 18)
> > +#define I915_DISPLAY_PORT_INTERRUPT			(1 << 17)
> > +#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1 << 16)
> > +#define I915_MASTER_ERROR_INTERRUPT			(1 << 15)
> > +#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1 << 14)
> > +#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1 << 14)
> /* p-state */
> > +#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1 << 13)
> > +#define I915_HWB_OOM_INTERRUPT				(1 << 13)
> > +#define I915_LPE_PIPE_C_INTERRUPT			(1 << 12)
> > +#define I915_SYNC_STATUS_INTERRUPT			(1 << 12)
> > +#define I915_MISC_INTERRUPT				(1 << 11)
> > +#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1 << 11)
> > +#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1 << 10)
> > +#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1 << 10)
> > +#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1 << 9)
> > +#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1 << 9)
> > +#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1 << 8)
> > +#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1 << 8)
> > +#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1 << 7)
> > +#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1 << 6)
> > +#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1 << 5)
> > +#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1 << 4)
> > +#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1 << 3)
> > +#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1 << 2)
> > +#define I915_DEBUG_INTERRUPT				(1 << 2)
> > +#define I915_WINVALID_INTERRUPT				(1 << 1)
> > +#define I915_USER_INTERRUPT				(1 << 1)
> > +#define I915_ASLE_INTERRUPT				(1 << 0)
> > +#define I915_BSD_USER_INTERRUPT				(1 << 25)
> > +
> >  #endif
> 
> --
> Jani Nikula, Intel

RE: [v2 10/19] drm/{i915, xe}: Remove i915_reg.h from g4x_dp.c

[Shankar, Uma]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, January 22, 2026 5:30 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v2 10/19] drm/{i915, xe}: Remove i915_reg.h from g4x_dp.c
> 
> On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Move DE_IRQ_REGS to common header to make g4x_dp.c free from
> > i915_reg.h dependency.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/g4x_dp.c            |  2 +-
> >  .../gpu/drm/i915/display/intel_display_regs.h    |  9 +++++++++
> >  drivers/gpu/drm/i915/i915_reg.h                  | 16 ----------------
> >  include/drm/intel/intel_gmd_common_regs.h        |  7 +++++++
> >  4 files changed, 17 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
> > b/drivers/gpu/drm/i915/display/g4x_dp.c
> > index 4cb753177fd8..b2b63e811776 100644
> > --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> > @@ -8,9 +8,9 @@
> >  #include <linux/string_helpers.h>
> >
> >  #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >
> >  #include "g4x_dp.h"
> > -#include "i915_reg.h"
> >  #include "intel_audio.h"
> >  #include "intel_backlight.h"
> >  #include "intel_connector.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index b26e6a4ee1c3..eabee5abc23b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -3104,4 +3104,13 @@ enum skl_power_gate {
> >  #define   MTL_N_OF_POPULATED_CH_MASK
> 	REG_GENMASK(7, 4)
> >  #define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
> >
> > +#define DEISR   _MMIO(0x44000)
> > +#define DEIMR   _MMIO(0x44004)
> > +#define DEIIR   _MMIO(0x44008)
> > +#define DEIER   _MMIO(0x4400c)
> > +
> > +#define DE_IRQ_REGS		I915_IRQ_REGS(DEIMR, \
> > +					      DEIER, \
> > +					      DEIIR)
> > +
> >  #endif /* __INTEL_DISPLAY_REGS_H__ */ diff --git
> > a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 504ba9b2fb5b..c0c2fab99a47 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -728,15 +728,6 @@
> >  #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master
> IER */
> >  #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
> >
> > -#define DEISR   _MMIO(0x44000)
> > -#define DEIMR   _MMIO(0x44004)
> > -#define DEIIR   _MMIO(0x44008)
> > -#define DEIER   _MMIO(0x4400c)
> > -
> > -#define DE_IRQ_REGS		I915_IRQ_REGS(DEIMR, \
> > -					      DEIER, \
> > -					      DEIIR)
> > -
> >  #define GTISR   _MMIO(0x44010)
> >  #define GTIMR   _MMIO(0x44014)
> >  #define GTIIR   _MMIO(0x44018)
> > @@ -864,13 +855,6 @@
> >  #define   MASK_WAKEMEM				REG_BIT(13)
> >  #define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
> >
> > -/* PCH */
> > -
> > -#define SDEISR  _MMIO(0xc4000)
> > -#define SDEIMR  _MMIO(0xc4004)
> > -#define SDEIIR  _MMIO(0xc4008)
> > -#define SDEIER  _MMIO(0xc400c)
> > -
> >  /* Icelake PPS_DATA and _ECC DIP Registers.
> >   * These are available for transcoders B,C and eDP.
> >   * Adding the _A so as to reuse the _MMIO_TRANS2 diff --git
> > a/include/drm/intel/intel_gmd_common_regs.h
> > b/include/drm/intel/intel_gmd_common_regs.h
> > index 2214cee38cf7..c8b2b5b2739c 100644
> > --- a/include/drm/intel/intel_gmd_common_regs.h
> > +++ b/include/drm/intel/intel_gmd_common_regs.h
> > @@ -148,4 +148,11 @@
> >  #define I915_ASLE_INTERRUPT				(1 << 0)
> >  #define I915_BSD_USER_INTERRUPT				(1 << 25)
> >
> > +/* PCH */
> > +
> > +#define SDEISR  _MMIO(0xc4000)
> > +#define SDEIMR  _MMIO(0xc4004)
> > +#define SDEIIR  _MMIO(0xc4008)
> > +#define SDEIER  _MMIO(0xc400c)
> 
> These are only used by display and gvt. I don't know what we're going to do about
> gvt in the long run, but at this point I'd be prepared to just include the necessary
> display register headers directly. This is what we do with all the other registers.
> There are no other users for these, and IMO shouldn't be in the common header.

Ok sure, will fix it.

Regards,
Uma Shankar

> BR,
> Jani.
> 
> > +
> >  #endif
> 
> --
> Jani Nikula, Intel

RE: [v2 15/19] drm/{i915, xe}: Remove i915_reg.h from intel_fifo_underrun.c

[Shankar, Uma]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, January 22, 2026 5:44 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v2 15/19] drm/{i915, xe}: Remove i915_reg.h from
> intel_fifo_underrun.c
> 
> On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Move GEN7_ERR_INT reg to common header to make intel_fifo_underrun.c
> > free from including i915_reg.h.
> 
> I think these should be in a display register header, not the common one. The
> users are display and gvt, apart from a single use in
> gt_record_global_regs() which should be moved to display. I can send a patch for
> that.

Thanks for sending the change Jani. I will fix this.

Regards,
Uma Shankar

> BR,
> Jani.
> 
> 
> 
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> >  .../drm/i915/display/intel_fifo_underrun.c    |  2 +-
> >  drivers/gpu/drm/i915/i915_reg.h               | 23 -------------------
> >  include/drm/intel/intel_gmd_common_regs.h     | 23 +++++++++++++++++++
> >  3 files changed, 24 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> > b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> > index b413b3e871d8..c834be759e40 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> > @@ -28,8 +28,8 @@
> >  #include <linux/seq_buf.h>
> >
> >  #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >
> > -#include "i915_reg.h"
> >  #include "intel_de.h"
> >  #include "intel_display_irq.h"
> >  #include "intel_display_regs.h"
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 62d58d7cfa7a..0af2c9c8dc0f
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -326,29 +326,6 @@
> >  #define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
> >  #define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)
> >
> > -#define GEN7_ERR_INT	_MMIO(0x44040)
> > -#define   ERR_INT_POISON		(1 << 31)
> > -#define   ERR_INT_INVALID_GTT_PTE	(1 << 29)
> > -#define   ERR_INT_INVALID_PTE_DATA	(1 << 28)
> > -#define   ERR_INT_SPRITE_C_FAULT	(1 << 23)
> > -#define   ERR_INT_PRIMARY_C_FAULT	(1 << 22)
> > -#define   ERR_INT_CURSOR_C_FAULT	(1 << 21)
> > -#define   ERR_INT_SPRITE_B_FAULT	(1 << 20)
> > -#define   ERR_INT_PRIMARY_B_FAULT	(1 << 19)
> > -#define   ERR_INT_CURSOR_B_FAULT	(1 << 18)
> > -#define   ERR_INT_SPRITE_A_FAULT	(1 << 17)
> > -#define   ERR_INT_PRIMARY_A_FAULT	(1 << 16)
> > -#define   ERR_INT_CURSOR_A_FAULT	(1 << 15)
> > -#define   ERR_INT_MMIO_UNCLAIMED	(1 << 13)
> > -#define   ERR_INT_PIPE_CRC_DONE_C	(1 << 8)
> > -#define   ERR_INT_FIFO_UNDERRUN_C	(1 << 6)
> > -#define   ERR_INT_PIPE_CRC_DONE_B	(1 << 5)
> > -#define   ERR_INT_FIFO_UNDERRUN_B	(1 << 3)
> > -#define   ERR_INT_PIPE_CRC_DONE_A	(1 << 2)
> > -#define   ERR_INT_PIPE_CRC_DONE(pipe)	(1 << (2 + (pipe) * 3))
> > -#define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
> > -#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
> > -
> >  #define FPGA_DBG		_MMIO(0x42300)
> >  #define   FPGA_DBG_RM_NOCLAIM	REG_BIT(31)
> >
> > diff --git a/include/drm/intel/intel_gmd_common_regs.h
> > b/include/drm/intel/intel_gmd_common_regs.h
> > index 049349c365e3..2b2a7f21529a 100644
> > --- a/include/drm/intel/intel_gmd_common_regs.h
> > +++ b/include/drm/intel/intel_gmd_common_regs.h
> > @@ -169,4 +169,27 @@
> >  #define   INSTPM_TLB_INVALIDATE	(1 << 9)
> >  #define   INSTPM_SYNC_FLUSH	(1 << 5)
> >
> > +#define GEN7_ERR_INT	_MMIO(0x44040)
> > +#define   ERR_INT_POISON		(1 << 31)
> > +#define   ERR_INT_INVALID_GTT_PTE	(1 << 29)
> > +#define   ERR_INT_INVALID_PTE_DATA	(1 << 28)
> > +#define   ERR_INT_SPRITE_C_FAULT	(1 << 23)
> > +#define   ERR_INT_PRIMARY_C_FAULT	(1 << 22)
> > +#define   ERR_INT_CURSOR_C_FAULT	(1 << 21)
> > +#define   ERR_INT_SPRITE_B_FAULT	(1 << 20)
> > +#define   ERR_INT_PRIMARY_B_FAULT	(1 << 19)
> > +#define   ERR_INT_CURSOR_B_FAULT	(1 << 18)
> > +#define   ERR_INT_SPRITE_A_FAULT	(1 << 17)
> > +#define   ERR_INT_PRIMARY_A_FAULT	(1 << 16)
> > +#define   ERR_INT_CURSOR_A_FAULT	(1 << 15)
> > +#define   ERR_INT_MMIO_UNCLAIMED	(1 << 13)
> > +#define   ERR_INT_PIPE_CRC_DONE_C	(1 << 8)
> > +#define   ERR_INT_FIFO_UNDERRUN_C	(1 << 6)
> > +#define   ERR_INT_PIPE_CRC_DONE_B	(1 << 5)
> > +#define   ERR_INT_FIFO_UNDERRUN_B	(1 << 3)
> > +#define   ERR_INT_PIPE_CRC_DONE_A	(1 << 2)
> > +#define   ERR_INT_PIPE_CRC_DONE(pipe)	(1 << (2 + (pipe) * 3))
> > +#define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
> > +#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
> > +
> >  #endif
> 
> --
> Jani Nikula, Intel

RE: [v2 16/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_irq.c

[Shankar, Uma]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, January 22, 2026 5:49 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v2 16/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_irq.c
> 
> On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Move VLV_IRQ_REGS to common header to make intel_display_irq.c free
> > from including i915_reg.h.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> >  .../gpu/drm/i915/display/intel_display_irq.c  |  2 +-
> > .../gpu/drm/i915/display/intel_display_regs.h | 28 +++++-----
> >  drivers/gpu/drm/i915/i915_reg.h               | 52 ------------------
> >  include/drm/intel/intel_gmd_common_regs.h     | 54 +++++++++++++++++++
> >  4 files changed, 69 insertions(+), 67 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> > b/drivers/gpu/drm/i915/display/intel_display_irq.c
> > index 9adeebb376b1..206c0d004646 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> > @@ -5,8 +5,8 @@
> >
> >  #include <drm/drm_print.h>
> >  #include <drm/drm_vblank.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >
> > -#include "i915_reg.h"
> >  #include "icl_dsi_regs.h"
> >  #include "intel_crtc.h"
> >  #include "intel_de.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index aafe71a3b410..fb21b1cf6124 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -90,20 +90,6 @@
> >  #define   DERRMR_PIPEC_VBLANK		(1 << 21)
> >  #define   DERRMR_PIPEC_HBLANK		(1 << 22)
> >
> > -#define VLV_IRQ_REGS		I915_IRQ_REGS(VLV_IMR, \
> > -					      VLV_IER, \
> > -					      VLV_IIR)
> > -
> > -#define VLV_EIR		_MMIO(VLV_DISPLAY_BASE + 0x20b0)
> > -#define VLV_EMR		_MMIO(VLV_DISPLAY_BASE + 0x20b4)
> > -#define VLV_ESR		_MMIO(VLV_DISPLAY_BASE + 0x20b8)
> > -#define   VLV_ERROR_GUNIT_TLB_DATA			(1 << 6)
> > -#define   VLV_ERROR_GUNIT_TLB_PTE			(1 << 5)
> > -#define   VLV_ERROR_PAGE_TABLE				(1 << 4)
> > -#define   VLV_ERROR_CLAIM				(1 << 0)
> > -
> > -#define VLV_ERROR_REGS		I915_ERROR_REGS(VLV_EMR,
> VLV_EIR)
> > -
> >  #define _MBUS_ABOX0_CTL			0x45038
> >  #define _MBUS_ABOX1_CTL			0x45048
> >  #define _MBUS_ABOX2_CTL			0x4504C
> > @@ -3166,4 +3152,18 @@ enum skl_power_gate {
> >  #define   FW_BLC_SELF_FIFO_MASK    REG_BIT(16) /* 945 only */
> >  #define   FW_BLC_SELF_EN           REG_BIT(15) /* 945 only */
> >
> > +#define VLV_IRQ_REGS		I915_IRQ_REGS(VLV_IMR, \
> > +					      VLV_IER, \
> > +					      VLV_IIR)
> > +
> > +#define VLV_EIR		_MMIO(VLV_DISPLAY_BASE + 0x20b0)
> > +#define VLV_EMR		_MMIO(VLV_DISPLAY_BASE + 0x20b4)
> > +#define VLV_ESR		_MMIO(VLV_DISPLAY_BASE + 0x20b8)
> > +#define   VLV_ERROR_GUNIT_TLB_DATA			(1 << 6)
> > +#define   VLV_ERROR_GUNIT_TLB_PTE			(1 << 5)
> > +#define   VLV_ERROR_PAGE_TABLE				(1 << 4)
> > +#define   VLV_ERROR_CLAIM				(1 << 0)
> > +
> > +#define VLV_ERROR_REGS		I915_ERROR_REGS(VLV_EMR,
> VLV_EIR)
> > +
> >  #endif /* __INTEL_DISPLAY_REGS_H__ */ diff --git
> > a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 0af2c9c8dc0f..a85e2d9ab561 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -336,9 +336,6 @@
> >
> >  #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
> >  #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
> > -#define SCPD0		_MMIO(0x209c) /* 915+ only */
> > -#define  SCPD_FBC_IGNORE_3D			(1 << 6)
> > -#define  CSTATE_RENDER_CLOCK_GATE_DISABLE	(1 << 5)
> >  #define GEN2_IER	_MMIO(0x20a0)
> >  #define GEN2_IIR	_MMIO(0x20a4)
> >  #define GEN2_IMR	_MMIO(0x20a8)
> > @@ -352,13 +349,6 @@
> >  #define   GINT_DIS		(1 << 22)
> >  #define   GCFG_DIS		(1 << 8)
> >  #define VLV_GUNIT_CLOCK_GATE2	_MMIO(VLV_DISPLAY_BASE +
> 0x2064)
> > -#define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
> > -#define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
> > -#define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
> > -#define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
> > -#define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
> > -#define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
> > -#define VLV_PCBR_ADDR_SHIFT	12
> >
> >  #define EIR		_MMIO(0x20b0)
> >  #define EMR		_MMIO(0x20b4)
> > @@ -683,11 +673,6 @@
> >  #define PCH_3DCGDIS1		_MMIO(0x46024)
> >  # define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
> >
> > -/* Display Internal Timeout Register */
> > -#define RM_TIMEOUT		_MMIO(0x42060)
> > -#define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
> > -#define  MMIO_TIMEOUT_US(us)	((us) << 0)
> > -
> >  #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master
> IER */
> >  #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
> >
> > @@ -700,24 +685,6 @@
> >  					      GTIER, \
> >  					      GTIIR)
> >
> > -#define GEN8_MASTER_IRQ			_MMIO(0x44200)
> > -#define  GEN8_MASTER_IRQ_CONTROL	(1 << 31)
> > -#define  GEN8_PCU_IRQ			(1 << 30)
> > -#define  GEN8_DE_PCH_IRQ		(1 << 23)
> > -#define  GEN8_DE_MISC_IRQ		(1 << 22)
> > -#define  GEN8_DE_PORT_IRQ		(1 << 20)
> > -#define  GEN8_DE_PIPE_C_IRQ		(1 << 18)
> > -#define  GEN8_DE_PIPE_B_IRQ		(1 << 17)
> > -#define  GEN8_DE_PIPE_A_IRQ		(1 << 16)
> > -#define  GEN8_DE_PIPE_IRQ(pipe)		(1 << (16 + (pipe)))
> > -#define  GEN8_GT_VECS_IRQ		(1 << 6)
> > -#define  GEN8_GT_GUC_IRQ		(1 << 5)
> > -#define  GEN8_GT_PM_IRQ			(1 << 4)
> > -#define  GEN8_GT_VCS1_IRQ		(1 << 3) /* NB: VCS2 in bspec! */
> > -#define  GEN8_GT_VCS0_IRQ		(1 << 2) /* NB: VCS1 in bpsec! */
> > -#define  GEN8_GT_BCS_IRQ		(1 << 1)
> > -#define  GEN8_GT_RCS_IRQ		(1 << 0)
> > -
> >  #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))  #define
> > GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))  #define
> > GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) @@ -743,25 +710,6
> > @@
> >  						      GEN8_PCU_IER, \
> >  						      GEN8_PCU_IIR)
> >
> > -#define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
> > -#define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
> > -#define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
> > -#define GEN11_GU_MISC_IER	_MMIO(0x444fc)
> > -#define  GEN11_GU_MISC_GSE	(1 << 27)
> > -
> > -#define GEN11_GU_MISC_IRQ_REGS
> 	I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
> > -						      GEN11_GU_MISC_IER, \
> > -						      GEN11_GU_MISC_IIR)
> > -
> > -#define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
> > -#define  GEN11_MASTER_IRQ		(1 << 31)
> > -#define  GEN11_PCU_IRQ			(1 << 30)
> > -#define  GEN11_GU_MISC_IRQ		(1 << 29)
> > -#define  GEN11_DISPLAY_IRQ		(1 << 16)
> > -#define  GEN11_GT_DW_IRQ(x)		(1 << (x))
> > -#define  GEN11_GT_DW1_IRQ		(1 << 1)
> > -#define  GEN11_GT_DW0_IRQ		(1 << 0)
> > -
> >  #define DG1_MSTR_TILE_INTR		_MMIO(0x190008)
> >  #define   DG1_MSTR_IRQ			REG_BIT(31)
> >  #define   DG1_MSTR_TILE(t)		REG_BIT(t)
> > diff --git a/include/drm/intel/intel_gmd_common_regs.h
> > b/include/drm/intel/intel_gmd_common_regs.h
> > index 2b2a7f21529a..9bc234135454 100644
> > --- a/include/drm/intel/intel_gmd_common_regs.h
> > +++ b/include/drm/intel/intel_gmd_common_regs.h
> > @@ -111,6 +111,9 @@
> >  #define   GMD_ID_STEP				REG_GENMASK(5, 0)
> >
> >  #define GEN2_ISR       _MMIO(0x20ac)
> > +#define SCPD0		_MMIO(0x209c) /* 915+ only */
> > +#define  SCPD_FBC_IGNORE_3D			(1 << 6)
> > +#define  CSTATE_RENDER_CLOCK_GATE_DISABLE	(1 << 5)
> >
> >  #define I915_PM_INTERRUPT				(1 << 31)
> >  #define I915_ISP_INTERRUPT				(1 << 22)
> > @@ -192,4 +195,55 @@
> >  #define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
> >  #define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
> >
> > +#define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
> > +#define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
> > +#define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
> > +#define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
> > +#define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
> > +#define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
> > +#define VLV_PCBR_ADDR_SHIFT	12
> > +
> > +#define GEN8_MASTER_IRQ			_MMIO(0x44200)
> > +#define  GEN8_MASTER_IRQ_CONTROL	(1 << 31)
> > +#define  GEN8_PCU_IRQ			(1 << 30)
> > +#define  GEN8_DE_PCH_IRQ		(1 << 23)
> > +#define  GEN8_DE_MISC_IRQ		(1 << 22)
> > +#define  GEN8_DE_PORT_IRQ		(1 << 20)
> > +#define  GEN8_DE_PIPE_C_IRQ		(1 << 18)
> > +#define  GEN8_DE_PIPE_B_IRQ		(1 << 17)
> > +#define  GEN8_DE_PIPE_A_IRQ		(1 << 16)
> > +#define  GEN8_DE_PIPE_IRQ(pipe)		(1 << (16 + (pipe)))
> > +#define  GEN8_GT_VECS_IRQ		(1 << 6)
> > +#define  GEN8_GT_GUC_IRQ		(1 << 5)
> > +#define  GEN8_GT_PM_IRQ			(1 << 4)
> > +#define  GEN8_GT_VCS1_IRQ		(1 << 3) /* NB: VCS2 in bspec! */
> > +#define  GEN8_GT_VCS0_IRQ		(1 << 2) /* NB: VCS1 in bpsec! */
> > +#define  GEN8_GT_BCS_IRQ		(1 << 1)
> > +#define  GEN8_GT_RCS_IRQ		(1 << 0)
> > +
> > +
> > +#define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
> > +#define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
> > +#define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
> > +#define GEN11_GU_MISC_IER	_MMIO(0x444fc)
> > +#define  GEN11_GU_MISC_GSE	(1 << 27)
> > +
> > +#define GEN11_GU_MISC_IRQ_REGS
> 	I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
> > +						      GEN11_GU_MISC_IER, \
> > +						      GEN11_GU_MISC_IIR)
> > +
> > +/* Display Internal Timeout Register */
> > +#define RM_TIMEOUT		_MMIO(0x42060)
> > +#define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
> > +#define  MMIO_TIMEOUT_US(us)	((us) << 0)
> 
> These should be in display.

Yeah right.

> > +
> > +#define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
> > +#define  GEN11_MASTER_IRQ		(1 << 31)
> > +#define  GEN11_PCU_IRQ			(1 << 30)
> > +#define  GEN11_GU_MISC_IRQ		(1 << 29)
> > +#define  GEN11_DISPLAY_IRQ		(1 << 16)
> > +#define  GEN11_GT_DW_IRQ(x)		(1 << (x))
> > +#define  GEN11_GT_DW1_IRQ		(1 << 1)
> > +#define  GEN11_GT_DW0_IRQ		(1 << 0)
> 
> All the irq registers should be a file of their own.

Sure, will take care of it.

Regards,
Uma Shankar
 
> > +
> >  #endif
> 
> --
> Jani Nikula, Intel

RE: [v2 17/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_power_well.c

[Shankar, Uma]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, January 22, 2026 5:50 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v2 17/19] drm/{i915, xe}: Remove i915_reg.h from
> intel_display_power_well.c
> 
> On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Make intel_display_power_well.c free from including i915_reg.h.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
> >  drivers/gpu/drm/i915/display/intel_display_regs.h       | 2 ++
> >  drivers/gpu/drm/i915/i915_reg.h                         | 3 ---
> >  3 files changed, 3 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > index db185a859133..8a1f1c61c6da 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > @@ -6,8 +6,8 @@
> >  #include <linux/iopoll.h>
> >
> >  #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> 
> Again, I dislike the catch-all header, because I have no idea why this is included.
> More granular is better.

Noted.

Regards,
Uma Shankar

> BR,
> Jani.
> 
> >
> > -#include "i915_reg.h"
> >  #include "intel_backlight_regs.h"
> >  #include "intel_combo_phy.h"
> >  #include "intel_combo_phy_regs.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index fb21b1cf6124..1def3dccdf61 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -319,6 +319,8 @@
> >  #define  FW_CSPWRDWNEN		(1 << 15)
> >
> >  #define MI_ARB_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6504)
> > +/* Disable display A/B trickle feed */
> > +#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
> >
> >  #define CZCLK_CDCLK_FREQ_RATIO	_MMIO(VLV_DISPLAY_BASE +
> 0x6508)
> >  #define   CDCLK_FREQ_SHIFT	4
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index a85e2d9ab561..c68a64bc7646
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -428,9 +428,6 @@
> >  #define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/*
> default */
> >  #define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)
> >
> > -/* Disable display A/B trickle feed */
> > -#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
> > -
> >  /* Set display plane priority */
> >  #define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display
> A > display B */
> >  #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display
> B > display A */
> 
> --
> Jani Nikula, Intel

RE: [v2 19/19] drm/{i915, xe}: Remove i915_reg.h from display

[Shankar, Uma]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, January 22, 2026 5:51 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v2 19/19] drm/{i915, xe}: Remove i915_reg.h from display
> 
> On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Make display files free from including i915_reg.h.
> 
> Yeah, I'd like this with more granular headers, please.

Thanks Jani for your valuable time, detailed review and all the suggestions
and feedback.

I will address the same and send the next version.

Regards,
Uma Shankar

> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/hsw_ips.c               | 2 +-
> >  drivers/gpu/drm/i915/display/i9xx_plane.c            | 1 -
> >  drivers/gpu/drm/i915/display/icl_dsi.c               | 1 -
> >  drivers/gpu/drm/i915/display/intel_backlight.c       | 1 -
> >  drivers/gpu/drm/i915/display/intel_bw.c              | 2 +-
> >  drivers/gpu/drm/i915/display/intel_casf.c            | 1 -
> >  drivers/gpu/drm/i915/display/intel_ddi.c             | 2 +-
> >  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
> >  drivers/gpu/drm/i915/display/intel_display_power.c   | 2 +-
> >  drivers/gpu/drm/i915/display/intel_display_wa.c      | 1 -
> >  drivers/gpu/drm/i915/display/intel_dmc.c             | 1 -
> >  drivers/gpu/drm/i915/display/intel_fdi.c             | 1 -
> >  drivers/gpu/drm/i915/display/intel_hdcp.c            | 2 +-
> >  drivers/gpu/drm/i915/display/intel_hotplug_irq.c     | 1 -
> >  drivers/gpu/drm/i915/display/intel_lt_phy.c          | 1 -
> >  drivers/gpu/drm/i915/display/intel_pps.c             | 1 -
> >  drivers/gpu/drm/i915/display/intel_tc.c              | 2 +-
> >  drivers/gpu/drm/i915/display/skl_watermark.c         | 2 +-
> >  drivers/gpu/drm/i915/display/vlv_dsi.c               | 1 -
> >  19 files changed, 8 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c
> > b/drivers/gpu/drm/i915/display/hsw_ips.c
> > index 008d339d5c21..290d54fe87e4 100644
> > --- a/drivers/gpu/drm/i915/display/hsw_ips.c
> > +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> > @@ -6,9 +6,9 @@
> >  #include <linux/debugfs.h>
> >
> >  #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >
> >  #include "hsw_ips.h"
> > -#include "i915_reg.h"
> >  #include "intel_color_regs.h"
> >  #include "intel_de.h"
> >  #include "intel_display_regs.h"
> > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
> > b/drivers/gpu/drm/i915/display/i9xx_plane.c
> > index b1fecf178906..9c16753a1f3b 100644
> > --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> > +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> > @@ -10,7 +10,6 @@
> >  #include <drm/drm_fourcc.h>
> >  #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> >  #include "i9xx_plane.h"
> >  #include "i9xx_plane_regs.h"
> >  #include "intel_atomic.h"
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index c8e0333706c1..7cf511a6c0f9 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -34,7 +34,6 @@
> >  #include <drm/drm_print.h>
> >  #include <drm/drm_probe_helper.h>
> >
> > -#include "i915_reg.h"
> >  #include "icl_dsi.h"
> >  #include "icl_dsi_regs.h"
> >  #include "intel_atomic.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
> > b/drivers/gpu/drm/i915/display/intel_backlight.c
> > index a68fdbd2acb9..34e95f05936e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_backlight.c
> > +++ b/drivers/gpu/drm/i915/display/intel_backlight.c
> > @@ -12,7 +12,6 @@
> >  #include <drm/drm_file.h>
> >  #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> >  #include "intel_backlight.h"
> >  #include "intel_backlight_regs.h"
> >  #include "intel_connector.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 4ee3f5172f4e..372081d80aa8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -5,8 +5,8 @@
> >
> >  #include <drm/drm_atomic_state_helper.h>  #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >
> > -#include "i915_reg.h"
> >  #include "intel_bw.h"
> >  #include "intel_crtc.h"
> >  #include "intel_display_core.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_casf.c
> > b/drivers/gpu/drm/i915/display/intel_casf.c
> > index 0fe4398a1a4e..b167af31de5b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_casf.c
> > +++ b/drivers/gpu/drm/i915/display/intel_casf.c
> > @@ -3,7 +3,6 @@
> >
> >  #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> >  #include "intel_casf.h"
> >  #include "intel_casf_regs.h"
> >  #include "intel_de.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index d8739e2bb004..4bec15352d0f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -33,8 +33,8 @@
> >  #include <drm/display/drm_scdc_helper.h>  #include <drm/drm_print.h>
> > #include <drm/drm_privacy_screen_consumer.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >
> > -#include "i915_reg.h"
> >  #include "icl_dsi.h"
> >  #include "intel_alpm.h"
> >  #include "intel_audio.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index aba13e8a9051..07cb56f80e88 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -13,9 +13,9 @@
> >  #include <drm/drm_file.h>
> >  #include <drm/drm_fourcc.h>
> >  #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >
> >  #include "hsw_ips.h"
> > -#include "i915_reg.h"
> >  #include "i9xx_wm_regs.h"
> >  #include "intel_alpm.h"
> >  #include "intel_bo.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index d27397f43863..20dadabcd812 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -7,8 +7,8 @@
> >  #include <linux/string_helpers.h>
> >
> >  #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >
> > -#include "i915_reg.h"
> >  #include "intel_backlight_regs.h"
> >  #include "intel_cdclk.h"
> >  #include "intel_clock_gating.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c
> > b/drivers/gpu/drm/i915/display/intel_display_wa.c
> > index 581d943b9bdc..518df619f5e5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> > @@ -5,7 +5,6 @@
> >
> >  #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> >  #include "intel_de.h"
> >  #include "intel_display_core.h"
> >  #include "intel_display_regs.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> > b/drivers/gpu/drm/i915/display/intel_dmc.c
> > index 1182bc9a2e6d..8df06b993890 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > @@ -29,7 +29,6 @@
> >  #include <drm/drm_file.h>
> >  #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> >  #include "intel_crtc.h"
> >  #include "intel_de.h"
> >  #include "intel_display_power_well.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
> > b/drivers/gpu/drm/i915/display/intel_fdi.c
> > index 5bb0090dd5ed..24ce8a7842c7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> > @@ -8,7 +8,6 @@
> >  #include <drm/drm_fixed.h>
> >  #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> >  #include "intel_atomic.h"
> >  #include "intel_crtc.h"
> >  #include "intel_ddi.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 7114fc405c29..db15bf1980c0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -17,8 +17,8 @@
> >  #include <drm/display/drm_hdcp_helper.h>  #include <drm/drm_print.h>
> > #include <drm/intel/i915_component.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >
> > -#include "i915_reg.h"
> >  #include "intel_connector.h"
> >  #include "intel_de.h"
> >  #include "intel_display_jiffies.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> > b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> > index 82c39e4ffa37..8865cb2ac569 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> > @@ -5,7 +5,6 @@
> >
> >  #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> >  #include "intel_de.h"
> >  #include "intel_display_irq.h"
> >  #include "intel_display_regs.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index b4b281ef258b..d17a9b013b67 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -5,7 +5,6 @@
> >
> >  #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> >  #include "intel_cx0_phy.h"
> >  #include "intel_cx0_phy_regs.h"
> >  #include "intel_ddi.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
> > b/drivers/gpu/drm/i915/display/intel_pps.c
> > index b217ec7aa758..2d799af73bb7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pps.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> > @@ -9,7 +9,6 @@
> >  #include <drm/drm_print.h>
> >
> >  #include "g4x_dp.h"
> > -#include "i915_reg.h"
> >  #include "intel_de.h"
> >  #include "intel_display_jiffies.h"
> >  #include "intel_display_power_well.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> > b/drivers/gpu/drm/i915/display/intel_tc.c
> > index 064f572bbc85..5784d5d5132d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > @@ -6,8 +6,8 @@
> >  #include <linux/iopoll.h>
> >
> >  #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >
> > -#include "i915_reg.h"
> >  #include "intel_atomic.h"
> >  #include "intel_cx0_phy_regs.h"
> >  #include "intel_ddi.h"
> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> > b/drivers/gpu/drm/i915/display/skl_watermark.c
> > index a6aab79812e5..410289b3fadd 100644
> > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> > @@ -7,8 +7,8 @@
> >
> >  #include <drm/drm_blend.h>
> >  #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >
> > -#include "i915_reg.h"
> >  #include "i9xx_wm.h"
> >  #include "intel_atomic.h"
> >  #include "intel_bw.h"
> > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
> > b/drivers/gpu/drm/i915/display/vlv_dsi.c
> > index d705af3bf8ba..67f0082d3a69 100644
> > --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> > @@ -33,7 +33,6 @@
> >  #include <drm/drm_print.h>
> >  #include <drm/drm_probe_helper.h>
> >
> > -#include "i915_reg.h"
> >  #include "intel_atomic.h"
> >  #include "intel_backlight.h"
> >  #include "intel_connector.h"
> 
> --
> Jani Nikula, Intel