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From: Sascha Bischoff <Sascha.Bischoff@arm.com>
To: "maz@kernel.org" <maz@kernel.org>
Cc: "yuzenghui@huawei.com" <yuzenghui@huawei.com>,
	"fuad.tabba@linux.dev" <fuad.tabba@linux.dev>,
	Timothy Hayes <Timothy.Hayes@arm.com>,
	Suzuki Poulose <Suzuki.Poulose@arm.com>, nd <nd@arm.com>,
	"peter.maydell@linaro.org" <peter.maydell@linaro.org>,
	"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	Joey Gouly <Joey.Gouly@arm.com>,
	"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
	"oliver.upton@linux.dev" <oliver.upton@linux.dev>
Subject: Re: [PATCH v4 03/48] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts
Date: Fri, 31 Jul 2026 07:21:07 +0000	[thread overview]
Message-ID: <3a5fe868fee31b62e66f7dc19865a83cdfadf6de.camel@arm.com> (raw)
In-Reply-To: <874ihnquni.wl-maz@kernel.org>

On Sat, 2026-07-25 at 10:35 +0100, Marc Zyngier wrote:
> On Fri, 24 Jul 2026 11:49:11 +0100,
> Sascha Bischoff <Sascha.Bischoff@arm.com> wrote:
> > 
> > Device-tree based GICv5 probing already passes the IRS details and
> > maintenance interrupt to KVM, but the ACPI path only initialises
> > the
> > irqchip and installs the ACPI IRQ model. As a result, KVM never
> > sees
> > the GICv5 host information required to probe the vGIC on ACPI
> > systems.
> > 
> > Add the ACPI equivalent of the DT KVM setup. Parse the MADT GICC
> > entries for the maintenance interrupt, require all relevant entries
> > to
> > agree, register the interrupt as a GICv5 PPI-encoded GSI, and pass
> > the
> > resulting IRQ together with the IRS base and coherency information
> > to
> > KVM. Native GICv5 does not require a maintenance interrupt unless
> > the
> > legacy GICv3-compatible CPU interface is present, so preserve the
> > existing no-maintenance-IRQ handling for that case.
> > 
> > Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
> > ---
> >  drivers/irqchip/irq-gic-v5.c | 100
> > +++++++++++++++++++++++++++++++++--
> >  1 file changed, 96 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-
> > gic-v5.c
> > index e7a7aedcfaf78..0d90675fb319b 100644
> > --- a/drivers/irqchip/irq-gic-v5.c
> > +++ b/drivers/irqchip/irq-gic-v5.c
> > @@ -1126,7 +1126,7 @@ static void gicv5_set_cpuif_idbits(void)
> >  #ifdef CONFIG_KVM
> >  static struct gic_kvm_info gic_v5_kvm_info __initdata;
> >  
> > -static void __init gic_of_setup_kvm_info(struct device_node *node)
> > +static void __init gic_setup_kvm_info(unsigned int maint_irq)
> >  {
> >  	struct gicv5_irs_chip_data *irs_data =
> > gicv5_irs_get_chip_data();
> >  
> > @@ -1137,17 +1137,19 @@ static void __init
> > gic_of_setup_kvm_info(struct device_node *node)
> >  	 */
> >  	if (!gicv5_global_data.virt_capable) {
> >  		pr_info("GIC implementation is not virtualization
> > capable\n");
> > -		return;
> > +		goto out_dispose_maint_irq;
> >  	}
> >  
> > -	gic_v5_kvm_info.type = GIC_V5;
> > +	if (WARN_ON(!irs_data))
> > +		goto out_dispose_maint_irq;
> >  
> > +	gic_v5_kvm_info.type = GIC_V5;
> >  	gic_v5_kvm_info.gicv5_irs.base = irs_data->irs_base;
> >  	gic_v5_kvm_info.gicv5_irs.non_coherent = !!(irs_data-
> > >flags & IRS_FLAGS_NON_COHERENT);
> >  
> >  	/* GIC Virtual CPU interface maintenance interrupt */
> >  	gic_v5_kvm_info.no_maint_irq_mask = false;
> > -	gic_v5_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
> > +	gic_v5_kvm_info.maint_irq = maint_irq;
> >  
> >  	/*
> >  	 * We require an MI if we have legacy support, but don't,
> > otherwise.
> > @@ -1162,11 +1164,100 @@ static void __init
> > gic_of_setup_kvm_info(struct device_node *node)
> >  		gic_v5_kvm_info.no_maint_irq_mask = true;
> >  
> >  	vgic_set_kvm_info(&gic_v5_kvm_info);
> > +	return;
> > +
> > +out_dispose_maint_irq:
> > +	irq_dispose_mapping(maint_irq);
> > +}
> > +
> > +static void __init gic_of_setup_kvm_info(struct device_node *node)
> > +{
> > +	/* GIC Virtual CPU interface maintenance interrupt */
> > +	gic_setup_kvm_info(irq_of_parse_and_map(node, 0));
> > +}
> > +
> > +#ifdef CONFIG_ACPI
> > +struct gicv5_acpi_kvm_info {
> > +	u32 maint_irq;
> > +	int maint_irq_mode;
> > +};
> > +
> > +static struct gicv5_acpi_kvm_info acpi_v5_kvm_info __initdata;
> > +
> > +static int __init gic_acpi_parse_virt_madt_gicc(union
> > acpi_subtable_headers *header,
> > +						const unsigned
> > long end)
> > +{
> > +	struct acpi_madt_generic_interrupt *gicc =
> > +		(struct acpi_madt_generic_interrupt *)header;
> > +	static int first_madt = true;
> > +	int maint_irq_mode;
> > +
> > +	if (!(gicc->flags &
> > +	      (ACPI_MADT_ENABLED |
> > ACPI_MADT_GICC_ONLINE_CAPABLE)))
> > +		return 0;
> > +
> > +	maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
> > +			 ACPI_EDGE_SENSITIVE :
> > ACPI_LEVEL_SENSITIVE;
> > +
> 
> This looks wrong, as the MI cannot be edge-triggered. This is
> cargo-culted from the GICv3 code, which is just as buggy (I'll go and
> clean it up).
> 
> This should simply be ignored, and the existence of the field shows
> how little understanding of the architecture the ACPI zealots have.

Have done that, and have broadly matched your GICv3 changes.

> 
> > +	if (first_madt) {
> > +		first_madt = false;
> > +
> > +		acpi_v5_kvm_info.maint_irq = gicc->vgic_interrupt;
> > +		acpi_v5_kvm_info.maint_irq_mode = maint_irq_mode;
> > +		return 0;
> > +	}
> > +
> > +	/* The maintenance interrupt must be the same for every
> > GICC entry. */
> > +	if (acpi_v5_kvm_info.maint_irq != gicc->vgic_interrupt ||
> > +	    acpi_v5_kvm_info.maint_irq_mode != maint_irq_mode)
> > +		return -EINVAL;
> 
> Similarly, this second check should be dropped. We're not in the
> business of validating ACPI tables. Print a FW_BUG warning if you
> want, but that's all that needs doing, and we don't need to screw the
> user over the FW's brokenness.

OK, done. I've left a warning, but otherwise continue.

> 
> > +
> > +	return 0;
> > +}
> > +
> > +static bool __init gic_acpi_collect_virt_info(void)
> > +{
> > +	int count;
> > +
> > +	count =
> > acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
> > +				     
> > gic_acpi_parse_virt_madt_gicc, 0);
> > +
> > +	return count > 0;
> > +}
> > +
> > +static void __init gic_acpi_setup_kvm_info(void)
> > +{
> > +	unsigned int maint_irq = 0;
> > +	int irq;
> > +
> > +	if (!gic_acpi_collect_virt_info()) {
> > +		pr_warn("Unable to get hardware information used
> > for virtualization\n");
> > +		return;
> > +	}
> > +
> > +	if (acpi_v5_kvm_info.maint_irq) {
> > +		irq = acpi_register_gsi(NULL,
> > acpi_v5_kvm_info.maint_irq,
> > +					acpi_v5_kvm_info.maint_irq
> > _mode,
> > +					ACPI_ACTIVE_HIGH);
> 
> Just hardcode the trigger mode here.

Done.

> 
> > +		if (irq > 0)
> > +			maint_irq = irq;
> > +		else
> > +			pr_warn("Failed to register GSI for GICv5
> > maintenance IRQ\n");
> > +	}
> > +
> > +	gic_setup_kvm_info(maint_irq);
> >  }
> > +#endif
> 
> nit: add '// CONFIG_ACPI' here, for consistency.

And done.

> 
> >  #else
> >  static inline void __init gic_of_setup_kvm_info(struct device_node
> > *node)
> >  {
> >  }
> > +
> > +#ifdef CONFIG_ACPI
> > +static inline void __init gic_acpi_setup_kvm_info(void)
> > +{
> > +}
> > +#endif
> >  #endif // CONFIG_KVM
> >  
> >  static int __init gicv5_init_common(struct fwnode_handle
> > *parent_domain)
> > @@ -1265,6 +1356,7 @@ static int __init gic_acpi_init(union
> > acpi_subtable_headers *header, const unsig
> >  		goto out_irs;
> >  
> >  	acpi_set_irq_model(ACPI_IRQ_MODEL_GIC_V5,
> > gic_v5_get_gsi_domain_id);
> > +	gic_acpi_setup_kvm_info();
> >  
> >  	return 0;
> >  
> 
> Thanks,
> 
> 	M.
> 
Thanks,
Sascha

  reply	other threads:[~2026-07-31  7:22 UTC|newest]

Thread overview: 110+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-24 10:48 [PATCH v4 00/48] KVM: arm64: Add GICv5 IRS support Sascha Bischoff
2026-07-24 10:48 ` [PATCH v4 01/48] irqchip/gic-v5: Allow KVM setup without a maintenance IRQ Sascha Bischoff
2026-07-24 11:21   ` sashiko-bot
2026-07-31  9:20     ` Sascha Bischoff
2026-07-24 10:48 ` [PATCH v4 02/48] irqchip/gic-v5: Provide OF IRS config frame attrs to KVM Sascha Bischoff
2026-07-24 11:10   ` sashiko-bot
2026-07-31  9:29     ` Sascha Bischoff
2026-07-25  9:06   ` Marc Zyngier
2026-07-25  9:18     ` Marc Zyngier
2026-07-24 10:49 ` [PATCH v4 03/48] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts Sascha Bischoff
2026-07-24 11:19   ` sashiko-bot
2026-07-25 10:08     ` Marc Zyngier
2026-07-28 12:14       ` Fuad Tabba
2026-07-31  7:18       ` Sascha Bischoff
2026-07-25  9:35   ` Marc Zyngier
2026-07-31  7:21     ` Sascha Bischoff [this message]
2026-07-24 10:49 ` [PATCH v4 04/48] KVM: arm64: gic-v5: Define remaining IRS MMIO registers Sascha Bischoff
2026-07-24 10:49 ` [PATCH v4 05/48] arm64/sysreg: Add GICv5 GIC VDPEND encoding Sascha Bischoff
2026-07-24 10:49 ` [PATCH v4 06/48] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields Sascha Bischoff
2026-07-24 11:14   ` sashiko-bot
2026-07-25 10:10     ` Marc Zyngier
2026-07-31  9:32     ` Sascha Bischoff
2026-07-24 10:50 ` [PATCH v4 07/48] KVM: arm64: gic-v5: Extract host IRS caps from IRS config frame Sascha Bischoff
2026-07-24 11:19   ` sashiko-bot
2026-07-31  9:35     ` Sascha Bischoff
2026-07-25 10:40   ` Marc Zyngier
2026-07-31  7:24     ` Sascha Bischoff
2026-07-24 10:50 ` [PATCH v4 08/48] KVM: arm64: gic-v5: Add VPE doorbell domain Sascha Bischoff
2026-07-24 11:11   ` sashiko-bot
2026-07-31  9:33     ` Sascha Bischoff
2026-07-25 10:56   ` Marc Zyngier
2026-07-31  8:35     ` Sascha Bischoff
2026-07-24 10:50 ` [PATCH v4 09/48] KVM: arm64: gic-v5: Create and manage VM and VPE tables Sascha Bischoff
2026-07-24 11:19   ` sashiko-bot
2026-08-07  8:06     ` Sascha Bischoff
2026-07-24 10:50 ` [PATCH v4 10/48] KVM: arm64: gic-v5: Introduce guest IST alloc and management Sascha Bischoff
2026-07-24 11:22   ` sashiko-bot
2026-07-27 16:39     ` Fuad Tabba
2026-08-07  8:27     ` Sascha Bischoff
2026-07-27 17:55   ` Fuad Tabba
2026-07-31  9:11     ` Sascha Bischoff
2026-07-24 10:51 ` [PATCH v4 11/48] KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops Sascha Bischoff
2026-07-24 11:20   ` sashiko-bot
2026-08-07  8:12     ` Sascha Bischoff
2026-07-24 10:51 ` [PATCH v4 12/48] KVM: arm64: gic-v5: Keep GICv5 vCPU limit model-specific Sascha Bischoff
2026-07-24 10:51 ` [PATCH v4 13/48] KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops Sascha Bischoff
2026-07-24 11:21   ` sashiko-bot
2026-07-31 13:15     ` Sascha Bischoff
2026-07-24 10:52 ` [PATCH v4 14/48] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells Sascha Bischoff
2026-07-24 11:27   ` sashiko-bot
2026-07-31 10:17     ` Sascha Bischoff
2026-07-24 10:52 ` [PATCH v4 15/48] KVM: arm64: gic-v5: Add resident/non-resident hyp calls Sascha Bischoff
2026-07-24 11:26   ` sashiko-bot
2026-07-31 13:16     ` Sascha Bischoff
2026-07-24 10:52 ` [PATCH v4 16/48] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI Sascha Bischoff
2026-07-24 11:41   ` sashiko-bot
2026-07-31 10:20     ` Sascha Bischoff
2026-07-24 10:52 ` [PATCH v4 17/48] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 18/48] KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 19/48] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI Sascha Bischoff
2026-07-24 11:30   ` sashiko-bot
2026-07-31 10:22     ` Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 20/48] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation Sascha Bischoff
2026-07-24 11:45   ` sashiko-bot
2026-08-03 10:21     ` Sascha Bischoff
2026-07-27 18:34   ` Fuad Tabba
2026-07-30 16:06     ` Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 21/48] KVM: arm64: gic-v5: Initialise per-VM IRS state Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 22/48] KVM: arm64: gic-v5: Register the IRS IODEV Sascha Bischoff
2026-07-24 11:33   ` sashiko-bot
2026-07-31 13:05     ` Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 23/48] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state Sascha Bischoff
2026-07-24 11:41   ` sashiko-bot
2026-07-24 10:54 ` [PATCH v4 24/48] KVM: arm64: selftests: Update vGICv5 selftest to set IRS address Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 25/48] KVM: arm64: gic-v5: Add GIC VDPEND hyp call Sascha Bischoff
2026-07-24 11:34   ` sashiko-bot
2026-07-31 13:18     ` Sascha Bischoff
2026-07-24 10:55 ` [PATCH v4 26/48] KVM: arm64: gic: Introduce set_pending_state() to irq_op Sascha Bischoff
2026-07-24 11:39   ` sashiko-bot
2026-07-31 13:37     ` Sascha Bischoff
2026-07-24 10:55 ` [PATCH v4 27/48] KVM: arm64: gic-v5: Support SPI injection Sascha Bischoff
2026-07-24 11:48   ` sashiko-bot
2026-07-31 13:49     ` Sascha Bischoff
2026-07-24 10:55 ` [PATCH v4 28/48] Documentation: KVM: Extend VGICv5 device attribute docs Sascha Bischoff
     [not found] ` <20260724104819.1296803-35-sascha.bischoff@arm.com>
2026-07-24 11:46   ` [PATCH v4 34/48] KVM: arm64: gic-v5: Add VGICv5 IST save/restore UAPI sashiko-bot
2026-07-31 14:35     ` Sascha Bischoff
     [not found] ` <20260724104819.1296803-31-sascha.bischoff@arm.com>
2026-07-24 11:52   ` [PATCH v4 30/48] KVM: arm64: gic-v5: Mask per-vcpu PPI state in vgic_v5_finalize_ppi_state() sashiko-bot
2026-07-31 14:21     ` Sascha Bischoff
     [not found] ` <20260724104819.1296803-42-sascha.bischoff@arm.com>
2026-07-24 12:02   ` [PATCH v4 41/48] KVM: selftests: Add VGICv5 NR_IRQS attribute tests sashiko-bot
2026-07-31 16:24     ` Sascha Bischoff
     [not found] ` <20260724104819.1296803-33-sascha.bischoff@arm.com>
2026-07-24 12:05   ` [PATCH v4 32/48] KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region sashiko-bot
2026-07-31 14:42     ` Sascha Bischoff
     [not found] ` <20260724104819.1296803-43-sascha.bischoff@arm.com>
2026-07-24 12:06   ` [PATCH v4 42/48] KVM: selftests: Add VGICv5 IRS_REGS attribute tests sashiko-bot
2026-07-31 15:52     ` Sascha Bischoff
     [not found] ` <20260724104819.1296803-32-sascha.bischoff@arm.com>
2026-07-24 12:09   ` [PATCH v4 31/48] KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors sashiko-bot
2026-07-31 14:27     ` Sascha Bischoff
     [not found] ` <20260724104819.1296803-47-sascha.bischoff@arm.com>
2026-07-24 12:15   ` [PATCH v4 46/48] KVM: selftests: Add VGICv5 SPI injection tests sashiko-bot
2026-07-31 14:54     ` Sascha Bischoff
     [not found] ` <20260724104819.1296803-48-sascha.bischoff@arm.com>
2026-07-24 12:18   ` [PATCH v4 47/48] KVM: selftests: Add VGICv5 LPI delivery tests sashiko-bot
2026-07-31 14:49     ` Sascha Bischoff
     [not found] ` <20260724104819.1296803-38-sascha.bischoff@arm.com>
2026-07-24 12:19   ` [PATCH v4 37/48] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs sashiko-bot
2026-07-31 14:46     ` Sascha Bischoff
     [not found] ` <20260724104819.1296803-30-sascha.bischoff@arm.com>
2026-07-24 12:19   ` [PATCH v4 29/48] KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd sashiko-bot
2026-07-31 14:13     ` Sascha Bischoff
     [not found] ` <20260724104819.1296803-36-sascha.bischoff@arm.com>
2026-07-24 12:02   ` [PATCH v4 35/48] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs sashiko-bot
2026-07-31 16:43     ` Sascha Bischoff
2026-07-27 18:56   ` Fuad Tabba
2026-07-31  8:55     ` Sascha Bischoff
     [not found] ` <20260724104819.1296803-39-sascha.bischoff@arm.com>
2026-07-27 19:26   ` [PATCH v4 38/48] Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST Fuad Tabba
2026-07-31  9:19     ` Sascha Bischoff

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