[RFC PATCH 01/22] dt-bindings: memory: cdns,k3-ddr: Add Cadence K3 DDR controller binding

[RFC PATCH 01/22] dt-bindings: memory: cdns,k3-ddr: Add Cadence K3 DDR controller binding

[MANNURU VENKATESWARLU]

Add device tree binding for the Cadence DDR controller used in TI K3 SoCs.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Gandhar Deshpande <g-deshpande@ti.com>
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
---
 .../memory-controllers/ti/cdns,k3-ddr.yaml    | 81 +++++++++++++++++++
 1 file changed, 81 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml

diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml b/Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml
new file mode 100644
index 0000000000000..89caeb111627a
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/ti/cdns,k3-ddr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence DDR controller for K3 devices
+
+maintainers:
+  - Santhosh Kumar K <s-k6@ti.com>
+  - Neha Malcom Francis <n-francis@ti.com>
+
+properties:
+  compatible:
+    const: cdns,k3-ddr
+
+  reg:
+    minItems: 3
+    maxItems: 3
+    description: |
+      Address ranges for the different register regions of the DDRSS controller.
+      - ctl_cfg: Controller configuration registers
+      - ctl_cfg_pi: PHY Interface configuration registers
+      - ctl_cfg_phy: PHY configuration registers
+
+  reg-names:
+    items:
+      - const: ctl_cfg
+      - const: ctl_cfg_pi
+      - const: ctl_cfg_phy
+
+  bootph-pre-ram: true
+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+    cbass_main {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      memorycontroller: memorycontroller@2980000 {
+        compatible = "ti,j721e-ddrss";
+        reg = <0x0 0x02990000 0x0 0x4000>,
+              <0x0 0x0114000 0x0 0x100>;
+        reg-names = "cfg", "ctrl_mmr_lp4";
+        power-domains = <&k3_pds 47 TI_SCI_PD_SHARED>,
+                        <&k3_pds 90 TI_SCI_PD_SHARED>;
+        interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges = <0x00 0x0000 0x00 0x02990000 0x00 0x4000>;
+        ti,ddr-freq1 = <0>;
+        ti,ddr-freq2 = <0>;
+        ti,ddr-fhs-cnt = <0>;
+        clocks = <&k3_clks 47 2>, <&k3_clks 30 9>;
+        bootph-pre-ram;
+
+        ddr: ddr@0 {
+          compatible = "cdns,k3-ddr";
+          reg = <0x00 0x0000 0x00 0x72c>,
+                <0x00 0x2000 0x00 0x4b0>,
+                <0x00 0x4000 0x00 0x163c>;
+          reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+          bootph-pre-ram;
+        };
+
+        ddr_pmu0: ddr-pmu@100 {
+          compatible = "ti,k3-ddr-pmu";
+          reg = <0x00 0x100 0x00 0x14>;
+        };
+      };
+    };
-- 
2.34.1

[RFC PATCH 02/22] dt-bindings: memory: ti,j7-ddrss: Add TI K3 DDRSS wrapper binding

[MANNURU VENKATESWARLU]

Add device tree binding for the TI wrapper module for the Cadence
DDRSS controller in K3 SoCs.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Gandhar Deshpande <g-deshpande@ti.com>
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
---
 .../memory-controllers/ti/ti,j7-ddrss.yaml    | 186 ++++++++++++++++++
 1 file changed, 186 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti/ti,j7-ddrss.yaml

diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/ti,j7-ddrss.yaml b/Documentation/devicetree/bindings/memory-controllers/ti/ti,j7-ddrss.yaml
new file mode 100644
index 0000000000000..f4bebabaeb111
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/ti,j7-ddrss.yaml
@@ -0,0 +1,186 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/ti/ti,j7-ddrss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI wrapper module for the Cadence DDRSS controller
+
+maintainers:
+  - Santhosh Kumar K <s-k6@ti.com>
+  - Neha Malcom Francis <n-francis@ti.com>
+
+description: |
+  The K3 DDR subsystem comprises DDR controller, DDR PHY and wrapper
+  logic to integrate these blocks in the device. The DDR subsystem is
+  used to provide an interface to external SDRAM devices which can be
+  utilized for storing program or data.
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - ti,j721s2-ddrss
+          - ti,j721e-ddrss
+          - ti,j7-ddrss
+          - ti,am62-ddrss
+          - ti,am62a-ddrss
+      - items:
+          - const: ti,am64-ddrss
+          - const: ti,am62-ddrss
+      - items:
+          - const: ti,am62p-ddrss
+          - const: ti,am62a-ddrss
+
+  reg:
+    minItems: 1
+    maxItems: 3
+    description: |
+      Register regions for the DDR subsystem wrapper. The number of regions
+      depends on the SoC variant:
+      - 1 region (ss_cfg): am62, am62p legacy layout
+      - 2 regions (cfg, ctrl_mmr_lp4): j7200, j721e
+      - 3 regions (cfg, ctrl_mmr_lp4, ss_cfg): j721s2, j784s4, am62a, am64
+
+  reg-names:
+    oneOf:
+      - items:
+          - const: ss_cfg
+      - items:
+          - const: cfg
+          - const: ctrl_mmr_lp4
+      - items:
+          - const: cfg
+          - const: ctrl_mmr_lp4
+          - const: ss_cfg
+
+  bootph-pre-ram: true
+
+  ranges:
+    minItems: 1
+
+  interrupts:
+    maxItems: 1
+    description: |
+      Interrupt line for the DDR subsystem controller. This interrupt is
+      typically used for temperature monitoring and error reporting.
+
+  power-domains:
+    minItems: 1
+    maxItems: 2
+    description: |
+      Power domains required by the DDR subsystem:
+      - an entry to TISCI DDR CFG device
+      - an entry to TISCI DDR DATA.
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+    description: |
+      - An entry to DDRSS clock
+      - An entry to SoC bypass clock
+
+  ti,ddr-freq0:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Initial DDR frequency in Hz before frequency switching. Present on
+      SoCs with three-frequency operation (j721s2, j784s4).
+
+  ti,ddr-freq1:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      Primary DDR frequency setting in Hz. This value is used for
+      normal operation of the DDR subsystem.
+
+  ti,ddr-freq2:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      Secondary DDR frequency setting in Hz. This value can be used
+      for power saving or performance modes.
+
+  ti,ddr-fhs-cnt:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      Frequency handover sequence count. This value defines how many
+      steps to use when switching between frequency settings.
+
+  instance:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Zero-based index identifying this DDR subsystem instance. Required on
+      multi-DDR SoCs (j721s2, j784s4) where two or more instances exist.
+
+  '#address-cells':
+    const: 2
+
+  '#size-cells':
+    const: 2
+
+patternProperties:
+  "^ddr@":
+    type: object
+
+  "^ddr-pmu@":
+    type: object
+    properties:
+      compatible:
+        const: ti,k3-ddr-pmu
+      reg:
+        maxItems: 1
+    required:
+      - compatible
+      - reg
+    additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - ranges
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+    cbass_main {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      memorycontroller: memorycontroller@2980000 {
+        compatible = "ti,j721e-ddrss";
+        reg = <0x0 0x02990000 0x0 0x4000>,
+              <0x0 0x0114000 0x0 0x100>;
+        reg-names = "cfg", "ctrl_mmr_lp4";
+        power-domains = <&k3_pds 47 TI_SCI_PD_SHARED>,
+                        <&k3_pds 90 TI_SCI_PD_SHARED>;
+        interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges = <0x00 0x0000 0x00 0x02990000 0x00 0x4000>;
+        ti,ddr-freq1 = <0>;
+        ti,ddr-freq2 = <0>;
+        ti,ddr-fhs-cnt = <0>;
+        clocks = <&k3_clks 47 2>, <&k3_clks 30 9>;
+        bootph-pre-ram;
+
+        ddr: ddr@0 {
+          compatible = "cdns,k3-ddr";
+          reg = <0x00 0x0000 0x00 0x72c>,
+                <0x00 0x2000 0x00 0x4b0>,
+                <0x00 0x4000 0x00 0x163c>;
+          reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+          bootph-pre-ram;
+        };
+
+        ddr_pmu0: ddr-pmu@100 {
+          compatible = "ti,k3-ddr-pmu";
+          reg = <0x00 0x100 0x00 0x14>;
+        };
+      };
+    };
-- 
2.34.1

[RFC PATCH 03/22] dt-bindings: memory: ti,j721s2-msmc: Add TI K3 MSMC binding

[MANNURU VENKATESWARLU]

Add DT binding for the TI K3 MSMC (Multi-Subsystem Memory
Controller) node present on J721S2, J784S4 and J742S2 SoCs. The
MSMC acts as a bus container for multiple DDR subsystem instances
and carries interleave configuration written by the bootloader.

Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
---
 .../memory-controllers/ti/ti,j721s2-msmc.yaml | 124 ++++++++++++++++++
 1 file changed, 124 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti/ti,j721s2-msmc.yaml

diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/ti,j721s2-msmc.yaml b/Documentation/devicetree/bindings/memory-controllers/ti/ti,j721s2-msmc.yaml
new file mode 100644
index 0000000000000..5ccdc546a121f
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/ti,j721s2-msmc.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/ti/ti,j721s2-msmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI K3 Multi-Subsystem Memory Controller (MSMC)
+
+maintainers:
+  - Neha Malcom Francis <n-francis@ti.com>
+
+description:
+  The K3 MSMC node is present on J721S2, J784S4, and J742S2 SoCs. It acts
+  as a bus container for multiple DDR subsystem instances and carries
+  metadata describing how DDR address space is interleaved across those
+  instances. All properties are configured by the bootloader at boot time
+  prior to OS handoff; the OS treats them as read-only.
+
+properties:
+  compatible:
+    items:
+      - const: ti,j721s2-msmc
+      - const: simple-bus
+
+  '#address-cells':
+    const: 2
+
+  '#size-cells':
+    const: 2
+
+  ranges: true
+
+  bootph-pre-ram: true
+
+  intrlv-gran:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      DDR address interleaving granularity.
+
+  intrlv-size:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      DDR address interleaving region size.
+
+  ecc-enable:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      ECC enable bitmask across DDR instances.
+
+  emif-config:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      EMIF hybrid DDR configuration select.
+
+  emif-active:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Bitmask of active EMIF instances.
+
+patternProperties:
+  "^memorycontroller@[0-9a-f]+$":
+    type: object
+    description: DDR subsystem child node, see ti,j7-ddrss.yaml.
+
+required:
+  - compatible
+  - '#address-cells'
+  - '#size-cells'
+  - ranges
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+    msmc0: msmc {
+        compatible = "ti,j721s2-msmc", "simple-bus";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges;
+        intrlv-gran = <0>;
+        intrlv-size = <0>;
+        ecc-enable  = <0>;
+        emif-config = <0>;
+        emif-active = <0>;
+        bootph-pre-ram;
+
+        memorycontroller0: memorycontroller@2980000 {
+            compatible = "ti,j721s2-ddrss";
+            reg = <0x0 0x02990000 0x0 0x4000>,
+                  <0x0 0x0114000 0x0 0x100>,
+                  <0x0 0x02980000 0x0 0x200>;
+            reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+            power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>,
+                            <&k3_pds 96 TI_SCI_PD_SHARED>;
+            interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+            #address-cells = <2>;
+            #size-cells = <2>;
+            ranges = <0x00 0x0000 0x00 0x02990000 0x00 0x4000>;
+            ti,ddr-freq0   = <0>;
+            ti,ddr-freq1   = <0>;
+            ti,ddr-freq2   = <0>;
+            ti,ddr-fhs-cnt = <0>;
+            clocks = <&k3_clks 138 0>, <&k3_clks 43 2>;
+            instance = <0>;
+            bootph-pre-ram;
+
+            ddr0: ddr@0 {
+                compatible = "cdns,k3-ddr";
+                reg = <0x00 0x0000 0x00 0x72c>,
+                      <0x00 0x2000 0x00 0x4b0>,
+                      <0x00 0x4000 0x00 0x163c>;
+                reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+                bootph-pre-ram;
+            };
+
+            ddr_pmu0: ddr-pmu@100 {
+                compatible = "ti,k3-ddr-pmu";
+                reg = <0x00 0x100 0x00 0x14>;
+            };
+        };
+    };
-- 
2.34.1

Re: [RFC PATCH 03/22] dt-bindings: memory: ti,j721s2-msmc: Add TI K3 MSMC binding

[Krzysztof Kozlowski]

On 14/07/2026 14:55, MANNURU VENKATESWARLU wrote:
> +required:
> +  - compatible
> +  - '#address-cells'
> +  - '#size-cells'
> +  - ranges
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/soc/ti,sci_pm_domain.h>
> +
> +    msmc0: msmc {
> +        compatible = "ti,j721s2-msmc", "simple-bus";

NAK

> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +        ranges;
> +        intrlv-gran = <0>;
> +        intrlv-size = <0>;
> +        ecc-enable  = <0>;
> +        emif-config = <0>;
> +        emif-active = <0>;

I do not accept downstream code sent to review.

Start doing proper internal reviews. This binding and DTS is absolutely
unacceptable, you just repeat all known mistakes ignoring any guidelines.

Best regards,
Krzysztof

Re: Re: [RFC PATCH 03/22] dt-bindings: memory: ti,j721s2-msmc: Add TI K3 MSMC binding

[MANNURU VENKATESWARLU]

On 15/07/26 10:27, Krzysztof Kozlowski wrote:
> On 14/07/2026 14: 55, MANNURU VENKATESWARLU wrote: > +required: > + - 
> compatible > + - '#address-cells' > + - '#size-cells' > + - ranges > + 
> > +additionalProperties: false > + > +examples: > + - | > + #include
> 
> On 14/07/2026 14:55, MANNURU VENKATESWARLU wrote:
> > +required:
> > +  - compatible
> > +  - '#address-cells'
> > +  - '#size-cells'
> > +  - ranges
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/soc/ti,sci_pm_domain.h>
> > +
> > +    msmc0: msmc {
> > +        compatible = "ti,j721s2-msmc", "simple-bus";
>
> NAK
Understood. The MSMC module has internal interleaving and ECC logic,
so it does not behave as simple-bus. I will drop the "simple-bus" 
fallback property
and create a new platform driver to wake up the inside child nodes.
>
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> > +        ranges;
> > +        intrlv-gran = <0>;
> > +        intrlv-size = <0>;
> > +        ecc-enable  = <0>;
> > +        emif-config = <0>;
> > +        emif-active = <0>;
>
> I do not accept downstream code sent to review.
>
> Start doing proper internal reviews. This binding and DTS is absolutely
> unacceptable, you just repeat all known mistakes ignoring any guidelines.
>
> Best regards,
> Krzysztof
Thank you,
VENKEY

Re: [RFC PATCH 01/22] dt-bindings: memory: cdns,k3-ddr: Add Cadence K3 DDR controller binding

[Krzysztof Kozlowski]

On 14/07/2026 14:55, MANNURU VENKATESWARLU wrote:
> Add device tree binding for the Cadence DDR controller used in TI K3 SoCs.
> 
> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
> Signed-off-by: Gandhar Deshpande <g-deshpande@ti.com>
> Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
> ---
>  .../memory-controllers/ti/cdns,k3-ddr.yaml    | 81 +++++++++++++++++++
>  1 file changed, 81 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml
> 

Where is the rest of 22 patches? I got only these three patches.


A nit, subject: drop second/last, redundant "bindings". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v7.1-rc7/source/Documentation/devicetree/bindings/submitting-patches.rst#L23

> diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml b/Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml
> new file mode 100644
> index 0000000000000..89caeb111627a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml
> @@ -0,0 +1,81 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/memory-controllers/ti/cdns,k3-ddr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Cadence DDR controller for K3 devices
> +
> +maintainers:
> +  - Santhosh Kumar K <s-k6@ti.com>
> +  - Neha Malcom Francis <n-francis@ti.com>
> +
> +properties:
> +  compatible:
> +    const: cdns,k3-ddr

cdns does not make a K3 SoC.

This is confusing. Are you sure you understand which company products
you are working on?


> +
> +  reg:
> +    minItems: 3

Drop.

> +    maxItems: 3
> +    description: |
> +      Address ranges for the different register regions of the DDRSS controller.
> +      - ctl_cfg: Controller configuration registers
> +      - ctl_cfg_pi: PHY Interface configuration registers
> +      - ctl_cfg_phy: PHY configuration registers

Describe items.

> +
> +  reg-names:
> +    items:
> +      - const: ctl_cfg
> +      - const: ctl_cfg_pi
> +      - const: ctl_cfg_phy
> +
> +  bootph-pre-ram: true

Nope

> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +
> +unevaluatedProperties: false

More NO.

Really, can't you make some internal review back there in TI to avoid
sending something which does not resemble upstream code at all?

> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/soc/ti,sci_pm_domain.h>
> +
> +    cbass_main {

NAK

> +      #address-cells = <2>;
> +      #size-cells = <2>;
> +
> +      memorycontroller: memorycontroller@2980000 {


git grep memorycontroller

And it did not made you thinking that name is wrong? I am done with it.


> +        compatible = "ti,j721e-ddrss";

Irrelevant. Which binding are you describing here?

Best regards,
Krzysztof

Re: Re: [RFC PATCH 01/22] dt-bindings: memory: cdns,k3-ddr: Add Cadence K3 DDR controller binding

[MANNURU VENKATESWARLU]

Hi Krzysztof,

Thank you for the review.

On 15/07/26 10:25, Krzysztof Kozlowski wrote:
> On 14/07/2026 14: 55, MANNURU VENKATESWARLU wrote: > Add device tree 
> binding for the Cadence DDR controller used in TI K3 SoCs. > > 
> Signed-off-by: Neha Malcom Francis <n-francis@ ti. com> > 
> Signed-off-by: Gandhar Deshpande <g-deshpande@ ti. com>
> 
> On 14/07/2026 14:55, MANNURU VENKATESWARLU wrote:
> > Add device tree binding for the Cadence DDR controller used in TI K3 SoCs.
> > 
> > Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
> > Signed-off-by: Gandhar Deshpande <g-deshpande@ti.com>
> > Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
> > ---
> >  .../memory-controllers/ti/cdns,k3-ddr.yaml    | 81 +++++++++++++++++++
> >  1 file changed, 81 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml
> > 
>
> Where is the rest of 22 patches? I got only these three patches.
>
Sorry for the threading issue. I ran separate 'git send-email' commands 
to target
specific maintainers for each patch, which accidentally broke the series 
layout.
Will fix this for v2 using a proper single-thread approach.

> A nit, subject: drop second/last, redundant "bindings". The
> "dt-bindings" prefix is already stating that these are bindings.
Noted, will drop "binding" from the subject line.
> See also:
> https://urldefense.com/v3/__https://elixir.bootlin.com/linux/v7.1-rc7/source/Documentation/devicetree/bindings/submitting-patches.rst*L23__;Iw!!G3vK!VufvdFJYWNjYPM5GnqHtPsbj-eGrx0jLrAx_YZJ4Zvxail86PMioiY6qiyoVVJs7LkAg0EUeVQ$
Thank you for the references.
> > diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml b/Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml
> > new file mode 100644
> > index 0000000000000..89caeb111627a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml
> > @@ -0,0 +1,81 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/memory-controllers/ti/cdns,k3-ddr.yaml*__;Iw!!G3vK!VufvdFJYWNjYPM5GnqHtPsbj-eGrx0jLrAx_YZJ4Zvxail86PMioiY6qiyoVVJs7LkDKAFfOoA$
> > +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!G3vK!VufvdFJYWNjYPM5GnqHtPsbj-eGrx0jLrAx_YZJ4Zvxail86PMioiY6qiyoVVJs7LkBLS4PG1w$
> > +
> > +title: Cadence DDR controller for K3 devices
> > +
> > +maintainers:
> > +  - Santhosh Kumar K <s-k6@ti.com>
> > +  - Neha Malcom Francis <n-francis@ti.com>
> > +
> > +properties:
> > +  compatible:
> > +    const: cdns,k3-ddr
>
> cdns does not make a K3 SoC.
Valid point. I will revisit the compatible string.
it likely should not carry the K3 suffix on the Cadence side,
using something like "cdns,ddr" instead.

> This is confusing. Are you sure you understand which company products
> you are working on?
>
>
> > +
> > +  reg:
> > +    minItems: 3
>
> Drop.
Will remove minItems.
> > +    maxItems: 3
> > +    description: |
> > +      Address ranges for the different register regions of the DDRSS controller.
> > +      - ctl_cfg: Controller configuration registers
> > +      - ctl_cfg_pi: PHY Interface configuration registers
> > +      - ctl_cfg_phy: PHY configuration registers
>
> Describe items.
Will describe each reg Item
> > +
> > +  reg-names:
> > +    items:
> > +      - const: ctl_cfg
> > +      - const: ctl_cfg_pi
> > +      - const: ctl_cfg_phy
> > +
> > +  bootph-pre-ram: true
>
> Nope
Agreed. Device Tree bindings must strictly describe the hardware itself,not
software or bootloader execution phases. I will remove this U-Boot specific
property entirely from the binding.
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - reg-names
> > +
> > +unevaluatedProperties: false
>
> More NO.
will replace with additionalProperties: false.
> Really, can't you make some internal review back there in TI to avoid
> sending something which does not resemble upstream code at all?
>
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/soc/ti,sci_pm_domain.h>
> > +
> > +    cbass_main {
>
> NAK
Understood, I will cleanup the example.
>
> > +      #address-cells = <2>;
> > +      #size-cells = <2>;
> > +
> > +      memorycontroller: memorycontroller@2980000 {
>
>
> git grep memorycontroller
>
> And it did not made you thinking that name is wrong? I am done with it.

Correct, my mistake. I will fix the node name to use the generic 
"memory-controller"
format.


>
> > +        compatible = "ti,j721e-ddrss";
>
> Irrelevant. Which binding are you describing here?
The example was Incorrectly focussed on the TI parent wrapper. I will 
trim the example
down to focus strictly on the ddr node.
> Best regards,
> Krzysztof
Thank you,
VENKEY