From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <dave.jiang@intel.com>
Subject: Re: [PATCH v2 1/5] cxl: Remove the CXL_DECODER_MIXED mistake
Date: Thu, 23 Jan 2025 15:49:02 +0000 [thread overview]
Message-ID: <20250123154902.00000c4b@huawei.com> (raw)
In-Reply-To: <173753635601.3849855.5582594127330525596.stgit@dwillia2-xfh.jf.intel.com>
On Wed, 22 Jan 2025 00:59:16 -0800
Dan Williams <dan.j.williams@intel.com> wrote:
> CXL_DECODER_MIXED is a safety mechanism introduced for the case where
> platform firmware has programmed an endpoint decoder that straddles a
> DPA partition boundary. While the kernel is careful to only allocate DPA
> capacity within a single partition there is no guarantee that platform
> firmware, or anything that touched the device before the current kernel,
> gets that right.
>
> However, __cxl_dpa_reserve() will never get to the CXL_DECODER_MIXED
> designation because of the way it tracks partition boundaries. A
> request_resource() that spans ->ram_res and ->pmem_res fails with the
> following signature:
>
> __cxl_dpa_reserve: cxl_port endpoint15: decoder15.0: failed to reserve allocation
>
> CXL_DECODER_MIXED is dead defensive programming after the driver has
> already given up on the device. It has never offered any protection in
> practice, just delete it.
>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
next prev parent reply other threads:[~2025-01-23 15:49 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-22 8:59 [PATCH v2 0/5] cxl: DPA partition metadata is a mess Dan Williams
2025-01-22 8:59 ` [PATCH v2 1/5] cxl: Remove the CXL_DECODER_MIXED mistake Dan Williams
2025-01-22 14:11 ` Ira Weiny
2025-01-23 15:49 ` Jonathan Cameron [this message]
2025-01-23 15:58 ` Alejandro Lucero Palau
2025-01-23 16:03 ` Dave Jiang
2025-01-22 8:59 ` [PATCH v2 2/5] cxl: Introduce to_{ram,pmem}_{res,perf}() helpers Dan Williams
2025-01-22 14:18 ` Ira Weiny
2025-01-23 15:57 ` Jonathan Cameron
2025-01-23 20:01 ` Dan Williams
2025-01-23 16:13 ` Dave Jiang
2025-01-23 16:25 ` Alejandro Lucero Palau
2025-01-23 21:04 ` Dan Williams
2025-01-24 10:15 ` Alejandro Lucero Palau
2025-01-25 0:45 ` Dan Williams
2025-01-22 8:59 ` [PATCH v2 3/5] cxl: Introduce 'struct cxl_dpa_partition' and 'struct cxl_range_info' Dan Williams
2025-01-22 14:53 ` Ira Weiny
2025-01-22 22:24 ` Dan Williams
2025-01-23 3:10 ` Ira Weiny
2025-01-23 16:09 ` Jonathan Cameron
2025-01-23 20:24 ` Dan Williams
2025-01-23 16:57 ` Dave Jiang
2025-01-23 17:00 ` Alejandro Lucero Palau
2025-01-23 22:43 ` Dan Williams
2025-01-23 17:17 ` Alejandro Lucero Palau
2025-01-23 22:48 ` Dan Williams
2025-01-24 10:29 ` Alejandro Lucero Palau
2025-01-22 8:59 ` [PATCH v2 4/5] cxl: Make cxl_dpa_alloc() DPA partition number agnostic Dan Williams
2025-01-22 16:29 ` Ira Weiny
2025-01-22 22:35 ` Dan Williams
2025-01-23 3:14 ` Ira Weiny
2025-01-23 3:28 ` Dan Williams
2025-01-23 16:41 ` Jonathan Cameron
2025-01-23 21:34 ` Dan Williams
2025-01-23 17:21 ` Alejandro Lucero Palau
2025-01-23 20:52 ` Dave Jiang
2025-01-22 8:59 ` [PATCH v2 5/5] cxl: Kill enum cxl_decoder_mode Dan Williams
2025-01-22 17:42 ` Ira Weiny
2025-01-22 22:58 ` Dan Williams
2025-01-23 3:39 ` Ira Weiny
2025-01-23 4:11 ` Dan Williams
2025-01-23 21:30 ` Dave Jiang
2025-01-24 22:22 ` Ira Weiny
2025-01-23 16:51 ` Jonathan Cameron
2025-01-23 21:50 ` Dan Williams
2025-01-23 17:20 ` Alejandro Lucero Palau
2025-01-23 21:29 ` Dave Jiang
2025-01-23 17:23 ` [PATCH v2 0/5] cxl: DPA partition metadata is a mess Alejandro Lucero Palau
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