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From: Dan Williams <dan.j.williams@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, Dave Jiang <dave.jiang@intel.com>,
	"Alejandro Lucero" <alucerop@amd.com>,
	Ira Weiny <ira.weiny@intel.com>
Subject: Re: [PATCH v2 5/5] cxl: Kill enum cxl_decoder_mode
Date: Thu, 23 Jan 2025 13:50:52 -0800	[thread overview]
Message-ID: <6792b9bc1d25c_20fa294cb@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20250123165103.00004379@huawei.com>

Jonathan Cameron wrote:
> On Wed, 22 Jan 2025 00:59:38 -0800
> Dan Williams <dan.j.williams@intel.com> wrote:
> 
> > Now that the operational mode of DPA capacity (ram vs pmem... etc) is
> > tracked in the partition, and no code paths have dependencies on the
> > mode implying the partition index, the ambiguous 'enum cxl_decoder_mode'
> > can be cleaned up, specifically this ambiguity on whether the operation
> > mode implied anything about the partition order.
> > 
> > Endpoint decoders simply reference their assigned partition where the
> > operational mode can be retrieved as partition mode.
> > 
> > With this in place PMEM can now be partition0 which happens today when
> > the RAM capacity size is zero. Dynamic RAM can appear above PMEM when
> > DCD arrives, etc. Code sequences that hard coded the "PMEM after RAM"
> > assumption can now just iterate partitions and consult the partition
> > mode after the fact.
> > 
> > Cc: Dave Jiang <dave.jiang@intel.com>
> > Cc: Alejandro Lucero <alucerop@amd.com>
> > Cc: Ira Weiny <ira.weiny@intel.com>
> > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> A few things inline.
> 
> Jonathan
> 
> > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> > index 591aeb26c9e1..bb478e7b12f6 100644
> > --- a/drivers/cxl/core/hdm.c
> > +++ b/drivers/cxl/core/hdm.c
[..]
> > -	/*
> > -	 * Only allow modes that are supported by the current partition
> > -	 * configuration
> > -	 */
> > -	if (mode == CXL_DECODER_PMEM && !cxl_pmem_size(cxlds)) {
> > -		dev_dbg(dev, "no available pmem capacity\n");
> > -		return -ENXIO;
> > +	part = -1;
> > +	for (int i = 0; i < cxlds->nr_partitions; i++)
> 
> Similar to previous comment can use early loop exit and
> part as the loop iteration variable short code and no magic i
> appears.

Yeah, might as well.

[..]
> > @@ -2728,11 +2733,17 @@ static int poison_by_decoder(struct device *dev, void *arg)
> >  		return rc;
> >  
> >  	cxlmd = cxled_to_memdev(cxled);
> > +	cxlds = cxlmd->cxlds;
> > +	if (cxled->part < 0)
> > +		mode = CXL_PARTMODE_NONE;
> Ah.  Here is our mysterious none.  Maybe add a comment on what
> this means in practice.  Race condition, actual hole, crazy decoder
> someone (e.g bios) setup?

I just fixed it up like this:

@@ -2724,15 +2729,18 @@ static int poison_by_decoder(struct device *dev, void *arg)
                return rc;
 
        cxled = to_cxl_endpoint_decoder(dev);
-       if (!cxled->dpa_res || !resource_size(cxled->dpa_res))
+       if (!cxled->dpa_res)
                return rc;
 
        cxlmd = cxled_to_memdev(cxled);
+       cxlds = cxlmd->cxlds;
+       mode = cxlds->part[cxled->part].mode;
+

...because there is no such thing as a decoder with allocated capacity
but no partition set, and an endpoint decoder will never be zero sized.

I also thought about adding a lockdep_assert_held(&cxl_dpa_rwsem)
because this function is a few calls away from that context, but will
just leave that alone for now.

  reply	other threads:[~2025-01-23 21:50 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-22  8:59 [PATCH v2 0/5] cxl: DPA partition metadata is a mess Dan Williams
2025-01-22  8:59 ` [PATCH v2 1/5] cxl: Remove the CXL_DECODER_MIXED mistake Dan Williams
2025-01-22 14:11   ` Ira Weiny
2025-01-23 15:49   ` Jonathan Cameron
2025-01-23 15:58   ` Alejandro Lucero Palau
2025-01-23 16:03   ` Dave Jiang
2025-01-22  8:59 ` [PATCH v2 2/5] cxl: Introduce to_{ram,pmem}_{res,perf}() helpers Dan Williams
2025-01-22 14:18   ` Ira Weiny
2025-01-23 15:57   ` Jonathan Cameron
2025-01-23 20:01     ` Dan Williams
2025-01-23 16:13   ` Dave Jiang
2025-01-23 16:25   ` Alejandro Lucero Palau
2025-01-23 21:04     ` Dan Williams
2025-01-24 10:15       ` Alejandro Lucero Palau
2025-01-25  0:45         ` Dan Williams
2025-01-22  8:59 ` [PATCH v2 3/5] cxl: Introduce 'struct cxl_dpa_partition' and 'struct cxl_range_info' Dan Williams
2025-01-22 14:53   ` Ira Weiny
2025-01-22 22:24     ` Dan Williams
2025-01-23  3:10       ` Ira Weiny
2025-01-23 16:09   ` Jonathan Cameron
2025-01-23 20:24     ` Dan Williams
2025-01-23 16:57   ` Dave Jiang
2025-01-23 17:00   ` Alejandro Lucero Palau
2025-01-23 22:43     ` Dan Williams
2025-01-23 17:17   ` Alejandro Lucero Palau
2025-01-23 22:48     ` Dan Williams
2025-01-24 10:29       ` Alejandro Lucero Palau
2025-01-22  8:59 ` [PATCH v2 4/5] cxl: Make cxl_dpa_alloc() DPA partition number agnostic Dan Williams
2025-01-22 16:29   ` Ira Weiny
2025-01-22 22:35     ` Dan Williams
2025-01-23  3:14       ` Ira Weiny
2025-01-23  3:28         ` Dan Williams
2025-01-23 16:41   ` Jonathan Cameron
2025-01-23 21:34     ` Dan Williams
2025-01-23 17:21   ` Alejandro Lucero Palau
2025-01-23 20:52   ` Dave Jiang
2025-01-22  8:59 ` [PATCH v2 5/5] cxl: Kill enum cxl_decoder_mode Dan Williams
2025-01-22 17:42   ` Ira Weiny
2025-01-22 22:58     ` Dan Williams
2025-01-23  3:39       ` Ira Weiny
2025-01-23  4:11         ` Dan Williams
2025-01-23 21:30     ` Dave Jiang
2025-01-24 22:22       ` Ira Weiny
2025-01-23 16:51   ` Jonathan Cameron
2025-01-23 21:50     ` Dan Williams [this message]
2025-01-23 17:20   ` Alejandro Lucero Palau
2025-01-23 21:29   ` Dave Jiang
2025-01-23 17:23 ` [PATCH v2 0/5] cxl: DPA partition metadata is a mess Alejandro Lucero Palau

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