Re: [PATCH v2 3/5] cxl: Introduce 'struct cxl_dpa_partition' and 'struct cxl_range_info'

[Dan Williams <dan.j.williams@intel.com>]

Alejandro Lucero Palau wrote:
> <snip>
> >   
> > -static inline struct resource *to_ram_res(struct cxl_dev_state *cxlds)
> > +
> > +/* Static RAM is only expected at partition 0. */
> 
> 
> This may be seen silly but Static Ram as SRAM has connotations which 
> could confuse people.
> 
> Maybe better to use Static partition for RAM.

Without the DCD code upstream even "Static partition" is "confusing",
"what's a non-static partition?". At some point people need to be
trusted to have context and share in the responsibility to resolve their
own confusion.

> It is far more concerning to me though Ira's comment about how can we be 
> sure there is going to be only one RAM or one PMEM partition.

Simply put, we can't.

Use cases evolve in unpredictable ways and folks will show up to address
those new use case when they arrive. I do not lose sleep over it due to
the open ecosystem, and in this case, economics:

- open ecosystem means someone can see us chatting about theoretical
  devices that complicate the implementation and either chime in and say
  "we have such a use case, here are the patches", or "it looks like
   mainline does not care about that particular degree of spec freedom, do
   we really want to go there with our device?".

- on economics: It is hard enough to get developers to care about NUMA
  effects let alone heterogenous memory performance within a single
  device. It would mean building a complicated device with heterogeneous
  media, or mixed memory controllers. The Type-2 series confirmed that
  single range RAM accelerator support is all that is needed for now.

My bar is "as simple as possible, but no simpler" especially when it
comes to user ABI extensions, because ABIs are forever.