From: Ben Cheatham <Benjamin.Cheatham@amd.com>
To: <linux-cxl@vger.kernel.org>
Cc: <benjamin.cheatham@amd.com>
Subject: [PATCH 11/17] cxl/core, port: Update devm_cxl_add_endpoint()
Date: Tue, 11 Nov 2025 15:40:26 -0600 [thread overview]
Message-ID: <20251111214032.8188-12-Benjamin.Cheatham@amd.com> (raw)
In-Reply-To: <20251111214032.8188-1-Benjamin.Cheatham@amd.com>
Update devm_cxl_add_endpoint(), and other functions it calls, to use
struct device instead of struct cxl_memdev to allow adding struct
cxl_cachedev endpoints to the port heirarchy.
Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
drivers/cxl/cache.c | 10 ++++++++++
drivers/cxl/core/port.c | 37 +++++++++++++++++++++++++++++--------
drivers/cxl/cxl.h | 3 ++-
drivers/cxl/mem.c | 2 +-
drivers/cxl/port.c | 13 ++++++++-----
drivers/cxl/private.h | 2 +-
6 files changed, 51 insertions(+), 16 deletions(-)
diff --git a/drivers/cxl/cache.c b/drivers/cxl/cache.c
index 4c9280c0ea72..dcc9816d9b37 100644
--- a/drivers/cxl/cache.c
+++ b/drivers/cxl/cache.c
@@ -81,6 +81,16 @@ static int cxl_cache_probe(struct device *dev)
scoped_guard(device, endpoint_parent) {
if (!cxlds->cxlmd)
cxl_dport_init_ras_reporting(dport, dev);
+
+ if (!endpoint_parent->driver) {
+ dev_err(dev, "CXL port topology %s not enabled\n",
+ dev_name(endpoint_parent));
+ return -ENXIO;
+ }
+
+ rc = devm_cxl_add_endpoint(endpoint_parent, dev, dport);
+ if (rc)
+ return rc;
}
return 0;
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index e79ec29d0bb6..dc001e136782 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -844,10 +844,11 @@ static void cxl_debugfs_create_dport_dir(struct cxl_dport *dport)
&cxl_einj_inject_fops);
}
-static bool is_cxl_ep_device(struct device *dev)
+bool is_cxl_ep_device(struct device *dev)
{
return is_cxl_memdev(dev) || is_cxl_cachedev(dev);
}
+EXPORT_SYMBOL_NS_GPL(is_cxl_ep_device, "CXL");
static int cxl_port_setup_endpoint(struct cxl_port *port)
{
@@ -1424,10 +1425,26 @@ static struct device *endpoint_host(struct cxl_port *endpoint)
return &port->dev;
}
+static void cxl_ep_dev_set_endpoint(struct device *ep_dev, struct cxl_port *ep)
+{
+ if (is_cxl_memdev(ep_dev))
+ to_cxl_memdev(ep_dev)->endpoint = ep;
+ else
+ to_cxl_cachedev(ep_dev)->endpoint = ep;
+}
+
+static struct cxl_port *cxl_ep_dev_get_endpoint(struct device *ep_dev)
+{
+ if (is_cxl_memdev(ep_dev))
+ return to_cxl_memdev(ep_dev)->endpoint;
+ else
+ return to_cxl_cachedev(ep_dev)->endpoint;
+}
+
static void delete_endpoint(void *data)
{
- struct cxl_memdev *cxlmd = data;
- struct cxl_port *endpoint = cxlmd->endpoint;
+ struct device *ep_dev = data;
+ struct cxl_port *endpoint = cxl_ep_dev_get_endpoint(ep_dev);
struct device *host = endpoint_host(endpoint);
scoped_guard(device, host) {
@@ -1436,21 +1453,25 @@ static void delete_endpoint(void *data)
devm_release_action(host, cxl_unlink_uport, endpoint);
devm_release_action(host, unregister_port, endpoint);
}
- cxlmd->endpoint = NULL;
+ cxl_ep_dev_set_endpoint(ep_dev, NULL);
}
put_device(&endpoint->dev);
put_device(host);
}
-int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint)
+int cxl_endpoint_autoremove(struct device *ep_dev, struct cxl_port *endpoint)
{
struct device *host = endpoint_host(endpoint);
- struct device *dev = &cxlmd->dev;
get_device(host);
get_device(&endpoint->dev);
- cxlmd->depth = endpoint->depth;
- return devm_add_action_or_reset(dev, delete_endpoint, cxlmd);
+
+ if (is_cxl_memdev(ep_dev))
+ to_cxl_memdev(ep_dev)->depth = endpoint->depth;
+ else
+ to_cxl_cachedev(ep_dev)->depth = endpoint->depth;
+
+ return devm_add_action_or_reset(ep_dev, delete_endpoint, ep_dev);
}
EXPORT_SYMBOL_NS_GPL(cxl_endpoint_autoremove, "CXL");
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 6c7b8278bec3..e8d66de469d6 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -917,6 +917,7 @@ struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev);
bool is_root_decoder(struct device *dev);
bool is_switch_decoder(struct device *dev);
bool is_endpoint_decoder(struct device *dev);
+bool is_cxl_ep_device(struct device *dev);
struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
unsigned int nr_targets);
struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
@@ -930,7 +931,7 @@ static inline int cxl_root_decoder_autoremove(struct device *host,
{
return cxl_decoder_autoremove(host, &cxlrd->cxlsd.cxld);
}
-int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint);
+int cxl_endpoint_autoremove(struct device *ep_dev, struct cxl_port *endpoint);
/**
* struct cxl_endpoint_dvsec_info - Cached DVSEC info
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index 35706ec1b7e1..336ae091aa07 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -139,7 +139,7 @@ static int cxl_mem_probe(struct device *dev)
return -ENXIO;
}
- rc = devm_cxl_add_endpoint(endpoint_parent, cxlmd, dport);
+ rc = devm_cxl_add_endpoint(endpoint_parent, dev, dport);
if (rc)
return rc;
}
diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index 14319219d23b..ae38b9965a84 100644
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -178,13 +178,16 @@ static struct cxl_driver cxl_port_driver = {
},
};
-int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
+int devm_cxl_add_endpoint(struct device *host, struct device *ep_dev,
struct cxl_dport *parent_dport)
{
struct cxl_port *parent_port = parent_dport->port;
struct cxl_port *endpoint, *iter, *down;
int rc;
+ if (!is_cxl_ep_device(ep_dev))
+ return -EINVAL;
+
/*
* Now that the path to the root is established record all the
* intervening ports in the chain.
@@ -193,22 +196,22 @@ int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
down = iter, iter = to_cxl_port(iter->dev.parent)) {
struct cxl_ep *ep;
- ep = cxl_ep_load(iter, &cxlmd->dev);
+ ep = cxl_ep_load(iter, ep_dev);
ep->next = down;
}
/* Note: endpoint port component registers are derived from @cxlds */
- endpoint = devm_cxl_add_port(host, &cxlmd->dev, CXL_RESOURCE_NONE,
+ endpoint = devm_cxl_add_port(host, ep_dev, CXL_RESOURCE_NONE,
parent_dport);
if (IS_ERR(endpoint))
return PTR_ERR(endpoint);
- rc = cxl_endpoint_autoremove(cxlmd, endpoint);
+ rc = cxl_endpoint_autoremove(ep_dev, endpoint);
if (rc)
return rc;
if (!endpoint->dev.driver) {
- dev_err(&cxlmd->dev, "%s failed probe\n",
+ dev_err(ep_dev, "%s failed probe\n",
dev_name(&endpoint->dev));
return -ENXIO;
}
diff --git a/drivers/cxl/private.h b/drivers/cxl/private.h
index 25e6bce2457f..96832ab594d8 100644
--- a/drivers/cxl/private.h
+++ b/drivers/cxl/private.h
@@ -10,7 +10,7 @@
#ifndef __CXL_PRIVATE_H__
#define __CXL_PRIVATE_H__
-int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
+int devm_cxl_add_endpoint(struct device *host, struct device *ep_dev,
struct cxl_dport *parent_dport);
struct cxl_cachedev *cxl_cachedev_alloc(struct cxl_dev_state *cxlds);
--
2.51.1
next prev parent reply other threads:[~2025-11-11 21:43 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-11 21:40 [RFC v2 PATCH 00/17] Initial CXL.cache device support Ben Cheatham
2025-11-11 21:40 ` [PATCH 01/17] cxl/port: Arrange for always synchronous endpoint attach Ben Cheatham
2025-11-17 15:56 ` Jonathan Cameron
2025-11-11 21:40 ` [PATCH 02/17] cxl: Move struct cxl_dev_state definition Ben Cheatham
2025-11-11 21:40 ` [PATCH 03/17] cxl/core: Add function for getting CXL cache info Ben Cheatham
2025-12-17 16:09 ` Jonathan Cameron
2025-12-17 18:01 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 04/17] cxl/core: Add CXL.cache device struct Ben Cheatham
2025-12-17 16:14 ` Jonathan Cameron
2025-11-11 21:40 ` [PATCH 05/17] cxl/cache: Add cxl_cache driver Ben Cheatham
2025-12-17 16:17 ` Jonathan Cameron
2025-12-17 18:01 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 06/17] cxl: Replace cxl_mem_find_port() with cxl_dev_find_port() Ben Cheatham
2025-12-17 16:18 ` Jonathan Cameron
2025-12-17 18:01 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 07/17] cxl: Change cxl_ep_load() to use struct device * parameter Ben Cheatham
2025-11-11 21:40 ` [PATCH 08/17] cxl/core: Update devm_cxl_enumerate_ports() Ben Cheatham
2025-11-11 21:40 ` [PATCH 09/17] cxl/port: Split endpoint port probe on device type Ben Cheatham
2025-11-11 21:40 ` [PATCH 10/17] cxl/cache, mem: Prevent RAS register mapping race Ben Cheatham
2025-12-17 16:23 ` Jonathan Cameron
2025-12-17 18:02 ` Cheatham, Benjamin
2025-11-11 21:40 ` Ben Cheatham [this message]
2025-11-11 21:40 ` [PATCH 12/17] cxl/core: Add CXL snoop filter setup and allocation Ben Cheatham
2025-12-17 16:35 ` Jonathan Cameron
2025-12-17 18:02 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 13/17] cxl/core: Add cache id verification Ben Cheatham
2025-12-22 13:47 ` Jonathan Cameron
2026-01-05 21:16 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 14/17] cxl/port: Add cache id programming Ben Cheatham
2025-11-11 21:40 ` [PATCH 15/17] cxl/port: Bypass cache id for singleton cache devices Ben Cheatham
2025-11-11 21:40 ` [PATCH 16/17] cxl/core: Add cache device attributes Ben Cheatham
2025-12-17 16:12 ` Jonathan Cameron
2025-12-17 18:02 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 17/17] cxl/core: Add cache device cache management attributes Ben Cheatham
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