From: "Cheatham, Benjamin" <benjamin.cheatham@amd.com>
To: Jonathan Cameron <jonathan.cameron@huawei.com>
Cc: <linux-cxl@vger.kernel.org>
Subject: Re: [PATCH 16/17] cxl/core: Add cache device attributes
Date: Wed, 17 Dec 2025 12:02:45 -0600 [thread overview]
Message-ID: <56ccb77b-5fcc-499a-b4e2-aa3979508c6b@amd.com> (raw)
In-Reply-To: <20251217161201.0000067f@huawei.com>
On 12/17/2025 10:12 AM, Jonathan Cameron wrote:
> On Tue, 11 Nov 2025 15:40:31 -0600
> Ben Cheatham <Benjamin.Cheatham@amd.com> wrote:
>
>> Add sysfs attributes for getting the numa node, CXL cache unit, and
>> CXL cache size for a cachedev.
>>
>> Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
> Documentation is king for ABI.
>
> Documentation/ABI/testing/sysfs-bus-cxl probably.
>
>> ---
>> drivers/cxl/core/cachedev.c | 85 +++++++++++++++++++++++++++++++++++++
>> 1 file changed, 85 insertions(+)
>>
>> diff --git a/drivers/cxl/core/cachedev.c b/drivers/cxl/core/cachedev.c
>> index 0b7430450b4e..d8bf18ec0579 100644
>> --- a/drivers/cxl/core/cachedev.c
>> +++ b/drivers/cxl/core/cachedev.c
>
>> +static ssize_t cache_size_show(struct device *dev, struct device_attribute *attr,
>> + char *buf)
>> +{
>> + struct cxl_cachedev *cxlcd = to_cxl_cachedev(dev);
>> + struct cxl_dev_state *cxlds = cxlcd->cxlds;
>> + struct cxl_cache_state cstate = cxlds->cstate;
>
> Why copy it? &cxlds->cstate;
> If there is a reason to copy add a comment.
It's a typo, it's supposed to be a pointer. I'll fix for v1.
>
>> +
>> + return sysfs_emit(buf, "%llu\n", cstate.size);
>
>> +}
>> +static DEVICE_ATTR_RO(cache_size);
>> +
>> +static ssize_t cache_unit_show(struct device *dev, struct device_attribute *attr,
>> + char *buf)
>> +{
>> + struct cxl_cachedev *cxlcd = to_cxl_cachedev(dev);
>> + struct cxl_dev_state *cxlds = cxlcd->cxlds;
>> + struct cxl_cache_state cstate = cxlds->cstate;
>> + char unit_buf[32];
>> + int rc;
>> +
>> + rc = string_get_size(cstate.size, 1, STRING_UNITS_2, unit_buf,
>> + sizeof(unit_buf) - 1);
>
> This reflects back to comment in earlier patch. Do we care about unit
> other than as a means to establish the size? I'm not sure they have
> meaning beyond allowing that register to express a larger range than
> if we did it on 64K always.
>
I'm not sure. I don't think it matters functionally, but it would probably be useful
for debug of cache devices. I don't think that is a big enough deal to warrant a
sysfs attribute though so I'll remove it (and the cxl_cache_state member). It can
always get added back later as a debugfs attribute when someone wants it.
Thanks,
Ben
>> + if (rc <= 0)
>> + return -ENXIO;
>> +
>> + return sysfs_emit(buf, "%s\n", unit_buf);
>> +}
>> +static DEVICE_ATTR_RO(cache_unit);
next prev parent reply other threads:[~2025-12-17 18:25 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-11 21:40 [RFC v2 PATCH 00/17] Initial CXL.cache device support Ben Cheatham
2025-11-11 21:40 ` [PATCH 01/17] cxl/port: Arrange for always synchronous endpoint attach Ben Cheatham
2025-11-17 15:56 ` Jonathan Cameron
2025-11-11 21:40 ` [PATCH 02/17] cxl: Move struct cxl_dev_state definition Ben Cheatham
2025-11-11 21:40 ` [PATCH 03/17] cxl/core: Add function for getting CXL cache info Ben Cheatham
2025-12-17 16:09 ` Jonathan Cameron
2025-12-17 18:01 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 04/17] cxl/core: Add CXL.cache device struct Ben Cheatham
2025-12-17 16:14 ` Jonathan Cameron
2025-11-11 21:40 ` [PATCH 05/17] cxl/cache: Add cxl_cache driver Ben Cheatham
2025-12-17 16:17 ` Jonathan Cameron
2025-12-17 18:01 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 06/17] cxl: Replace cxl_mem_find_port() with cxl_dev_find_port() Ben Cheatham
2025-12-17 16:18 ` Jonathan Cameron
2025-12-17 18:01 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 07/17] cxl: Change cxl_ep_load() to use struct device * parameter Ben Cheatham
2025-11-11 21:40 ` [PATCH 08/17] cxl/core: Update devm_cxl_enumerate_ports() Ben Cheatham
2025-11-11 21:40 ` [PATCH 09/17] cxl/port: Split endpoint port probe on device type Ben Cheatham
2025-11-11 21:40 ` [PATCH 10/17] cxl/cache, mem: Prevent RAS register mapping race Ben Cheatham
2025-12-17 16:23 ` Jonathan Cameron
2025-12-17 18:02 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 11/17] cxl/core, port: Update devm_cxl_add_endpoint() Ben Cheatham
2025-11-11 21:40 ` [PATCH 12/17] cxl/core: Add CXL snoop filter setup and allocation Ben Cheatham
2025-12-17 16:35 ` Jonathan Cameron
2025-12-17 18:02 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 13/17] cxl/core: Add cache id verification Ben Cheatham
2025-12-22 13:47 ` Jonathan Cameron
2026-01-05 21:16 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 14/17] cxl/port: Add cache id programming Ben Cheatham
2025-11-11 21:40 ` [PATCH 15/17] cxl/port: Bypass cache id for singleton cache devices Ben Cheatham
2025-11-11 21:40 ` [PATCH 16/17] cxl/core: Add cache device attributes Ben Cheatham
2025-12-17 16:12 ` Jonathan Cameron
2025-12-17 18:02 ` Cheatham, Benjamin [this message]
2025-11-11 21:40 ` [PATCH 17/17] cxl/core: Add cache device cache management attributes Ben Cheatham
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