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From: Jonathan Cameron <jonathan.cameron@huawei.com>
To: Ben Cheatham <Benjamin.Cheatham@amd.com>
Cc: <linux-cxl@vger.kernel.org>
Subject: Re: [PATCH 10/17] cxl/cache, mem: Prevent RAS register mapping race
Date: Wed, 17 Dec 2025 16:23:57 +0000	[thread overview]
Message-ID: <20251217162357.0000209c@huawei.com> (raw)
In-Reply-To: <20251111214032.8188-11-Benjamin.Cheatham@amd.com>

On Tue, 11 Nov 2025 15:40:25 -0600
Ben Cheatham <Benjamin.Cheatham@amd.com> wrote:

> CXL type 2 devices will register both a struct cxl_memdev and struct
> cxl_cachedev, both of which will attempt to map the parent dport's RAS
> registers in cxl_dport_init_ras_reporting(). While the immediate call
> fails gracefully, an error is emitted in the dmesg log by
> cxl_map_component_regs().
> 
> Avoid this error message by checking if the RAS registers are already
> mapped while the port's device lock is held.

This seems misleading. The check seems to be one whether
cdlds->cxlmd or cxlcd have already been configured rather than
just the RAS registers.

> 
> Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
> ---
>  drivers/cxl/cache.c | 11 +++++++++++
>  drivers/cxl/mem.c   |  5 +++--
>  2 files changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/cxl/cache.c b/drivers/cxl/cache.c
> index 630452d53acc..4c9280c0ea72 100644
> --- a/drivers/cxl/cache.c
> +++ b/drivers/cxl/cache.c
> @@ -58,6 +58,7 @@ static int cxl_cache_probe(struct device *dev)
>  {
>  	struct cxl_cachedev *cxlcd = to_cxl_cachedev(dev);
>  	struct cxl_dev_state *cxlds = cxlcd->cxlds;
> +	struct device *endpoint_parent;
>  	struct cxl_dport *dport;
>  	int rc;
>  
> @@ -72,6 +73,16 @@ static int cxl_cache_probe(struct device *dev)
>  		return -ENXIO;
>  	}
>  
> +	if (dport->rch)
> +		endpoint_parent = parent_port->uport_dev;
> +	else
> +		endpoint_parent = &parent_port->dev;
> +
> +	scoped_guard(device, endpoint_parent) {
> +		if (!cxlds->cxlmd)
> +			cxl_dport_init_ras_reporting(dport, dev);
> +	}
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> index 3b230f8c5925..35706ec1b7e1 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/mem.c
> @@ -129,9 +129,10 @@ static int cxl_mem_probe(struct device *dev)
>  	else
>  		endpoint_parent = &parent_port->dev;
>  
> -	cxl_dport_init_ras_reporting(dport, dev);
> -
>  	scoped_guard(device, endpoint_parent) {
> +		if (!cxlds->cxlcd)
> +			cxl_dport_init_ras_reporting(dport, dev);
> +
>  		if (!endpoint_parent->driver) {
>  			dev_err(dev, "CXL port topology %s not enabled\n",
>  				dev_name(endpoint_parent));


  reply	other threads:[~2025-12-17 16:24 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-11 21:40 [RFC v2 PATCH 00/17] Initial CXL.cache device support Ben Cheatham
2025-11-11 21:40 ` [PATCH 01/17] cxl/port: Arrange for always synchronous endpoint attach Ben Cheatham
2025-11-17 15:56   ` Jonathan Cameron
2025-11-11 21:40 ` [PATCH 02/17] cxl: Move struct cxl_dev_state definition Ben Cheatham
2025-11-11 21:40 ` [PATCH 03/17] cxl/core: Add function for getting CXL cache info Ben Cheatham
2025-12-17 16:09   ` Jonathan Cameron
2025-12-17 18:01     ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 04/17] cxl/core: Add CXL.cache device struct Ben Cheatham
2025-12-17 16:14   ` Jonathan Cameron
2025-11-11 21:40 ` [PATCH 05/17] cxl/cache: Add cxl_cache driver Ben Cheatham
2025-12-17 16:17   ` Jonathan Cameron
2025-12-17 18:01     ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 06/17] cxl: Replace cxl_mem_find_port() with cxl_dev_find_port() Ben Cheatham
2025-12-17 16:18   ` Jonathan Cameron
2025-12-17 18:01     ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 07/17] cxl: Change cxl_ep_load() to use struct device * parameter Ben Cheatham
2025-11-11 21:40 ` [PATCH 08/17] cxl/core: Update devm_cxl_enumerate_ports() Ben Cheatham
2025-11-11 21:40 ` [PATCH 09/17] cxl/port: Split endpoint port probe on device type Ben Cheatham
2025-11-11 21:40 ` [PATCH 10/17] cxl/cache, mem: Prevent RAS register mapping race Ben Cheatham
2025-12-17 16:23   ` Jonathan Cameron [this message]
2025-12-17 18:02     ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 11/17] cxl/core, port: Update devm_cxl_add_endpoint() Ben Cheatham
2025-11-11 21:40 ` [PATCH 12/17] cxl/core: Add CXL snoop filter setup and allocation Ben Cheatham
2025-12-17 16:35   ` Jonathan Cameron
2025-12-17 18:02     ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 13/17] cxl/core: Add cache id verification Ben Cheatham
2025-12-22 13:47   ` Jonathan Cameron
2026-01-05 21:16     ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 14/17] cxl/port: Add cache id programming Ben Cheatham
2025-11-11 21:40 ` [PATCH 15/17] cxl/port: Bypass cache id for singleton cache devices Ben Cheatham
2025-11-11 21:40 ` [PATCH 16/17] cxl/core: Add cache device attributes Ben Cheatham
2025-12-17 16:12   ` Jonathan Cameron
2025-12-17 18:02     ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 17/17] cxl/core: Add cache device cache management attributes Ben Cheatham

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