[PATCH 15/17] cxl/port: Bypass cache id for singleton cache devices

[Ben Cheatham <Benjamin.Cheatham@amd.com>]

The CXL cache id capability is required to have multiple CXL cache
devices in the same virtual hierarchy (VH), but is not required if there
is only a single cache device in the VH. If the host does not support
the cache id capability and there is only a single device in the VH,
skip allocation and programming of the capability.

Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 drivers/cxl/core/port.c |  1 +
 drivers/cxl/port.c      | 34 ++++++++++++++++++++++++++++++++--
 2 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index e6e25a201ff9..3d9da6c3f672 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -617,6 +617,7 @@ struct cxl_port *parent_port_of(struct cxl_port *port)
 		return NULL;
 	return port->parent_dport->port;
 }
+EXPORT_SYMBOL_NS_GPL(parent_port_of, "CXL");
 
 static void unregister_port(void *_port)
 {
diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index 4cecb731ec5b..68b6d9e34706 100644
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -98,6 +98,28 @@ static int cxl_mem_endpoint_port_probe(struct cxl_port *port)
 	return 0;
 }
 
+static bool cxl_endpoint_is_only_cachedev(struct cxl_port *endpoint)
+{
+	unsigned long index;
+	struct cxl_ep *ep;
+	int cnt;
+
+	for (struct cxl_port *port = endpoint;
+	     !is_cxl_root(parent_port_of(port)); port = parent_port_of(port)) {
+		cnt = 0;
+
+		xa_for_each(&port->endpoints, index, ep) {
+			if (is_cxl_cachedev(ep->ep))
+				cnt++;
+
+			if (cnt > 1)
+				return false;
+		}
+	}
+
+	return true;
+}
+
 static void free_cache_id(void *data)
 {
 	struct cxl_cachedev *cxlcd = data;
@@ -113,8 +135,16 @@ static int cxl_cache_endpoint_port_probe(struct cxl_port *port)
 	int rc, orig, id;
 
 	rc = cxl_endpoint_map_cache_id_regs(port);
-	if (rc)
-		return rc;
+	if (rc) {
+		/*
+		 * It's fine to not have cache id capabilities if this cachedev
+		 * is the only one in its VH
+		 */
+		if (cxl_endpoint_is_only_cachedev(port))
+			return 0;
+
+		return -EBUSY;
+	}
 
 	guard(mutex)(&cache_id_lock);
 	rc = cxl_endpoint_get_cache_id(port, &orig);
-- 
2.51.1