From: Jonathan Cameron <jonathan.cameron@huawei.com>
To: Ben Cheatham <Benjamin.Cheatham@amd.com>
Cc: <linux-cxl@vger.kernel.org>
Subject: Re: [PATCH 16/17] cxl/core: Add cache device attributes
Date: Wed, 17 Dec 2025 16:12:01 +0000 [thread overview]
Message-ID: <20251217161201.0000067f@huawei.com> (raw)
In-Reply-To: <20251111214032.8188-17-Benjamin.Cheatham@amd.com>
On Tue, 11 Nov 2025 15:40:31 -0600
Ben Cheatham <Benjamin.Cheatham@amd.com> wrote:
> Add sysfs attributes for getting the numa node, CXL cache unit, and
> CXL cache size for a cachedev.
>
> Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
Documentation is king for ABI.
Documentation/ABI/testing/sysfs-bus-cxl probably.
> ---
> drivers/cxl/core/cachedev.c | 85 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 85 insertions(+)
>
> diff --git a/drivers/cxl/core/cachedev.c b/drivers/cxl/core/cachedev.c
> index 0b7430450b4e..d8bf18ec0579 100644
> --- a/drivers/cxl/core/cachedev.c
> +++ b/drivers/cxl/core/cachedev.c
> +static ssize_t cache_size_show(struct device *dev, struct device_attribute *attr,
> + char *buf)
> +{
> + struct cxl_cachedev *cxlcd = to_cxl_cachedev(dev);
> + struct cxl_dev_state *cxlds = cxlcd->cxlds;
> + struct cxl_cache_state cstate = cxlds->cstate;
Why copy it? &cxlds->cstate;
If there is a reason to copy add a comment.
> +
> + return sysfs_emit(buf, "%llu\n", cstate.size);
> +}
> +static DEVICE_ATTR_RO(cache_size);
> +
> +static ssize_t cache_unit_show(struct device *dev, struct device_attribute *attr,
> + char *buf)
> +{
> + struct cxl_cachedev *cxlcd = to_cxl_cachedev(dev);
> + struct cxl_dev_state *cxlds = cxlcd->cxlds;
> + struct cxl_cache_state cstate = cxlds->cstate;
> + char unit_buf[32];
> + int rc;
> +
> + rc = string_get_size(cstate.size, 1, STRING_UNITS_2, unit_buf,
> + sizeof(unit_buf) - 1);
This reflects back to comment in earlier patch. Do we care about unit
other than as a means to establish the size? I'm not sure they have
meaning beyond allowing that register to express a larger range than
if we did it on 64K always.
> + if (rc <= 0)
> + return -ENXIO;
> +
> + return sysfs_emit(buf, "%s\n", unit_buf);
> +}
> +static DEVICE_ATTR_RO(cache_unit);
next prev parent reply other threads:[~2025-12-17 16:12 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-11 21:40 [RFC v2 PATCH 00/17] Initial CXL.cache device support Ben Cheatham
2025-11-11 21:40 ` [PATCH 01/17] cxl/port: Arrange for always synchronous endpoint attach Ben Cheatham
2025-11-17 15:56 ` Jonathan Cameron
2025-11-11 21:40 ` [PATCH 02/17] cxl: Move struct cxl_dev_state definition Ben Cheatham
2025-11-11 21:40 ` [PATCH 03/17] cxl/core: Add function for getting CXL cache info Ben Cheatham
2025-12-17 16:09 ` Jonathan Cameron
2025-12-17 18:01 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 04/17] cxl/core: Add CXL.cache device struct Ben Cheatham
2025-12-17 16:14 ` Jonathan Cameron
2025-11-11 21:40 ` [PATCH 05/17] cxl/cache: Add cxl_cache driver Ben Cheatham
2025-12-17 16:17 ` Jonathan Cameron
2025-12-17 18:01 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 06/17] cxl: Replace cxl_mem_find_port() with cxl_dev_find_port() Ben Cheatham
2025-12-17 16:18 ` Jonathan Cameron
2025-12-17 18:01 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 07/17] cxl: Change cxl_ep_load() to use struct device * parameter Ben Cheatham
2025-11-11 21:40 ` [PATCH 08/17] cxl/core: Update devm_cxl_enumerate_ports() Ben Cheatham
2025-11-11 21:40 ` [PATCH 09/17] cxl/port: Split endpoint port probe on device type Ben Cheatham
2025-11-11 21:40 ` [PATCH 10/17] cxl/cache, mem: Prevent RAS register mapping race Ben Cheatham
2025-12-17 16:23 ` Jonathan Cameron
2025-12-17 18:02 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 11/17] cxl/core, port: Update devm_cxl_add_endpoint() Ben Cheatham
2025-11-11 21:40 ` [PATCH 12/17] cxl/core: Add CXL snoop filter setup and allocation Ben Cheatham
2025-12-17 16:35 ` Jonathan Cameron
2025-12-17 18:02 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 13/17] cxl/core: Add cache id verification Ben Cheatham
2025-12-22 13:47 ` Jonathan Cameron
2026-01-05 21:16 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 14/17] cxl/port: Add cache id programming Ben Cheatham
2025-11-11 21:40 ` [PATCH 15/17] cxl/port: Bypass cache id for singleton cache devices Ben Cheatham
2025-11-11 21:40 ` [PATCH 16/17] cxl/core: Add cache device attributes Ben Cheatham
2025-12-17 16:12 ` Jonathan Cameron [this message]
2025-12-17 18:02 ` Cheatham, Benjamin
2025-11-11 21:40 ` [PATCH 17/17] cxl/core: Add cache device cache management attributes Ben Cheatham
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20251217161201.0000067f@huawei.com \
--to=jonathan.cameron@huawei.com \
--cc=Benjamin.Cheatham@amd.com \
--cc=linux-cxl@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox