* [PATCH v1 01/20] dt-bindings: pinctrl: Add starfive,jhb100-sys0-pinctrl
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-28 10:34 ` Linus Walleij
2026-04-24 11:13 ` [PATCH v1 02/20] pinctrl: starfive: Add StarFive JHB100 sys0 controller driver Changhuang Liang
` (19 subsequent siblings)
20 siblings, 1 reply; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC System-0(sys0) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../pinctrl/starfive,jhb100-sys0-pinctrl.yaml | 155 ++++++++++++++++++
1 file changed, 155 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml
new file mode 100644
index 000000000000..21be5717cb74
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml
@@ -0,0 +1,155 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys0-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 System-0 Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "sys0" pinctrl domain.
+
+ The "sys0" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the SYS0 Pin Controller, there are 4 multi-function GPIO_PADs. Each of them can be multiplexed
+ to different hardware blocks through function selection and each iopad has a maximum of up to 2
+ functions - 0 and 1. Function 0 is the default function which is generally the GPIO function
+ (or occasionally, it can be a peripheral signal). Function 1 is the alternate function or
+ peripheral signal that can be routed to the iopad. The function selection is carried out by
+ writing the function number to the iopad function select register.
+ Each iopad is configurable with parameters such as input-enable, internal pull-up/pull-down bias,
+ drive strength, schmitt trigger, slew rate, and debounce width.
+
+maintainers:
+ - Alex Soo <yuklin.soo@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-sys0-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ gpio-line-names: true
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate and drive strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ unevaluatedProperties: false
+
+ properties:
+ pinmux:
+ description: |
+ The list of GPIOs and their function select.
+ The PINMUX macros are used to configure the
+ function selection.
+
+ bias-disable: true
+
+ bias-pull-up:
+ type: boolean
+
+ bias-pull-down:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-enable: true
+
+ input-disable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow (half frequency)
+ 1: fast
+
+ starfive,debounce-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ description:
+ Debounce width 0 = Disabled, Others = 80ns*N stages
+
+required:
+ - compatible
+ - reg
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_sys0: pinctrl@13080000 {
+ compatible = "starfive,jhb100-sys0-pinctrl";
+ reg = <0x0 0x13080000 0x0 0x800>;
+ resets = <&sys0crg 2>;
+ interrupts = <56>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_sys0 0 0 4>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH v1 01/20] dt-bindings: pinctrl: Add starfive,jhb100-sys0-pinctrl
2026-04-24 11:13 ` [PATCH v1 01/20] dt-bindings: pinctrl: Add starfive,jhb100-sys0-pinctrl Changhuang Liang
@ 2026-04-28 10:34 ` Linus Walleij
0 siblings, 0 replies; 34+ messages in thread
From: Linus Walleij @ 2026-04-28 10:34 UTC (permalink / raw)
To: Changhuang Liang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski, linux-gpio,
linux-kernel, devicetree, linux-riscv, Lianfeng Ouyang
Hi Changhuang,
thanks for your patch!
On Fri, Apr 24, 2026 at 1:13 PM Changhuang Liang
<changhuang.liang@starfivetech.com> wrote:
> Add pinctrl bindings for StarFive JHB100 SoC System-0(sys0) pinctrl
> controller.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
(...)
> + properties:
> + pinmux:
> + description: |
> + The list of GPIOs and their function select.
> + The PINMUX macros are used to configure the
> + function selection.
> +
> + bias-disable: true
> +
> + bias-pull-up:
> + type: boolean
> +
> + bias-pull-down:
> + type: boolean
> +
> + drive-strength:
> + enum: [ 2, 4, 8, 12 ]
> +
> + drive-strength-microamp:
> + enum: [ 2000, 4000, 8000, 12000 ]
> +
> + input-enable: true
> +
> + input-disable: true
> +
> + input-schmitt-enable: true
> +
> + input-schmitt-disable: true
> +
> + slew-rate:
> + enum: [ 0, 1 ]
> + default: 0
> + description: |
> + 0: slow (half frequency)
> + 1: fast
> +
> + starfive,debounce-width:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0
> + description:
> + Debounce width 0 = Disabled, Others = 80ns*N stages
The argument to the existing
input-debounce is expressed in microseconds. Just recalculate
that value to your "width"? If you need more granularity add a
generic property input-debound-nanoseconds = <...>;
The code you submitted contains these undocumented properties,
copied from the driver review:
> +static const struct pinconf_generic_params jhb100_custom_bindings[] = {
> + { "starfive,gmac-vsel", STARFIVE_PIN_CONFIG_GMAC_VSEL, 0 },
Can't you use the existing "power-source" instead? It's fine if it's only
applicable to a few pins. This is overly specific.
> + { "starfive,drive-i2c-fast-mode", STARFIVE_PIN_DRIVE_I2C_FAST_MODE, 0 },
> + { "starfive,drive-i2c-fast-mode-plus", STARFIVE_PIN_DRIVE_I2C_FAST_MODE_PLUS, 0 },
It's not special that things are for i2c. Use the generic
slew-rate for these two, it describes how fast something is.
> + { "starfive,i2c-open-drain-pull-up-ohm", STARFIVE_PIN_OPEN_DRAIN_PULLUP_SELECT, 0 },
Use the existing drive-open-drain; with the existing bias-pull-up = <ohms>;
two properties. No need to be fancy and create a new property for this.
> + { "starfive,vga-rte", STARFIVE_PIN_VGA_RTE_SELECT, 0 },
No idea what this is...
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v1 02/20] pinctrl: starfive: Add StarFive JHB100 sys0 controller driver
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
2026-04-24 11:13 ` [PATCH v1 01/20] dt-bindings: pinctrl: Add starfive,jhb100-sys0-pinctrl Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-28 10:29 ` Linus Walleij
2026-04-24 11:13 ` [PATCH v1 03/20] dt-bindings: pinctrl: Add starfive,jhb100-sys0h-pinctrl Changhuang Liang
` (18 subsequent siblings)
20 siblings, 1 reply; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC System-0(sys0) pinctrl
controller.
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
MAINTAINERS | 8 +
drivers/pinctrl/starfive/Kconfig | 21 +
drivers/pinctrl/starfive/Makefile | 3 +
.../starfive/pinctrl-starfive-jhb100-sys0.c | 111 +
.../starfive/pinctrl-starfive-jhb100.c | 1821 +++++++++++++++++
.../starfive/pinctrl-starfive-jhb100.h | 191 ++
6 files changed, 2155 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100.c
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 4ddf8ba2e60d..b3ad0dee7307 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25319,6 +25319,14 @@ L: linux-riscv@lists.infradead.org
S: Maintained
F: arch/riscv/boot/dts/starfive/jhb100*
+STARFIVE JHB100 PINCTRL DRIVERS
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
+M: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
+L: linux-gpio@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/pinctrl/starfive,jhb1*.yaml
+F: drivers/pinctrl/starfive/pinctrl-starfive-jhb1*
+
STARFIVE JHB100 RESET CONTROLLER DRIVERS
M: Changhuang Liang <changhuang.liang@starfivetech.com>
S: Maintained
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index 8192ac2087fc..dc53070ee2c8 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -49,3 +49,24 @@ config PINCTRL_STARFIVE_JH7110_AON
This also provides an interface to the GPIO pins not used by other
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+
+config PINCTRL_STARFIVE_JHB100
+ bool
+ select GENERIC_PINCONF
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select GPIOLIB
+ select GPIOLIB_IRQCHIP
+ select OF_GPIO
+
+config PINCTRL_STARFIVE_JHB100_SYS0
+ tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ depends on OF
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support system-0 pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index ee0d32d085cb..c0d368f413bc 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -5,3 +5,6 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7100) += pinctrl-starfive-jh7100.o
obj-$(CONFIG_PINCTRL_STARFIVE_JH7110) += pinctrl-starfive-jh7110.o
obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_SYS) += pinctrl-starfive-jh7110-sys.o
obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o
+
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c
new file mode 100644
index 000000000000..1ee3e9a617da
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC System-0 domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+static const struct jhb100_pin_layout_desc jhb100_sys0_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 3, .name = "gpio", .gpio_func_sel = 0, },
+ { .pin_start = 3, .pin_cnt = 1, .name = "bmcpcierp_pe2rst_out", .gpio_func_sel = 1, },
+ { .pin_start = 4, .pin_cnt = 1, .name = "testen", .gpio_func_sel = -1, },
+ { .pin_start = 5, .pin_cnt = 1, .name = "syspok_in", .gpio_func_sel = -1, },
+ { .pin_start = 6, .pin_cnt = 1, .name = "sysrstn_in", .gpio_func_sel = -1, },
+ { .pin_start = 7, .pin_cnt = 1, .name = "perstn0_in", .gpio_func_sel = -1, },
+ { .pin_start = 8, .pin_cnt = 1, .name = "perstn1_in", .gpio_func_sel = -1, },
+ { .pin_start = 9, .pin_cnt = 1, .name = "aprstn_out", .gpio_func_sel = -1, },
+ { .pin_start = 10, .pin_cnt = 1, .name = "pcierp_wake", .gpio_func_sel = -1, },
+ { 0xff },
+};
+
+static struct config_reg_layout_desc jhb100_sys0_pinctrl_crl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 4,
+ .drive_strength_2bit = { .shift = 0, .width = 2 },
+ .input_enable = { .shift = 2, .width = 1 },
+ .pull_down = { .shift = 3, .width = 1 },
+ .pull_up = { .shift = 4, .width = 1 },
+ .slew_rate = { .shift = 5, .width = 1 },
+ .schmitt_trigger_select = { .shift = 6, .width = 1 },
+ .reserved = { .shift = 7, .width = 8 },
+ .debounce_width = { .shift = 15, .width = 17 },
+ },
+ {
+ .pin_start = 4,
+ .pin_cnt = 5,
+ .schmitt_trigger_select = { .shift = 0, .width = 1 },
+ .reserved = { .shift = 1, .width = 31 },
+ },
+ {
+ .pin_start = 9,
+ .pin_cnt = 1,
+ .drive_strength_2bit = { .shift = 0, .width = 2 },
+ .slew_rate = { .shift = 2, .width = 1 },
+ .reserved = { .shift = 3, .width = 29 },
+ },
+ {
+ .pin_start = 10,
+ .pin_cnt = 1,
+ .drive_strength_2bit = { .shift = 0, .width = 2 },
+ .input_enable = { .shift = 2, .width = 1 },
+ .pull_down = { .shift = 3, .width = 1 },
+ .pull_up = { .shift = 4, .width = 1 },
+ .slew_rate = { .shift = 5, .width = 1 },
+ .schmitt_trigger_select = { .shift = 6, .width = 1 },
+ .reserved = { .shift = 7, .width = 25 },
+ },
+ { 0xff },
+};
+
+struct starfive_pinctrl_regs jhb100_sys0_pinctrl_regs = {
+ .config = { .reg = 0x0c, .width_per_pin = 1 },
+ .output = { .reg = 0x38, .width_per_pin = 1 },
+ .output_en = { .reg = 0x3c, .width_per_pin = 1 },
+ .gpio_status = { .reg = 0x40, .width_per_pin = 1 },
+ .func_sel = { .reg = 0x44, .width_per_pin = 2 },
+ .irq_en = { .reg = 0x48, .width_per_pin = 1 },
+ .irq_status = { .reg = 0x4c, .width_per_pin = 1 },
+ .irq_clr = { .reg = 0x50, .width_per_pin = 1 },
+ .irq_trigger = { .reg = 0x54, .width_per_pin = 1 },
+ .irq_level = { .reg = 0x58, .width_per_pin = 1 },
+ .irq_both_edge = { .reg = 0x5c, .width_per_pin = 1 },
+ .irq_edge = { .reg = 0x60, .width_per_pin = 1 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_sys0_pinctrl_info = {
+ .name = "jhb100-sys0",
+ .gc_base = -1,
+ .pl_desc = jhb100_sys0_pl_desc,
+ .crl_desc = jhb100_sys0_pinctrl_crl_desc,
+ .regs = &jhb100_sys0_pinctrl_regs,
+};
+
+static const struct of_device_id jhb100_sys0_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-sys0-pinctrl",
+ .data = &jhb100_sys0_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_sys0_pinctrl_of_match);
+
+static struct platform_driver jhb100_sys0_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-sys0-pinctrl",
+ .of_match_table = jhb100_sys0_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_sys0_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC System-0 domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.c
new file mode 100644
index 000000000000..3e4c60d17bb8
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.c
@@ -0,0 +1,1821 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/minmax.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/seq_file.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/sort.h>
+
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+#define GPOUT_LOW 0
+#define GPOUT_HIGH 1
+
+#define GPOEN_ENABLE 0
+#define GPOEN_DISABLE 1
+
+#define MAX_DEBOUNCE_WIDTH_STAGES 0x1FFFF
+
+/* Custom pinconf parameters */
+#define STARFIVE_PIN_CONFIG_GMAC_VSEL (PIN_CONFIG_END + 1)
+#define STARFIVE_PIN_CONFIG_DEBOUNCE_WIDTH (PIN_CONFIG_END + 2)
+#define STARFIVE_PIN_DRIVE_I2C_FAST_MODE (PIN_CONFIG_END + 3)
+#define STARFIVE_PIN_DRIVE_I2C_FAST_MODE_PLUS (PIN_CONFIG_END + 4)
+#define STARFIVE_PIN_OPEN_DRAIN_PULLUP_SELECT (PIN_CONFIG_END + 5)
+#define STARFIVE_PIN_VGA_RTE_SELECT (PIN_CONFIG_END + 6)
+
+struct field_info {
+ const char *name;
+ unsigned int shift;
+ unsigned int width;
+ unsigned int end;
+};
+
+static const struct pinconf_generic_params jhb100_custom_bindings[] = {
+ { "starfive,gmac-vsel", STARFIVE_PIN_CONFIG_GMAC_VSEL, 0 },
+ { "starfive,debounce-width", STARFIVE_PIN_CONFIG_DEBOUNCE_WIDTH, 0 },
+ { "starfive,drive-i2c-fast-mode", STARFIVE_PIN_DRIVE_I2C_FAST_MODE, 0 },
+ { "starfive,drive-i2c-fast-mode-plus", STARFIVE_PIN_DRIVE_I2C_FAST_MODE_PLUS, 0 },
+ { "starfive,i2c-open-drain-pull-up-ohm", STARFIVE_PIN_OPEN_DRAIN_PULLUP_SELECT, 0 },
+ { "starfive,vga-rte", STARFIVE_PIN_VGA_RTE_SELECT, 0 },
+};
+
+static unsigned int jhb100_pinmux_pin(u32 v)
+{
+ return FIELD_GET(GENMASK(7, 0), v);
+}
+
+static u32 jhb100_pinmux_function(u32 v)
+{
+ return FIELD_GET(GENMASK(9, 8), v);
+}
+
+static u32 jhb100_get_func_sel(struct jhb100_pinctrl *sfp, unsigned int pin)
+{
+ struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ unsigned int offset = 4 * (pin / 16);
+ unsigned int shift = pinctrl_regs->func_sel.width_per_pin * (pin % 16);
+ u32 func_sel_mask;
+ u32 func_sel;
+ void __iomem *reg_gpio_func_sel;
+ unsigned long flags;
+
+ reg_gpio_func_sel = sfp->base + pinctrl_regs->func_sel.reg + offset;
+ func_sel_mask = GENMASK(pinctrl_regs->func_sel.width_per_pin - 1, 0) << shift;
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ func_sel = readl_relaxed(reg_gpio_func_sel);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+
+ return (func_sel & func_sel_mask) >> shift;
+}
+
+static struct config_reg_layout_desc *get_crl_desc_by_pin(struct jhb100_pinctrl *sfp,
+ unsigned int pin)
+{
+ struct config_reg_layout_desc *crl_desc = sfp->info->crl_desc;
+ unsigned int i = 0;
+
+ do {
+ if (pin >= crl_desc[i].pin_start &&
+ pin < crl_desc[i].pin_start + crl_desc[i].pin_cnt)
+ return &crl_desc[i];
+ } while (crl_desc[i++].pin_start != 0xff);
+
+ return NULL;
+}
+
+static struct jhb100_pinctrl *jhb100_from_irq_data(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+
+ return container_of(gc, struct jhb100_pinctrl, gc);
+}
+
+static struct jhb100_pinctrl *jhb100_from_irq_desc(struct irq_desc *desc)
+{
+ struct gpio_chip *gc = irq_desc_get_handler_data(desc);
+
+ return container_of(gc, struct jhb100_pinctrl, gc);
+}
+
+static int jhb100_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **maps,
+ unsigned int *num_maps)
+{
+ struct jhb100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
+ unsigned int old_num_funs, new_num_funs;
+ struct device *dev = sfp->gc.parent;
+ struct device_node *child;
+ struct pinctrl_map *map;
+ struct property *pinmux_p;
+ const char **pgnames;
+ const char *mux_grpname = NULL;
+ const char *grpname = NULL;
+ int ngroups;
+ int nmaps;
+ int ret;
+
+ ngroups = 0;
+ for_each_child_of_node(np, child)
+ ngroups += 1;
+ nmaps = 2 * ngroups;
+
+ pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);
+ if (!pgnames)
+ return -ENOMEM;
+
+ map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
+ if (!map)
+ return -ENOMEM;
+
+ nmaps = 0;
+ ngroups = 0;
+ mutex_lock(&sfp->mutex);
+ for_each_child_of_node(np, child) {
+ unsigned int old_num_groups, new_num_groups;
+ const char *pin_grpname;
+ int nmux;
+ int *mpins;
+ u32 *pinmux;
+ int i;
+
+ pinmux_p = of_find_property(child, "pinmux", NULL);
+ if (!pinmux_p) {
+ dev_err(dev,
+ "%pOFn.%pOFn: no muxing or pin config is specified\n",
+ np, child);
+ ret = -EINVAL;
+ goto put_child;
+ } else {
+ nmux = of_property_count_u32_elems(child, "pinmux");
+ if (nmux < 1) {
+ dev_err(dev,
+ "invalid pinctrl group %pOFn.%pOFn: no pinmux is set\n",
+ np, child);
+ ret = -EINVAL;
+ goto put_child;
+ }
+ }
+
+ grpname = kasprintf(GFP_KERNEL, "%pOFn.%pOFn", np, child);
+ if (!grpname) {
+ ret = -ENOMEM;
+ goto put_child;
+ }
+
+ pgnames[ngroups] = devm_kstrdup(dev, grpname, GFP_KERNEL);
+ if (!pgnames[ngroups]) {
+ ret = -ENOMEM;
+ goto free_grpname;
+ }
+ ngroups++;
+
+ pin_grpname = devm_kstrdup(dev, grpname, GFP_KERNEL);
+ if (!pin_grpname) {
+ ret = -ENOMEM;
+ goto free_grpname;
+ }
+
+ mux_grpname = kstrdup(grpname, GFP_KERNEL);
+ if (!mux_grpname) {
+ ret = -ENOMEM;
+ goto free_grpname;
+ }
+
+ mpins = devm_kcalloc(dev, nmux, sizeof(*mpins), GFP_KERNEL);
+ if (!mpins) {
+ ret = -ENOMEM;
+ goto free_mux_grpname;
+ }
+
+ pinmux = devm_kcalloc(dev, nmux, sizeof(*pinmux), GFP_KERNEL);
+ if (!pinmux) {
+ ret = -ENOMEM;
+ goto free_mux_grpname;
+ }
+
+ ret = of_property_read_u32_array(child, "pinmux", pinmux, nmux);
+ if (ret)
+ goto free_mux_grpname;
+
+ for (i = 0; i < nmux; i++)
+ mpins[i] = jhb100_pinmux_pin(pinmux[i]);
+
+ map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
+ map[nmaps].data.mux.function = np->name;
+ map[nmaps].data.mux.group = mux_grpname;
+ nmaps += 1;
+
+ old_num_groups = pctldev->num_groups;
+
+ ret = pinctrl_generic_add_group(pctldev, pin_grpname,
+ mpins, nmux, pinmux);
+ if (ret < 0) {
+ dev_err(dev, "error adding group %s: %d\n", pin_grpname, ret);
+ goto free_mux_grpname;
+ }
+
+ new_num_groups = pctldev->num_groups;
+ if (new_num_groups == old_num_groups) {
+ devm_kfree(dev, mpins);
+ devm_kfree(dev, pinmux);
+ devm_kfree(dev, pin_grpname);
+ }
+
+ ret = pinconf_generic_parse_dt_config(child, pctldev,
+ &map[nmaps].data.configs.configs,
+ &map[nmaps].data.configs.num_configs);
+ if (ret) {
+ dev_err(dev, "error parsing pin config of group %s: %d\n",
+ grpname, ret);
+ goto free_mux_grpname;
+ }
+
+ /* don't create a map if there are no pinconf settings */
+ if (map[nmaps].data.configs.num_configs == 0) {
+ kfree(grpname);
+ continue;
+ }
+
+ map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
+ map[nmaps].data.configs.group_or_pin = grpname;
+ nmaps += 1;
+ }
+
+ old_num_funs = pctldev->num_functions;
+ ret = pinmux_generic_add_function(pctldev, np->name,
+ pgnames, ngroups, NULL);
+ if (ret < 0) {
+ dev_err(dev, "error adding function %s: %d\n", np->name, ret);
+ goto free_mux_grpname;
+ }
+
+ new_num_funs = pctldev->num_functions;
+ if (new_num_funs == old_num_funs) {
+ int i;
+
+ for (i = 0; i < ngroups; i++)
+ devm_kfree(dev, pgnames[i]);
+
+ devm_kfree(dev, pgnames);
+ }
+
+ mutex_unlock(&sfp->mutex);
+
+ *maps = map;
+ *num_maps = nmaps;
+ return 0;
+
+free_mux_grpname:
+ kfree(mux_grpname);
+
+free_grpname:
+ kfree(grpname);
+
+put_child:
+ of_node_put(child);
+ mutex_unlock(&sfp->mutex);
+ kfree(map);
+ return ret;
+}
+
+static void jhb100_dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map,
+ unsigned int num_maps)
+{
+ int i;
+
+ for (i = 0; i < num_maps; i++) {
+ switch (map[i].type) {
+ case PIN_MAP_TYPE_MUX_GROUP:
+ kfree(map[i].data.mux.group);
+ break;
+ case PIN_MAP_TYPE_CONFIGS_GROUP:
+ kfree(map[i].data.configs.group_or_pin);
+ default:
+ break;
+ }
+ }
+
+ pinctrl_utils_free_map(pctldev, map, num_maps);
+}
+
+static const struct pinctrl_ops jhb100_pinctrl_ops = {
+ .get_groups_count = pinctrl_generic_get_group_count,
+ .get_group_name = pinctrl_generic_get_group_name,
+ .get_group_pins = pinctrl_generic_get_group_pins,
+ .dt_node_to_map = jhb100_dt_node_to_map,
+ .dt_free_map = jhb100_dt_free_map,
+};
+
+static void jhb100_set_gpioval(struct jhb100_pinctrl *sfp, unsigned int pin,
+ unsigned int val)
+{
+ const struct jhb100_pinctrl_domain_info *info = sfp->info;
+ unsigned int offset = 4 * (pin / 32);
+ unsigned int shift = 1 * (pin % 32);
+ unsigned int fs_offset = 4 * (pin / 16);
+ unsigned int fs_shift = 2 * (pin % 16);
+ u32 gpio_o_mask;
+ u32 gpio_oen_mask;
+ u32 func_sel_mask;
+ u32 dout, doen, fs;
+ void __iomem *reg_gpio_o;
+ void __iomem *reg_gpio_oen;
+ void __iomem *reg_gpio_func_sel;
+ unsigned long flags;
+
+ reg_gpio_o = sfp->base + info->regs->output.reg + offset;
+ reg_gpio_oen = sfp->base + info->regs->output_en.reg + offset;
+ reg_gpio_func_sel = sfp->base + info->regs->func_sel.reg + fs_offset;
+
+ gpio_o_mask = GENMASK(info->regs->output.width_per_pin - 1, 0) << shift;
+ gpio_oen_mask = GENMASK(info->regs->output_en.width_per_pin - 1, 0) << shift;
+ func_sel_mask = GENMASK(info->regs->func_sel.width_per_pin - 1, 0) << fs_shift;
+ dout = val << shift;
+ doen = 0;
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ fs = readl_relaxed(reg_gpio_func_sel);
+ if (fs & func_sel_mask) {
+ fs &= ~func_sel_mask;
+ writel_relaxed(fs, reg_gpio_func_sel);
+ }
+ dout |= readl_relaxed(reg_gpio_o) & ~gpio_o_mask;
+ writel_relaxed(dout, reg_gpio_o);
+ doen |= readl_relaxed(reg_gpio_oen) & ~gpio_oen_mask;
+ writel_relaxed(doen, reg_gpio_oen);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static void jhb100_set_function(struct jhb100_pinctrl *sfp,
+ unsigned int pin, u32 func)
+{
+ struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ void __iomem *func_sel_reg;
+ unsigned long flags;
+ u32 func_sel_mask;
+ u32 func_sel_val;
+ unsigned int offset = 4 * (pin / (32 / pinctrl_regs->func_sel.width_per_pin));
+ unsigned int shift = pinctrl_regs->func_sel.width_per_pin *
+ (pin % (32 / pinctrl_regs->func_sel.width_per_pin));
+
+ if (!pinctrl_regs->func_sel.reg || !pinctrl_regs->func_sel.width_per_pin)
+ return;
+
+ func_sel_reg = sfp->base + pinctrl_regs->func_sel.reg + offset;
+ func_sel_mask = GENMASK(pinctrl_regs->func_sel.width_per_pin - 1, 0) << shift;
+ func_sel_val = func << shift;
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ func_sel_val |= readl_relaxed(func_sel_reg) & ~func_sel_mask;
+ writel_relaxed(func_sel_val, func_sel_reg);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static int jhb100_set_one_pin_mux(struct jhb100_pinctrl *sfp,
+ unsigned int pin,
+ u32 func,
+ int val)
+{
+ const struct pinctrl_pin_desc *desc = &sfp->pins[pin];
+ struct device *dev = sfp->gc.parent;
+ int gpio_func_sel = sfp->gpio_func_sel_arr[pin];
+
+ jhb100_set_function(sfp, pin, func);
+
+ if (pin < sfp->gc.ngpio && (val == 0 || val == 1)) {
+ if (func == gpio_func_sel)
+ jhb100_set_gpioval(sfp, pin, val);
+ else
+ dev_err(dev, "pin (%s) is not a GPIO. func=%d/%d\n",
+ desc->name, func, gpio_func_sel);
+ }
+
+ return 0;
+}
+
+static int jhb100_set_mux(struct pinctrl_dev *pctldev,
+ unsigned int fsel, unsigned int gsel)
+{
+ struct jhb100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
+ const struct group_desc *group;
+ const u32 *pinmux;
+ unsigned int i;
+
+ group = pinctrl_generic_get_group(pctldev, gsel);
+ if (!group)
+ return -EINVAL;
+
+ pinmux = group->data;
+
+ for (i = 0; i < group->grp.npins; i++) {
+ u32 v = pinmux[i];
+
+ jhb100_set_one_pin_mux(sfp,
+ jhb100_pinmux_pin(v),
+ jhb100_pinmux_function(v),
+ -1);
+ }
+
+ return 0;
+}
+
+static const struct pinmux_ops jhb100_pinmux_ops = {
+ .get_functions_count = pinmux_generic_get_function_count,
+ .get_function_name = pinmux_generic_get_function_name,
+ .get_function_groups = pinmux_generic_get_function_groups,
+ .set_mux = jhb100_set_mux,
+};
+
+static const u8 jhb100_drive_strength_ma[4] = { 2, 4, 8, 12 };
+
+static const u8 jhb100_drive_strength_ma_3bit[8] = { 2, 5, 8, 10, 14, 16, 18, 20 };
+
+static u32 jhb100_padcfg_ds_to_mA(u32 padcfg)
+{
+ return jhb100_drive_strength_ma[padcfg];
+}
+
+static u32 jhb100_padcfg_ds_to_mA_3bit(u32 padcfg)
+{
+ return jhb100_drive_strength_ma_3bit[padcfg];
+}
+
+static u32 jhb100_padcfg_ds_to_uA(u32 padcfg)
+{
+ return (jhb100_drive_strength_ma[padcfg] * 1000);
+}
+
+static u32 jhb100_padcfg_ds_to_uA_3bit(u32 padcfg)
+{
+ return (jhb100_drive_strength_ma_3bit[padcfg] * 1000);
+}
+
+static u32 jhb100_padcfg_ds_from_mA(u32 v)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(jhb100_drive_strength_ma); i++) {
+ if (v <= jhb100_drive_strength_ma[i])
+ break;
+ }
+ return i;
+}
+
+static u32 jhb100_padcfg_ds_from_mA_3bit(u32 v)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(jhb100_drive_strength_ma_3bit); i++) {
+ if (v <= jhb100_drive_strength_ma_3bit[i])
+ break;
+ }
+ return i;
+}
+
+static u32 jhb100_padcfg_ds_from_uA(u32 v)
+{
+ /* Convert from uA to mA */
+ v /= 1000;
+
+ return jhb100_padcfg_ds_from_mA(v);
+}
+
+static u32 jhb100_padcfg_ds_from_uA_3bit(u32 v)
+{
+ /* Convert from uA to mA */
+ v /= 1000;
+
+ return jhb100_padcfg_ds_from_mA_3bit(v);
+}
+
+static void jhb100_padcfg_rmw(struct jhb100_pinctrl *sfp,
+ unsigned int pin, u32 mask, u32 value)
+{
+ void __iomem *reg;
+ unsigned int offset;
+ unsigned long flags;
+ int padcfg_base;
+
+ padcfg_base = sfp->info->regs->config.reg;
+
+ offset = 4 * pin;
+
+ reg = sfp->base + padcfg_base + offset;
+
+ value &= mask;
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ value |= readl_relaxed(reg) & ~mask;
+ writel_relaxed(value, reg);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static int jhb100_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *config)
+{
+ struct jhb100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
+ int param = pinconf_to_config_param(*config);
+ struct device *dev = sfp->gc.parent;
+ struct config_reg_layout_desc *crl_desc;
+ unsigned int offset;
+ u32 padcfg, arg;
+ bool enabled;
+ int padcfg_base;
+
+ padcfg_base = sfp->info->regs->config.reg;
+
+ offset = 4 * pin;
+
+ if (pin <= sfp->npins)
+ padcfg = readl_relaxed(sfp->base + padcfg_base + offset);
+ else
+ return -EINVAL;
+
+ crl_desc = get_crl_desc_by_pin(sfp, pin);
+ if (!crl_desc) {
+ dev_err(dev, "pin %d can't not found reg layout descriptor\n", pin);
+ return -EINVAL;
+ }
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ arg = 0;
+
+ if (!RL_DESC_SUPPORTED(crl_desc, pull_down) ||
+ !RL_DESC_SUPPORTED(crl_desc, pull_up))
+ return -EOPNOTSUPP;
+
+ enabled = !(padcfg & (RL_DESC_GENMASK(crl_desc, pull_down) |
+ RL_DESC_GENMASK(crl_desc, pull_up)));
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ arg = 1;
+
+ if (!RL_DESC_SUPPORTED(crl_desc, pull_down))
+ return -EOPNOTSUPP;
+
+ enabled = (padcfg & RL_DESC_GENMASK(crl_desc, pull_down))
+ >> RL_DESC_SHIFT(crl_desc, pull_down);
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ arg = 1;
+
+ if (!RL_DESC_SUPPORTED(crl_desc, pull_up))
+ return -EOPNOTSUPP;
+
+ enabled = (padcfg & RL_DESC_GENMASK(crl_desc, pull_up))
+ >> RL_DESC_SHIFT(crl_desc, pull_up);
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ enabled = true;
+
+ if (RL_DESC_SUPPORTED(crl_desc, drive_strength_2bit))
+ arg = jhb100_padcfg_ds_to_mA(padcfg <<
+ RL_DESC_SHIFT(crl_desc,
+ drive_strength_2bit));
+ else if (RL_DESC_SUPPORTED(crl_desc, drive_strength_3bit))
+ arg = jhb100_padcfg_ds_to_mA_3bit(padcfg <<
+ RL_DESC_SHIFT(crl_desc,
+ drive_strength_3bit));
+ else
+ return -EOPNOTSUPP;
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH_UA:
+ enabled = true;
+
+ if (RL_DESC_SUPPORTED(crl_desc, drive_strength_2bit))
+ arg = jhb100_padcfg_ds_to_uA(padcfg
+ << RL_DESC_SHIFT(crl_desc, drive_strength_2bit));
+ else if (RL_DESC_SUPPORTED(crl_desc, drive_strength_3bit))
+ arg = jhb100_padcfg_ds_to_uA_3bit(padcfg
+ << RL_DESC_SHIFT(crl_desc, drive_strength_3bit));
+ else
+ return -EOPNOTSUPP;
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ if (!RL_DESC_SUPPORTED(crl_desc, input_enable))
+ return -EOPNOTSUPP;
+
+ enabled = (padcfg & RL_DESC_GENMASK(crl_desc, input_enable))
+ >> RL_DESC_SHIFT(crl_desc, input_enable);
+ arg = enabled;
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ if (!RL_DESC_SUPPORTED(crl_desc, schmitt_trigger_select))
+ return -EOPNOTSUPP;
+
+ enabled = (padcfg & RL_DESC_GENMASK(crl_desc, schmitt_trigger_select))
+ >> RL_DESC_SHIFT(crl_desc, schmitt_trigger_select);
+ arg = enabled;
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ enabled = true;
+
+ if (!RL_DESC_SUPPORTED(crl_desc, slew_rate))
+ return -EOPNOTSUPP;
+
+ arg = (padcfg & RL_DESC_GENMASK(crl_desc, slew_rate))
+ >> RL_DESC_SHIFT(crl_desc, slew_rate);
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, arg);
+ return enabled ? 0 : -EINVAL;
+}
+
+static int jhb100_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned int gpio, unsigned long *config,
+ unsigned int num_configs)
+{
+ struct jhb100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
+ struct device *dev = sfp->gc.parent;
+ struct config_reg_layout_desc *crl_desc;
+ u32 param;
+ u32 arg;
+ u32 value;
+ u32 mask;
+ int i;
+
+ crl_desc = get_crl_desc_by_pin(sfp, gpio);
+ if (!crl_desc) {
+ dev_err(dev, "pin %d can't not found reg layout descriptor\n", gpio);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < num_configs; i++) {
+ param = pinconf_to_config_param(config[i]);
+ arg = pinconf_to_config_argument(config[i]);
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (!RL_DESC_SUPPORTED(crl_desc, pull_down) ||
+ !RL_DESC_SUPPORTED(crl_desc, pull_up))
+ return -EOPNOTSUPP;
+
+ mask = RL_DESC_GENMASK(crl_desc, pull_down) |
+ RL_DESC_GENMASK(crl_desc, pull_up);
+ value = 0;
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (!RL_DESC_SUPPORTED(crl_desc, pull_down) ||
+ !RL_DESC_SUPPORTED(crl_desc, pull_up))
+ return -EOPNOTSUPP;
+
+ mask = RL_DESC_GENMASK(crl_desc, pull_down) |
+ RL_DESC_GENMASK(crl_desc, pull_up);
+ value = RL_DESC_GENMASK(crl_desc, pull_down);
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (!RL_DESC_SUPPORTED(crl_desc, pull_down) ||
+ !RL_DESC_SUPPORTED(crl_desc, pull_up))
+ return -EOPNOTSUPP;
+
+ mask = RL_DESC_GENMASK(crl_desc, pull_down) |
+ RL_DESC_GENMASK(crl_desc, pull_up);
+ value = RL_DESC_GENMASK(crl_desc, pull_up);
+ break;
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ return 0;
+ case PIN_CONFIG_INPUT_ENABLE:
+ if (!RL_DESC_SUPPORTED(crl_desc, input_enable))
+ return -EOPNOTSUPP;
+
+ mask = RL_DESC_GENMASK(crl_desc, input_enable);
+ value = arg ? RL_DESC_GENMASK(crl_desc, input_enable) : 0;
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ if (!RL_DESC_SUPPORTED(crl_desc, schmitt_trigger_select))
+ return -EOPNOTSUPP;
+
+ mask = RL_DESC_GENMASK(crl_desc, schmitt_trigger_select);
+ value = arg ? RL_DESC_GENMASK(crl_desc, schmitt_trigger_select) : 0;
+ break;
+ case STARFIVE_PIN_CONFIG_DEBOUNCE_WIDTH:
+ if (arg > MAX_DEBOUNCE_WIDTH_STAGES)
+ arg = MAX_DEBOUNCE_WIDTH_STAGES;
+
+ if (!RL_DESC_SUPPORTED(crl_desc, debounce_width))
+ return -EOPNOTSUPP;
+
+ mask = RL_DESC_GENMASK(crl_desc, debounce_width);
+ value = arg ? (arg << RL_DESC_SHIFT(crl_desc, debounce_width)) : 0;
+ break;
+ case STARFIVE_PIN_CONFIG_GMAC_VSEL:
+ if (!RL_DESC_SUPPORTED_FUNC(crl_desc, vsel,
+ BIT(jhb100_get_func_sel(sfp, gpio))))
+ return -EOPNOTSUPP;
+
+ mask = RL_DESC_GENMASK(crl_desc, vsel);
+ value = arg ? arg << RL_DESC_SHIFT(crl_desc, vsel) : 0;
+ break;
+ case STARFIVE_PIN_VGA_RTE_SELECT:
+ if (!RL_DESC_SUPPORTED(crl_desc, retention_signal_bus))
+ return -EOPNOTSUPP;
+
+ mask = RL_DESC_GENMASK(crl_desc, retention_signal_bus);
+ value = arg ? RL_DESC_GENMASK(crl_desc, retention_signal_bus) : 0;
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ jhb100_padcfg_rmw(sfp, gpio, mask, value);
+ }
+
+ return 0;
+}
+
+static int jhb100_pinconf_group_get(struct pinctrl_dev *pctldev,
+ unsigned int gsel,
+ unsigned long *config)
+{
+ const struct group_desc *group;
+
+ group = pinctrl_generic_get_group(pctldev, gsel);
+ if (!group)
+ return -EINVAL;
+
+ return jhb100_pinconf_get(pctldev, group->grp.pins[0], config);
+}
+
+static int jhb100_pinconf_group_set(struct pinctrl_dev *pctldev,
+ unsigned int gsel,
+ unsigned long *configs,
+ unsigned int num_configs)
+{
+ struct jhb100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
+ struct device *dev = sfp->gc.parent;
+ struct config_reg_layout_desc *crl_desc;
+ const struct group_desc *group;
+ u32 mask, value;
+ int i;
+
+ group = pinctrl_generic_get_group(pctldev, gsel);
+ if (!group)
+ return -EINVAL;
+
+ mask = 0;
+ value = 0;
+ for (i = 0; i < num_configs; i++) {
+ int param = pinconf_to_config_param(configs[i]);
+ u32 arg = pinconf_to_config_argument(configs[i]);
+
+ crl_desc = get_crl_desc_by_pin(sfp, group->grp.pins[0]);
+ if (!crl_desc) {
+ dev_err(dev, "pin %d can't not found reg layout descriptor\n",
+ group->grp.pins[i]);
+ return -EINVAL;
+ }
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (!RL_DESC_SUPPORTED(crl_desc, pull_down) ||
+ !RL_DESC_SUPPORTED(crl_desc, pull_up))
+ return -EOPNOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, pull_down) |
+ RL_DESC_GENMASK(crl_desc, pull_up);
+ value &= ~(RL_DESC_GENMASK(crl_desc, pull_down) |
+ RL_DESC_GENMASK(crl_desc, pull_up));
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (!arg || !RL_DESC_SUPPORTED(crl_desc, pull_down) ||
+ !RL_DESC_SUPPORTED(crl_desc, pull_up))
+ return -EOPNOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, pull_down) |
+ RL_DESC_GENMASK(crl_desc, pull_up);
+ value &= ~(RL_DESC_GENMASK(crl_desc, pull_down) |
+ RL_DESC_GENMASK(crl_desc, pull_up));
+ value |= RL_DESC_GENMASK(crl_desc, pull_down);
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (!arg || !RL_DESC_SUPPORTED(crl_desc, pull_down) ||
+ !RL_DESC_SUPPORTED(crl_desc, pull_up))
+ return -EOPNOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, pull_down) |
+ RL_DESC_GENMASK(crl_desc, pull_up);
+ value &= ~(RL_DESC_GENMASK(crl_desc, pull_down) |
+ RL_DESC_GENMASK(crl_desc, pull_up));
+ value |= RL_DESC_GENMASK(crl_desc, pull_up);
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ if (RL_DESC_SUPPORTED(crl_desc, drive_strength_2bit)) {
+ mask |= RL_DESC_GENMASK(crl_desc, drive_strength_2bit);
+ value &= ~RL_DESC_GENMASK(crl_desc, drive_strength_2bit);
+ value |= jhb100_padcfg_ds_from_mA(arg) <<
+ RL_DESC_SHIFT(crl_desc, drive_strength_2bit);
+ } else if (RL_DESC_SUPPORTED(crl_desc, drive_strength_3bit)) {
+ mask |= RL_DESC_GENMASK(crl_desc, drive_strength_3bit);
+ value &= ~RL_DESC_GENMASK(crl_desc, drive_strength_3bit);
+ value |= jhb100_padcfg_ds_from_mA_3bit(arg) <<
+ RL_DESC_SHIFT(crl_desc, drive_strength_3bit);
+ } else {
+ return -EOPNOTSUPP;
+ }
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH_UA:
+ if (RL_DESC_SUPPORTED(crl_desc, drive_strength_2bit)) {
+ mask |= RL_DESC_GENMASK(crl_desc, drive_strength_2bit);
+ value &= ~RL_DESC_GENMASK(crl_desc, drive_strength_2bit);
+ value |= jhb100_padcfg_ds_from_uA(arg) <<
+ RL_DESC_SHIFT(crl_desc, drive_strength_2bit);
+ } else if (RL_DESC_SUPPORTED(crl_desc, drive_strength_3bit)) {
+ mask |= RL_DESC_GENMASK(crl_desc, drive_strength_3bit);
+ value &= ~RL_DESC_GENMASK(crl_desc, drive_strength_3bit);
+ value |= jhb100_padcfg_ds_from_uA_3bit(arg) <<
+ RL_DESC_SHIFT(crl_desc, drive_strength_3bit);
+ } else {
+ return -EOPNOTSUPP;
+ }
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ if (!RL_DESC_SUPPORTED(crl_desc, input_enable))
+ return -EOPNOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, input_enable);
+ value = arg ? (value | RL_DESC_GENMASK(crl_desc, input_enable))
+ : value;
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ if (!RL_DESC_SUPPORTED(crl_desc, schmitt_trigger_select))
+ return -EOPNOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, schmitt_trigger_select);
+ value = arg
+ ? (value | RL_DESC_GENMASK(crl_desc, schmitt_trigger_select))
+ : value;
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ if (!RL_DESC_SUPPORTED(crl_desc, slew_rate))
+ return -EOPNOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, slew_rate);
+ value = arg ? (value | RL_DESC_GENMASK(crl_desc, slew_rate)) : value;
+ break;
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ if (!RL_DESC_SUPPORTED(crl_desc, mode_select))
+ return -EOPNOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, mode_select);
+ value &= ~RL_DESC_GENMASK(crl_desc, mode_select);
+ value |= JHB100_PUSH_PULL <<
+ RL_DESC_SHIFT(crl_desc, mode_select);
+ break;
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ if (!RL_DESC_SUPPORTED(crl_desc, mode_select))
+ return -EOPNOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, mode_select);
+ value &= ~RL_DESC_GENMASK(crl_desc, mode_select);
+ value |= JHB100_OPEN_DRAIN <<
+ RL_DESC_SHIFT(crl_desc, mode_select);
+ break;
+ case STARFIVE_PIN_DRIVE_I2C_FAST_MODE:
+ if (!RL_DESC_SUPPORTED(crl_desc, mode_select))
+ return -EOPNOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, mode_select);
+ value &= ~RL_DESC_GENMASK(crl_desc, mode_select);
+ value |= JHB100_LEGACY_FAST_MODE <<
+ RL_DESC_SHIFT(crl_desc, mode_select);
+ break;
+ case STARFIVE_PIN_DRIVE_I2C_FAST_MODE_PLUS:
+ if (!RL_DESC_SUPPORTED(crl_desc, mode_select))
+ return -EOPNOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, mode_select);
+ value &= ~RL_DESC_GENMASK(crl_desc, mode_select);
+ value |= JHB100_LEGACY_FAST_MODE_PLUS <<
+ RL_DESC_SHIFT(crl_desc, mode_select);
+ break;
+ case STARFIVE_PIN_OPEN_DRAIN_PULLUP_SELECT:
+ if (!RL_DESC_SUPPORTED(crl_desc, open_drain_pull_up_sel))
+ return -EOPNOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, open_drain_pull_up_sel);
+ value &= ~RL_DESC_GENMASK(crl_desc, open_drain_pull_up_sel);
+ switch (arg) {
+ case 600:
+ value |= JHB100_I2C_OPEN_DRAIN_PU_600_OHMS <<
+ RL_DESC_SHIFT(crl_desc, open_drain_pull_up_sel);
+ break;
+ case 900:
+ value |= JHB100_I2C_OPEN_DRAIN_PU_900_OHMS <<
+ RL_DESC_SHIFT(crl_desc, open_drain_pull_up_sel);
+ break;
+ case 1200:
+ value |= JHB100_I2C_OPEN_DRAIN_PU_1200_OHMS <<
+ RL_DESC_SHIFT(crl_desc, open_drain_pull_up_sel);
+ break;
+ case 2000:
+ value |= JHB100_I2C_OPEN_DRAIN_PU_2000_OHMS <<
+ RL_DESC_SHIFT(crl_desc, open_drain_pull_up_sel);
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+ break;
+ case STARFIVE_PIN_CONFIG_DEBOUNCE_WIDTH:
+ if (!RL_DESC_SUPPORTED(crl_desc, debounce_width))
+ return -EOPNOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, debounce_width);
+ value &= ~RL_DESC_GENMASK(crl_desc, debounce_width);
+ value = arg
+ ? (value | (arg << RL_DESC_SHIFT(crl_desc, debounce_width)))
+ : value;
+ break;
+ case STARFIVE_PIN_CONFIG_GMAC_VSEL:
+ if (!RL_DESC_SUPPORTED(crl_desc, vsel))
+ return -EOPNOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, vsel);
+ value &= ~RL_DESC_GENMASK(crl_desc, vsel);
+ value = arg
+ ? (value | (arg << RL_DESC_SHIFT(crl_desc, vsel)))
+ : value;
+ break;
+ case STARFIVE_PIN_VGA_RTE_SELECT:
+ if (!RL_DESC_SUPPORTED(crl_desc, retention_signal_bus))
+ return -EOPNOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, retention_signal_bus);
+ value &= ~RL_DESC_GENMASK(crl_desc, retention_signal_bus);
+ value = arg
+ ? (value | (arg << RL_DESC_SHIFT(crl_desc, retention_signal_bus)))
+ : value;
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+ }
+
+ for (i = 0; i < group->grp.npins; i++)
+ jhb100_padcfg_rmw(sfp, group->grp.pins[i], mask, value);
+
+ return 0;
+}
+
+static const struct pinconf_ops jhb100_pinconf_ops = {
+ .pin_config_get = jhb100_pinconf_get,
+ .pin_config_set = jhb100_pinconf_set,
+ .pin_config_group_get = jhb100_pinconf_group_get,
+ .pin_config_group_set = jhb100_pinconf_group_set,
+ .is_generic = true,
+};
+
+static int jhb100_gpio_get_direction(struct gpio_chip *gc,
+ unsigned int gpio)
+{
+ struct jhb100_pinctrl *sfp = container_of(gc, struct jhb100_pinctrl, gc);
+ const struct jhb100_pinctrl_domain_info *info = sfp->info;
+ unsigned int offset = 4 * (gpio / 32);
+ unsigned int shift = 1 * (gpio % 32);
+ u32 gpio_oen_mask;
+ u32 doen;
+ void __iomem *reg_gpio_oen;
+
+ reg_gpio_oen = sfp->base + info->regs->output_en.reg + offset;
+ gpio_oen_mask = GENMASK(info->regs->output_en.width_per_pin - 1, 0) << shift;
+
+ doen = (readl_relaxed(reg_gpio_oen) & gpio_oen_mask) >> shift;
+
+ return doen == GPOEN_ENABLE ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
+}
+
+static int jhb100_gpio_direction_input(struct gpio_chip *gc,
+ unsigned int gpio)
+{
+ struct jhb100_pinctrl *sfp = container_of(gc, struct jhb100_pinctrl, gc);
+ struct device *dev = sfp->gc.parent;
+ struct config_reg_layout_desc *crl_desc;
+
+ crl_desc = get_crl_desc_by_pin(sfp, gpio);
+ if (!crl_desc) {
+ dev_err(dev, "pin %d can't not found reg layout descriptor\n",
+ gpio);
+ return -EINVAL;
+ }
+
+ jhb100_padcfg_rmw(sfp, gpio,
+ RL_DESC_GENMASK(crl_desc, input_enable) |
+ RL_DESC_GENMASK(crl_desc, schmitt_trigger_select),
+ RL_DESC_GENMASK(crl_desc, input_enable) |
+ RL_DESC_GENMASK(crl_desc, schmitt_trigger_select));
+
+ jhb100_set_one_pin_mux(sfp, gpio, 0, -1);
+
+ return 0;
+}
+
+static int jhb100_gpio_direction_output(struct gpio_chip *gc,
+ unsigned int gpio, int value)
+{
+ struct jhb100_pinctrl *sfp = container_of(gc, struct jhb100_pinctrl, gc);
+ struct device *dev = sfp->gc.parent;
+ struct config_reg_layout_desc *crl_desc;
+
+ jhb100_set_one_pin_mux(sfp, gpio, 0,
+ value ? GPOUT_HIGH : GPOUT_LOW);
+
+ crl_desc = get_crl_desc_by_pin(sfp, gpio);
+ if (!crl_desc) {
+ dev_err(dev, "pin %d can't not found reg layout descriptor\n",
+ gpio);
+ return -EINVAL;
+ }
+
+ jhb100_padcfg_rmw(sfp, gpio,
+ RL_DESC_GENMASK(crl_desc, input_enable) |
+ RL_DESC_GENMASK(crl_desc, schmitt_trigger_select) |
+ RL_DESC_GENMASK(crl_desc, pull_down) |
+ RL_DESC_GENMASK(crl_desc, pull_up),
+ 0);
+
+ return 0;
+}
+
+static int jhb100_gpio_get(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct jhb100_pinctrl *sfp = container_of(gc, struct jhb100_pinctrl, gc);
+ const struct jhb100_pinctrl_domain_info *info = sfp->info;
+ unsigned int offset = 4 * (gpio / 32);
+ unsigned int shift = 1 * (gpio % 32);
+ u32 gpio_oen_mask = GENMASK(info->regs->output_en.width_per_pin - 1, 0) << shift;
+ u32 doen = 0;
+ void __iomem *reg_gpio_oen;
+ void __iomem *reg;
+ unsigned long flags;
+
+ reg_gpio_oen = sfp->base + info->regs->output_en.reg + offset;
+ reg = sfp->base + info->regs->gpio_status.reg + offset;
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ doen = readl_relaxed(reg_gpio_oen) | gpio_oen_mask;
+ writel_relaxed(doen, reg_gpio_oen);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+
+ return !!(readl_relaxed(reg) & BIT(gpio % 32));
+}
+
+static int jhb100_gpio_set(struct gpio_chip *gc, unsigned int gpio, int value)
+{
+ struct jhb100_pinctrl *sfp = container_of(gc, struct jhb100_pinctrl, gc);
+ const struct jhb100_pinctrl_domain_info *info = sfp->info;
+ unsigned int offset = 4 * (gpio / 32);
+ unsigned int shift = 1 * (gpio % 32);
+ void __iomem *reg_dout;
+ u32 dout;
+ u32 mask;
+ unsigned long flags;
+
+ reg_dout = sfp->base + info->regs->output.reg + offset;
+ dout = (value ? GPOUT_HIGH : GPOUT_LOW) << shift;
+ mask = GENMASK(info->regs->output.width_per_pin - 1, 0) << shift;
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ dout |= readl_relaxed(reg_dout) & ~mask;
+ writel_relaxed(dout, reg_dout);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+
+ return 0;
+}
+
+static void jhb100_irq_ack(struct irq_data *d)
+{
+ struct jhb100_pinctrl *sfp = jhb100_from_irq_data(d);
+ struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ void __iomem *ic;
+ u32 mask;
+ unsigned long flags;
+ u32 value;
+
+ ic = sfp->base + pinctrl_regs->irq_clr.reg + 4 * (gpio / 32);
+ mask = BIT(gpio % 32);
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ value = readl_relaxed(ic) & ~mask;
+ writel_relaxed(value | mask, ic);
+ value = readl_relaxed(ic) & ~mask;
+ writel_relaxed(value, ic);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static void jhb100_irq_mask(struct irq_data *d)
+{
+ struct jhb100_pinctrl *sfp = jhb100_from_irq_data(d);
+ struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ void __iomem *ien;
+ u32 mask;
+ unsigned long flags;
+ u32 value;
+
+ ien = sfp->base + pinctrl_regs->irq_en.reg + 4 * (gpio / 32);
+ mask = BIT(gpio % 32);
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ value = readl_relaxed(ien) & ~mask;
+ writel_relaxed(value, ien);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+
+ gpiochip_disable_irq(&sfp->gc, d->hwirq);
+}
+
+static void jhb100_irq_mask_ack(struct irq_data *d)
+{
+ struct jhb100_pinctrl *sfp = jhb100_from_irq_data(d);
+ struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ void __iomem *ien;
+ void __iomem *ic;
+ u32 mask = BIT(gpio % 32);
+ unsigned long flags;
+ u32 value;
+
+ ien = sfp->base + pinctrl_regs->irq_en.reg + 4 * (gpio / 32);
+ ic = sfp->base + pinctrl_regs->irq_clr.reg + 4 * (gpio / 32);
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ value = readl_relaxed(ien) & ~mask;
+ writel_relaxed(value, ien);
+
+ value = readl_relaxed(ic) & ~mask;
+ writel_relaxed(value | mask, ic);
+ value = readl_relaxed(ic) & ~mask;
+ writel_relaxed(value, ic);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static void jhb100_irq_unmask(struct irq_data *d)
+{
+ struct jhb100_pinctrl *sfp = jhb100_from_irq_data(d);
+ struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ void __iomem *ien;
+ u32 mask;
+ unsigned long flags;
+ u32 value;
+
+ ien = sfp->base + pinctrl_regs->irq_en.reg + 4 * (gpio / 32);
+ mask = BIT(gpio % 32);
+
+ gpiochip_enable_irq(&sfp->gc, d->hwirq);
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ value = readl_relaxed(ien) | mask;
+ writel_relaxed(value, ien);
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+}
+
+static int jhb100_irq_set_type(struct irq_data *d, unsigned int trigger)
+{
+ struct jhb100_pinctrl *sfp = jhb100_from_irq_data(d);
+ struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ void __iomem *base;
+ u32 mask;
+ u32 irq_type, edge_both, polarity;
+ unsigned long flags;
+
+ base = sfp->base + 4 * (gpio / 32);
+ mask = BIT(gpio % 32);
+
+ switch (trigger) {
+ case IRQ_TYPE_EDGE_RISING:
+ irq_type = mask; /* 1: edge triggered */
+ edge_both = 0; /* 0: single edge */
+ polarity = mask; /* 1: rising edge */
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ irq_type = mask; /* 1: edge triggered */
+ edge_both = 0; /* 0: single edge */
+ polarity = 0; /* 0: falling edge */
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ irq_type = mask; /* 1: edge triggered */
+ edge_both = mask; /* 1: both edges */
+ polarity = 0; /* 0: ignored */
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ irq_type = 0; /* 0: level triggered */
+ edge_both = 0; /* 0: ignored */
+ polarity = mask; /* 1: high level */
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ irq_type = 0; /* 0: level triggered */
+ edge_both = 0; /* 0: ignored */
+ polarity = 0; /* 0: low level */
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (trigger & IRQ_TYPE_EDGE_BOTH)
+ irq_set_handler_locked(d, handle_edge_irq);
+ else
+ irq_set_handler_locked(d, handle_level_irq);
+
+ raw_spin_lock_irqsave(&sfp->lock, flags);
+ irq_type |= readl_relaxed(base + pinctrl_regs->irq_trigger.reg) & ~mask;
+ writel_relaxed(irq_type, base + pinctrl_regs->irq_trigger.reg);
+
+ edge_both |= readl_relaxed(base + pinctrl_regs->irq_both_edge.reg) & ~mask;
+ writel_relaxed(edge_both, base + pinctrl_regs->irq_both_edge.reg);
+
+ if (irq_type & mask) { /* edge polarity */
+ polarity |= readl_relaxed(base + pinctrl_regs->irq_edge.reg) & ~mask;
+ writel_relaxed(polarity, base + pinctrl_regs->irq_edge.reg);
+ } else if (irq_type == 0) { /* level polarity */
+ polarity |= readl_relaxed(base + pinctrl_regs->irq_level.reg) & ~mask;
+ writel_relaxed(polarity, base + pinctrl_regs->irq_level.reg);
+ }
+ raw_spin_unlock_irqrestore(&sfp->lock, flags);
+ return 0;
+}
+
+static int jhb100_irq_set_wake(struct irq_data *d, unsigned int enable)
+{
+ struct jhb100_pinctrl *sfp = jhb100_from_irq_data(d);
+ int ret = 0;
+
+ if (enable)
+ ret = enable_irq_wake(sfp->wakeup_irq);
+ else
+ ret = disable_irq_wake(sfp->wakeup_irq);
+ if (ret)
+ dev_err(sfp->dev, "failed to %s wake-up interrupt\n",
+ enable ? "enable" : "disable");
+
+ return ret;
+}
+
+static void jhb100_irq_print_chip(struct irq_data *d, struct seq_file *p)
+{
+ struct jhb100_pinctrl *sfp = jhb100_from_irq_data(d);
+
+ seq_printf(p, sfp->gc.label);
+}
+
+static const struct irq_chip jhb100_irq_chip = {
+ .irq_ack = jhb100_irq_ack,
+ .irq_mask = jhb100_irq_mask,
+ .irq_mask_ack = jhb100_irq_mask_ack,
+ .irq_unmask = jhb100_irq_unmask,
+ .irq_set_type = jhb100_irq_set_type,
+ .irq_set_wake = jhb100_irq_set_wake,
+ .irq_print_chip = jhb100_irq_print_chip,
+ .flags = IRQCHIP_SET_TYPE_MASKED |
+ IRQCHIP_IMMUTABLE |
+ IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND |
+ IRQCHIP_MASK_ON_SUSPEND |
+ IRQCHIP_SKIP_SET_WAKE,
+ GPIOCHIP_IRQ_RESOURCE_HELPERS,
+};
+
+static void jhb100_gpio_irq_handler(struct irq_desc *desc)
+{
+ struct jhb100_pinctrl *sfp = jhb100_from_irq_desc(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct gpio_irq_chip *girq = &sfp->gc.irq;
+ struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ unsigned long is;
+ unsigned int pin;
+ unsigned int total, size, remain = sfp->npins;
+
+ chained_irq_enter(chip, desc);
+
+ for (total = 0, size = 0; total < sfp->npins; total += 32, remain -= size) {
+ is = readl_relaxed(sfp->base + pinctrl_regs->irq_status.reg +
+ (total >> 3));
+ size = umin(remain, 32);
+
+ for_each_set_bit(pin, &is, size) {
+ if (sfp->gpio_func_sel_arr[pin] >= 0)
+ generic_handle_domain_irq(girq->domain, pin);
+ }
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static int jhb100_gpio_init_hw(struct gpio_chip *gc)
+{
+ struct jhb100_pinctrl *sfp = container_of(gc, struct jhb100_pinctrl, gc);
+ struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ unsigned int i;
+
+ for (i = 0; i < sfp->npins; i += 32) {
+ /* mask all GPIO interrupts */
+ writel_relaxed(0U, sfp->base + pinctrl_regs->irq_en.reg + (i >> 3));
+ /* clear all interrupts */
+ writel_relaxed(~0U, sfp->base + pinctrl_regs->irq_clr.reg + (i >> 3));
+ writel_relaxed(0U, sfp->base + pinctrl_regs->irq_clr.reg + (i >> 3));
+ }
+
+ return 0;
+}
+
+static int field_compare(const void *a, const void *b)
+{
+ const struct field_info *fa = (const struct field_info *)a;
+ const struct field_info *fb = (const struct field_info *)b;
+
+ if (fa->shift < fb->shift)
+ return -1;
+
+ if (fa->shift > fb->shift)
+ return 1;
+
+ return 0;
+}
+
+static int check_crl_desc(struct jhb100_pinctrl *sfp, unsigned int index,
+ const struct config_reg_layout_desc *desc)
+{
+ struct device *dev = sfp->gc.parent;
+ struct field_info *fields;
+ int field_cnt = 0;
+ int num, i;
+
+ num = sizeof(struct config_reg_layout_desc) / sizeof(struct reg_layout_field);
+
+ fields = kcalloc(num, sizeof(struct field_info), GFP_KERNEL);
+ if (!fields)
+ return -ENOMEM;
+
+ #define COLLECT_FIELD(field) \
+ do { \
+ if (desc->field.width > 0) { \
+ fields[field_cnt].name = #field; \
+ fields[field_cnt].shift = desc->field.shift; \
+ fields[field_cnt].width = desc->field.width; \
+ fields[field_cnt].end = desc->field.shift + desc->field.width; \
+ field_cnt++; \
+ } \
+ } while (0)
+
+ /* same as struct config_reg_layout_desc filed except for pin_start and pin_cnt */
+ COLLECT_FIELD(debounce_width);
+ COLLECT_FIELD(drive_strength_2bit);
+ COLLECT_FIELD(drive_strength_3bit);
+ COLLECT_FIELD(function);
+ COLLECT_FIELD(input_enable);
+ COLLECT_FIELD(vsel);
+ COLLECT_FIELD(mode_select);
+ COLLECT_FIELD(open_drain_pull_up_sel);
+ COLLECT_FIELD(pull_down);
+ COLLECT_FIELD(pull_up);
+ COLLECT_FIELD(reserved);
+ COLLECT_FIELD(retention_signal_bus);
+ COLLECT_FIELD(schmitt_trigger_select);
+ COLLECT_FIELD(slew_rate);
+
+ #undef COLLECT_FIELD
+
+ sort(fields, field_cnt, sizeof(struct field_info), field_compare, NULL);
+
+ for (i = 0; i < field_cnt; i++) {
+ if (fields[i].end > 32) {
+ dev_err(dev,
+ "layout %d: field %s exceeds 32bit [shift=%u, width=%u, end=%u]\n",
+ index, fields[i].name,
+ fields[i].shift, fields[i].width, fields[i].end);
+ goto failed;
+ }
+
+ if (i < field_cnt - 1) {
+ if (fields[i].end > fields[i + 1].shift) {
+ dev_err(dev,
+ "layout %d: field overlap: %s[%u:%u] with %s[%u:%u]\n",
+ index, fields[i].name, fields[i].end - 1,
+ fields[i].shift, fields[i + 1].name,
+ fields[i + 1].end - 1, fields[i + 1].shift);
+ goto failed;
+ }
+ }
+ }
+
+ if (desc->reserved.width > 0) {
+ unsigned int used_mask = 0;
+ unsigned int reserved_mask = 0;
+
+ for (i = 0; i < field_cnt; i++) {
+ if (strcmp(fields[i].name, "reserved"))
+ used_mask |= GENMASK(fields[i].end - 1, fields[i].shift);
+ else
+ reserved_mask |= GENMASK(fields[i].end - 1, fields[i].shift);
+ }
+
+ if ((used_mask | reserved_mask) != 0xFFFFFFFF) {
+ dev_err(dev,
+ "layout %d: reserved field not cover all unused bits\n",
+ index);
+ dev_err(dev,
+ "used mask: 0x%08X, reserved mask: 0x%08X, combined: 0x%08X\n",
+ used_mask, reserved_mask, used_mask | reserved_mask);
+ }
+ }
+
+ kfree(fields);
+ return 0;
+
+failed:
+ kfree(fields);
+ return -EINVAL;
+}
+
+static int check_layout_pin_range(struct jhb100_pinctrl *sfp,
+ const struct config_reg_layout_desc *descs,
+ unsigned int num_desc)
+{
+ struct device *dev = sfp->gc.parent;
+
+ if (descs[num_desc - 1].pin_start + descs[num_desc - 1].pin_cnt > sfp->npins) {
+ dev_err(dev, "layout %u pin_start[%u] + pin_cnt[%u] exceeds pin number[%u]\n",
+ num_desc - 1, descs[num_desc - 1].pin_start,
+ descs[num_desc - 1].pin_cnt, sfp->npins);
+ return -EINVAL;
+ }
+
+ for (int i = 0; i < num_desc; i++) {
+ if (descs[i].pin_start == 0xff)
+ break;
+
+ if (i < num_desc - 1) {
+ if (descs[i].pin_start + descs[i].pin_cnt > descs[i + 1].pin_start) {
+ dev_err(dev, "pin range: [%u-%u] overlaps with [%u-%u]\n",
+ descs[i].pin_start, descs[i].pin_cnt,
+ descs[i + 1].pin_start, descs[i + 1].pin_cnt);
+ return -EINVAL;
+ }
+
+ if (descs[i].pin_start + descs[i].pin_cnt < descs[i + 1].pin_start) {
+ dev_err(dev, "pin range: [%u-%u] -> [%u-%u] has gap\n",
+ descs[i].pin_start, descs[i].pin_cnt,
+ descs[i + 1].pin_start, descs[i + 1].pin_cnt);
+ return -EINVAL;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int check_pinctrl_layouts(struct jhb100_pinctrl *sfp,
+ const struct config_reg_layout_desc *layouts)
+{
+ struct device *dev = sfp->gc.parent;
+ int i = 0, err_cnt = 0, ret;
+
+ if (!layouts) {
+ dev_err(dev, "layout pointer is NULL\n");
+ return -EINVAL;
+ }
+
+ while (layouts[i].pin_start != 0xff) {
+ ret = check_crl_desc(sfp, i, &layouts[i]);
+ if (ret) {
+ dev_err(dev, "layout %d check failed\n", i);
+ err_cnt++;
+ }
+
+ if (++i > 100) {
+ dev_err(dev, "too many layouts or missing 0xff for end\n");
+ return -EINVAL;
+ }
+ }
+
+ if (!err_cnt) {
+ ret = check_layout_pin_range(sfp, layouts, i);
+ if (ret)
+ err_cnt++;
+ }
+
+ if (err_cnt) {
+ dev_err(dev, "pinctrl layout check finish with %d error(s)\n", err_cnt);
+ return -EINVAL;
+ }
+
+ dev_info(dev, "pinctrl layout check completed!\n");
+ return 0;
+}
+
+static
+struct pinctrl_pin_desc *devm_create_pins_from_pld(struct device *dev,
+ const struct jhb100_pin_layout_desc *desc,
+ const char *prefix,
+ unsigned int *total_pins,
+ unsigned int *total_gpios,
+ int **gpio_func_sel_arr)
+{
+ struct pinctrl_pin_desc *pins = NULL;
+ unsigned int i, j, ngpios = 0, npins = 0, pin_index = 0;
+ unsigned int same_name_found = 0;
+ int *arr;
+
+ if (!dev || !desc || !prefix) {
+ dev_err(dev, "Invalid parameters: desc=%p, prefix=%s\n",
+ desc, prefix);
+ return ERR_PTR(-EINVAL);
+ }
+
+ for (i = 0; desc[i].pin_start != 0xff; i++) {
+ if (!desc[i].pin_cnt) {
+ dev_err(dev, "Invalid pin cnt\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ npins += desc[i].pin_cnt;
+ }
+
+ if (npins == 0) {
+ dev_err(dev, "No pins defined\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ dev_dbg(dev, "Total pins to create: %d\n", npins);
+
+ pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
+ if (!pins)
+ return ERR_PTR(-ENOMEM);
+
+ arr = devm_kzalloc(dev, npins, GFP_KERNEL);
+ if (!arr)
+ return ERR_PTR(-ENOMEM);
+
+ for (i = 0; desc[i].pin_start != 0xff; i++) {
+ same_name_found = 0;
+
+ for (j = 0; j < i; j++) {
+ if (!strcmp(desc[j].name, desc[i].name)) {
+ same_name_found = 1;
+ break;
+ }
+ }
+
+ for (j = 0; j < desc[i].pin_cnt; j++) {
+ char *name = NULL;
+ int pin_num = desc[i].pin_start + j;
+
+ pins[pin_index].number = pin_num;
+ if (same_name_found) {
+ name = devm_kasprintf(dev, GFP_KERNEL, "%s_%s_%d",
+ prefix, desc[i].name,
+ desc[i].pin_start + j);
+ } else {
+ if (desc[i].pin_cnt > 1)
+ name = devm_kasprintf(dev, GFP_KERNEL, "%s_%s_%d",
+ prefix, desc[i].name, j);
+ else
+ name = devm_kasprintf(dev, GFP_KERNEL, "%s_%s",
+ prefix, desc[i].name);
+ }
+
+ if (!name) {
+ dev_err(dev, "Failed to allocate pin name for pin %d\n",
+ pin_num);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ if (!strcmp(desc[i].name, "gpio") || desc[i].gpio_func_sel != -1)
+ ngpios++;
+
+ pins[pin_index].name = name;
+ arr[pin_index] = desc[i].gpio_func_sel;
+ pin_index++;
+ }
+ }
+
+ *total_pins = npins;
+ *total_gpios = ngpios;
+ *gpio_func_sel_arr = arr;
+
+ return pins;
+}
+
+static int of_pinvref_get(struct device *dev, const struct pinvref_desc *pv_desc, u32 *val)
+{
+ char prop_name[32];
+ struct device_node *np = dev->of_node;
+ int ret;
+
+ snprintf(prop_name, sizeof(prop_name), "%s-vref", pv_desc->name);
+ dev_dbg(dev, "Looking up %s from node %pOF\n", prop_name, np);
+
+ ret = of_property_read_u32(np, prop_name, val);
+ if (ret) {
+ dev_err(dev, "Looking up %s in node %pOF failed: %d\n", prop_name, np, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int starfive_pinvref_set(struct device *dev, void __iomem *reg,
+ unsigned int val, const struct pinvref_desc *pv_desc)
+{
+ if (!pv_desc->range)
+ return 0;
+
+ if (pv_desc->range & BIT(val)) {
+ writel(val, reg);
+ } else {
+ dev_err(dev, "pin vref range is unsupported(%lx/%x)\n", BIT(val), pv_desc->range);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int starfive_pinvref_init(struct device *dev, void __iomem *base,
+ struct starfive_pinctrl_regs *pinctrl_regs)
+{
+ int ret = 0;
+ unsigned int val, i = 0;
+ struct pinvref_reg *vref;
+
+ vref = &pinctrl_regs->vref;
+ if (!vref->pv_desc)
+ return ret;
+
+ while (vref->pv_desc[i].name) {
+ ret = of_pinvref_get(dev, &vref->pv_desc[i], &val);
+ if (!ret)
+ ret = starfive_pinvref_set(dev, base + vref->reg + i * 4,
+ val, &vref->pv_desc[i]);
+ i++;
+ }
+
+ return ret;
+}
+
+int jhb100_pinctrl_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct gpio_irq_chip *girq;
+ const struct jhb100_pinctrl_domain_info *info;
+ struct jhb100_pinctrl *sfp;
+ struct pinctrl_desc *jhb100_pinctrl_desc;
+ struct reset_control *rst;
+ struct clk *clk;
+ int ret;
+
+ info = of_device_get_match_data(&pdev->dev);
+ if (!info)
+ return -ENODEV;
+
+ sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
+ if (!sfp)
+ return -ENOMEM;
+
+ sfp->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(sfp->base))
+ return PTR_ERR(sfp->base);
+
+ clk = devm_clk_get_optional_enabled(dev, NULL);
+ if (IS_ERR(clk))
+ return dev_err_probe(dev, PTR_ERR(clk), "could not get & enable clock\n");
+
+ rst = devm_reset_control_array_get_optional_shared(dev);
+ if (IS_ERR(rst))
+ return dev_err_probe(dev, PTR_ERR(rst), "could not get reset control\n");
+
+ /*
+ * we don't want to assert reset and risk undoing pin muxing for the
+ * early boot serial console, but let's make sure the reset line is
+ * deasserted in case someone runs a really minimal bootloader.
+ */
+ ret = reset_control_deassert(rst);
+ if (ret)
+ return dev_err_probe(dev, ret, "could not deassert reset\n");
+
+ sfp->pins = devm_create_pins_from_pld(dev, info->pl_desc, info->name,
+ &sfp->npins, &sfp->ngpios,
+ &sfp->gpio_func_sel_arr);
+ if (IS_ERR(sfp->pins))
+ return PTR_ERR(sfp->pins);
+
+ jhb100_pinctrl_desc = devm_kzalloc(&pdev->dev,
+ sizeof(*jhb100_pinctrl_desc),
+ GFP_KERNEL);
+ if (!jhb100_pinctrl_desc)
+ return -ENOMEM;
+
+ jhb100_pinctrl_desc->name = dev_name(dev);
+ jhb100_pinctrl_desc->num_custom_params = ARRAY_SIZE(jhb100_custom_bindings);
+ jhb100_pinctrl_desc->custom_params = jhb100_custom_bindings;
+ jhb100_pinctrl_desc->pctlops = &jhb100_pinctrl_ops;
+ jhb100_pinctrl_desc->pmxops = &jhb100_pinmux_ops;
+ jhb100_pinctrl_desc->confops = &jhb100_pinconf_ops;
+ jhb100_pinctrl_desc->owner = THIS_MODULE;
+ jhb100_pinctrl_desc->pins = sfp->pins;
+ jhb100_pinctrl_desc->npins = sfp->npins;
+
+ sfp->info = info;
+ sfp->dev = dev;
+ platform_set_drvdata(pdev, sfp);
+ sfp->gc.parent = dev;
+ raw_spin_lock_init(&sfp->lock);
+ mutex_init(&sfp->mutex);
+
+ ret = devm_pinctrl_register_and_init(dev, jhb100_pinctrl_desc,
+ sfp, &sfp->pctl);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "could not register pinctrl driver\n");
+
+ sfp->gc.label = dev_name(dev);
+ sfp->gc.owner = THIS_MODULE;
+ sfp->gc.request = pinctrl_gpio_request;
+ sfp->gc.free = pinctrl_gpio_free;
+ sfp->gc.get_direction = jhb100_gpio_get_direction;
+ sfp->gc.direction_input = jhb100_gpio_direction_input;
+ sfp->gc.direction_output = jhb100_gpio_direction_output;
+ sfp->gc.get = jhb100_gpio_get;
+ sfp->gc.set = jhb100_gpio_set;
+ sfp->gc.set_config = gpiochip_generic_config;
+ sfp->gc.base = info->gc_base;
+ sfp->gc.ngpio = sfp->ngpios;
+
+ girq = &sfp->gc.irq;
+
+ if (info->regs->irq_edge.reg) {
+ gpio_irq_chip_set_chip(girq, &jhb100_irq_chip);
+ girq->parent_handler = jhb100_gpio_irq_handler;
+ girq->num_parents = 1;
+ girq->parents = devm_kcalloc(dev, girq->num_parents,
+ sizeof(*girq->parents),
+ GFP_KERNEL);
+ if (!girq->parents)
+ return -ENOMEM;
+
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_bad_irq;
+ girq->init_hw = jhb100_gpio_init_hw;
+
+ ret = platform_get_irq(pdev, 0);
+ if (ret < 0)
+ return ret;
+
+ girq->parents[0] = ret;
+ }
+
+ ret = pinctrl_enable(sfp->pctl);
+ if (ret)
+ return ret;
+
+ if (sfp->gc.ngpio > 0) {
+ ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
+ if (ret)
+ return dev_err_probe(dev, ret, "could not register gpiochip\n");
+
+ dev_info(dev, "StarFive JHB100 GPIO chip registered %d GPIOs\n",
+ sfp->gc.ngpio);
+ }
+
+ ret = check_pinctrl_layouts(sfp, info->crl_desc);
+ if (ret)
+ return ret;
+
+ ret = starfive_pinvref_init(dev, sfp->base, info->regs);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(jhb100_pinctrl_probe);
+
+MODULE_DESCRIPTION("Pinctrl driver for the StarFive JHB100 SoC");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.h b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.h
new file mode 100644
index 000000000000..a5e7c788ba13
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#ifndef __PINCTRL_STARFIVE_JHB100_H__
+#define __PINCTRL_STARFIVE_JHB100_H__
+
+#include <linux/gpio/driver.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "../core.h"
+
+#define PER2_GMAC_RGMII_FUNC 1
+#define PER2_GMAC_RMII_FUNC 2
+#define PER3_GMAC_RMII_FUNC 1
+
+/* mode select */
+#define JHB100_PUSH_PULL 0
+#define JHB100_OPEN_DRAIN 1
+#define JHB100_LEGACY_FAST_MODE_PLUS 2
+#define JHB100_LEGACY_FAST_MODE 3
+
+/* i2c open-drain pull-up select */
+#define JHB100_I2C_OPEN_DRAIN_PU_600_OHMS 0
+#define JHB100_I2C_OPEN_DRAIN_PU_900_OHMS 1
+#define JHB100_I2C_OPEN_DRAIN_PU_1200_OHMS 2
+#define JHB100_I2C_OPEN_DRAIN_PU_2000_OHMS 3
+
+struct jhb100_pin_layout_desc {
+ unsigned int pin_start;
+ unsigned int pin_cnt;
+ const char *name;
+ int gpio_func_sel;
+};
+
+struct jhb100_pinctrl {
+ struct device *dev;
+ struct gpio_chip gc;
+ struct pinctrl_gpio_range gpios;
+ raw_spinlock_t lock;
+ const char *iodomain_name;
+ void __iomem *base;
+ struct pinctrl_dev *pctl;
+ /* register read/write mutex */
+ struct mutex mutex;
+ const struct jhb100_pinctrl_domain_info *info;
+ /* wakeup */
+ int wakeup_gpio;
+ int wakeup_irq;
+ struct irq_domain *irq_domain;
+ const struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+ unsigned int ngpios;
+ int *gpio_func_sel_arr;
+};
+
+/* pinref voltage range */
+#define JHB100_PINVREF_3_3V 0
+#define JHB100_PINVREF_2_5V 1
+#define JHB100_PINVREF_1_8V 2
+
+struct pinvref_desc {
+ const char *name;
+ unsigned int range;
+};
+
+struct pinvref_reg {
+ unsigned int reg;
+ const struct pinvref_desc *pv_desc;
+};
+
+struct gpio_irq_reg {
+ unsigned int reg;
+ unsigned int width_per_pin;
+};
+
+struct starfive_pinctrl_regs {
+ struct pinvref_reg vref;
+ struct gpio_irq_reg config;
+ struct gpio_irq_reg output;
+ struct gpio_irq_reg output_en;
+ struct gpio_irq_reg func_sel;
+ struct gpio_irq_reg gpio_status;
+ struct gpio_irq_reg irq_en;
+ struct gpio_irq_reg irq_status;
+ struct gpio_irq_reg irq_clr;
+ struct gpio_irq_reg irq_trigger;
+ struct gpio_irq_reg irq_level;
+ struct gpio_irq_reg irq_both_edge;
+ struct gpio_irq_reg irq_edge;
+};
+
+struct reg_layout_field {
+ unsigned char shift;
+ unsigned char width;
+ unsigned int func;
+};
+
+#define RL_DESC_SUPPORTED(crl_desc, field) ({ \
+ typeof(crl_desc) _desc = (crl_desc); \
+ (_desc && _desc->field.width > 0); \
+})
+
+#define RL_DESC_SHIFT(crl_desc, field) ({ \
+ typeof(crl_desc) __desc = (crl_desc); \
+ __desc->field.shift; \
+})
+
+#define RL_DESC_GENMASK(crl_desc, field) ({ \
+ typeof(crl_desc) __desc = (crl_desc); \
+ RL_DESC_SUPPORTED(__desc, field) ? \
+ GENMASK(__desc->field.shift + __desc->field.width - 1, __desc->field.shift) : 0; \
+})
+
+#define RL_DESC_SUPPORTED_FUNC(crl_desc, field, pinfunc) ({ \
+ typeof(crl_desc) _desc = (crl_desc); \
+ (_desc && _desc->field.width > 0 && \
+ (!_desc->field.func || (_desc->field.func & pinfunc))); \
+})
+
+struct config_reg_layout_desc {
+ unsigned int pin_start;
+ unsigned int pin_cnt;
+
+ struct reg_layout_field debounce_width;
+ struct reg_layout_field drive_strength_2bit;
+ struct reg_layout_field drive_strength_3bit;
+ struct reg_layout_field function;
+ struct reg_layout_field input_enable;
+ struct reg_layout_field vsel;
+ struct reg_layout_field mode_select;
+ struct reg_layout_field open_drain_pull_up_sel;
+ struct reg_layout_field pull_down;
+ struct reg_layout_field pull_up;
+ struct reg_layout_field reserved;
+ struct reg_layout_field retention_signal_bus;
+ struct reg_layout_field schmitt_trigger_select;
+ struct reg_layout_field slew_rate;
+};
+
+struct funcsel_reg_layout_desc {
+ unsigned int pin_start;
+ unsigned int pin_cnt;
+ unsigned int width;
+};
+
+struct jhb100_pinctrl_domain_info {
+ const char *name;
+ unsigned int gc_base;
+ const struct pinctrl_pin_desc *pins;
+ const struct jhb100_pin_layout_desc *pl_desc;
+ struct config_reg_layout_desc *crl_desc;
+ struct starfive_pinctrl_regs *regs;
+};
+
+static inline irq_hw_number_t pin_to_hwirq(struct jhb100_pinctrl *sfp)
+{
+ return sfp->wakeup_gpio - sfp->info->gc_base;
+}
+
+int jhb100_pinctrl_probe(struct platform_device *pdev);
+
+void pinctrl_utils_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map, unsigned int num_maps);
+int pinmux_generic_get_function_count(struct pinctrl_dev *pctldev);
+const char *pinmux_generic_get_function_name(struct pinctrl_dev *pctldev,
+ unsigned int selector);
+int pinmux_generic_get_function_groups(struct pinctrl_dev *pctldev,
+ unsigned int selector,
+ const char * const **groups,
+ unsigned int * const num_groups);
+int pinmux_generic_add_function(struct pinctrl_dev *pctldev,
+ const char *name,
+ const char * const *groups,
+ unsigned int const num_groups,
+ void *data);
+
+#if defined(CONFIG_GENERIC_PINCONF) && defined(CONFIG_OF)
+int pinconf_generic_parse_dt_config(struct device_node *np,
+ struct pinctrl_dev *pctldev,
+ unsigned long **configs,
+ unsigned int *nconfigs);
+#endif
+
+#endif /* __PINCTRL_STARFIVE_JHB100_H__ */
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH v1 02/20] pinctrl: starfive: Add StarFive JHB100 sys0 controller driver
2026-04-24 11:13 ` [PATCH v1 02/20] pinctrl: starfive: Add StarFive JHB100 sys0 controller driver Changhuang Liang
@ 2026-04-28 10:29 ` Linus Walleij
0 siblings, 0 replies; 34+ messages in thread
From: Linus Walleij @ 2026-04-28 10:29 UTC (permalink / raw)
To: Changhuang Liang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski, linux-gpio,
linux-kernel, devicetree, linux-riscv, Lianfeng Ouyang
Hi Changhuang,
thanks for your patch!
On Fri, Apr 24, 2026 at 1:13 PM Changhuang Liang
<changhuang.liang@starfivetech.com> wrote:
> Add pinctrl driver for StarFive JHB100 SoC System-0(sys0) pinctrl
> controller.
>
> Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
(...)
> +config PINCTRL_STARFIVE_JHB100
> + bool
> + select GENERIC_PINCONF
> + select GENERIC_PINCTRL_GROUPS
> + select GENERIC_PINMUX_FUNCTIONS
Neat that you use the generic stuff!
> +#include <linux/pinctrl/consumer.h>
Do you really need the consumer header?
> +/* Custom pinconf parameters */
> +#define STARFIVE_PIN_CONFIG_GMAC_VSEL (PIN_CONFIG_END + 1)
> +#define STARFIVE_PIN_CONFIG_DEBOUNCE_WIDTH (PIN_CONFIG_END + 2)
Hm I wonder about this...
> +#define STARFIVE_PIN_DRIVE_I2C_FAST_MODE (PIN_CONFIG_END + 3)
> +#define STARFIVE_PIN_DRIVE_I2C_FAST_MODE_PLUS (PIN_CONFIG_END + 4)
> +#define STARFIVE_PIN_OPEN_DRAIN_PULLUP_SELECT (PIN_CONFIG_END + 5)
But the existing pullup already takes an argument. This looks wrong.
> +static const struct pinconf_generic_params jhb100_custom_bindings[] = {
> + { "starfive,gmac-vsel", STARFIVE_PIN_CONFIG_GMAC_VSEL, 0 },
Can't you use the existing "power-source" instead? It's fine if it's only
applicable to a few pins. This is overly specific.
> + { "starfive,debounce-width", STARFIVE_PIN_CONFIG_DEBOUNCE_WIDTH, 0 },
Don't know about this... sounds like the argument to the existing
input-debounce which is expressed in microseconds. Just recalculate
that value to your "width"?
> + { "starfive,drive-i2c-fast-mode", STARFIVE_PIN_DRIVE_I2C_FAST_MODE, 0 },
> + { "starfive,drive-i2c-fast-mode-plus", STARFIVE_PIN_DRIVE_I2C_FAST_MODE_PLUS, 0 },
It's not special that things are for i2c. Use the generic
slew-rate for these two, it describes how fast something is.
> + { "starfive,i2c-open-drain-pull-up-ohm", STARFIVE_PIN_OPEN_DRAIN_PULLUP_SELECT, 0 },
Use the existing drive-open-drain; with the exitsing bias-pull-up = <ohms>;
two properties. No need to be fancy and create a new property for this.
> + { "starfive,vga-rte", STARFIVE_PIN_VGA_RTE_SELECT, 0 },
No idea what this is...
> +static int jhb100_dt_node_to_map(struct pinctrl_dev *pctldev,
> + struct device_node *np,
> + struct pinctrl_map **maps,
> + unsigned int *num_maps)
Long complicated function. Try to use the generic helper instead and
extend it if need be.
> +static void jhb100_dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map,
> + unsigned int num_maps)
Use the generic helper instead.
> +static const struct pinctrl_ops jhb100_pinctrl_ops = {
> + .get_groups_count = pinctrl_generic_get_group_count,
> + .get_group_name = pinctrl_generic_get_group_name,
> + .get_group_pins = pinctrl_generic_get_group_pins,
> + .dt_node_to_map = jhb100_dt_node_to_map,
> + .dt_free_map = jhb100_dt_free_map,
Maybe the need for this goes away if you just use the generic properties
instead?
> +static void jhb100_set_gpioval(struct jhb100_pinctrl *sfp, unsigned int pin,
> + unsigned int val)
> +{
> + const struct jhb100_pinctrl_domain_info *info = sfp->info;
> + unsigned int offset = 4 * (pin / 32);
> + unsigned int shift = 1 * (pin % 32);
> + unsigned int fs_offset = 4 * (pin / 16);
> + unsigned int fs_shift = 2 * (pin % 16);
All of these are signs that the GPIOs are "banked" into 32
GPIOs per bank, and I think the chips get simpler and easier
to use if they get split into threecell DT phandles.
> +static int jhb100_gpio_get_direction(struct gpio_chip *gc,
> + unsigned int gpio)
> +{
> + struct jhb100_pinctrl *sfp = container_of(gc, struct jhb100_pinctrl, gc);
> + const struct jhb100_pinctrl_domain_info *info = sfp->info;
> + unsigned int offset = 4 * (gpio / 32);
> + unsigned int shift = 1 * (gpio % 32);
Here too.
> +static void jhb100_gpio_irq_handler(struct irq_desc *desc)
> +{
> + struct jhb100_pinctrl *sfp = jhb100_from_irq_desc(desc);
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> + struct gpio_irq_chip *girq = &sfp->gc.irq;
> + struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
> + unsigned long is;
> + unsigned int pin;
> + unsigned int total, size, remain = sfp->npins;
> +
> + chained_irq_enter(chip, desc);
> +
> + for (total = 0, size = 0; total < sfp->npins; total += 32, remain -= size) {
> + is = readl_relaxed(sfp->base + pinctrl_regs->irq_status.reg +
> + (total >> 3));
> + size = umin(remain, 32);
> +
> + for_each_set_bit(pin, &is, size) {
> + if (sfp->gpio_func_sel_arr[pin] >= 0)
> + generic_handle_domain_irq(girq->domain, pin);
> + }
> + }
> +
> + chained_irq_exit(chip, desc);
> +}
And since the IRQs are groups per 32 pins I think this will become much
easier if you break the GPIOs into banks.
(...)
> +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.h
> +struct starfive_pinctrl_regs {
> + struct pinvref_reg vref;
> + struct gpio_irq_reg config;
> + struct gpio_irq_reg output;
> + struct gpio_irq_reg output_en;
> + struct gpio_irq_reg func_sel;
> + struct gpio_irq_reg gpio_status;
> + struct gpio_irq_reg irq_en;
> + struct gpio_irq_reg irq_status;
> + struct gpio_irq_reg irq_clr;
> + struct gpio_irq_reg irq_trigger;
> + struct gpio_irq_reg irq_level;
> + struct gpio_irq_reg irq_both_edge;
> + struct gpio_irq_reg irq_edge;
> +};
If you want to keep a cache of all registers around, use regmap-mmio.
> +int jhb100_pinctrl_probe(struct platform_device *pdev);
> +
> +void pinctrl_utils_free_map(struct pinctrl_dev *pctldev,
> + struct pinctrl_map *map, unsigned int num_maps);
> +int pinmux_generic_get_function_count(struct pinctrl_dev *pctldev);
> +const char *pinmux_generic_get_function_name(struct pinctrl_dev *pctldev,
> + unsigned int selector);
> +int pinmux_generic_get_function_groups(struct pinctrl_dev *pctldev,
> + unsigned int selector,
> + const char * const **groups,
> + unsigned int * const num_groups);
> +int pinmux_generic_add_function(struct pinctrl_dev *pctldev,
> + const char *name,
> + const char * const *groups,
> + unsigned int const num_groups,
> + void *data);
> +
> +#if defined(CONFIG_GENERIC_PINCONF) && defined(CONFIG_OF)
> +int pinconf_generic_parse_dt_config(struct device_node *np,
> + struct pinctrl_dev *pctldev,
> + unsigned long **configs,
> + unsigned int *nconfigs);
> +#endif
Why is there a copy of the generic function headers here?
It looks wrong.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v1 03/20] dt-bindings: pinctrl: Add starfive,jhb100-sys0h-pinctrl
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
2026-04-24 11:13 ` [PATCH v1 01/20] dt-bindings: pinctrl: Add starfive,jhb100-sys0-pinctrl Changhuang Liang
2026-04-24 11:13 ` [PATCH v1 02/20] pinctrl: starfive: Add StarFive JHB100 sys0 controller driver Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-24 11:13 ` [PATCH v1 04/20] pinctrl: starfive: Add StarFive JHB100 sys0h controller driver Changhuang Liang
` (17 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC System-0 host(sys0h) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../starfive,jhb100-sys0h-pinctrl.yaml | 156 ++++++++++++++++++
1 file changed, 156 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0h-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0h-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0h-pinctrl.yaml
new file mode 100644
index 000000000000..fffaa8a0db0e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0h-pinctrl.yaml
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys0h-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 System-0 Host Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "sys0h" pinctrl domain.
+
+ The "sys0h" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the SYS0H Pin Controller, there are 12 multi-function GPIO_PADs. Each of them can be
+ multiplexed to different hardware blocks through function selection. Each iopad has a maximum
+ of up to 3 functions - 0, 1, 2, and 3. Function 0 is the default function which is generally
+ the GPIO function (or occasionally, it can be a peripheral signal). Functions 1, 2, and 3 are
+ the alternate functions or peripheral signals that can be routed to the iopad.
+ The function selection can be carried out by writing the function number to the iopad function
+ select register.
+ Each iopad is configurable with parameters such as input-enable, internal pull-up/pull-down
+ bias, drive strength, schmitt trigger, slew rate, and debounce width.
+
+maintainers:
+ - Alex Soo <yuklin.soo@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-sys0h-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ gpio-line-names: true
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate and drive strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ unevaluatedProperties: false
+
+ properties:
+ pinmux:
+ description: |
+ The list of GPIOs and their function select.
+ The PINMUX macros are used to configure the
+ function selection.
+
+ bias-disable: true
+
+ bias-pull-up:
+ type: boolean
+
+ bias-pull-down:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-enable: true
+
+ input-disable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow (half frequency)
+ 1: fast
+
+ starfive,debounce-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ description:
+ Debounce width 0 = Disabled, Others = 80ns*N stages
+
+required:
+ - compatible
+ - reg
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_sys0h: pinctrl@13080800 {
+ compatible = "starfive,jhb100-sys0h-pinctrl";
+ reg = <0x0 0x13080800 0x0 0x800>;
+ resets = <&sys0crg 3>;
+ interrupts = <57>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_sys0h 0 0 12>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v1 04/20] pinctrl: starfive: Add StarFive JHB100 sys0h controller driver
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (2 preceding siblings ...)
2026-04-24 11:13 ` [PATCH v1 03/20] dt-bindings: pinctrl: Add starfive,jhb100-sys0h-pinctrl Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-24 11:13 ` [PATCH v1 05/20] dt-bindings: pinctrl: Add starfive,jhb100-sys1-pinctrl Changhuang Liang
` (16 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC System-0 Host(sys0h) pinctrl
controller.
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 12 +++
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-sys0h.c | 81 +++++++++++++++++++
3 files changed, 94 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0h.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index dc53070ee2c8..8739ed1ca350 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -70,3 +70,15 @@ config PINCTRL_STARFIVE_JHB100_SYS0
This also provides an interface to the GPIO pins not used by other
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+
+config PINCTRL_STARFIVE_JHB100_SYS0H
+ tristate "StarFive JHB100 SoC System-0 Host pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ depends on OF
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support System-0 Host pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index c0d368f413bc..b26156a6d0eb 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0h.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0h.c
new file mode 100644
index 000000000000..42fbbcd92550
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0h.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC System-0 host domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+static const struct jhb100_pin_layout_desc jhb100_sys0h_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 7, .name = "gpio", .gpio_func_sel = 0 },
+ { .pin_start = 7, .pin_cnt = 1, .name = "espi0_reset", .gpio_func_sel = 1 },
+ { .pin_start = 8, .pin_cnt = 4, .name = "gpio", .gpio_func_sel = 0 },
+ { 0xff },
+};
+
+static struct config_reg_layout_desc jhb100_sys0h_pinctrl_rl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 12,
+ .drive_strength_2bit = { .shift = 0, .width = 2 },
+ .input_enable = { .shift = 2, .width = 1 },
+ .pull_down = { .shift = 3, .width = 1 },
+ .pull_up = { .shift = 4, .width = 1 },
+ .slew_rate = { .shift = 5, .width = 1 },
+ .schmitt_trigger_select = { .shift = 6, .width = 1 },
+ .reserved = { .shift = 7, .width = 8 },
+ .debounce_width = { .shift = 15, .width = 17 },
+ },
+ { 0xff },
+};
+
+struct starfive_pinctrl_regs jhb100_sys0h_pinctrl_regs = {
+ .config = { .reg = 0x04, .width_per_pin = 1 },
+ .output = { .reg = 0x34, .width_per_pin = 1 },
+ .output_en = { .reg = 0x38, .width_per_pin = 1 },
+ .gpio_status = { .reg = 0x3c, .width_per_pin = 1 },
+ .func_sel = { .reg = 0x40, .width_per_pin = 2 },
+ .irq_en = { .reg = 0x44, .width_per_pin = 1 },
+ .irq_status = { .reg = 0x48, .width_per_pin = 1 },
+ .irq_clr = { .reg = 0x4c, .width_per_pin = 1 },
+ .irq_trigger = { .reg = 0x50, .width_per_pin = 1 },
+ .irq_level = { .reg = 0x54, .width_per_pin = 1 },
+ .irq_both_edge = { .reg = 0x58, .width_per_pin = 1 },
+ .irq_edge = { .reg = 0x5c, .width_per_pin = 1 },
+};
+
+static struct jhb100_pinctrl_domain_info jhb100_sys0h_pinctrl_info = {
+ .name = "jhb100-sys0h",
+ .gc_base = -1,
+ .pl_desc = jhb100_sys0h_pl_desc,
+ .crl_desc = jhb100_sys0h_pinctrl_rl_desc,
+ .regs = &jhb100_sys0h_pinctrl_regs,
+};
+
+static const struct of_device_id jhb100_sys0h_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-sys0h-pinctrl",
+ .data = &jhb100_sys0h_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_sys0h_pinctrl_of_match);
+
+static struct platform_driver jhb100_sys0h_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-sys0h-pinctrl",
+ .of_match_table = jhb100_sys0h_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_sys0h_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC System-0 host domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v1 05/20] dt-bindings: pinctrl: Add starfive,jhb100-sys1-pinctrl
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (3 preceding siblings ...)
2026-04-24 11:13 ` [PATCH v1 04/20] pinctrl: starfive: Add StarFive JHB100 sys0h controller driver Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-24 11:13 ` [PATCH v1 06/20] pinctrl: starfive: Add StarFive JHB100 sys1 controller driver Changhuang Liang
` (15 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC System-1(sys1) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../pinctrl/starfive,jhb100-sys1-pinctrl.yaml | 155 ++++++++++++++++++
1 file changed, 155 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys1-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys1-pinctrl.yaml
new file mode 100644
index 000000000000..b297f48ecdf8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys1-pinctrl.yaml
@@ -0,0 +1,155 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys1-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 System-1 Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "sys1" pinctrl domain.
+
+ The "sys1" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the SYS1 Pin Controller, there are 8 multi-function GPIO_PADs. Each of them can be multiplexed
+ to different hardware blocks through function selection. Each iopad has a maximum of up to 4
+ functions - 0, 1, 2, and 3. Function 0 is the default function which is generally the GPIO function
+ (or occasionally, it can be a peripheral signal). Function 1, 2, and 3 are the alternate functions
+ or peripheral signals that can be routed to the iopad. The function selection can be carried
+ out by writing the function number to the iopad function select register.
+ Each iopad is configurable with parameters such as input-enable, internal pull-up/pull-down
+ bias, drive strength, schmitt trigger, slew rate, and debounce width.
+
+maintainers:
+ - Alex Soo <yuklin.soo@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-sys1-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ gpio-line-names: true
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate and drive strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ unevaluatedProperties: false
+
+ properties:
+ pinmux:
+ description: |
+ The list of GPIOs and their function select.
+ The PINMUX macros are used to configure the
+ function selection.
+
+ bias-disable: true
+
+ bias-pull-up:
+ type: boolean
+
+ bias-pull-down:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-enable: true
+
+ input-disable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow (half frequency)
+ 1: fast
+
+ starfive,debounce-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ description:
+ Debounce width 0 = Disabled, Others = 80ns*N stages
+
+required:
+ - compatible
+ - reg
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_sys1: pinctrl@13081000 {
+ compatible = "starfive,jhb100-sys1-pinctrl";
+ reg = <0x0 0x13081000 0x0 0x1000>;
+ resets = <&sys1crg 2>;
+ interrupts = <58>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_sys1 0 0 8>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v1 06/20] pinctrl: starfive: Add StarFive JHB100 sys1 controller driver
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (4 preceding siblings ...)
2026-04-24 11:13 ` [PATCH v1 05/20] dt-bindings: pinctrl: Add starfive,jhb100-sys1-pinctrl Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-24 11:13 ` [PATCH v1 07/20] dt-bindings: pinctrl: Add starfive,jhb100-sys2-pinctrl Changhuang Liang
` (14 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC System-1(sys1) pinctrl
controller.
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 12 +++
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-sys1.c | 80 +++++++++++++++++++
3 files changed, 93 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys1.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index 8739ed1ca350..fb1d4991800b 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -82,3 +82,15 @@ config PINCTRL_STARFIVE_JHB100_SYS0H
This also provides an interface to the GPIO pins not used by other
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+
+config PINCTRL_STARFIVE_JHB100_SYS1
+ tristate "StarFive JHB100 SoC System-1 pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ depends on OF
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support System-1 pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index b26156a6d0eb..8d96cf80d377 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys1.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys1.c
new file mode 100644
index 000000000000..1b24691eaa8b
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys1.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC System-1 domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+static const struct jhb100_pin_layout_desc jhb100_sys1_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 7, .name = "gpio", .gpio_func_sel = 0 },
+ { .pin_start = 7, .pin_cnt = 1, .name = "espi1_reset", .gpio_func_sel = 1 },
+ { 0xff },
+};
+
+static struct config_reg_layout_desc jhb100_sys1_pinctrl_rl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 8,
+ .drive_strength_2bit = { .shift = 0, .width = 2 },
+ .input_enable = { .shift = 2, .width = 1 },
+ .pull_down = { .shift = 3, .width = 1 },
+ .pull_up = { .shift = 4, .width = 1 },
+ .slew_rate = { .shift = 5, .width = 1 },
+ .schmitt_trigger_select = { .shift = 6, .width = 1 },
+ .reserved = { .shift = 7, .width = 8 },
+ .debounce_width = { .shift = 15, .width = 17 },
+ },
+ { 0xff },
+};
+
+struct starfive_pinctrl_regs jhb100_sys1_pinctrl_regs = {
+ .config = { .reg = 0x04, .width_per_pin = 1 },
+ .output = { .reg = 0x24, .width_per_pin = 1 },
+ .output_en = { .reg = 0x28, .width_per_pin = 1 },
+ .gpio_status = { .reg = 0x2c, .width_per_pin = 1 },
+ .func_sel = { .reg = 0x30, .width_per_pin = 2 },
+ .irq_en = { .reg = 0x34, .width_per_pin = 1 },
+ .irq_status = { .reg = 0x38, .width_per_pin = 1 },
+ .irq_clr = { .reg = 0x3c, .width_per_pin = 1 },
+ .irq_trigger = { .reg = 0x40, .width_per_pin = 1 },
+ .irq_level = { .reg = 0x44, .width_per_pin = 1 },
+ .irq_both_edge = { .reg = 0x48, .width_per_pin = 1 },
+ .irq_edge = { .reg = 0x4c, .width_per_pin = 1 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_sys1_pinctrl_info = {
+ .name = "jhb100-sys1",
+ .gc_base = -1,
+ .pl_desc = jhb100_sys1_pl_desc,
+ .crl_desc = jhb100_sys1_pinctrl_rl_desc,
+ .regs = &jhb100_sys1_pinctrl_regs,
+};
+
+static const struct of_device_id jhb100_sys1_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-sys1-pinctrl",
+ .data = &jhb100_sys1_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_sys1_pinctrl_of_match);
+
+static struct platform_driver jhb100_sys1_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-sys1-pinctrl",
+ .of_match_table = jhb100_sys1_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_sys1_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC System-1 domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v1 07/20] dt-bindings: pinctrl: Add starfive,jhb100-sys2-pinctrl
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (5 preceding siblings ...)
2026-04-24 11:13 ` [PATCH v1 06/20] pinctrl: starfive: Add StarFive JHB100 sys1 controller driver Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-25 10:28 ` Krzysztof Kozlowski
2026-04-24 11:13 ` [PATCH v1 08/20] pinctrl: starfive: Add StarFive JHB100 sys2 controller driver Changhuang Liang
` (13 subsequent siblings)
20 siblings, 1 reply; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC System-2(sys2) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../pinctrl/starfive,jhb100-sys2-pinctrl.yaml | 178 ++++++++++++++++++
1 file changed, 178 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml
new file mode 100644
index 000000000000..9decffaf0b72
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml
@@ -0,0 +1,178 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys2-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 System-2 Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "sys2" pinctrl domain.
+
+ The "sys2" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the SYS2 Pin Controller, there are 37 multi-function GPIO_PADs. Each of them can be
+ multiplexed to different hardware blocks through function selection. Each iopad has a maximum
+ of up to 4 functions - 0, 1, 2, and 3. Function 0 is the default function which is the GPIO
+ function. Function 1, 2, and 3 are the alternate functions or peripheral signals that can be
+ routed to the iopad. The function selection can be carried out by writing the function number
+ to the iopad function select register.
+ Each iopad is configurable with parameters such as input-enable, internal pull-up/pull-down
+ bias, drive strength, schmitt trigger, slew rate, and debounce width.
+
+ This domain contains an IO group which support voltage levels 1.8V and 3.3V
+ 1. gpiow - comprises PAD_GPIO_A36 through PAD_GPIO_A39.
+ 2. gpiow-inner - comprises PAD_GPIO_A40 through PAD_GPIO_A43.
+
+ This IO group must be configured with a voltage setting that matches the external voltage level
+ provided to the IO group.
+
+maintainers:
+ - Alex Soo <yuklin.soo@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-sys2-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ gpio-line-names: true
+
+ gpiow-vref:
+ default: 0
+ description: |
+ Voltage reference value for the IO group "gpiow"
+ 0: voltage reference value for 3.3V
+ 2: voltage reference value for 1.8V
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 2]
+
+ gpiow-inner-vref:
+ default: 0
+ description: |
+ Voltage reference value for the IO group "gpiow-inner"
+ 0: voltage reference value for 3.3V
+ 2: voltage reference value for 1.8V
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 2]
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate and drive strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ unevaluatedProperties: false
+
+ properties:
+ pinmux:
+ description: |
+ The list of GPIOs and their function select.
+ The PINMUX macros are used to configure the
+ function selection.
+
+ bias-disable: true
+
+ bias-pull-up:
+ type: boolean
+
+ bias-pull-down:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-enable: true
+
+ input-disable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow (half frequency)
+ 1: fast
+
+ starfive,debounce-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ description:
+ Debounce width 0 = Disabled, Others = 80ns*N stages
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_sys2: pinctrl@13082000 {
+ compatible = "starfive,jhb100-sys2-pinctrl";
+ reg = <0x0 0x13082000 0x0 0x1000>;
+ interrupts = <59>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_sys2 0 0 37>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH v1 07/20] dt-bindings: pinctrl: Add starfive,jhb100-sys2-pinctrl
2026-04-24 11:13 ` [PATCH v1 07/20] dt-bindings: pinctrl: Add starfive,jhb100-sys2-pinctrl Changhuang Liang
@ 2026-04-25 10:28 ` Krzysztof Kozlowski
0 siblings, 0 replies; 34+ messages in thread
From: Krzysztof Kozlowski @ 2026-04-25 10:28 UTC (permalink / raw)
To: Changhuang Liang
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski, linux-gpio,
linux-kernel, devicetree, linux-riscv, Lianfeng Ouyang
On Fri, Apr 24, 2026 at 04:13:17AM -0700, Changhuang Liang wrote:
> +description: |
> + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
> +
> + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
> + per2, per2pok, per3, adc0, adc1, emmc, and vga.
> + This document provides an overview of the "sys2" pinctrl domain.
> +
> + The "sys2" domain has a pin controller which provides
> + - function selection for GPIO pads.
> + - GPIO pad configuration.
> + - GPIO interrupt handling.
> +
> + In the SYS2 Pin Controller, there are 37 multi-function GPIO_PADs. Each of them can be
> + multiplexed to different hardware blocks through function selection. Each iopad has a maximum
> + of up to 4 functions - 0, 1, 2, and 3. Function 0 is the default function which is the GPIO
> + function. Function 1, 2, and 3 are the alternate functions or peripheral signals that can be
> + routed to the iopad. The function selection can be carried out by writing the function number
> + to the iopad function select register.
> + Each iopad is configurable with parameters such as input-enable, internal pull-up/pull-down
> + bias, drive strength, schmitt trigger, slew rate, and debounce width.
> +
> + This domain contains an IO group which support voltage levels 1.8V and 3.3V
> + 1. gpiow - comprises PAD_GPIO_A36 through PAD_GPIO_A39.
> + 2. gpiow-inner - comprises PAD_GPIO_A40 through PAD_GPIO_A43.
> +
> + This IO group must be configured with a voltage setting that matches the external voltage level
> + provided to the IO group.
Wrap at 80.
Please wrap code according to the preferred limit expressed in Kernel
coding style (checkpatch is not a coding style description, but only a
tool). However don't wrap blindly (see Kernel coding style).
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v1 08/20] pinctrl: starfive: Add StarFive JHB100 sys2 controller driver
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (6 preceding siblings ...)
2026-04-24 11:13 ` [PATCH v1 07/20] dt-bindings: pinctrl: Add starfive,jhb100-sys2-pinctrl Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-24 11:13 ` [PATCH v1 09/20] dt-bindings: pinctrl: Add starfive,jhb100-per0-pinctrl Changhuang Liang
` (12 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC System-2(sys2) pinctrl
controller.
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 12 ++
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-sys2.c | 109 ++++++++++++++++++
3 files changed, 122 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys2.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index fb1d4991800b..7d68cf6ebd90 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -94,3 +94,15 @@ config PINCTRL_STARFIVE_JHB100_SYS1
This also provides an interface to the GPIO pins not used by other
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+
+config PINCTRL_STARFIVE_JHB100_SYS2
+ tristate "StarFive JHB100 SoC System-2 pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ depends on OF
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support System-2 pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index 8d96cf80d377..b817ad93b91d 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS2) += pinctrl-starfive-jhb100-sys2.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys2.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys2.c
new file mode 100644
index 000000000000..7b2c7c30e29f
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys2.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC System-2 domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+static const struct jhb100_pin_layout_desc jhb100_sys2_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 37, .name = "gpio", .gpio_func_sel = 0 },
+ { .pin_start = 37, .pin_cnt = 1, .name = "jtag_tck", .gpio_func_sel = -1 },
+ { .pin_start = 38, .pin_cnt = 1, .name = "jtag_tresetn", .gpio_func_sel = -1 },
+ { .pin_start = 39, .pin_cnt = 1, .name = "jtag_tmc", .gpio_func_sel = -1 },
+ { .pin_start = 40, .pin_cnt = 1, .name = "jtag_tdi", .gpio_func_sel = -1 },
+ { .pin_start = 41, .pin_cnt = 1, .name = "jtag_tdo", .gpio_func_sel = -1 },
+ { .pin_start = 42, .pin_cnt = 1, .name = "jtag_hpd", .gpio_func_sel = -1 },
+ { 0xff },
+};
+
+static struct config_reg_layout_desc jhb100_sys2_pinctrl_rl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 37,
+ .drive_strength_2bit = { .shift = 0, .width = 2 },
+ .input_enable = { .shift = 2, .width = 1 },
+ .pull_down = { .shift = 3, .width = 1 },
+ .pull_up = { .shift = 4, .width = 1 },
+ .slew_rate = { .shift = 5, .width = 1 },
+ .schmitt_trigger_select = { .shift = 6, .width = 1 },
+ .reserved = { .shift = 7, .width = 8 },
+ .debounce_width = { .shift = 15, .width = 17 },
+ },
+ {
+ .pin_start = 37,
+ .pin_cnt = 5,
+ .drive_strength_2bit = { .shift = 0, .width = 2 },
+ .input_enable = { .shift = 2, .width = 1 },
+ .pull_down = { .shift = 3, .width = 1 },
+ .pull_up = { .shift = 4, .width = 1 },
+ .slew_rate = { .shift = 5, .width = 1 },
+ .schmitt_trigger_select = { .shift = 6, .width = 1 },
+ .reserved = { .shift = 7, .width = 25 },
+ },
+ { 0xff },
+};
+
+static const struct pinvref_desc pinvref_desc_sys2[] = {
+ {
+ .name = "gpiow",
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ {
+ .name = "gpiow-inner",
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ { NULL },
+};
+
+struct starfive_pinctrl_regs jhb100_sys2_pinctrl_regs = {
+ .vref = { .reg = 0x000, .pv_desc = pinvref_desc_sys2 },
+ .config = { .reg = 0x010, .width_per_pin = 1 },
+ .output = { .reg = 0x0bc, .width_per_pin = 1 },
+ .output_en = { .reg = 0x0c4, .width_per_pin = 1 },
+ .gpio_status = { .reg = 0x0cc, .width_per_pin = 1 },
+ .func_sel = { .reg = 0x0d4, .width_per_pin = 2 },
+ .irq_en = { .reg = 0x0e0, .width_per_pin = 1 },
+ .irq_status = { .reg = 0x0e8, .width_per_pin = 1 },
+ .irq_clr = { .reg = 0x0f0, .width_per_pin = 1 },
+ .irq_trigger = { .reg = 0x0f8, .width_per_pin = 1 },
+ .irq_level = { .reg = 0x100, .width_per_pin = 1 },
+ .irq_both_edge = { .reg = 0x108, .width_per_pin = 1 },
+ .irq_edge = { .reg = 0x110, .width_per_pin = 1 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_sys2_pinctrl_info = {
+ .name = "jhb100-sys2",
+ .gc_base = -1,
+ .pl_desc = jhb100_sys2_pl_desc,
+ .crl_desc = jhb100_sys2_pinctrl_rl_desc,
+ .regs = &jhb100_sys2_pinctrl_regs,
+};
+
+static const struct of_device_id jhb100_sys2_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-sys2-pinctrl",
+ .data = &jhb100_sys2_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_sys2_pinctrl_of_match);
+
+static struct platform_driver jhb100_sys2_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-sys2-pinctrl",
+ .of_match_table = jhb100_sys2_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_sys2_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC System-2 domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v1 09/20] dt-bindings: pinctrl: Add starfive,jhb100-per0-pinctrl
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (7 preceding siblings ...)
2026-04-24 11:13 ` [PATCH v1 08/20] pinctrl: starfive: Add StarFive JHB100 sys2 controller driver Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-24 11:13 ` [PATCH v1 10/20] pinctrl: starfive: Add StarFive JHB100 per0 controller driver Changhuang Liang
` (11 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC Peripheral-0(per0) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../pinctrl/starfive,jhb100-per0-pinctrl.yaml | 219 ++++++++++++++++++
1 file changed, 219 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml
new file mode 100644
index 000000000000..b69b9b21cac6
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml
@@ -0,0 +1,219 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per0-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 Peripheral-0 Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "per0" pinctrl domain.
+
+ The "per0" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the Peripheral-0 Pin Controller, there are 60 multi-function GPIO_PADs. Each of them
+ can be multiplexed to several hardware blocks through function selection. Each iopad
+ has a maximum of up to 3 functions - 0, 1, and 2. Function 0 is the default function
+ which is generally the GPIO function. Function 1 and 2 are the alternate function or
+ signal of an iopad. The function 1 and function 2 are other optional functions or
+ peripheral signals that can be routed to an iopad. The function selection can be carried
+ out by writing the function number to the iopad function select register.
+ Each iopad is configurable with parameters such as input-enable, internal pull-up/pull-down
+ bias, push-pull/Open-drain mode select, schmitt trigger, open-drain pull-up select,
+ and debounce width.
+
+ This domain contains 4 IO groups which support voltage levels 1.8V and 3.3V
+ gpioe-i3c0 - comprises PAD_GPIO_B8 through PAD_GPIO_B11, PAD_GPIO_B32, and PAD_GPIO_B33.
+ gpioe-i3c1 - comprises PAD_GPIO_B12 through PAD_GPIO_B15, PAD_GPIO_B34, and PAD_GPIO_B35.
+ gpioe-i3c2 - comprises PAD_GPIO_B16 through PAD_GPIO_B23.
+ gpioe-i3c4 - comprises PAD_GPIO_B36 through PAD_GPIO_B43.
+
+ Each of the above IO groups must be configured with a voltage setting that matches the external
+ voltage level provided to the IO group.
+
+maintainers:
+ - Alex Soo <yuklin.soo@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-per0-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ gpio-line-names: true
+
+ gpioe-i3c0-vref:
+ description: |
+ Voltage reference value for the IO group "gpioe-i3c0"
+ 0: voltage reference value for 3.3V
+ 2: voltage reference value for 1.8V
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 2]
+ default: 0
+
+ gpioe-i3c1-vref:
+ description: |
+ Voltage reference value for the IO group "gpioe-i3c1"
+ 0: voltage reference value for 3.3V
+ 2: voltage reference value for 1.8V
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 2]
+ default: 0
+
+ gpioe-i3c2-vref:
+ description: |
+ Voltage reference value for the IO group "gpioe-i3c2"
+ 0: voltage reference value for 3.3V
+ 2: voltage reference value for 1.8V
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 2]
+ default: 0
+
+ gpioe-i3c4-vref:
+ description: |
+ Voltage reference value for the IO group "gpioe-i3c4"
+ 0: voltage reference value for 3.3V
+ 2: voltage reference value for 1.8V
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 2]
+ default: 0
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate and drive strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ unevaluatedProperties: false
+
+ properties:
+ pinmux:
+ description: |
+ The list of GPIOs and their function select.
+ The PINMUX macros are used to configure the
+ function selection.
+
+ bias-disable: true
+
+ bias-pull-up:
+ type: boolean
+
+ bias-pull-down:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-enable: true
+
+ input-disable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow (half frequency)
+ 1: fast
+
+ starfive,debounce-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ description:
+ Debounce width 0 = Disabled, Others = 80ns*N stages
+
+ starfive,drive-i2c-fast-mode:
+ type: boolean
+ description:
+ Enable I2C fast mode drive
+
+ starfive,drive-i2c-fast-mode-plus:
+ type: boolean
+ description:
+ Enable I2C fast mode plus drive
+
+ starfive,i2c-open-drain-pull-up-ohm:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ open drain pull-up select
+ enum: [600, 900, 1200, 2000]
+ default: 600
+
+required:
+ - compatible
+ - reg
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_per0: pinctrl@11a0a000 {
+ compatible = "starfive,jhb100-per0-pinctrl";
+ reg = <0x0 0x11a0a000 0x0 0x1000>;
+ resets = <&per0crg 0>;
+ interrupts = <60>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per0 0 0 60>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v1 10/20] pinctrl: starfive: Add StarFive JHB100 per0 controller driver
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (8 preceding siblings ...)
2026-04-24 11:13 ` [PATCH v1 09/20] dt-bindings: pinctrl: Add starfive,jhb100-per0-pinctrl Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-24 11:13 ` [PATCH v1 11/20] dt-bindings: pinctrl: Add starfive,jhb100-per1-pinctrl Changhuang Liang
` (10 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC Peripheral-0(per0) pinctrl
controller.
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 12 +++
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-per0.c | 100 ++++++++++++++++++
3 files changed, 113 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per0.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index 7d68cf6ebd90..e5afd937c4a1 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -59,6 +59,18 @@ config PINCTRL_STARFIVE_JHB100
select GPIOLIB_IRQCHIP
select OF_GPIO
+config PINCTRL_STARFIVE_JHB100_PER0
+ tristate "StarFive JHB100 SoC Peripheral-0 pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ depends on OF
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support Peripheral-0 pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
+
config PINCTRL_STARFIVE_JHB100_SYS0
tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index b817ad93b91d..f2bb0c35a2a0 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_SYS) += pinctrl-starfive-jh7110-sys.o
obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per0.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per0.c
new file mode 100644
index 000000000000..bc708775d466
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per0.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC Peripheral-0 domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+static const struct jhb100_pin_layout_desc jhb100_per0_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 60, .name = "gpio", .gpio_func_sel = 0 },
+ { 0xff },
+};
+
+static struct config_reg_layout_desc jhb100_per0_pinctrl_rl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 60,
+ .input_enable = { .shift = 0, .width = 1 },
+ .mode_select = { .shift = 1, .width = 2 },
+ .pull_down = { .shift = 3, .width = 1 },
+ .pull_up = { .shift = 4, .width = 1 },
+ .open_drain_pull_up_sel = { .shift = 5, .width = 2 },
+ .schmitt_trigger_select = { .shift = 7, .width = 1 },
+ .reserved = { .shift = 8, .width = 7 },
+ .debounce_width = { .shift = 15, .width = 17 },
+ },
+ { 0xff },
+};
+
+static const struct pinvref_desc pinvref_desc_per0[] = {
+ {
+ .name = "gpioe-i3c0",
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ {
+ .name = "gpioe-i3c1",
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ {
+ .name = "gpioe-i3c2",
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ {
+ .name = "gpioe-i3c4",
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ { NULL },
+};
+
+struct starfive_pinctrl_regs jhb100_per0_pinctrl_regs = {
+ .vref = { .reg = 0x004, .pv_desc = pinvref_desc_per0 },
+ .config = { .reg = 0x014, .width_per_pin = 32 },
+ .output = { .reg = 0x104, .width_per_pin = 1 },
+ .output_en = { .reg = 0x10c, .width_per_pin = 1 },
+ .gpio_status = { .reg = 0x114, .width_per_pin = 1 },
+ .func_sel = { .reg = 0x11c, .width_per_pin = 2 },
+ .irq_en = { .reg = 0x12c, .width_per_pin = 1 },
+ .irq_status = { .reg = 0x134, .width_per_pin = 1 },
+ .irq_clr = { .reg = 0x13c, .width_per_pin = 1 },
+ .irq_trigger = { .reg = 0x144, .width_per_pin = 1 },
+ .irq_level = { .reg = 0x14c, .width_per_pin = 1 },
+ .irq_both_edge = { .reg = 0x154, .width_per_pin = 1 },
+ .irq_edge = { .reg = 0x15c, .width_per_pin = 1 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_per0_pinctrl_info = {
+ .name = "jhb100-per0",
+ .gc_base = -1,
+ .pl_desc = jhb100_per0_pl_desc,
+ .crl_desc = jhb100_per0_pinctrl_rl_desc,
+ .regs = &jhb100_per0_pinctrl_regs,
+};
+
+static const struct of_device_id jhb100_per0_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-per0-pinctrl",
+ .data = &jhb100_per0_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per0_pinctrl_of_match);
+
+static struct platform_driver jhb100_per0_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-per0-pinctrl",
+ .of_match_table = jhb100_per0_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_per0_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC Peripheral-0 domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v1 11/20] dt-bindings: pinctrl: Add starfive,jhb100-per1-pinctrl
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (9 preceding siblings ...)
2026-04-24 11:13 ` [PATCH v1 10/20] pinctrl: starfive: Add StarFive JHB100 per0 controller driver Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-24 16:56 ` Conor Dooley
2026-04-28 11:08 ` Linus Walleij
2026-04-24 11:13 ` [PATCH v1 12/20] pinctrl: starfive: Add StarFive JHB100 per1 controller driver Changhuang Liang
` (9 subsequent siblings)
20 siblings, 2 replies; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC Peripheral-1(per1) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../pinctrl/starfive,jhb100-per1-pinctrl.yaml | 217 ++++++++++++++++++
1 file changed, 217 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml
new file mode 100644
index 000000000000..b2af4df874df
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml
@@ -0,0 +1,217 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per1-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 Peripheral-1 Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "per1" pinctrl domain.
+
+ The "per1" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the Peripheral-1 Pin Controller, there are 36 multi-function GPIO_PADs. Each of them
+ can be multiplexed to several peripherals through function selection. Each iopad has a
+ maximum of up to 3 functions - 0, 1, and 2. Function 0 is the default function which is
+ generally the GPIO function. Function 1 and 2 are the alternate functions or peripheral
+ signals that can be routed to the iopad. The function selection can be carried out by
+ writing the function number to the iopad function select register.
+ Each iopad is configurable with parameters such as input-enable, internal pull-up/pull-down
+ bias, drive strength, schmitt trigger, slew rate, and debounce width.
+
+ This domain contains 4 IO groups which support voltage levels 1.8V and 3.3V
+ gpioe-spi - comprises PAD_GPIO_C0 through PAD_GPIO_C4.
+ gpioe-qspi0 - comprises PAD_GPIO_C5 through PAD_GPIO_C11.
+ gpioe-qspi1 - comprises PAD_GPIO_C12 through PAD_GPIO_C19.
+ gpioe-qspi2 - comprises PAD_GPIO_C20 through PAD_GPIO_C27.
+
+ Each of the above IO groups must be configured with a voltage setting that matches the external
+ voltage level provided to the IO group.
+
+maintainers:
+ - Alex Soo <yuklin.soo@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-per1-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ gpio-line-names: true
+
+ gpioe-spi-vref:
+ description: |
+ Voltage reference value for the IO group "gpioe-spi"
+ 0: voltage reference value for 3.3V
+ 2: voltage reference value for 1.8V
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 2]
+ default: 0
+
+ gpioe-qspi0-vref:
+ description: |
+ Voltage reference value for the IO group "gpioe-qspi0"
+ 0: voltage reference value for 3.3V
+ 2: voltage reference value for 1.8V
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 2]
+ default: 0
+
+ gpioe-qspi1-vref:
+ description: |
+ Voltage reference value for the IO group "gpioe-qspi1"
+ 0: voltage reference value for 3.3V
+ 2: voltage reference value for 1.8V
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 2]
+ default: 0
+
+ gpioe-qspi2-vref:
+ description: |
+ Voltage reference value for the IO group "gpioe-qspi2"
+ 0: voltage reference value for 3.3V
+ 2: voltage reference value for 1.8V
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 2]
+ default: 0
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate and drive strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ unevaluatedProperties: false
+
+ properties:
+ pinmux:
+ description: |
+ The list of GPIOs and their function select.
+ The PINMUX macros are used to configure the
+ function selection.
+
+ bias-disable: true
+
+ bias-pull-up:
+ type: boolean
+
+ bias-pull-down:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-enable: true
+
+ input-disable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow (half frequency)
+ 1: fast
+
+ starfive,debounce-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ description:
+ Debounce width 0 = Disabled, Others = 80ns*N stages
+
+ starfive,drive-i2c-fast-mode:
+ type: boolean
+ description:
+ Enable I2C fast mode drive
+
+ starfive,drive-i2c-fast-mode-plus:
+ type: boolean
+ description:
+ Enable I2C fast mode plus drive
+
+ starfive,i2c-open-drain-pull-up-ohm:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ open drain pull-up select
+ enum: [600, 900, 1200, 2000]
+ default: 600
+
+required:
+ - compatible
+ - reg
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_per1: pinctrl@11b42000 {
+ compatible = "starfive,jhb100-per1-pinctrl";
+ reg = <0x0 0x11b42000 0x0 0x800>;
+ resets = <&per1crg 0>;
+ interrupts = <61>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per1 0 0 36>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH v1 11/20] dt-bindings: pinctrl: Add starfive,jhb100-per1-pinctrl
2026-04-24 11:13 ` [PATCH v1 11/20] dt-bindings: pinctrl: Add starfive,jhb100-per1-pinctrl Changhuang Liang
@ 2026-04-24 16:56 ` Conor Dooley
2026-04-28 1:28 ` Changhuang Liang
2026-04-28 11:08 ` Linus Walleij
1 sibling, 1 reply; 34+ messages in thread
From: Conor Dooley @ 2026-04-24 16:56 UTC (permalink / raw)
To: Changhuang Liang
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski, linux-gpio,
linux-kernel, devicetree, linux-riscv, Lianfeng Ouyang
[-- Attachment #1: Type: text/plain, Size: 9013 bytes --]
On Fri, Apr 24, 2026 at 04:13:21AM -0700, Changhuang Liang wrote:
> Add pinctrl bindings for StarFive JHB100 SoC Peripheral-1(per1) pinctrl
> controller.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
There's a lot of binding here, and I think a bunch of them have similar
questions to be answered, so I am just going to review this one for now.
> ---
> .../pinctrl/starfive,jhb100-per1-pinctrl.yaml | 217 ++++++++++++++++++
> 1 file changed, 217 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml
> new file mode 100644
> index 000000000000..b2af4df874df
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml
> @@ -0,0 +1,217 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per1-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JHB100 Peripheral-1 Pin Controller
> +
> +description: |
> + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
> +
> + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
> + per2, per2pok, per3, adc0, adc1, emmc, and vga.
> + This document provides an overview of the "per1" pinctrl domain.
> +
> + The "per1" domain has a pin controller which provides
> + - function selection for GPIO pads.
> + - GPIO pad configuration.
> + - GPIO interrupt handling.
> +
> + In the Peripheral-1 Pin Controller, there are 36 multi-function GPIO_PADs. Each of them
> + can be multiplexed to several peripherals through function selection. Each iopad has a
> + maximum of up to 3 functions - 0, 1, and 2. Function 0 is the default function which is
> + generally the GPIO function. Function 1 and 2 are the alternate functions or peripheral
> + signals that can be routed to the iopad. The function selection can be carried out by
> + writing the function number to the iopad function select register.
> + Each iopad is configurable with parameters such as input-enable, internal pull-up/pull-down
> + bias, drive strength, schmitt trigger, slew rate, and debounce width.
> +
> + This domain contains 4 IO groups which support voltage levels 1.8V and 3.3V
> + gpioe-spi - comprises PAD_GPIO_C0 through PAD_GPIO_C4.
> + gpioe-qspi0 - comprises PAD_GPIO_C5 through PAD_GPIO_C11.
> + gpioe-qspi1 - comprises PAD_GPIO_C12 through PAD_GPIO_C19.
> + gpioe-qspi2 - comprises PAD_GPIO_C20 through PAD_GPIO_C27.
> +
> + Each of the above IO groups must be configured with a voltage setting that matches the external
> + voltage level provided to the IO group.
> +
> +maintainers:
> + - Alex Soo <yuklin.soo@starfivetech.com>
> +
> +properties:
> + compatible:
> + items:
> + - const: starfive,jhb100-per1-pinctrl
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + interrupt-controller: true
> +
> + '#interrupt-cells':
> + const: 2
> +
> + gpio-controller: true
> +
> + '#gpio-cells':
> + const: 2
> +
> + gpio-ranges:
> + maxItems: 1
> +
> + gpio-line-names: true
> +
> + gpioe-spi-vref:
Why are these custom properties required?
This sounds like the sort of information that could be gleaned from the
"power-source" property.
> + description: |
> + Voltage reference value for the IO group "gpioe-spi"
> + 0: voltage reference value for 3.3V
> + 2: voltage reference value for 1.8V
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 2]
> + default: 0
> +
> + gpioe-qspi0-vref:
> + description: |
> + Voltage reference value for the IO group "gpioe-qspi0"
> + 0: voltage reference value for 3.3V
> + 2: voltage reference value for 1.8V
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 2]
> + default: 0
> +
> + gpioe-qspi1-vref:
> + description: |
> + Voltage reference value for the IO group "gpioe-qspi1"
> + 0: voltage reference value for 3.3V
> + 2: voltage reference value for 1.8V
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 2]
> + default: 0
> +
> + gpioe-qspi2-vref:
> + description: |
> + Voltage reference value for the IO group "gpioe-qspi2"
> + 0: voltage reference value for 3.3V
> + 2: voltage reference value for 1.8V
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 2]
> + default: 0
> +
> +patternProperties:
> + '-grp$':
> + type: object
> + additionalProperties: false
> + patternProperties:
> + '-pins$':
> + type: object
> + description: |
> + A pinctrl node should contain at least one subnode representing the
> + pinctrl groups available in the domain. Each subnode will list the
> + pins it needs, and how they should be configured, with regard to
> + function selection, bias, input enable/disable, input schmitt
> + trigger enable/disable, slew-rate and drive strength.
> + allOf:
> + - $ref: /schemas/pinctrl/pincfg-node.yaml
> + - $ref: /schemas/pinctrl/pinmux-node.yaml
> + unevaluatedProperties: false
> +
> + properties:
> + pinmux:
> + description: |
> + The list of GPIOs and their function select.
> + The PINMUX macros are used to configure the
> + function selection.
Why is the pinmux property needed?
Can you use pins and function instead?
Looking at the defines that you have added, it appears that lots of
defines for the same peripheral share the same numerical values,
suggesting that across peripheral, all (or most) pins would share the
same mux setting/"function select", suggesting that pins/function would
suffice.
I'd like to see some justification for pinmux being the right solution
here, like the "function select" used by one peripheral being
significantly different for many of its pins.
> +
> + bias-disable: true
> +
> + bias-pull-up:
> + type: boolean
> +
> + bias-pull-down:
> + type: boolean
> +
> + drive-strength:
> + enum: [ 2, 4, 8, 12 ]
> +
> + drive-strength-microamp:
> + enum: [ 2000, 4000, 8000, 12000 ]
> +
> + input-enable: true
> +
> + input-disable: true
> +
> + input-schmitt-enable: true
> +
> + input-schmitt-disable: true
> +
> + slew-rate:
> + enum: [ 0, 1 ]
> + default: 0
> + description: |
> + 0: slow (half frequency)
> + 1: fast
> +
> + starfive,debounce-width:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0
> + description:
> + Debounce width 0 = Disabled, Others = 80ns*N stages
This sounds like it should be called "debounce-stages".
> +
> + starfive,drive-i2c-fast-mode:
> + type: boolean
> + description:
> + Enable I2C fast mode drive
> +
> + starfive,drive-i2c-fast-mode-plus:
> + type: boolean
> + description:
> + Enable I2C fast mode plus drive
> +
> + starfive,i2c-open-drain-pull-up-ohm:
> + $ref: /schemas/types.yaml#/definitions/uint32
The unit of resistance is "ohms" in dt-schema, if you swap to that you
won't need the $ref.
> + description:
> + open drain pull-up select
> + enum: [600, 900, 1200, 2000]
> + default: 600
> +
> +required:
> + - compatible
> + - reg
> + - resets
> + - interrupts
> + - interrupt-controller
> + - '#interrupt-cells'
> + - gpio-controller
> + - '#gpio-cells'
> + - gpio-ranges
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + pinctrl_per1: pinctrl@11b42000 {
Drop the label here, since there's no users.
Cheers,
Conor.
> + compatible = "starfive,jhb100-per1-pinctrl";
> + reg = <0x0 0x11b42000 0x0 0x800>;
> + resets = <&per1crg 0>;
> + interrupts = <61>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl_per1 0 0 36>;
> + };
> + };
> --
> 2.25.1
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH v1 11/20] dt-bindings: pinctrl: Add starfive,jhb100-per1-pinctrl
2026-04-24 16:56 ` Conor Dooley
@ 2026-04-28 1:28 ` Changhuang Liang
2026-04-28 18:51 ` Conor Dooley
0 siblings, 1 reply; 34+ messages in thread
From: Changhuang Liang @ 2026-04-28 1:28 UTC (permalink / raw)
To: Conor Dooley
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski,
linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Lianfeng Ouyang
Hi, Conor
Thanks for the review.
> On Fri, Apr 24, 2026 at 04:13:21AM -0700, Changhuang Liang wrote:
> > Add pinctrl bindings for StarFive JHB100 SoC Peripheral-1(per1)
> > pinctrl controller.
> >
> > Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
>
> There's a lot of binding here, and I think a bunch of them have similar
> questions to be answered, so I am just going to review this one for now.
>
> > ---
> > .../pinctrl/starfive,jhb100-per1-pinctrl.yaml | 217
> > ++++++++++++++++++
> > 1 file changed, 217 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl
> > .yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinct
> > rl.yaml
> > b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinct
> > rl.yaml
> > new file mode 100644
> > index 000000000000..b2af4df874df
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-p
> > +++ inctrl.yaml
> > @@ -0,0 +1,217 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2
> > +---
> > +$id:
> > +http://devicetree.org/schemas/pinctrl/starfive,jhb100-per1-pinctrl.ya
> > +ml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: StarFive JHB100 Peripheral-1 Pin Controller
> > +
> > +description: |
> > + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
> > +
> > + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2,
> > + per0, per1, per2, per2pok, per3, adc0, adc1, emmc, and vga.
> > + This document provides an overview of the "per1" pinctrl domain.
> > +
> > + The "per1" domain has a pin controller which provides
> > + - function selection for GPIO pads.
> > + - GPIO pad configuration.
> > + - GPIO interrupt handling.
> > +
> > + In the Peripheral-1 Pin Controller, there are 36 multi-function
> > + GPIO_PADs. Each of them can be multiplexed to several peripherals
> > + through function selection. Each iopad has a maximum of up to 3
> > + functions - 0, 1, and 2. Function 0 is the default function which is
> > + generally the GPIO function. Function 1 and 2 are the alternate
> > + functions or peripheral signals that can be routed to the iopad. The
> function selection can be carried out by writing the function number to the
> iopad function select register.
> > + Each iopad is configurable with parameters such as input-enable,
> > + internal pull-up/pull-down bias, drive strength, schmitt trigger, slew rate,
> and debounce width.
> > +
> > + This domain contains 4 IO groups which support voltage levels 1.8V
> > + and 3.3V gpioe-spi - comprises PAD_GPIO_C0 through PAD_GPIO_C4.
> > + gpioe-qspi0 - comprises PAD_GPIO_C5 through PAD_GPIO_C11.
> > + gpioe-qspi1 - comprises PAD_GPIO_C12 through PAD_GPIO_C19.
> > + gpioe-qspi2 - comprises PAD_GPIO_C20 through PAD_GPIO_C27.
> > +
> > + Each of the above IO groups must be configured with a voltage
> > + setting that matches the external voltage level provided to the IO group.
> > +
> > +maintainers:
> > + - Alex Soo <yuklin.soo@starfivetech.com>
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: starfive,jhb100-per1-pinctrl
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + interrupt-controller: true
> > +
> > + '#interrupt-cells':
> > + const: 2
> > +
> > + gpio-controller: true
> > +
> > + '#gpio-cells':
> > + const: 2
> > +
> > + gpio-ranges:
> > + maxItems: 1
> > +
> > + gpio-line-names: true
> > +
> > + gpioe-spi-vref:
>
> Why are these custom properties required?
> This sounds like the sort of information that could be gleaned from the
> "power-source" property.
The voltage configuration here applies to multiple pin groups, making it less suitable to use power-source.
In patch 13, we defined a starfive,gmac-vsel property, which can be applied to individual pins. It might be
more appropriate to use power-source.
>
> > + description: |
> > + Voltage reference value for the IO group "gpioe-spi"
> > + 0: voltage reference value for 3.3V
> > + 2: voltage reference value for 1.8V
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [0, 2]
> > + default: 0
> > +
> > + gpioe-qspi0-vref:
> > + description: |
> > + Voltage reference value for the IO group "gpioe-qspi0"
> > + 0: voltage reference value for 3.3V
> > + 2: voltage reference value for 1.8V
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [0, 2]
> > + default: 0
> > +
> > + gpioe-qspi1-vref:
> > + description: |
> > + Voltage reference value for the IO group "gpioe-qspi1"
> > + 0: voltage reference value for 3.3V
> > + 2: voltage reference value for 1.8V
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [0, 2]
> > + default: 0
> > +
> > + gpioe-qspi2-vref:
> > + description: |
> > + Voltage reference value for the IO group "gpioe-qspi2"
> > + 0: voltage reference value for 3.3V
> > + 2: voltage reference value for 1.8V
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [0, 2]
> > + default: 0
> > +
> > +patternProperties:
> > + '-grp$':
> > + type: object
> > + additionalProperties: false
> > + patternProperties:
> > + '-pins$':
> > + type: object
> > + description: |
> > + A pinctrl node should contain at least one subnode
> representing the
> > + pinctrl groups available in the domain. Each subnode will list
> the
> > + pins it needs, and how they should be configured, with regard
> to
> > + function selection, bias, input enable/disable, input schmitt
> > + trigger enable/disable, slew-rate and drive strength.
> > + allOf:
> > + - $ref: /schemas/pinctrl/pincfg-node.yaml
> > + - $ref: /schemas/pinctrl/pinmux-node.yaml
> > + unevaluatedProperties: false
> > +
> > + properties:
> > + pinmux:
> > + description: |
> > + The list of GPIOs and their function select.
> > + The PINMUX macros are used to configure the
> > + function selection.
>
> Why is the pinmux property needed?
> Can you use pins and function instead?
>
> Looking at the defines that you have added, it appears that lots of defines for
> the same peripheral share the same numerical values, suggesting that across
> peripheral, all (or most) pins would share the same mux setting/"function
> select", suggesting that pins/function would suffice.
>
> I'd like to see some justification for pinmux being the right solution here, like
> the "function select" used by one peripheral being significantly different for
> many of its pins.
We think that implementing this in the pinmux will be relatively simple. It avoids
the need to create a large number of mapping relationships in the driver, which
simplifies our driver implementation. I'm not sure if you'll find this explanation
acceptable.
> > +
> > + bias-disable: true
> > +
> > + bias-pull-up:
> > + type: boolean
> > +
> > + bias-pull-down:
> > + type: boolean
> > +
> > + drive-strength:
> > + enum: [ 2, 4, 8, 12 ]
> > +
> > + drive-strength-microamp:
> > + enum: [ 2000, 4000, 8000, 12000 ]
> > +
> > + input-enable: true
> > +
> > + input-disable: true
> > +
> > + input-schmitt-enable: true
> > +
> > + input-schmitt-disable: true
> > +
> > + slew-rate:
> > + enum: [ 0, 1 ]
> > + default: 0
> > + description: |
> > + 0: slow (half frequency)
> > + 1: fast
> > +
> > + starfive,debounce-width:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + default: 0
> > + description:
> > + Debounce width 0 = Disabled, Others = 80ns*N stages
>
> This sounds like it should be called "debounce-stages".
>
> > +
> > + starfive,drive-i2c-fast-mode:
> > + type: boolean
> > + description:
> > + Enable I2C fast mode drive
> > +
> > + starfive,drive-i2c-fast-mode-plus:
> > + type: boolean
> > + description:
> > + Enable I2C fast mode plus drive
> > +
> > + starfive,i2c-open-drain-pull-up-ohm:
> > + $ref: /schemas/types.yaml#/definitions/uint32
>
> The unit of resistance is "ohms" in dt-schema, if you swap to that you won't
> need the $ref.
>
> > + description:
> > + open drain pull-up select
> > + enum: [600, 900, 1200, 2000]
> > + default: 600
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - resets
> > + - interrupts
> > + - interrupt-controller
> > + - '#interrupt-cells'
> > + - gpio-controller
> > + - '#gpio-cells'
> > + - gpio-ranges
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + pinctrl_per1: pinctrl@11b42000 {
>
> Drop the label here, since there's no users.
This label is referenced in gpio-ranges.
>
> Cheers,
> Conor.
>
> > + compatible = "starfive,jhb100-per1-pinctrl";
> > + reg = <0x0 0x11b42000 0x0 0x800>;
> > + resets = <&per1crg 0>;
> > + interrupts = <61>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + gpio-ranges = <&pinctrl_per1 0 0 36>;
> > + };
> > + };
> > --
> > 2.25.1
> >
Best Regards,
Changhuang
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH v1 11/20] dt-bindings: pinctrl: Add starfive,jhb100-per1-pinctrl
2026-04-28 1:28 ` Changhuang Liang
@ 2026-04-28 18:51 ` Conor Dooley
0 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2026-04-28 18:51 UTC (permalink / raw)
To: Changhuang Liang
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski,
linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Lianfeng Ouyang
[-- Attachment #1: Type: text/plain, Size: 3345 bytes --]
On Tue, Apr 28, 2026 at 01:28:05AM +0000, Changhuang Liang wrote:
> > On Fri, Apr 24, 2026 at 04:13:21AM -0700, Changhuang Liang wrote:
> > > Add pinctrl bindings for StarFive JHB100 SoC Peripheral-1(per1)
> > > pinctrl controller.
> > >
> > > Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> > > + properties:
> > > + pinmux:
> > > + description: |
> > > + The list of GPIOs and their function select.
> > > + The PINMUX macros are used to configure the
> > > + function selection.
> >
> > Why is the pinmux property needed?
> > Can you use pins and function instead?
> >
> > Looking at the defines that you have added, it appears that lots of defines for
> > the same peripheral share the same numerical values, suggesting that across
> > peripheral, all (or most) pins would share the same mux setting/"function
> > select", suggesting that pins/function would suffice.
> >
> > I'd like to see some justification for pinmux being the right solution here, like
> > the "function select" used by one peripheral being significantly different for
> > many of its pins.
>
> We think that implementing this in the pinmux will be relatively simple. It avoids
> the need to create a large number of mapping relationships in the driver, which
> simplifies our driver implementation. I'm not sure if you'll find this explanation
> acceptable.
I don't really see how pins + functions would require lots of "mapping
relationships". Instead of having
+/* pinctrl_sys2 pad function selection */
+#define FUNC_SYS2_UART_CTS 1
+#define FUNC_SYS2_UART_RTS 1
+#define FUNC_SYS2_UART_DCD 1
+#define FUNC_SYS2_UART_DSR 1
+#define FUNC_SYS2_UART_DTR 1
+#define FUNC_SYS2_UART_RI 1
+#define FUNC_SYS2_UART0_TX 1
+#define FUNC_SYS2_UART0_RX 1
+#define FUNC_SYS2_UART1_TX 1
+#define FUNC_SYS2_UART1_RX 1
+#define FUNC_SYS2_UART2_TX 1
+#define FUNC_SYS2_UART2_RX 1
+#define FUNC_SYS2_UART3_TX 1
+#define FUNC_SYS2_UART3_RX 1
+#define FUNC_SYS2_UART4_TX 1
+#define FUNC_SYS2_UART4_RX 1
+#define FUNC_SYS2_UART5_TX 1
+#define FUNC_SYS2_UART5_RX 1
+#define FUNC_SYS2_UART6_TX 1
+#define FUNC_SYS2_UART6_RX 1
+#define FUNC_SYS2_UART7_TX 1
+#define FUNC_SYS2_UART7_RX 1
+#define FUNC_SYS2_UART8_TX 1
+#define FUNC_SYS2_UART8_RX 1
+#define FUNC_SYS2_UART9_TX 1
+#define FUNC_SYS2_UART9_RX 1
+#define FUNC_SYS2_UART10_TX 1
+#define FUNC_SYS2_UART10_RX 1
+#define FUNC_SYS2_UART11_TX 1
+#define FUNC_SYS2_UART11_RX 1
+#define FUNC_SYS2_UART12_TX 1
+#define FUNC_SYS2_UART12_RX 1
+#define FUNC_SYS2_UART13_TX 1
+#define FUNC_SYS2_UART13_RX 1
+#define FUNC_SYS2_UART14_TX 1
+#define FUNC_SYS2_UART14_RX 1
you just define a function called "uart" and have a simple map of
that string to the number 1. You end up with a single array with the
relationships, not lots.
Frankly, pinmux just does not seem appropriate to me when it looks like
90%+ of the pin mappings for a peripheral share the same function value.
There appears only to be a rare number of cases where that doesn't
apply, but that could be handled by having them represented by a
different group/pins node with a different function.
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^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v1 11/20] dt-bindings: pinctrl: Add starfive,jhb100-per1-pinctrl
2026-04-24 11:13 ` [PATCH v1 11/20] dt-bindings: pinctrl: Add starfive,jhb100-per1-pinctrl Changhuang Liang
2026-04-24 16:56 ` Conor Dooley
@ 2026-04-28 11:08 ` Linus Walleij
1 sibling, 0 replies; 34+ messages in thread
From: Linus Walleij @ 2026-04-28 11:08 UTC (permalink / raw)
To: Changhuang Liang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski, linux-gpio,
linux-kernel, devicetree, linux-riscv, Lianfeng Ouyang
Hi Changhuang,
thanks for your patch!
On Fri, Apr 24, 2026 at 1:14 PM Changhuang Liang
<changhuang.liang@starfivetech.com> wrote:
> Add pinctrl bindings for StarFive JHB100 SoC Peripheral-1(per1) pinctrl
> controller.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
(...)
> + This domain contains 4 IO groups which support voltage levels 1.8V and 3.3V
> + gpioe-spi - comprises PAD_GPIO_C0 through PAD_GPIO_C4.
> + gpioe-qspi0 - comprises PAD_GPIO_C5 through PAD_GPIO_C11.
> + gpioe-qspi1 - comprises PAD_GPIO_C12 through PAD_GPIO_C19.
> + gpioe-qspi2 - comprises PAD_GPIO_C20 through PAD_GPIO_C27.
> +
> + Each of the above IO groups must be configured with a voltage setting that matches the external
> + voltage level provided to the IO group.
So your hardware has groups and support some properties on the group level.
So expose these groups and make these properties configurable per group
instead of inventing per-group properties.
> + gpioe-spi-vref:
> + gpioe-qspi0-vref:
> + gpioe-qspi1-vref:
> + gpioe-qspi2-vref:
Create proper groups in the pin controller then use the
standard pincfg property power-source = <...>; for this.
Example for a simple default hog:
pinctrl {
/* Hog the QSPI pins */
pinctrl-names = "default";
pinctrl-0 = <&qspi_default>;
qspi_default: pinctrl-qspi {
config {
groups = "gpioe-qspi-pins";
power-source = <2>;
};
};
};
The groups can be orthogonal to other pin handling, that's
fine. Implement .pin_config_group_set in struct pinconf_ops.
> + starfive,debounce-width:
> + starfive,drive-i2c-fast-mode:
> + starfive,drive-i2c-fast-mode-plus:
> + starfive,i2c-open-drain-pull-up-ohm:
I already adressed these in other review comments. Get rid of
them in favor of standard pinconfig bindings.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v1 12/20] pinctrl: starfive: Add StarFive JHB100 per1 controller driver
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (10 preceding siblings ...)
2026-04-24 11:13 ` [PATCH v1 11/20] dt-bindings: pinctrl: Add starfive,jhb100-per1-pinctrl Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-24 11:13 ` [PATCH v1 13/20] dt-bindings: pinctrl: Add starfive,jhb100-per2-pinctrl Changhuang Liang
` (8 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC Peripheral-1(per1) pinctrl
controller.
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 12 ++
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-per1.c | 112 ++++++++++++++++++
3 files changed, 125 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index e5afd937c4a1..c5937207b2d3 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -71,6 +71,18 @@ config PINCTRL_STARFIVE_JHB100_PER0
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+config PINCTRL_STARFIVE_JHB100_PER1
+ tristate "StarFive JHB100 SoC Peripheral-1 pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ depends on OF
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support Peripheral-1 pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
+
config PINCTRL_STARFIVE_JHB100_SYS0
tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index f2bb0c35a2a0..6beef7e313ef 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER1) += pinctrl-starfive-jhb100-per1.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c
new file mode 100644
index 000000000000..fcdc326ac50f
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC Peripheral-1 domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+static const struct jhb100_pin_layout_desc jhb100_per1_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 36, .name = "gpio", .gpio_func_sel = 0 },
+ { 0xff },
+};
+
+static struct config_reg_layout_desc jhb100_per1_pinctr_rldesc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 32,
+ .drive_strength_2bit = { .shift = 0, .width = 2 },
+ .input_enable = { .shift = 2, .width = 1 },
+ .pull_down = { .shift = 3, .width = 1 },
+ .pull_up = { .shift = 4, .width = 1 },
+ .slew_rate = { .shift = 5, .width = 1 },
+ .schmitt_trigger_select = { .shift = 6, .width = 1 },
+ .reserved = { .shift = 7, .width = 8 },
+ .debounce_width = { .shift = 15, .width = 17 },
+ },
+ {
+ .pin_start = 32,
+ .pin_cnt = 4,
+ .input_enable = { .shift = 0, .width = 1 },
+ .mode_select = { .shift = 1, .width = 2 },
+ .pull_down = { .shift = 3, .width = 1 },
+ .pull_up = { .shift = 4, .width = 1 },
+ .open_drain_pull_up_sel = { .shift = 5, .width = 2 },
+ .schmitt_trigger_select = { .shift = 7, .width = 1 },
+ .reserved = { .shift = 8, .width = 7 },
+ .debounce_width = { .shift = 15, .width = 17 },
+ },
+ { 0xff },
+};
+
+static const struct pinvref_desc pinvref_desc_per0[] = {
+ {
+ .name = "gpioe-spi",
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ {
+ .name = "gpioe-qspi0",
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ {
+ .name = "gpioe-qspi1",
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ {
+ .name = "gpioe-qspi2",
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ { NULL },
+};
+
+struct starfive_pinctrl_regs jhb100_per1_pinctrl_regs = {
+ .vref = { .reg = 0x00, .pv_desc = pinvref_desc_per0 },
+ .config = { .reg = 0x14, .width_per_pin = 32 },
+ .output = { .reg = 0xa4, .width_per_pin = 1 },
+ .output_en = { .reg = 0xac, .width_per_pin = 1 },
+ .gpio_status = { .reg = 0xb4, .width_per_pin = 1 },
+ .func_sel = { .reg = 0xbc, .width_per_pin = 2 },
+ .irq_en = { .reg = 0xc8, .width_per_pin = 1 },
+ .irq_status = { .reg = 0xd0, .width_per_pin = 1 },
+ .irq_clr = { .reg = 0xd8, .width_per_pin = 1 },
+ .irq_trigger = { .reg = 0xe0, .width_per_pin = 1 },
+ .irq_level = { .reg = 0xe8, .width_per_pin = 1 },
+ .irq_both_edge = { .reg = 0xf0, .width_per_pin = 1 },
+ .irq_edge = { .reg = 0xf8, .width_per_pin = 1 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_per1_pinctrl_info = {
+ .name = "jhb100-per1",
+ .gc_base = -1,
+ .pl_desc = jhb100_per1_pl_desc,
+ .crl_desc = jhb100_per1_pinctr_rldesc,
+ .regs = &jhb100_per1_pinctrl_regs,
+};
+
+static const struct of_device_id jhb100_per1_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-per1-pinctrl",
+ .data = &jhb100_per1_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per1_pinctrl_of_match);
+
+static struct platform_driver jhb100_per1_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-per1-pinctrl",
+ .of_match_table = jhb100_per1_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_per1_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC Peripheral-1 domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v1 13/20] dt-bindings: pinctrl: Add starfive,jhb100-per2-pinctrl
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (11 preceding siblings ...)
2026-04-24 11:13 ` [PATCH v1 12/20] pinctrl: starfive: Add StarFive JHB100 per1 controller driver Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-24 13:17 ` Rob Herring (Arm)
2026-04-24 11:13 ` [PATCH v1 14/20] pinctrl: starfive: Add StarFive JHB100 per2 controller driver Changhuang Liang
` (7 subsequent siblings)
20 siblings, 1 reply; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC Peripheral-2(per2) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../pinctrl/starfive,jhb100-per2-pinctrl.yaml | 178 ++++++++++++++++++
1 file changed, 178 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2-pinctrl.yaml
new file mode 100644
index 000000000000..0dad00b7365b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2-pinctrl.yaml
@@ -0,0 +1,178 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per2-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 Peripheral-2 Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "per2" pinctrl domain.
+
+ The "per2" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the Peripheral-2 Pin Controller, there are 31 multi-function GPIO_PADs. Each of them can be
+ multiplexed to several peripherals through function selection. Each iopad has a maximum of
+ up to 4 functions - 0, 1, 2, and 3. Function 0 is the default function which is generally
+ the GPIO function. Function 1, 2, and 3 are the alternate functions or peripheral signals
+ that can be routed to an iopad. The function selection can be carried out by writing the
+ function number to the iopad function select register.
+ Each iopad is configurable with parameters such as input-enable, internal pull-up/pull-down
+ bias, drive strength, schmitt trigger, slew rate, and debounce width.
+
+ This domain contains an IO group which support voltage levels 1.8V, 2.5V, and 3.3V
+ 1. gpionw - comprises PAD_GPIO_D19 through PAD_GPIO_D30.
+
+ Each of the above IO groups must be configured with a voltage setting that matches the external
+ voltage level provided to the IO group.
+
+maintainers:
+ - Alex Soo <yuklin.soo@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-per2-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ gpio-line-names: true
+
+ gpionw-vref:
+ default: 0
+ description: |
+ Voltage reference value for the IO group "gpionw"
+ 0: voltage reference value for 3.3V
+ 1: voltage reference value for 2.5V
+ 2: voltage reference value for 1.8V
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate and drive strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ unevaluatedProperties: false
+
+ properties:
+ pinmux:
+ description: |
+ The list of GPIOs and their function select.
+ The PINMUX macros are used to configure the
+ function selection.
+
+ bias-disable: true
+
+ bias-pull-up:
+ type: boolean
+
+ bias-pull-down:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-enable: true
+
+ input-disable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow (half frequency)
+ 1: fast
+
+ starfive,gmac-vsel:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ description:
+ RGMII mode voltage select 0 = 1.8V/3.3V, 1 = 2.5V
+ enum: [0, 1]
+
+ starfive,debounce-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ description:
+ Debounce width 0 = Disabled, Others = 80ns*N stages
+
+required:
+ - compatible
+ - reg
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_per2: pinctrl@11bc2000 {
+ compatible = "starfive,jhb100-per2-pinctrl";
+ reg = <0x0 0x11bc2000 0x0 0x400>;
+ resets = <&per2crg 0>;
+ interrupts = <62>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per2 0 0 31>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH v1 13/20] dt-bindings: pinctrl: Add starfive,jhb100-per2-pinctrl
2026-04-24 11:13 ` [PATCH v1 13/20] dt-bindings: pinctrl: Add starfive,jhb100-per2-pinctrl Changhuang Liang
@ 2026-04-24 13:17 ` Rob Herring (Arm)
0 siblings, 0 replies; 34+ messages in thread
From: Rob Herring (Arm) @ 2026-04-24 13:17 UTC (permalink / raw)
To: Changhuang Liang
Cc: devicetree, Bartosz Golaszewski, Palmer Dabbelt,
Emil Renner Berthing, Alexandre Ghiti, Conor Dooley,
Krzysztof Kozlowski, Paul Walmsley, Lianfeng Ouyang,
Philipp Zabel, linux-kernel, Linus Walleij, Albert Ou,
linux-riscv, linux-gpio
On Fri, 24 Apr 2026 04:13:23 -0700, Changhuang Liang wrote:
> Add pinctrl bindings for StarFive JHB100 SoC Peripheral-2(per2) pinctrl
> controller.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
> .../pinctrl/starfive,jhb100-per2-pinctrl.yaml | 178 ++++++++++++++++++
> 1 file changed, 178 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2-pinctrl.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/net/renesas,ether.example.dtb: ethernet-phy@1 (ethernet-phy-id0022.1537): compatible: ['ethernet-phy-id0022.1537', 'ethernet-phy-ieee802.3-c22'] is too long
from schema $id: http://devicetree.org/schemas/net/micrel.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260424111330.702272-14-changhuang.liang@starfivetech.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v1 14/20] pinctrl: starfive: Add StarFive JHB100 per2 controller driver
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (12 preceding siblings ...)
2026-04-24 11:13 ` [PATCH v1 13/20] dt-bindings: pinctrl: Add starfive,jhb100-per2-pinctrl Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-24 11:13 ` [PATCH v1 15/20] dt-bindings: pinctrl: Add starfive,jhb100-per2pok-pinctrl Changhuang Liang
` (6 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC Peripheral-2(per2) pinctrl
controller.
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 12 +++
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-per2.c | 102 ++++++++++++++++++
3 files changed, 115 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index c5937207b2d3..765379bf3d52 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -83,6 +83,18 @@ config PINCTRL_STARFIVE_JHB100_PER1
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+config PINCTRL_STARFIVE_JHB100_PER2
+ tristate "StarFive JHB100 SoC Peripheral-2 pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ depends on OF
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support Peripheral-2 pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
+
config PINCTRL_STARFIVE_JHB100_SYS0
tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index 6beef7e313ef..33213bd1919f 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER1) += pinctrl-starfive-jhb100-per1.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER2) += pinctrl-starfive-jhb100-per2.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2.c
new file mode 100644
index 000000000000..d4c2927f1014
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC Peripheral-2 domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+static const struct jhb100_pin_layout_desc jhb100_per2_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 15, .name = "gpio", .gpio_func_sel = 0 },
+ { .pin_start = 15, .pin_cnt = 1, .name = "gpio", .gpio_func_sel = -1 },
+ { .pin_start = 16, .pin_cnt = 15, .name = "gpio", .gpio_func_sel = 0 },
+ { 0xff },
+};
+
+static struct config_reg_layout_desc jhb100_per2_pinctrl_rl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 19,
+ .drive_strength_2bit = { .shift = 0, .width = 2 },
+ .input_enable = { .shift = 2, .width = 1 },
+ .pull_down = { .shift = 3, .width = 1 },
+ .pull_up = { .shift = 4, .width = 1 },
+ .slew_rate = { .shift = 5, .width = 1 },
+ .schmitt_trigger_select = { .shift = 6, .width = 1 },
+ .reserved = { .shift = 7, .width = 8 },
+ .debounce_width = { .shift = 15, .width = 17 },
+ },
+ {
+ .pin_start = 19,
+ .pin_cnt = 12,
+ .input_enable = { .shift = 0, .width = 1 },
+ .slew_rate = { .shift = 1, .width = 1 },
+ .vsel = { .shift = 2, .width = 2,
+ .func = BIT(PER2_GMAC_RGMII_FUNC) |
+ BIT(PER2_GMAC_RMII_FUNC) },
+ .reserved = {.shift = 4, .width = 11 },
+ .debounce_width = {.shift = 15, .width = 17 },
+ },
+ { 0xff },
+};
+
+static const struct pinvref_desc pinvref_desc_per2[] = {
+ {
+ .name = "gpionw",
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_2_5V) |
+ BIT(JHB100_PINVREF_3_3V)
+ },
+ { NULL },
+};
+
+struct starfive_pinctrl_regs jhb100_per2_pinctrl_regs = {
+ .vref = { .reg = 0x00, .pv_desc = pinvref_desc_per2 },
+ .config = { .reg = 0x04, .width_per_pin = 1 },
+ .output = { .reg = 0x80, .width_per_pin = 1 },
+ .output_en = { .reg = 0x84, .width_per_pin = 1 },
+ .gpio_status = { .reg = 0x88, .width_per_pin = 1 },
+ .func_sel = { .reg = 0x8c, .width_per_pin = 2 },
+ .irq_en = { .reg = 0x94, .width_per_pin = 1 },
+ .irq_status = { .reg = 0x98, .width_per_pin = 1 },
+ .irq_clr = { .reg = 0x9c, .width_per_pin = 1 },
+ .irq_trigger = { .reg = 0xa0, .width_per_pin = 1 },
+ .irq_level = { .reg = 0xa4, .width_per_pin = 1 },
+ .irq_both_edge = { .reg = 0xa8, .width_per_pin = 1 },
+ .irq_edge = { .reg = 0xac, .width_per_pin = 1 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_per2_pinctrl_info = {
+ .name = "jhb100-per2",
+ .gc_base = -1,
+ .pl_desc = jhb100_per2_pl_desc,
+ .crl_desc = jhb100_per2_pinctrl_rl_desc,
+ .regs = &jhb100_per2_pinctrl_regs,
+};
+
+static const struct of_device_id jhb100_per2_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-per2-pinctrl",
+ .data = &jhb100_per2_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per2_pinctrl_of_match);
+
+static struct platform_driver jhb100_per2_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-per2-pinctrl",
+ .of_match_table = jhb100_per2_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_per2_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC Peripheral-2 domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v1 15/20] dt-bindings: pinctrl: Add starfive,jhb100-per2pok-pinctrl
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (13 preceding siblings ...)
2026-04-24 11:13 ` [PATCH v1 14/20] pinctrl: starfive: Add StarFive JHB100 per2 controller driver Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-24 11:13 ` [PATCH v1 16/20] pinctrl: starfive: Add StarFive JHB100 per2pok controller driver Changhuang Liang
` (5 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC Peripheral-2 Power OK
(per2pok) pinctrl controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../starfive,jhb100-per2pok-pinctrl.yaml | 154 ++++++++++++++++++
1 file changed, 154 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2pok-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2pok-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2pok-pinctrl.yaml
new file mode 100644
index 000000000000..339123082f15
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2pok-pinctrl.yaml
@@ -0,0 +1,154 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per2pok-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 Peripheral-2 Power OK Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "bper2pok" pinctrl domain.
+
+ The "per2pok" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO interrupt handling.
+
+ In the Peripheral-2 Power OK Pin Controller, there are 18 multi-function GPIO_PADs. Each can be
+ multiplexed to several peripherals through function selection. Each iopad has a maximum
+ of up to 4 functions - 0, 1, 2, and 3. Function 0 is the default function or generally the
+ GPIO function. Function 1, 2, and 3 are alternate functions or peripheral signals that can
+ routed to an iopad. The function selection can be carried out by writing the function
+ number to the iopad function select register.
+ Each iopad is configurable with parameters such as input-enable, internal pull-up/pull-down
+ bias, drive strength, schmitt trigger, slew rate, and debounce width.
+
+maintainers:
+ - Alex Soo <yuklin.soo@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-per2pok-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ gpio-line-names: true
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate and drive strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ unevaluatedProperties: false
+
+ properties:
+ pinmux:
+ description: |
+ The list of GPIOs and their function select.
+ The PINMUX macros are used to configure the
+ function selection.
+
+ bias-disable: true
+
+ bias-pull-up:
+ type: boolean
+
+ bias-pull-down:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-enable: true
+
+ input-disable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow (half frequency)
+ 1: fast
+
+ starfive,debounce-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ description:
+ Debounce width 0 = Disabled, Others = 80ns*N stages
+
+required:
+ - compatible
+ - reg
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_per2pok: pinctrl@11bc2400 {
+ compatible = "starfive,jhb100-per2pok-pinctrl";
+ reg = <0x0 0x11bc2400 0x0 0x400>;
+ resets = <&per2crg 1>;
+ interrupts = <63>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per2pok 0 0 18>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v1 16/20] pinctrl: starfive: Add StarFive JHB100 per2pok controller driver
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (14 preceding siblings ...)
2026-04-24 11:13 ` [PATCH v1 15/20] dt-bindings: pinctrl: Add starfive,jhb100-per2pok-pinctrl Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-24 11:13 ` [PATCH v1 17/20] dt-bindings: pinctrl: Add starfive,jhb100-per3-pinctrl Changhuang Liang
` (4 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC Peripheral-2 Power OK
(per2pok) pinctrl controller.
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 12 +++
drivers/pinctrl/starfive/Makefile | 1 +
.../pinctrl-starfive-jhb100-per2pok.c | 80 +++++++++++++++++++
3 files changed, 93 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2pok.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index 765379bf3d52..ed29f87e9d7a 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -95,6 +95,18 @@ config PINCTRL_STARFIVE_JHB100_PER2
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+config PINCTRL_STARFIVE_JHB100_PER2POK
+ tristate "StarFive JHB100 SoC Peripheral-2 Power OK pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ depends on OF
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support Peripheral-2 Power OK pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
+
config PINCTRL_STARFIVE_JHB100_SYS0
tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index 33213bd1919f..213002da9cdd 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER1) += pinctrl-starfive-jhb100-per1.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER2) += pinctrl-starfive-jhb100-per2.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER2POK) += pinctrl-starfive-jhb100-per2pok.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2pok.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2pok.c
new file mode 100644
index 000000000000..31ff047e63a4
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2pok.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC Peripheral-2 Power OK domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+static const struct jhb100_pin_layout_desc jhb100_per2pok_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 10, .name = "gpio", .gpio_func_sel = 0 },
+ { .pin_start = 10, .pin_cnt = 8, .name = "pwm_channel", .gpio_func_sel = 1 },
+ { 0xff },
+};
+
+static struct config_reg_layout_desc jhb100_per2pok_pinctrl_rl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 18,
+ .drive_strength_2bit = { .shift = 0, .width = 2 },
+ .input_enable = { .shift = 2, .width = 1 },
+ .pull_down = { .shift = 3, .width = 1 },
+ .pull_up = { .shift = 4, .width = 1 },
+ .slew_rate = { .shift = 5, .width = 1 },
+ .schmitt_trigger_select = { .shift = 6, .width = 1 },
+ .reserved = { .shift = 7, .width = 8 },
+ .debounce_width = { .shift = 15, .width = 17 },
+ },
+ { 0xff },
+};
+
+struct starfive_pinctrl_regs jhb100_per2pok_pinctrl_regs = {
+ .config = { .reg = 0x04, .width_per_pin = 1 },
+ .output = { .reg = 0x4c, .width_per_pin = 1 },
+ .output_en = { .reg = 0x50, .width_per_pin = 1 },
+ .gpio_status = { .reg = 0x54, .width_per_pin = 1 },
+ .func_sel = { .reg = 0x58, .width_per_pin = 2 },
+ .irq_en = { .reg = 0x60, .width_per_pin = 1 },
+ .irq_status = { .reg = 0x64, .width_per_pin = 1 },
+ .irq_clr = { .reg = 0x68, .width_per_pin = 1 },
+ .irq_trigger = { .reg = 0x6c, .width_per_pin = 1 },
+ .irq_level = { .reg = 0x70, .width_per_pin = 1 },
+ .irq_both_edge = { .reg = 0x74, .width_per_pin = 1 },
+ .irq_edge = { .reg = 0x78, .width_per_pin = 1 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_per2pok_pinctrl_info = {
+ .name = "jhb100-per2pok",
+ .gc_base = -1,
+ .pl_desc = jhb100_per2pok_pl_desc,
+ .crl_desc = jhb100_per2pok_pinctrl_rl_desc,
+ .regs = &jhb100_per2pok_pinctrl_regs,
+};
+
+static const struct of_device_id jhb100_per2pok_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-per2pok-pinctrl",
+ .data = &jhb100_per2pok_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per2pok_pinctrl_of_match);
+
+static struct platform_driver jhb100_per2pok_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-per2pok-pinctrl",
+ .of_match_table = jhb100_per2pok_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_per2pok_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC Peripheral-2 Power OK domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v1 17/20] dt-bindings: pinctrl: Add starfive,jhb100-per3-pinctrl
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (15 preceding siblings ...)
2026-04-24 11:13 ` [PATCH v1 16/20] pinctrl: starfive: Add StarFive JHB100 per2pok controller driver Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-24 11:13 ` [PATCH v1 18/20] pinctrl: starfive: Add StarFive JHB100 per3 controller driver Changhuang Liang
` (3 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC Peripheral-3(per3) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../pinctrl/starfive,jhb100-per3-pinctrl.yaml | 177 ++++++++++++++++++
1 file changed, 177 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per3-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per3-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per3-pinctrl.yaml
new file mode 100644
index 000000000000..263392a5774c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per3-pinctrl.yaml
@@ -0,0 +1,177 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per3-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 Peripheral-3 Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "per3" pinctrl domain.
+
+ The "per3" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO interrupt handling.
+
+ In the Peripheral-3 Pin Controller, there are 11 multi-function GPIO_PADs. Each of them
+ can be multiplexed to several peripherals through function selection. Each iopad has a
+ maximum of up to 2 functions - 0 and 1. Function 0 is the default function which is
+ generally the GPIO function. Function 1 is the alternate function or peripheral signal
+ that can be routed to an iopad. The function selection can be carried out by writing
+ the function number to the iopad function select register.
+ Each iopad is configurable with parameters such as input-enable, internal pull-up/pull-down
+ bias, drive strength, schmitt trigger, slew rate, and debounce width.
+
+ This domain contains an IO group which support voltage levels 1.8V, 2.5V, and 3.3V
+ 1. gpios - comprises PAD_GPIO_E0 through PAD_GPIO_E10.
+
+ Each of the above IO groups must be configured with a voltage setting that matches the external
+ voltage level provided to the IO group.
+
+maintainers:
+ - Alex Soo <yuklin.soo@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-per3-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ gpio-line-names: true
+
+ gpios-vref:
+ default: 0
+ description: |
+ Voltage reference value for the IO group "gpios"
+ 0: voltage reference value for 3.3V
+ 1: voltage reference value for 2.5V
+ 2: voltage reference value for 1.8V
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate and drive strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ unevaluatedProperties: false
+
+ properties:
+ pinmux:
+ description: |
+ The list of GPIOs and their function select.
+ The PINMUX macros are used to configure the
+ function selection.
+
+ bias-disable: true
+
+ bias-pull-up:
+ type: boolean
+
+ bias-pull-down:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-enable: true
+
+ input-disable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow (half frequency)
+ 1: fast
+
+ starfive,gmac-vsel:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ description:
+ RGMII mode voltage select 0 = 1.8V/3.3V, 1 = 2.5V
+ enum: [0, 1]
+
+ starfive,debounce-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ description:
+ Debounce width 0 = Disabled, Others = 80ns*N stages
+
+required:
+ - compatible
+ - reg
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_per3: pinctrl@11c42000 {
+ compatible = "starfive,jhb100-per3-pinctrl";
+ reg = <0x0 0x11c42000 0x0 0x1000>;
+ resets = <&per3crg 6>;
+ interrupts = <64>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per3 0 0 11>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v1 18/20] pinctrl: starfive: Add StarFive JHB100 per3 controller driver
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (16 preceding siblings ...)
2026-04-24 11:13 ` [PATCH v1 17/20] dt-bindings: pinctrl: Add starfive,jhb100-per3-pinctrl Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-24 11:13 ` [PATCH v1 19/20] riscv: dts: starfive: Add StarFive JHB100 pin function definitions Changhuang Liang
` (2 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC Peripheral-3(per3) pinctrl
controller.
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 12 +++
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-per3.c | 101 ++++++++++++++++++
3 files changed, 114 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per3.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index ed29f87e9d7a..07cef96f8e90 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -107,6 +107,18 @@ config PINCTRL_STARFIVE_JHB100_PER2POK
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+config PINCTRL_STARFIVE_JHB100_PER3
+ tristate "StarFive JHB100 SoC Peripheral-3 pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ depends on OF
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support Peripheral-3 pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
+
config PINCTRL_STARFIVE_JHB100_SYS0
tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index 213002da9cdd..351fce524fec 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER1) += pinctrl-starfive-jhb100-per1.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER2) += pinctrl-starfive-jhb100-per2.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER2POK) += pinctrl-starfive-jhb100-per2pok.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER3) += pinctrl-starfive-jhb100-per3.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per3.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per3.c
new file mode 100644
index 000000000000..a2e6ea4097a5
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per3.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC Peripheral-3 domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+static const struct jhb100_pin_layout_desc jhb100_per3_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 11, .name = "gpio", .gpio_func_sel = 0 },
+ { .pin_start = 11, .pin_cnt = 1, .name = "peci1_out", .gpio_func_sel = -1 },
+ { .pin_start = 12, .pin_cnt = 1, .name = "peci2_out", .gpio_func_sel = -1 },
+ { 0xff },
+};
+
+static struct config_reg_layout_desc jhb100_per3_pinctrl_rl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 2,
+ .drive_strength_2bit = { .shift = 0, .width = 2 },
+ .input_enable = { .shift = 2, .width = 1 },
+ .pull_down = { .shift = 3, .width = 1 },
+ .pull_up = { .shift = 4, .width = 1 },
+ .slew_rate = { .shift = 5, .width = 1 },
+ .schmitt_trigger_select = { .shift = 6, .width = 1 },
+ .reserved = { .shift = 7, .width = 8 },
+ .debounce_width = { .shift = 15, .width = 17 },
+ },
+ {
+ .pin_start = 2,
+ .pin_cnt = 9,
+ .input_enable = { .shift = 0, .width = 1 },
+ .slew_rate = { .shift = 1, .width = 1 },
+ .vsel = { .shift = 2, .width = 2,
+ .func = BIT(PER3_GMAC_RMII_FUNC) },
+ .reserved = { .shift = 4, .width = 11 },
+ .debounce_width = { .shift = 15, .width = 17 },
+ },
+ { 0xff },
+};
+
+static const struct pinvref_desc pinvref_desc_per3[] = {
+ {
+ .name = "gpios",
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_2_5V) |
+ BIT(JHB100_PINVREF_3_3V)
+ },
+ { NULL },
+};
+
+struct starfive_pinctrl_regs jhb100_per3_pinctrl_regs = {
+ .vref = { .reg = 0x00, .pv_desc = pinvref_desc_per3 },
+ .config = { .reg = 0x04, .width_per_pin = 1 },
+ .output = { .reg = 0x30, .width_per_pin = 1 },
+ .output_en = { .reg = 0x34, .width_per_pin = 1 },
+ .gpio_status = { .reg = 0x38, .width_per_pin = 1 },
+ .func_sel = { .reg = 0x3c, .width_per_pin = 2 },
+ .irq_en = { .reg = 0x40, .width_per_pin = 1 },
+ .irq_status = { .reg = 0x44, .width_per_pin = 1 },
+ .irq_clr = { .reg = 0x48, .width_per_pin = 1 },
+ .irq_trigger = { .reg = 0x4c, .width_per_pin = 1 },
+ .irq_level = { .reg = 0x50, .width_per_pin = 1 },
+ .irq_both_edge = { .reg = 0x54, .width_per_pin = 1 },
+ .irq_edge = { .reg = 0x58, .width_per_pin = 1 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_per3_pinctrl_info = {
+ .name = "jhb100-per3",
+ .gc_base = -1,
+ .pl_desc = jhb100_per3_pl_desc,
+ .crl_desc = jhb100_per3_pinctrl_rl_desc,
+ .regs = &jhb100_per3_pinctrl_regs,
+};
+
+static const struct of_device_id jhb100_per3_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-per3-pinctrl",
+ .data = &jhb100_per3_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per3_pinctrl_of_match);
+
+static struct platform_driver jhb100_per3_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-per3-pinctrl",
+ .of_match_table = jhb100_per3_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_per3_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC Peripheral-3 domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v1 19/20] riscv: dts: starfive: Add StarFive JHB100 pin function definitions
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (17 preceding siblings ...)
2026-04-24 11:13 ` [PATCH v1 18/20] pinctrl: starfive: Add StarFive JHB100 per3 controller driver Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-24 17:00 ` Conor Dooley
2026-04-24 11:13 ` [PATCH v1 20/20] riscv: dts: starfive: jhb100: Add pinctrl nodes Changhuang Liang
2026-04-28 10:11 ` [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Linus Walleij
20 siblings, 1 reply; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
From: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Add pin function definitions for StarFive JHB100 SoC.
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jhb100-pinfunc.h | 642 ++++++++++++++++++
1 file changed, 642 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jhb100-pinfunc.h
diff --git a/arch/riscv/boot/dts/starfive/jhb100-pinfunc.h b/arch/riscv/boot/dts/starfive/jhb100-pinfunc.h
new file mode 100644
index 000000000000..cddad07444b0
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jhb100-pinfunc.h
@@ -0,0 +1,642 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ */
+
+#ifndef __JHB100_PINFUNC_H__
+#define __JHB100_PINFUNC_H__
+
+/*
+ * pinmux bits:
+ * | 31 - 10 | 9 - 8 | 7 - 0 |
+ * | reserved | function | gpio nr |
+ *
+ * func: function value: 0, 1, or 2
+ * gpio nr: gpio pad number, 0 through ngpios - 1
+ */
+#define PINMUX(n, func) ((((func) & 0x3) << 8) | ((n) & 0xff))
+
+/* pinctrl_sys0 pad numbers */
+#define PADNUM_SYS0_GPIO_A0 0
+#define PADNUM_SYS0_GPIO_A1 1
+#define PADNUM_SYS0_GPIO_A2 2
+#define PADNUM_SYS0_GPIO_A3 3
+
+/* pinctrl_sys0h pad numbers */
+#define PADNUM_SYS0H_GPIO_A4 0
+#define PADNUM_SYS0H_GPIO_A5 1
+#define PADNUM_SYS0H_GPIO_A6 2
+#define PADNUM_SYS0H_GPIO_A7 3
+#define PADNUM_SYS0H_GPIO_A8 4
+#define PADNUM_SYS0H_GPIO_A9 5
+#define PADNUM_SYS0H_GPIO_A10 6
+#define PADNUM_SYS0H_GPIO_A11 7
+#define PADNUM_SYS0H_GPIO_A12 8
+#define PADNUM_SYS0H_GPIO_A13 9
+#define PADNUM_SYS0H_GPIO_A14 10
+#define PADNUM_SYS0H_GPIO_A15 11
+
+/* pinctrl_sys1 pad numbers */
+#define PADNUM_SYS1_GPIO_A16 0
+#define PADNUM_SYS1_GPIO_A17 1
+#define PADNUM_SYS1_GPIO_A18 2
+#define PADNUM_SYS1_GPIO_A19 3
+#define PADNUM_SYS1_GPIO_A20 4
+#define PADNUM_SYS1_GPIO_A21 5
+#define PADNUM_SYS1_GPIO_A22 6
+#define PADNUM_SYS1_GPIO_A23 7
+
+/* pinctrl_sys2 pad numbers */
+#define PADNUM_SYS2_GPIO_A24 0
+#define PADNUM_SYS2_GPIO_A25 1
+#define PADNUM_SYS2_GPIO_A26 2
+#define PADNUM_SYS2_GPIO_A27 3
+#define PADNUM_SYS2_GPIO_A28 4
+#define PADNUM_SYS2_GPIO_A29 5
+#define PADNUM_SYS2_GPIO_A30 6
+#define PADNUM_SYS2_GPIO_A31 7
+#define PADNUM_SYS2_GPIO_A32 8
+#define PADNUM_SYS2_GPIO_A33 9
+#define PADNUM_SYS2_GPIO_A34 10
+#define PADNUM_SYS2_GPIO_A35 11
+#define PADNUM_SYS2_GPIO_A36 12
+#define PADNUM_SYS2_GPIO_A37 13
+#define PADNUM_SYS2_GPIO_A38 14
+#define PADNUM_SYS2_GPIO_A39 15
+#define PADNUM_SYS2_GPIO_A40 16
+#define PADNUM_SYS2_GPIO_A41 17
+#define PADNUM_SYS2_GPIO_A42 18
+#define PADNUM_SYS2_GPIO_A43 19
+#define PADNUM_SYS2_GPIO_A44 20
+#define PADNUM_SYS2_GPIO_A45 21
+#define PADNUM_SYS2_GPIO_A46 22
+#define PADNUM_SYS2_GPIO_A47 23
+#define PADNUM_SYS2_GPIO_A48 24
+#define PADNUM_SYS2_GPIO_A49 25
+#define PADNUM_SYS2_GPIO_A50 26
+#define PADNUM_SYS2_GPIO_A51 27
+#define PADNUM_SYS2_GPIO_A52 28
+#define PADNUM_SYS2_GPIO_A53 29
+#define PADNUM_SYS2_GPIO_A54 30
+#define PADNUM_SYS2_GPIO_A55 31
+#define PADNUM_SYS2_GPIO_A56 32
+#define PADNUM_SYS2_GPIO_A57 33
+#define PADNUM_SYS2_GPIO_A58 34
+#define PADNUM_SYS2_GPIO_A59 35
+#define PADNUM_SYS2_GPIO_A60 36
+
+/* pinctrl_per0 pad numbers */
+#define PADNUM_PER0_GPIO_B0 0
+#define PADNUM_PER0_GPIO_B1 1
+#define PADNUM_PER0_GPIO_B2 2
+#define PADNUM_PER0_GPIO_B3 3
+#define PADNUM_PER0_GPIO_B4 4
+#define PADNUM_PER0_GPIO_B5 5
+#define PADNUM_PER0_GPIO_B6 6
+#define PADNUM_PER0_GPIO_B7 7
+#define PADNUM_PER0_GPIO_B8 8
+#define PADNUM_PER0_GPIO_B9 9
+#define PADNUM_PER0_GPIO_B10 10
+#define PADNUM_PER0_GPIO_B11 11
+#define PADNUM_PER0_GPIO_B12 12
+#define PADNUM_PER0_GPIO_B13 13
+#define PADNUM_PER0_GPIO_B14 14
+#define PADNUM_PER0_GPIO_B15 15
+#define PADNUM_PER0_GPIO_B16 16
+#define PADNUM_PER0_GPIO_B17 17
+#define PADNUM_PER0_GPIO_B18 18
+#define PADNUM_PER0_GPIO_B19 19
+#define PADNUM_PER0_GPIO_B20 20
+#define PADNUM_PER0_GPIO_B21 21
+#define PADNUM_PER0_GPIO_B22 22
+#define PADNUM_PER0_GPIO_B23 23
+#define PADNUM_PER0_GPIO_B24 24
+#define PADNUM_PER0_GPIO_B25 25
+#define PADNUM_PER0_GPIO_B26 26
+#define PADNUM_PER0_GPIO_B27 27
+#define PADNUM_PER0_GPIO_B28 28
+#define PADNUM_PER0_GPIO_B29 29
+#define PADNUM_PER0_GPIO_B30 30
+#define PADNUM_PER0_GPIO_B31 31
+#define PADNUM_PER0_GPIO_B32 32
+#define PADNUM_PER0_GPIO_B33 33
+#define PADNUM_PER0_GPIO_B34 34
+#define PADNUM_PER0_GPIO_B35 35
+#define PADNUM_PER0_GPIO_B36 36
+#define PADNUM_PER0_GPIO_B37 37
+#define PADNUM_PER0_GPIO_B38 38
+#define PADNUM_PER0_GPIO_B39 39
+#define PADNUM_PER0_GPIO_B40 40
+#define PADNUM_PER0_GPIO_B41 41
+#define PADNUM_PER0_GPIO_B42 42
+#define PADNUM_PER0_GPIO_B43 43
+#define PADNUM_PER0_GPIO_B44 44
+#define PADNUM_PER0_GPIO_B45 45
+#define PADNUM_PER0_GPIO_B46 46
+#define PADNUM_PER0_GPIO_B47 47
+#define PADNUM_PER0_GPIO_B48 48
+#define PADNUM_PER0_GPIO_B49 49
+#define PADNUM_PER0_GPIO_B50 50
+#define PADNUM_PER0_GPIO_B51 51
+#define PADNUM_PER0_GPIO_B52 52
+#define PADNUM_PER0_GPIO_B53 53
+#define PADNUM_PER0_GPIO_B54 54
+#define PADNUM_PER0_GPIO_B55 55
+#define PADNUM_PER0_GPIO_B56 56
+#define PADNUM_PER0_GPIO_B57 57
+#define PADNUM_PER0_GPIO_B58 58
+#define PADNUM_PER0_GPIO_B59 59
+
+/* pinctrl_per1 pad numbers */
+#define PADNUM_PER1_GPIO_C0 0
+#define PADNUM_PER1_GPIO_C1 1
+#define PADNUM_PER1_GPIO_C2 2
+#define PADNUM_PER1_GPIO_C3 3
+#define PADNUM_PER1_GPIO_C4 4
+#define PADNUM_PER1_GPIO_C5 5
+#define PADNUM_PER1_GPIO_C6 6
+#define PADNUM_PER1_GPIO_C7 7
+#define PADNUM_PER1_GPIO_C8 8
+#define PADNUM_PER1_GPIO_C9 9
+#define PADNUM_PER1_GPIO_C10 10
+#define PADNUM_PER1_GPIO_C11 11
+#define PADNUM_PER1_GPIO_C12 12
+#define PADNUM_PER1_GPIO_C13 13
+#define PADNUM_PER1_GPIO_C14 14
+#define PADNUM_PER1_GPIO_C15 15
+#define PADNUM_PER1_GPIO_C16 16
+#define PADNUM_PER1_GPIO_C17 17
+#define PADNUM_PER1_GPIO_C18 18
+#define PADNUM_PER1_GPIO_C19 19
+#define PADNUM_PER1_GPIO_C20 20
+#define PADNUM_PER1_GPIO_C21 21
+#define PADNUM_PER1_GPIO_C22 22
+#define PADNUM_PER1_GPIO_C23 23
+#define PADNUM_PER1_GPIO_C24 24
+#define PADNUM_PER1_GPIO_C25 25
+#define PADNUM_PER1_GPIO_C26 26
+#define PADNUM_PER1_GPIO_C27 27
+#define PADNUM_PER1_GPIO_C28 28
+#define PADNUM_PER1_GPIO_C29 29
+#define PADNUM_PER1_GPIO_C30 30
+#define PADNUM_PER1_GPIO_C31 31
+#define PADNUM_PER1_GPIO_C32 32
+#define PADNUM_PER1_GPIO_C33 33
+#define PADNUM_PER1_GPIO_C34 34
+#define PADNUM_PER1_GPIO_C35 35
+
+/* pinctrl_per0 pad numbers */
+#define PADNUM_PER2_GPIO_D0 0
+#define PADNUM_PER2_GPIO_D1 1
+#define PADNUM_PER2_GPIO_D2 2
+#define PADNUM_PER2_GPIO_D3 3
+#define PADNUM_PER2_GPIO_D4 4
+#define PADNUM_PER2_GPIO_D5 5
+#define PADNUM_PER2_GPIO_D6 6
+#define PADNUM_PER2_GPIO_D7 7
+#define PADNUM_PER2_GPIO_D8 8
+#define PADNUM_PER2_GPIO_D9 9
+#define PADNUM_PER2_GPIO_D10 10
+#define PADNUM_PER2_GPIO_D11 11
+#define PADNUM_PER2_GPIO_D12 12
+#define PADNUM_PER2_GPIO_D13 13
+#define PADNUM_PER2_GPIO_D14 14
+#define PADNUM_PER2_GPIO_D15 15
+#define PADNUM_PER2_GPIO_D16 16
+#define PADNUM_PER2_GPIO_D17 17
+#define PADNUM_PER2_GPIO_D18 18
+#define PADNUM_PER2_GPIO_D19 19
+#define PADNUM_PER2_GPIO_D20 20
+#define PADNUM_PER2_GPIO_D21 21
+#define PADNUM_PER2_GPIO_D22 22
+#define PADNUM_PER2_GPIO_D23 23
+#define PADNUM_PER2_GPIO_D24 24
+#define PADNUM_PER2_GPIO_D25 25
+#define PADNUM_PER2_GPIO_D26 26
+#define PADNUM_PER2_GPIO_D27 27
+#define PADNUM_PER2_GPIO_D28 28
+#define PADNUM_PER2_GPIO_D29 29
+#define PADNUM_PER2_GPIO_D30 30
+
+/* pinctrl_per2pok pad numbers */
+#define PADNUM_PER2POK_GPIO_D31 0
+#define PADNUM_PER2POK_GPIO_D32 1
+#define PADNUM_PER2POK_GPIO_D33 2
+#define PADNUM_PER2POK_GPIO_D34 3
+#define PADNUM_PER2POK_GPIO_D35 4
+#define PADNUM_PER2POK_GPIO_D36 5
+#define PADNUM_PER2POK_GPIO_D37 6
+#define PADNUM_PER2POK_GPIO_D38 7
+#define PADNUM_PER2POK_GPIO_D39 8
+#define PADNUM_PER2POK_GPIO_D40 9
+#define PADNUM_PER2POK_GPIO_D41 10
+#define PADNUM_PER2POK_GPIO_D42 11
+#define PADNUM_PER2POK_GPIO_D43 12
+#define PADNUM_PER2POK_GPIO_D44 13
+#define PADNUM_PER2POK_GPIO_D45 14
+#define PADNUM_PER2POK_GPIO_D46 15
+#define PADNUM_PER2POK_GPIO_D47 16
+#define PADNUM_PER2POK_GPIO_D48 17
+
+/* pinctrl_per3 pad numbers */
+#define PADNUM_PER3_GPIO_E0 0
+#define PADNUM_PER3_GPIO_E1 1
+#define PADNUM_PER3_GPIO_E2 2
+#define PADNUM_PER3_GPIO_E3 3
+#define PADNUM_PER3_GPIO_E4 4
+#define PADNUM_PER3_GPIO_E5 5
+#define PADNUM_PER3_GPIO_E6 6
+#define PADNUM_PER3_GPIO_E7 7
+#define PADNUM_PER3_GPIO_E8 8
+#define PADNUM_PER3_GPIO_E9 9
+#define PADNUM_PER3_GPIO_E10 10
+#define PADNUM_PER3_GPIO_E11 11
+
+/* Function Selection */
+
+/* pinctrl_sys0 pad function selection */
+#define FUNC_SYS0_DOM_HOSTSS_AUXPWRGOOD0 1
+#define FUNC_SYS0_DOM_HOSTSS_AUXPWRGOOD1 1
+#define FUNC_SYS0_HBLED 1
+#define FUNC_SYS0_PE2RST_OUT 0
+#define FUNC_SYS0_GPIO3 1
+
+/* pinctrl_sys0h pad function selection */
+#define FUNC_SYS0H_ESPI0_DATA0 1
+#define FUNC_SYS0H_ESPI0_DATA1 1
+#define FUNC_SYS0H_ESPI0_DATA2 1
+#define FUNC_SYS0H_ESPI0_DATA3 1
+#define FUNC_SYS0H_ESPI0_CLK 1
+#define FUNC_SYS0H_ESPI0_CS 1
+#define FUNC_SYS0H_ESPI0_ALERT 1
+#define FUNC_SYS0H_ESPI0_RESET 0
+#define FUNC_SYS0H_GPIO7 1
+#define FUNC_SYS0H_ESPI0_VW0 1
+#define FUNC_SYS0H_ESPI0_VW1 1
+#define FUNC_SYS0H_ESPI0_VW2 1
+#define FUNC_SYS0H_ESPI0_VW3 1
+#define FUNC_SYS0H_ESPI1_VW0 2
+#define FUNC_SYS0H_ESPI1_VW1 2
+#define FUNC_SYS0H_ESPI1_VW2 2
+#define FUNC_SYS0H_ESPI1_VW3 2
+#define FUNC_SYS0H_SCAP_TRIG0_A 3
+#define FUNC_SYS0H_SCAP_TRIG1_A 3
+
+/* pinctrl_sys1 pad numbers */
+#define FUNC_SYS1_ESPI1_DATA0 1
+#define FUNC_SYS1_ESPI1_DATA1 1
+#define FUNC_SYS1_ESPI1_DATA2 1
+#define FUNC_SYS1_ESPI1_DATA3 1
+#define FUNC_SYS1_ESPI1_CLK 1
+#define FUNC_SYS1_ESPI1_CS 1
+#define FUNC_SYS1_ESPI1_ALERT 1
+#define FUNC_SYS1_ESPI1_RESET 0
+#define FUNC_SYS1_GPIO7 1
+
+#define FUNC_SYS1_HOST0_PORT80_DATA_OUT0 2
+#define FUNC_SYS1_HOST0_PORT80_DATA_OUT1 2
+#define FUNC_SYS1_HOST0_PORT80_DATA_OUT2 2
+#define FUNC_SYS1_HOST0_PORT80_DATA_OUT3 2
+#define FUNC_SYS1_HOST0_PORT80_DATA_OUT4 2
+#define FUNC_SYS1_HOST0_PORT80_DATA_OUT5 2
+#define FUNC_SYS1_HOST0_PORT80_DATA_OUT6 2
+#define FUNC_SYS1_HOST0_PORT80_DATA_OUT7 2
+
+#define FUNC_SYS1_HOST1_PORT80_DATA_OUT0 3
+#define FUNC_SYS1_HOST1_PORT80_DATA_OUT1 3
+#define FUNC_SYS1_HOST1_PORT80_DATA_OUT2 3
+#define FUNC_SYS1_HOST1_PORT80_DATA_OUT3 3
+#define FUNC_SYS1_HOST1_PORT80_DATA_OUT4 3
+#define FUNC_SYS1_HOST1_PORT80_DATA_OUT5 3
+#define FUNC_SYS1_HOST1_PORT80_DATA_OUT6 3
+#define FUNC_SYS1_HOST1_PORT80_DATA_OUT7 3
+
+/* pinctrl_sys2 pad function selection */
+#define FUNC_SYS2_UART_CTS 1
+#define FUNC_SYS2_UART_RTS 1
+#define FUNC_SYS2_UART_DCD 1
+#define FUNC_SYS2_UART_DSR 1
+#define FUNC_SYS2_UART_DTR 1
+#define FUNC_SYS2_UART_RI 1
+#define FUNC_SYS2_UART0_TX 1
+#define FUNC_SYS2_UART0_RX 1
+#define FUNC_SYS2_UART1_TX 1
+#define FUNC_SYS2_UART1_RX 1
+#define FUNC_SYS2_UART2_TX 1
+#define FUNC_SYS2_UART2_RX 1
+#define FUNC_SYS2_UART3_TX 1
+#define FUNC_SYS2_UART3_RX 1
+#define FUNC_SYS2_UART4_TX 1
+#define FUNC_SYS2_UART4_RX 1
+#define FUNC_SYS2_UART5_TX 1
+#define FUNC_SYS2_UART5_RX 1
+#define FUNC_SYS2_UART6_TX 1
+#define FUNC_SYS2_UART6_RX 1
+#define FUNC_SYS2_UART7_TX 1
+#define FUNC_SYS2_UART7_RX 1
+#define FUNC_SYS2_UART8_TX 1
+#define FUNC_SYS2_UART8_RX 1
+#define FUNC_SYS2_UART9_TX 1
+#define FUNC_SYS2_UART9_RX 1
+#define FUNC_SYS2_UART10_TX 1
+#define FUNC_SYS2_UART10_RX 1
+#define FUNC_SYS2_UART11_TX 1
+#define FUNC_SYS2_UART11_RX 1
+#define FUNC_SYS2_UART12_TX 1
+#define FUNC_SYS2_UART12_RX 1
+#define FUNC_SYS2_UART13_TX 1
+#define FUNC_SYS2_UART13_RX 1
+#define FUNC_SYS2_UART14_TX 1
+#define FUNC_SYS2_UART14_RX 1
+
+#define FUNC_SYS2_I2C8_SMBALERT 2
+#define FUNC_SYS2_I2C9_SMBALERT 2
+#define FUNC_SYS2_I2C10_SMBALERT 2
+#define FUNC_SYS2_I2C11_SMBALERT 2
+#define FUNC_SYS2_I2C12_SMBALERT 2
+#define FUNC_SYS2_I2C13_SMBALERT 2
+#define FUNC_SYS2_I2C14_SMBALERT 2
+#define FUNC_SYS2_I2C15_SMBALERT 2
+#define FUNC_SYS2_HOST0_PORT80_DATA_OUT0 2
+#define FUNC_SYS2_HOST0_PORT80_DATA_OUT1 2
+#define FUNC_SYS2_HOST0_PORT80_DATA_OUT2 2
+#define FUNC_SYS2_HOST0_PORT80_DATA_OUT3 2
+#define FUNC_SYS2_HOST0_PORT80_DATA_OUT4 2
+#define FUNC_SYS2_HOST0_PORT80_DATA_OUT5 2
+#define FUNC_SYS2_HOST0_PORT80_DATA_OUT6 2
+#define FUNC_SYS2_HOST0_PORT80_DATA_OUT7 2
+#define FUNC_SYS2_JTAG_MST_TDI 2
+#define FUNC_SYS2_JTAG_MST_TRST_N 2
+#define FUNC_SYS2_JTAG_MST_TMS 2
+#define FUNC_SYS2_JTAG_MST_TCK 2
+#define FUNC_SYS2_JTAG_MST_TDO 2
+
+#define FUNC_SYS2_HOST1_PORT80_DATA_OUT0 3
+#define FUNC_SYS2_HOST1_PORT80_DATA_OUT1 3
+#define FUNC_SYS2_HOST1_PORT80_DATA_OUT2 3
+#define FUNC_SYS2_HOST1_PORT80_DATA_OUT3 3
+#define FUNC_SYS2_HOST1_PORT80_DATA_OUT4 3
+#define FUNC_SYS2_HOST1_PORT80_DATA_OUT5 3
+#define FUNC_SYS2_HOST1_PORT80_DATA_OUT6 3
+#define FUNC_SYS2_HOST1_PORT80_DATA_OUT7 3
+
+/* pinctrl_per0 function numbers */
+#define FUNC_PER0_I2C0_CLK 1
+#define FUNC_PER0_I2C0_DATA 1
+#define FUNC_PER0_I2C1_CLK 1
+#define FUNC_PER0_I2C1_DATA 1
+#define FUNC_PER0_I2C2_CLK 1
+#define FUNC_PER0_I2C2_DATA 1
+#define FUNC_PER0_I2C3_CLK 1
+#define FUNC_PER0_I2C3_DATA 1
+#define FUNC_PER0_I2C4_CLK 1
+#define FUNC_PER0_I2C4_DATA 1
+#define FUNC_PER0_I2C5_CLK 1
+#define FUNC_PER0_I2C5_DATA 1
+#define FUNC_PER0_I2C6_CLK 1
+#define FUNC_PER0_I2C6_DATA 1
+#define FUNC_PER0_I2C7_CLK 1
+#define FUNC_PER0_I2C7_DATA 1
+#define FUNC_PER0_I2C8_CLK 1
+#define FUNC_PER0_I2C8_DATA 1
+#define FUNC_PER0_I2C9_CLK 1
+#define FUNC_PER0_I2C9_DATA 1
+#define FUNC_PER0_I2C10_CLK 1
+#define FUNC_PER0_I2C10_DATA 1
+#define FUNC_PER0_I2C11_CLK 1
+#define FUNC_PER0_I2C11_DATA 1
+#define FUNC_PER0_I2C12_CLK 1
+#define FUNC_PER0_I2C12_DATA 1
+#define FUNC_PER0_I2C13_CLK 1
+#define FUNC_PER0_I2C13_DATA 1
+#define FUNC_PER0_SMBUS0_SMBALERT 1
+#define FUNC_PER0_SMBUS1_SMBALERT 1
+#define FUNC_PER0_SMBUS2_SMBALERT 1
+#define FUNC_PER0_SMBUS3_SMBALERT 1
+#define FUNC_PER0_SMBUS4_SMBALERT 1
+#define FUNC_PER0_SMBUS5_SMBALERT 1
+#define FUNC_PER0_SMBUS6_SMBALERT 1
+#define FUNC_PER0_SMBUS7_SMBALERT 1
+#define FUNC_PER0_MIPI_I3C12_SCL0 1
+#define FUNC_PER0_MIPI_I3C12_SDA0 1
+#define FUNC_PER0_MIPI_I3C13_SCL0 1
+#define FUNC_PER0_MIPI_I3C13_SDA0 1
+#define FUNC_PER0_MIPI_I3C14_SCL0 1
+#define FUNC_PER0_MIPI_I3C14_SDA0 1
+#define FUNC_PER0_MIPI_I3C15_SCL0 1
+#define FUNC_PER0_MIPI_I3C15_SDA0 1
+#define FUNC_PER0_MIPI_I3C0_SCL0 1
+#define FUNC_PER0_MIPI_I3C0_SDA0 1
+#define FUNC_PER0_MIPI_I3C1_SCL0 1
+#define FUNC_PER0_MIPI_I3C1_SDA0 1
+#define FUNC_PER0_MIPI_I3C2_SCL0 1
+#define FUNC_PER0_MIPI_I3C2_SDA0 1
+#define FUNC_PER0_MIPI_I3C3_SCL0 1
+#define FUNC_PER0_MIPI_I3C3_SDA0 1
+#define FUNC_PER0_MIPI_I3C4_SCL1 1
+#define FUNC_PER0_MIPI_I3C4_SDA1 1
+#define FUNC_PER0_MIPI_I3C5_SCL1 1
+#define FUNC_PER0_MIPI_I3C5_SDA1 1
+#define FUNC_PER0_MIPI_I3C6_SCL1 1
+#define FUNC_PER0_MIPI_I3C6_SDA1 1
+#define FUNC_PER0_MIPI_I3C7_SCL1 1
+#define FUNC_PER0_MIPI_I3C7_SDA1 1
+
+#define FUNC_PER0_MIPI_I3C4_SCL0 2
+#define FUNC_PER0_MIPI_I3C4_SDA0 2
+#define FUNC_PER0_MIPI_I3C5_SCL0 2
+#define FUNC_PER0_MIPI_I3C5_SDA0 2
+#define FUNC_PER0_MIPI_I3C6_SCL0 2
+#define FUNC_PER0_MIPI_I3C6_SDA0 2
+#define FUNC_PER0_MIPI_I3C7_SCL0 2
+#define FUNC_PER0_MIPI_I3C7_SDA0 2
+#define FUNC_PER0_MIPI_I3C8_SCL0 2
+#define FUNC_PER0_MIPI_I3C8_SDA0 2
+#define FUNC_PER0_MIPI_I3C9_SCL0 2
+#define FUNC_PER0_MIPI_I3C9_SDA0 2
+#define FUNC_PER0_MIPI_I3C10_SCL0 2
+#define FUNC_PER0_MIPI_I3C10_SDA0 2
+#define FUNC_PER0_MIPI_I3C11_SCL0 2
+#define FUNC_PER0_MIPI_I3C11_SDA0 2
+#define FUNC_PER0_GMAC2_MDC 2
+#define FUNC_PER0_GMAC2_MDIO 2
+#define FUNC_PER0_GMAC3_MDC 2
+#define FUNC_PER0_GMAC3_MDIO 2
+#define FUNC_PER0_GMAC1_MDC 2
+#define FUNC_PER0_GMAC1_MDIO 2
+#define FUNC_PER0_WDT0_3_OR_RESET_OUTPUT 2
+#define FUNC_PER0_WDT_SECRP_RESET_OUTPUT 2
+#define FUNC_PER0_WDT4_RESET_OUTPUT 2
+#define FUNC_PER0_WDT4_RESTART_INPUT 2
+
+/* pinctrl_per1 pad function selection */
+#define FUNC_PER1_SPI0_N_SS_OUT_0 1
+#define FUNC_PER1_SPI0_N_SS_OUT_1 1
+#define FUNC_PER1_SPI0_SCLK_OUT 1
+#define FUNC_PER1_SPI0_TX 1
+#define FUNC_PER1_SPI0_RX 1
+#define FUNC_PER1_SFC0_N_SS_OUT_0 1
+#define FUNC_PER1_SFC0_N_SS_OUT_1 1
+#define FUNC_PER1_SFC0_SCLK_OUT 1
+#define FUNC_PER1_SFC0_IO0 1
+#define FUNC_PER1_SFC0_IO1 1
+#define FUNC_PER1_SFC0_IO2 1
+#define FUNC_PER1_SFC0_IO3 1
+#define FUNC_PER1_SFC1_N_SS_OUT_0 1
+#define FUNC_PER1_SFC1_N_SS_OUT_1 1
+#define FUNC_PER1_SFC1_N_SS_OUT_2 1
+#define FUNC_PER1_SFC1_SCLK_OUT 1
+#define FUNC_PER1_SFC1_IO0 1
+#define FUNC_PER1_SFC1_IO1 1
+#define FUNC_PER1_SFC1_IO2 1
+#define FUNC_PER1_SFC1_IO3 1
+#define FUNC_PER1_SFC2_N_SS_OUT_0 1
+#define FUNC_PER1_SFC2_N_SS_OUT_1 1
+#define FUNC_PER1_SFC2_N_SS_OUT_2 1
+#define FUNC_PER1_SFC2_SCLK_OUT 1
+#define FUNC_PER1_SFC2_IO0 1
+#define FUNC_PER1_SFC2_IO1 1
+#define FUNC_PER1_SFC2_IO2 1
+#define FUNC_PER1_SFC2_IO3 1
+#define FUNC_PER1_SGPIO0_M_CLK 1
+#define FUNC_PER1_SGPIO0_M_LOAD 1
+#define FUNC_PER1_SGPIO0_M_DATA_OUT 1
+#define FUNC_PER1_SGPIO0_M_DATA_IN 1
+#define FUNC_PER1_I2C14_CLK 1
+#define FUNC_PER1_I2C14_DATA 1
+#define FUNC_PER1_I2C15_CLK 1
+#define FUNC_PER1_I2C15_DATA 1
+
+#define FUNC_PER1_SGPIO1_M_CLK 2
+#define FUNC_PER1_SGPIO1_M_LOAD 2
+#define FUNC_PER1_SGPIO1_M_DATA_OUT 2
+#define FUNC_PER1_SGPIO1_M_DATA_IN 2
+
+/* pinctrl_per2 function selection */
+#define FUNC_PER2_FAN0_TACH_I_0 1
+#define FUNC_PER2_FAN0_TACH_I_1 1
+#define FUNC_PER2_FAN0_TACH_I_2 1
+#define FUNC_PER2_FAN0_TACH_I_3 1
+#define FUNC_PER2_FAN0_TACH_I_4 1
+#define FUNC_PER2_FAN0_TACH_I_5 1
+#define FUNC_PER2_FAN0_TACH_I_6 1
+#define FUNC_PER2_FAN0_TACH_I_7 1
+#define FUNC_PER2_FAN0_TACH_I_8 1
+#define FUNC_PER2_FAN0_TACH_I_9 1
+#define FUNC_PER2_FAN0_TACH_I_10 1
+#define FUNC_PER2_FAN0_TACH_I_11 1
+#define FUNC_PER2_FAN0_TACH_I_12 1
+#define FUNC_PER2_FAN0_TACH_I_13 1
+#define FUNC_PER2_FAN0_TACH_I_14 1
+#define FUNC_PER2_FAN0_TACH_I_15 1
+#define FUNC_PER2_GMAC2_RGMII_RX_CLK 1
+#define FUNC_PER2_GMAC2_RGMII_RXCTL 1
+#define FUNC_PER2_GMAC2_RGMII_PHY_RXD0 1
+#define FUNC_PER2_GMAC2_RGMII_PHY_RXD1 1
+#define FUNC_PER2_GMAC2_RGMII_PHY_RXD2 1
+#define FUNC_PER2_GMAC2_RGMII_PHY_RXD3 1
+#define FUNC_PER2_GMAC2_RGMII_TX_CLK 1
+#define FUNC_PER2_GMAC2_RGMII_TXCTL 1
+#define FUNC_PER2_GMAC2_RGMII_PHY_TX0 1
+#define FUNC_PER2_GMAC2_RGMII_PHY_TX1 1
+#define FUNC_PER2_GMAC2_RGMII_PHY_TX2 1
+#define FUNC_PER2_GMAC2_RGMII_PHY_TX3 1
+
+#define FUNC_PER2_GMAC2_RMII_RX_CLK 2
+#define FUNC_PER2_GMAC2_RMII_CRSDV 2
+#define FUNC_PER2_GMAC2_RMII_PHY_RXD0 2
+#define FUNC_PER2_GMAC2_RMII_PHY_RXD1 2
+#define FUNC_PER2_GMAC2_RMII_RX_CKO 2
+#define FUNC_PER2_GMAC2_RMII_TXEN 2
+#define FUNC_PER2_GMAC2_RMII_PHY_TXD0 2
+#define FUNC_PER2_GMAC2_RMII_PHY_TXD1 2
+
+#define FUNC_PER2_HOSTSS0_PORT80_DATA_OUT0 2
+#define FUNC_PER2_HOSTSS0_PORT80_DATA_OUT1 2
+#define FUNC_PER2_HOSTSS0_PORT80_DATA_OUT2 2
+#define FUNC_PER2_HOSTSS0_PORT80_DATA_OUT3 2
+#define FUNC_PER2_HOSTSS0_PORT80_DATA_OUT4 2
+#define FUNC_PER2_HOSTSS0_PORT80_DATA_OUT5 2
+#define FUNC_PER2_HOSTSS0_PORT80_DATA_OUT6 2
+#define FUNC_PER2_HOSTSS0_PORT80_DATA_OUT7 2
+#define FUNC_PER2_HOSTSS1_PORT80_DATA_OUT0 3
+#define FUNC_PER2_HOSTSS1_PORT80_DATA_OUT1 3
+#define FUNC_PER2_HOSTSS1_PORT80_DATA_OUT2 3
+#define FUNC_PER2_HOSTSS1_PORT80_DATA_OUT3 3
+#define FUNC_PER2_HOSTSS1_PORT80_DATA_OUT4 3
+#define FUNC_PER2_HOSTSS1_PORT80_DATA_OUT5 3
+#define FUNC_PER2_HOSTSS1_PORT80_DATA_OUT6 3
+#define FUNC_PER2_HOSTSS1_PORT80_DATA_OUT7 3
+
+/* pinctrl_per2pok function selection */
+#define FUNC_PER2POK_PWM0_CHANNEL0 0
+#define FUNC_PER2POK_PWM0_CHANNEL1 0
+#define FUNC_PER2POK_PWM0_CHANNEL2 0
+#define FUNC_PER2POK_PWM0_CHANNEL3 0
+#define FUNC_PER2POK_PWM0_CHANNEL4 0
+#define FUNC_PER2POK_PWM0_CHANNEL5 0
+#define FUNC_PER2POK_PWM0_CHANNEL6 0
+#define FUNC_PER2POK_PWM0_CHANNEL7 0
+
+#define FUNC_PER2POK_CAN0_TXD 1
+#define FUNC_PER2POK_CAN0_RXD 1
+#define FUNC_PER2POK_CAN0_STBY 1
+#define FUNC_PER2POK_CAN1_TXD 1
+#define FUNC_PER2POK_CAN1_RXD 1
+#define FUNC_PER2POK_CAN1_STBY 1
+#define FUNC_PER2POK_GPIO_PASSTHRU1_IN 1
+#define FUNC_PER2POK_GPIO_PASSTHRU1_OUT 1
+#define FUNC_PER2POK_GPIO_PASSTHRU2_IN 1
+#define FUNC_PER2POK_GPIO_PASSTHRU2_OUT 1
+#define FUNC_PER2POK_GPIO10 1
+#define FUNC_PER2POK_GPIO11 1
+#define FUNC_PER2POK_GPIO12 1
+#define FUNC_PER2POK_GPIO13 1
+#define FUNC_PER2POK_GPIO14 1
+#define FUNC_PER2POK_GPIO15 1
+#define FUNC_PER2POK_GPIO16 1
+#define FUNC_PER2POK_GPIO17 1
+
+#define FUNC_PER2POK_GPIO_PASSTHRU3_IN 2
+#define FUNC_PER2POK_GPIO_PASSTHRU3_OUT 2
+#define FUNC_PER2POK_HOSTSS0_PORT80_DATA_OUT0 2
+#define FUNC_PER2POK_HOSTSS0_PORT80_DATA_OUT1 2
+#define FUNC_PER2POK_HOSTSS0_PORT80_DATA_OUT2 2
+#define FUNC_PER2POK_HOSTSS0_PORT80_DATA_OUT3 2
+#define FUNC_PER2POK_HOSTSS0_PORT80_DATA_OUT4 2
+#define FUNC_PER2POK_HOSTSS0_PORT80_DATA_OUT5 2
+#define FUNC_PER2POK_HOSTSS0_PORT80_DATA_OUT6 2
+#define FUNC_PER2POK_HOSTSS0_PORT80_DATA_OUT7 2
+
+#define FUNC_PER2POK_HOSTSS1_PORT80_DATA_OUT0 3
+#define FUNC_PER2POK_HOSTSS1_PORT80_DATA_OUT1 3
+#define FUNC_PER2POK_HOSTSS1_PORT80_DATA_OUT2 3
+#define FUNC_PER2POK_HOSTSS1_PORT80_DATA_OUT3 3
+#define FUNC_PER2POK_HOSTSS1_PORT80_DATA_OUT4 3
+#define FUNC_PER2POK_HOSTSS1_PORT80_DATA_OUT5 3
+#define FUNC_PER2POK_HOSTSS1_PORT80_DATA_OUT6 3
+#define FUNC_PER2POK_HOSTSS1_PORT80_DATA_OUT7 3
+
+/* pinctrl_per3 function selection */
+#define FUNC_PER3_GMAC0_MDC 1
+#define FUNC_PER3_GMAC0_MDIO 1
+#define FUNC_PER3_GMAC0_RMII_RCLKI 1
+#define FUNC_PER3_GMAC0_RMII_RCLKO 1
+#define FUNC_PER3_GMAC0_RMII_CRSDV 1
+#define FUNC_PER3_GMAC0_RMII_PHY_RXD0 1
+#define FUNC_PER3_GMAC0_RMII_PHY_RXD1 1
+#define FUNC_PER3_GMAC0_RMII_TXEN 1
+#define FUNC_PER3_GMAC0_RMII_PHY_TXD0 1
+#define FUNC_PER3_GMAC0_RMII_PHY_TXD1 1
+
+/* gpio func sel value */
+#define FUNC_SEL0_GPIO 0
+#define FUNC_SEL1_GPIO 1
+
+/* vref value */
+#define JHB100_PINVREF_3_3V 0
+#define JHB100_PINVREF_2_5V 1
+#define JHB100_PINVREF_1_8V 2
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH v1 19/20] riscv: dts: starfive: Add StarFive JHB100 pin function definitions
2026-04-24 11:13 ` [PATCH v1 19/20] riscv: dts: starfive: Add StarFive JHB100 pin function definitions Changhuang Liang
@ 2026-04-24 17:00 ` Conor Dooley
0 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2026-04-24 17:00 UTC (permalink / raw)
To: Changhuang Liang
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski, linux-gpio,
linux-kernel, devicetree, linux-riscv, Lianfeng Ouyang
[-- Attachment #1: Type: text/plain, Size: 15635 bytes --]
On Fri, Apr 24, 2026 at 04:13:29AM -0700, Changhuang Liang wrote:
+
> +/* Function Selection */
> +
> +/* pinctrl_sys0 pad function selection */
> +#define FUNC_SYS0_DOM_HOSTSS_AUXPWRGOOD0 1
> +#define FUNC_SYS0_DOM_HOSTSS_AUXPWRGOOD1 1
> +#define FUNC_SYS0_HBLED 1
> +#define FUNC_SYS0_PE2RST_OUT 0
> +#define FUNC_SYS0_GPIO3 1
> +
> +/* pinctrl_sys0h pad function selection */
> +#define FUNC_SYS0H_ESPI0_DATA0 1
> +#define FUNC_SYS0H_ESPI0_DATA1 1
> +#define FUNC_SYS0H_ESPI0_DATA2 1
> +#define FUNC_SYS0H_ESPI0_DATA3 1
> +#define FUNC_SYS0H_ESPI0_CLK 1
> +#define FUNC_SYS0H_ESPI0_CS 1
> +#define FUNC_SYS0H_ESPI0_ALERT 1
> +#define FUNC_SYS0H_ESPI0_RESET 0
> +#define FUNC_SYS0H_GPIO7 1
> +#define FUNC_SYS0H_ESPI0_VW0 1
> +#define FUNC_SYS0H_ESPI0_VW1 1
> +#define FUNC_SYS0H_ESPI0_VW2 1
> +#define FUNC_SYS0H_ESPI0_VW3 1
> +#define FUNC_SYS0H_ESPI1_VW0 2
> +#define FUNC_SYS0H_ESPI1_VW1 2
> +#define FUNC_SYS0H_ESPI1_VW2 2
> +#define FUNC_SYS0H_ESPI1_VW3 2
> +#define FUNC_SYS0H_SCAP_TRIG0_A 3
> +#define FUNC_SYS0H_SCAP_TRIG1_A 3
I'll be blunt here, I hate this. The sheer number of repeated numbers
between each pin of a function suggests to me that the approach is
wrong.
At the very least, the number of defines could be significantly reduced,
but the whole approach of using pinmux is called into question here in
my opinion.
Conor.
> +
> +/* pinctrl_sys1 pad numbers */
> +#define FUNC_SYS1_ESPI1_DATA0 1
> +#define FUNC_SYS1_ESPI1_DATA1 1
> +#define FUNC_SYS1_ESPI1_DATA2 1
> +#define FUNC_SYS1_ESPI1_DATA3 1
> +#define FUNC_SYS1_ESPI1_CLK 1
> +#define FUNC_SYS1_ESPI1_CS 1
> +#define FUNC_SYS1_ESPI1_ALERT 1
> +#define FUNC_SYS1_ESPI1_RESET 0
> +#define FUNC_SYS1_GPIO7 1
> +
> +#define FUNC_SYS1_HOST0_PORT80_DATA_OUT0 2
> +#define FUNC_SYS1_HOST0_PORT80_DATA_OUT1 2
> +#define FUNC_SYS1_HOST0_PORT80_DATA_OUT2 2
> +#define FUNC_SYS1_HOST0_PORT80_DATA_OUT3 2
> +#define FUNC_SYS1_HOST0_PORT80_DATA_OUT4 2
> +#define FUNC_SYS1_HOST0_PORT80_DATA_OUT5 2
> +#define FUNC_SYS1_HOST0_PORT80_DATA_OUT6 2
> +#define FUNC_SYS1_HOST0_PORT80_DATA_OUT7 2
> +
> +#define FUNC_SYS1_HOST1_PORT80_DATA_OUT0 3
> +#define FUNC_SYS1_HOST1_PORT80_DATA_OUT1 3
> +#define FUNC_SYS1_HOST1_PORT80_DATA_OUT2 3
> +#define FUNC_SYS1_HOST1_PORT80_DATA_OUT3 3
> +#define FUNC_SYS1_HOST1_PORT80_DATA_OUT4 3
> +#define FUNC_SYS1_HOST1_PORT80_DATA_OUT5 3
> +#define FUNC_SYS1_HOST1_PORT80_DATA_OUT6 3
> +#define FUNC_SYS1_HOST1_PORT80_DATA_OUT7 3
> +
> +/* pinctrl_sys2 pad function selection */
> +#define FUNC_SYS2_UART_CTS 1
> +#define FUNC_SYS2_UART_RTS 1
> +#define FUNC_SYS2_UART_DCD 1
> +#define FUNC_SYS2_UART_DSR 1
> +#define FUNC_SYS2_UART_DTR 1
> +#define FUNC_SYS2_UART_RI 1
> +#define FUNC_SYS2_UART0_TX 1
> +#define FUNC_SYS2_UART0_RX 1
> +#define FUNC_SYS2_UART1_TX 1
> +#define FUNC_SYS2_UART1_RX 1
> +#define FUNC_SYS2_UART2_TX 1
> +#define FUNC_SYS2_UART2_RX 1
> +#define FUNC_SYS2_UART3_TX 1
> +#define FUNC_SYS2_UART3_RX 1
> +#define FUNC_SYS2_UART4_TX 1
> +#define FUNC_SYS2_UART4_RX 1
> +#define FUNC_SYS2_UART5_TX 1
> +#define FUNC_SYS2_UART5_RX 1
> +#define FUNC_SYS2_UART6_TX 1
> +#define FUNC_SYS2_UART6_RX 1
> +#define FUNC_SYS2_UART7_TX 1
> +#define FUNC_SYS2_UART7_RX 1
> +#define FUNC_SYS2_UART8_TX 1
> +#define FUNC_SYS2_UART8_RX 1
> +#define FUNC_SYS2_UART9_TX 1
> +#define FUNC_SYS2_UART9_RX 1
> +#define FUNC_SYS2_UART10_TX 1
> +#define FUNC_SYS2_UART10_RX 1
> +#define FUNC_SYS2_UART11_TX 1
> +#define FUNC_SYS2_UART11_RX 1
> +#define FUNC_SYS2_UART12_TX 1
> +#define FUNC_SYS2_UART12_RX 1
> +#define FUNC_SYS2_UART13_TX 1
> +#define FUNC_SYS2_UART13_RX 1
> +#define FUNC_SYS2_UART14_TX 1
> +#define FUNC_SYS2_UART14_RX 1
> +
> +#define FUNC_SYS2_I2C8_SMBALERT 2
> +#define FUNC_SYS2_I2C9_SMBALERT 2
> +#define FUNC_SYS2_I2C10_SMBALERT 2
> +#define FUNC_SYS2_I2C11_SMBALERT 2
> +#define FUNC_SYS2_I2C12_SMBALERT 2
> +#define FUNC_SYS2_I2C13_SMBALERT 2
> +#define FUNC_SYS2_I2C14_SMBALERT 2
> +#define FUNC_SYS2_I2C15_SMBALERT 2
> +#define FUNC_SYS2_HOST0_PORT80_DATA_OUT0 2
> +#define FUNC_SYS2_HOST0_PORT80_DATA_OUT1 2
> +#define FUNC_SYS2_HOST0_PORT80_DATA_OUT2 2
> +#define FUNC_SYS2_HOST0_PORT80_DATA_OUT3 2
> +#define FUNC_SYS2_HOST0_PORT80_DATA_OUT4 2
> +#define FUNC_SYS2_HOST0_PORT80_DATA_OUT5 2
> +#define FUNC_SYS2_HOST0_PORT80_DATA_OUT6 2
> +#define FUNC_SYS2_HOST0_PORT80_DATA_OUT7 2
> +#define FUNC_SYS2_JTAG_MST_TDI 2
> +#define FUNC_SYS2_JTAG_MST_TRST_N 2
> +#define FUNC_SYS2_JTAG_MST_TMS 2
> +#define FUNC_SYS2_JTAG_MST_TCK 2
> +#define FUNC_SYS2_JTAG_MST_TDO 2
> +
> +#define FUNC_SYS2_HOST1_PORT80_DATA_OUT0 3
> +#define FUNC_SYS2_HOST1_PORT80_DATA_OUT1 3
> +#define FUNC_SYS2_HOST1_PORT80_DATA_OUT2 3
> +#define FUNC_SYS2_HOST1_PORT80_DATA_OUT3 3
> +#define FUNC_SYS2_HOST1_PORT80_DATA_OUT4 3
> +#define FUNC_SYS2_HOST1_PORT80_DATA_OUT5 3
> +#define FUNC_SYS2_HOST1_PORT80_DATA_OUT6 3
> +#define FUNC_SYS2_HOST1_PORT80_DATA_OUT7 3
> +
> +/* pinctrl_per0 function numbers */
> +#define FUNC_PER0_I2C0_CLK 1
> +#define FUNC_PER0_I2C0_DATA 1
> +#define FUNC_PER0_I2C1_CLK 1
> +#define FUNC_PER0_I2C1_DATA 1
> +#define FUNC_PER0_I2C2_CLK 1
> +#define FUNC_PER0_I2C2_DATA 1
> +#define FUNC_PER0_I2C3_CLK 1
> +#define FUNC_PER0_I2C3_DATA 1
> +#define FUNC_PER0_I2C4_CLK 1
> +#define FUNC_PER0_I2C4_DATA 1
> +#define FUNC_PER0_I2C5_CLK 1
> +#define FUNC_PER0_I2C5_DATA 1
> +#define FUNC_PER0_I2C6_CLK 1
> +#define FUNC_PER0_I2C6_DATA 1
> +#define FUNC_PER0_I2C7_CLK 1
> +#define FUNC_PER0_I2C7_DATA 1
> +#define FUNC_PER0_I2C8_CLK 1
> +#define FUNC_PER0_I2C8_DATA 1
> +#define FUNC_PER0_I2C9_CLK 1
> +#define FUNC_PER0_I2C9_DATA 1
> +#define FUNC_PER0_I2C10_CLK 1
> +#define FUNC_PER0_I2C10_DATA 1
> +#define FUNC_PER0_I2C11_CLK 1
> +#define FUNC_PER0_I2C11_DATA 1
> +#define FUNC_PER0_I2C12_CLK 1
> +#define FUNC_PER0_I2C12_DATA 1
> +#define FUNC_PER0_I2C13_CLK 1
> +#define FUNC_PER0_I2C13_DATA 1
> +#define FUNC_PER0_SMBUS0_SMBALERT 1
> +#define FUNC_PER0_SMBUS1_SMBALERT 1
> +#define FUNC_PER0_SMBUS2_SMBALERT 1
> +#define FUNC_PER0_SMBUS3_SMBALERT 1
> +#define FUNC_PER0_SMBUS4_SMBALERT 1
> +#define FUNC_PER0_SMBUS5_SMBALERT 1
> +#define FUNC_PER0_SMBUS6_SMBALERT 1
> +#define FUNC_PER0_SMBUS7_SMBALERT 1
> +#define FUNC_PER0_MIPI_I3C12_SCL0 1
> +#define FUNC_PER0_MIPI_I3C12_SDA0 1
> +#define FUNC_PER0_MIPI_I3C13_SCL0 1
> +#define FUNC_PER0_MIPI_I3C13_SDA0 1
> +#define FUNC_PER0_MIPI_I3C14_SCL0 1
> +#define FUNC_PER0_MIPI_I3C14_SDA0 1
> +#define FUNC_PER0_MIPI_I3C15_SCL0 1
> +#define FUNC_PER0_MIPI_I3C15_SDA0 1
> +#define FUNC_PER0_MIPI_I3C0_SCL0 1
> +#define FUNC_PER0_MIPI_I3C0_SDA0 1
> +#define FUNC_PER0_MIPI_I3C1_SCL0 1
> +#define FUNC_PER0_MIPI_I3C1_SDA0 1
> +#define FUNC_PER0_MIPI_I3C2_SCL0 1
> +#define FUNC_PER0_MIPI_I3C2_SDA0 1
> +#define FUNC_PER0_MIPI_I3C3_SCL0 1
> +#define FUNC_PER0_MIPI_I3C3_SDA0 1
> +#define FUNC_PER0_MIPI_I3C4_SCL1 1
> +#define FUNC_PER0_MIPI_I3C4_SDA1 1
> +#define FUNC_PER0_MIPI_I3C5_SCL1 1
> +#define FUNC_PER0_MIPI_I3C5_SDA1 1
> +#define FUNC_PER0_MIPI_I3C6_SCL1 1
> +#define FUNC_PER0_MIPI_I3C6_SDA1 1
> +#define FUNC_PER0_MIPI_I3C7_SCL1 1
> +#define FUNC_PER0_MIPI_I3C7_SDA1 1
> +
> +#define FUNC_PER0_MIPI_I3C4_SCL0 2
> +#define FUNC_PER0_MIPI_I3C4_SDA0 2
> +#define FUNC_PER0_MIPI_I3C5_SCL0 2
> +#define FUNC_PER0_MIPI_I3C5_SDA0 2
> +#define FUNC_PER0_MIPI_I3C6_SCL0 2
> +#define FUNC_PER0_MIPI_I3C6_SDA0 2
> +#define FUNC_PER0_MIPI_I3C7_SCL0 2
> +#define FUNC_PER0_MIPI_I3C7_SDA0 2
> +#define FUNC_PER0_MIPI_I3C8_SCL0 2
> +#define FUNC_PER0_MIPI_I3C8_SDA0 2
> +#define FUNC_PER0_MIPI_I3C9_SCL0 2
> +#define FUNC_PER0_MIPI_I3C9_SDA0 2
> +#define FUNC_PER0_MIPI_I3C10_SCL0 2
> +#define FUNC_PER0_MIPI_I3C10_SDA0 2
> +#define FUNC_PER0_MIPI_I3C11_SCL0 2
> +#define FUNC_PER0_MIPI_I3C11_SDA0 2
> +#define FUNC_PER0_GMAC2_MDC 2
> +#define FUNC_PER0_GMAC2_MDIO 2
> +#define FUNC_PER0_GMAC3_MDC 2
> +#define FUNC_PER0_GMAC3_MDIO 2
> +#define FUNC_PER0_GMAC1_MDC 2
> +#define FUNC_PER0_GMAC1_MDIO 2
> +#define FUNC_PER0_WDT0_3_OR_RESET_OUTPUT 2
> +#define FUNC_PER0_WDT_SECRP_RESET_OUTPUT 2
> +#define FUNC_PER0_WDT4_RESET_OUTPUT 2
> +#define FUNC_PER0_WDT4_RESTART_INPUT 2
> +
> +/* pinctrl_per1 pad function selection */
> +#define FUNC_PER1_SPI0_N_SS_OUT_0 1
> +#define FUNC_PER1_SPI0_N_SS_OUT_1 1
> +#define FUNC_PER1_SPI0_SCLK_OUT 1
> +#define FUNC_PER1_SPI0_TX 1
> +#define FUNC_PER1_SPI0_RX 1
> +#define FUNC_PER1_SFC0_N_SS_OUT_0 1
> +#define FUNC_PER1_SFC0_N_SS_OUT_1 1
> +#define FUNC_PER1_SFC0_SCLK_OUT 1
> +#define FUNC_PER1_SFC0_IO0 1
> +#define FUNC_PER1_SFC0_IO1 1
> +#define FUNC_PER1_SFC0_IO2 1
> +#define FUNC_PER1_SFC0_IO3 1
> +#define FUNC_PER1_SFC1_N_SS_OUT_0 1
> +#define FUNC_PER1_SFC1_N_SS_OUT_1 1
> +#define FUNC_PER1_SFC1_N_SS_OUT_2 1
> +#define FUNC_PER1_SFC1_SCLK_OUT 1
> +#define FUNC_PER1_SFC1_IO0 1
> +#define FUNC_PER1_SFC1_IO1 1
> +#define FUNC_PER1_SFC1_IO2 1
> +#define FUNC_PER1_SFC1_IO3 1
> +#define FUNC_PER1_SFC2_N_SS_OUT_0 1
> +#define FUNC_PER1_SFC2_N_SS_OUT_1 1
> +#define FUNC_PER1_SFC2_N_SS_OUT_2 1
> +#define FUNC_PER1_SFC2_SCLK_OUT 1
> +#define FUNC_PER1_SFC2_IO0 1
> +#define FUNC_PER1_SFC2_IO1 1
> +#define FUNC_PER1_SFC2_IO2 1
> +#define FUNC_PER1_SFC2_IO3 1
> +#define FUNC_PER1_SGPIO0_M_CLK 1
> +#define FUNC_PER1_SGPIO0_M_LOAD 1
> +#define FUNC_PER1_SGPIO0_M_DATA_OUT 1
> +#define FUNC_PER1_SGPIO0_M_DATA_IN 1
> +#define FUNC_PER1_I2C14_CLK 1
> +#define FUNC_PER1_I2C14_DATA 1
> +#define FUNC_PER1_I2C15_CLK 1
> +#define FUNC_PER1_I2C15_DATA 1
> +
> +#define FUNC_PER1_SGPIO1_M_CLK 2
> +#define FUNC_PER1_SGPIO1_M_LOAD 2
> +#define FUNC_PER1_SGPIO1_M_DATA_OUT 2
> +#define FUNC_PER1_SGPIO1_M_DATA_IN 2
> +
> +/* pinctrl_per2 function selection */
> +#define FUNC_PER2_FAN0_TACH_I_0 1
> +#define FUNC_PER2_FAN0_TACH_I_1 1
> +#define FUNC_PER2_FAN0_TACH_I_2 1
> +#define FUNC_PER2_FAN0_TACH_I_3 1
> +#define FUNC_PER2_FAN0_TACH_I_4 1
> +#define FUNC_PER2_FAN0_TACH_I_5 1
> +#define FUNC_PER2_FAN0_TACH_I_6 1
> +#define FUNC_PER2_FAN0_TACH_I_7 1
> +#define FUNC_PER2_FAN0_TACH_I_8 1
> +#define FUNC_PER2_FAN0_TACH_I_9 1
> +#define FUNC_PER2_FAN0_TACH_I_10 1
> +#define FUNC_PER2_FAN0_TACH_I_11 1
> +#define FUNC_PER2_FAN0_TACH_I_12 1
> +#define FUNC_PER2_FAN0_TACH_I_13 1
> +#define FUNC_PER2_FAN0_TACH_I_14 1
> +#define FUNC_PER2_FAN0_TACH_I_15 1
> +#define FUNC_PER2_GMAC2_RGMII_RX_CLK 1
> +#define FUNC_PER2_GMAC2_RGMII_RXCTL 1
> +#define FUNC_PER2_GMAC2_RGMII_PHY_RXD0 1
> +#define FUNC_PER2_GMAC2_RGMII_PHY_RXD1 1
> +#define FUNC_PER2_GMAC2_RGMII_PHY_RXD2 1
> +#define FUNC_PER2_GMAC2_RGMII_PHY_RXD3 1
> +#define FUNC_PER2_GMAC2_RGMII_TX_CLK 1
> +#define FUNC_PER2_GMAC2_RGMII_TXCTL 1
> +#define FUNC_PER2_GMAC2_RGMII_PHY_TX0 1
> +#define FUNC_PER2_GMAC2_RGMII_PHY_TX1 1
> +#define FUNC_PER2_GMAC2_RGMII_PHY_TX2 1
> +#define FUNC_PER2_GMAC2_RGMII_PHY_TX3 1
> +
> +#define FUNC_PER2_GMAC2_RMII_RX_CLK 2
> +#define FUNC_PER2_GMAC2_RMII_CRSDV 2
> +#define FUNC_PER2_GMAC2_RMII_PHY_RXD0 2
> +#define FUNC_PER2_GMAC2_RMII_PHY_RXD1 2
> +#define FUNC_PER2_GMAC2_RMII_RX_CKO 2
> +#define FUNC_PER2_GMAC2_RMII_TXEN 2
> +#define FUNC_PER2_GMAC2_RMII_PHY_TXD0 2
> +#define FUNC_PER2_GMAC2_RMII_PHY_TXD1 2
> +
> +#define FUNC_PER2_HOSTSS0_PORT80_DATA_OUT0 2
> +#define FUNC_PER2_HOSTSS0_PORT80_DATA_OUT1 2
> +#define FUNC_PER2_HOSTSS0_PORT80_DATA_OUT2 2
> +#define FUNC_PER2_HOSTSS0_PORT80_DATA_OUT3 2
> +#define FUNC_PER2_HOSTSS0_PORT80_DATA_OUT4 2
> +#define FUNC_PER2_HOSTSS0_PORT80_DATA_OUT5 2
> +#define FUNC_PER2_HOSTSS0_PORT80_DATA_OUT6 2
> +#define FUNC_PER2_HOSTSS0_PORT80_DATA_OUT7 2
> +#define FUNC_PER2_HOSTSS1_PORT80_DATA_OUT0 3
> +#define FUNC_PER2_HOSTSS1_PORT80_DATA_OUT1 3
> +#define FUNC_PER2_HOSTSS1_PORT80_DATA_OUT2 3
> +#define FUNC_PER2_HOSTSS1_PORT80_DATA_OUT3 3
> +#define FUNC_PER2_HOSTSS1_PORT80_DATA_OUT4 3
> +#define FUNC_PER2_HOSTSS1_PORT80_DATA_OUT5 3
> +#define FUNC_PER2_HOSTSS1_PORT80_DATA_OUT6 3
> +#define FUNC_PER2_HOSTSS1_PORT80_DATA_OUT7 3
> +
> +/* pinctrl_per2pok function selection */
> +#define FUNC_PER2POK_PWM0_CHANNEL0 0
> +#define FUNC_PER2POK_PWM0_CHANNEL1 0
> +#define FUNC_PER2POK_PWM0_CHANNEL2 0
> +#define FUNC_PER2POK_PWM0_CHANNEL3 0
> +#define FUNC_PER2POK_PWM0_CHANNEL4 0
> +#define FUNC_PER2POK_PWM0_CHANNEL5 0
> +#define FUNC_PER2POK_PWM0_CHANNEL6 0
> +#define FUNC_PER2POK_PWM0_CHANNEL7 0
> +
> +#define FUNC_PER2POK_CAN0_TXD 1
> +#define FUNC_PER2POK_CAN0_RXD 1
> +#define FUNC_PER2POK_CAN0_STBY 1
> +#define FUNC_PER2POK_CAN1_TXD 1
> +#define FUNC_PER2POK_CAN1_RXD 1
> +#define FUNC_PER2POK_CAN1_STBY 1
> +#define FUNC_PER2POK_GPIO_PASSTHRU1_IN 1
> +#define FUNC_PER2POK_GPIO_PASSTHRU1_OUT 1
> +#define FUNC_PER2POK_GPIO_PASSTHRU2_IN 1
> +#define FUNC_PER2POK_GPIO_PASSTHRU2_OUT 1
> +#define FUNC_PER2POK_GPIO10 1
> +#define FUNC_PER2POK_GPIO11 1
> +#define FUNC_PER2POK_GPIO12 1
> +#define FUNC_PER2POK_GPIO13 1
> +#define FUNC_PER2POK_GPIO14 1
> +#define FUNC_PER2POK_GPIO15 1
> +#define FUNC_PER2POK_GPIO16 1
> +#define FUNC_PER2POK_GPIO17 1
> +
> +#define FUNC_PER2POK_GPIO_PASSTHRU3_IN 2
> +#define FUNC_PER2POK_GPIO_PASSTHRU3_OUT 2
> +#define FUNC_PER2POK_HOSTSS0_PORT80_DATA_OUT0 2
> +#define FUNC_PER2POK_HOSTSS0_PORT80_DATA_OUT1 2
> +#define FUNC_PER2POK_HOSTSS0_PORT80_DATA_OUT2 2
> +#define FUNC_PER2POK_HOSTSS0_PORT80_DATA_OUT3 2
> +#define FUNC_PER2POK_HOSTSS0_PORT80_DATA_OUT4 2
> +#define FUNC_PER2POK_HOSTSS0_PORT80_DATA_OUT5 2
> +#define FUNC_PER2POK_HOSTSS0_PORT80_DATA_OUT6 2
> +#define FUNC_PER2POK_HOSTSS0_PORT80_DATA_OUT7 2
> +
> +#define FUNC_PER2POK_HOSTSS1_PORT80_DATA_OUT0 3
> +#define FUNC_PER2POK_HOSTSS1_PORT80_DATA_OUT1 3
> +#define FUNC_PER2POK_HOSTSS1_PORT80_DATA_OUT2 3
> +#define FUNC_PER2POK_HOSTSS1_PORT80_DATA_OUT3 3
> +#define FUNC_PER2POK_HOSTSS1_PORT80_DATA_OUT4 3
> +#define FUNC_PER2POK_HOSTSS1_PORT80_DATA_OUT5 3
> +#define FUNC_PER2POK_HOSTSS1_PORT80_DATA_OUT6 3
> +#define FUNC_PER2POK_HOSTSS1_PORT80_DATA_OUT7 3
> +
> +/* pinctrl_per3 function selection */
> +#define FUNC_PER3_GMAC0_MDC 1
> +#define FUNC_PER3_GMAC0_MDIO 1
> +#define FUNC_PER3_GMAC0_RMII_RCLKI 1
> +#define FUNC_PER3_GMAC0_RMII_RCLKO 1
> +#define FUNC_PER3_GMAC0_RMII_CRSDV 1
> +#define FUNC_PER3_GMAC0_RMII_PHY_RXD0 1
> +#define FUNC_PER3_GMAC0_RMII_PHY_RXD1 1
> +#define FUNC_PER3_GMAC0_RMII_TXEN 1
> +#define FUNC_PER3_GMAC0_RMII_PHY_TXD0 1
> +#define FUNC_PER3_GMAC0_RMII_PHY_TXD1 1
> +
> +/* gpio func sel value */
> +#define FUNC_SEL0_GPIO 0
> +#define FUNC_SEL1_GPIO 1
> +
> +/* vref value */
> +#define JHB100_PINVREF_3_3V 0
> +#define JHB100_PINVREF_2_5V 1
> +#define JHB100_PINVREF_1_8V 2
> +
> +#endif
> --
> 2.25.1
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v1 20/20] riscv: dts: starfive: jhb100: Add pinctrl nodes
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (18 preceding siblings ...)
2026-04-24 11:13 ` [PATCH v1 19/20] riscv: dts: starfive: Add StarFive JHB100 pin function definitions Changhuang Liang
@ 2026-04-24 11:13 ` Changhuang Liang
2026-04-24 17:01 ` Conor Dooley
2026-04-28 10:11 ` [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Linus Walleij
20 siblings, 1 reply; 34+ messages in thread
From: Changhuang Liang @ 2026-04-24 11:13 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl nodes for starfive JHB100 SoC. They contain
pinctrl_per0/pinctrl_per1/pinctrl_per2/pinctrl_per2pok/pinctrl_per3/
pinctrl_sys0/pinctrl_sys0h/pinctrl_sys1/pinctrl_sys2.
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../boot/dts/starfive/jhb100-evb1-eth.dts | 27 +++++
arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi | 4 +
.../boot/dts/starfive/jhb100-pinctrl.dtsi | 19 ++++
arch/riscv/boot/dts/starfive/jhb100.dtsi | 107 ++++++++++++++++++
4 files changed, 157 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi
diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
index 62cd046e1224..f7e82f9d0ff1 100644
--- a/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
+++ b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
@@ -4,3 +4,30 @@
*/
#include "jhb100-evb1.dtsi"
+
+&pinctrl_per0 {
+ gpioe-i3c0-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOB8-11, 32-33 */
+ gpioe-i3c1-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOB12-15, 34-35 */
+ gpioe-i3c2-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOB16-23 */
+ gpioe-i3c4-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOB36-43 */
+};
+
+&pinctrl_per1 {
+ gpioe-spi-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOC0-4 */
+ gpioe-qspi0-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOC5-11 */
+ gpioe-qspi1-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOC12-19 */
+ gpioe-qspi2-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOC20-27 */
+};
+
+&pinctrl_per2 {
+ gpionw-vref = <JHB100_PINVREF_1_8V>; /* VREF for GPIOD19-30 */
+};
+
+&pinctrl_per3 {
+ gpios-vref = <JHB100_PINVREF_1_8V>; /* VREF for GPIOE0-10 */
+};
+
+&pinctrl_sys2 {
+ gpiow-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOA36-39 */
+ gpiow-inner-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOA40-43 */
+};
diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi b/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
index 462b6fb7953b..acd5949bcfdb 100644
--- a/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
+++ b/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
@@ -3,7 +3,9 @@
* Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
*/
+#include "jhb100-pinfunc.h"
#include "jhb100.dtsi"
+#include "jhb100-pinctrl.dtsi"
/ {
model = "StarFive JHB100 EVB-1";
@@ -29,4 +31,6 @@ memory@40000000 {
&uart6 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart6_pins>;
};
diff --git a/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi b/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi
new file mode 100644
index 000000000000..d12b79376521
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2025-2026 StarFive Technology Co., Ltd.
+ */
+
+&pinctrl_sys2 {
+ uart6_pins: uart6-grp {
+ uart6-tx-pins {
+ pinmux = <PINMUX(PADNUM_SYS2_GPIO_A38,
+ FUNC_SYS2_UART6_TX)>;
+ };
+
+ uart6-rx-pins {
+ pinmux = <PINMUX(PADNUM_SYS2_GPIO_A39,
+ FUNC_SYS2_UART6_RX)>;
+ input-enable;
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
index 700d00f800bc..74d427d7f2df 100644
--- a/arch/riscv/boot/dts/starfive/jhb100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
@@ -425,6 +425,18 @@ per0crg: clock-controller@11a08000 {
#reset-cells = <1>;
};
+ pinctrl_per0: pinctrl@11a0a000 {
+ compatible = "starfive,jhb100-per0-pinctrl";
+ reg = <0x0 0x11a0a000 0x0 0x1000>;
+ resets = <&per0crg JHB100_PER0RST_GPIO_IOMUX_PRESETN>;
+ interrupts = <60>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per0 0 0 60>;
+ };
+
per1crg: clock-controller@11b40000 {
compatible = "starfive,jhb100-per1crg";
reg = <0x0 0x11b40000 0x0 0x1000>;
@@ -440,6 +452,18 @@ per1crg: clock-controller@11b40000 {
#reset-cells = <1>;
};
+ pinctrl_per1: pinctrl@11b42000 {
+ compatible = "starfive,jhb100-per1-pinctrl";
+ reg = <0x0 0x11b42000 0x0 0x800>;
+ resets = <&per1crg JHB100_PER1RST_IOMUX_PRESETN>;
+ interrupts = <61>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per1 0 0 36>;
+ };
+
per2crg: clock-controller@11bc0000 {
compatible = "starfive,jhb100-per2crg";
reg = <0x0 0x11bc0000 0x0 0x1000>;
@@ -461,6 +485,30 @@ per2crg: clock-controller@11bc0000 {
#reset-cells = <1>;
};
+ pinctrl_per2: pinctrl@11bc2000 {
+ compatible = "starfive,jhb100-per2-pinctrl";
+ reg = <0x0 0x11bc2000 0x0 0x400>;
+ resets = <&per2crg JHB100_PER2RST_IOMUX_PRESETN>;
+ interrupts = <62>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per2 0 0 31>;
+ };
+
+ pinctrl_per2pok: pinctrl@11bc2400 {
+ compatible = "starfive,jhb100-per2pok-pinctrl";
+ reg = <0x0 0x11bc2400 0x0 0x400>;
+ resets = <&per2crg JHB100_PER2RST_POK_IOMUX_PRESETN>;
+ interrupts = <63>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per2pok 0 0 18>;
+ };
+
per3crg: clock-controller@11c40000 {
compatible = "starfive,jhb100-per3crg";
reg = <0x0 0x11c40000 0x0 0x1000>;
@@ -480,6 +528,18 @@ per3crg: clock-controller@11c40000 {
#reset-cells = <1>;
};
+ pinctrl_per3: pinctrl@11c42000 {
+ compatible = "starfive,jhb100-per3-pinctrl";
+ reg = <0x0 0x11c42000 0x0 0x1000>;
+ resets = <&per3crg JHB100_PER3RST_IOMUX_PRESETN>;
+ interrupts = <64>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per3 0 0 11>;
+ };
+
sys0crg: clock-controller@13000000 {
compatible = "starfive,jhb100-sys0crg";
reg = <0x0 0x13000000 0x0 0x4000>;
@@ -513,6 +573,53 @@ sys2crg: clock-controller@13008000 {
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ pinctrl_sys0: pinctrl@13080000 {
+ compatible = "starfive,jhb100-sys0-pinctrl";
+ reg = <0x0 0x13080000 0x0 0x800>;
+ resets = <&sys0crg JHB100_SYS0RST_SYS0_IOMUX_PRESETN>;
+ interrupts = <56>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_sys0 0 0 4>;
+ };
+
+ pinctrl_sys0h: pinctrl@13080800 {
+ compatible = "starfive,jhb100-sys0h-pinctrl";
+ reg = <0x0 0x13080800 0x0 0x800>;
+ resets = <&sys0crg JHB100_SYS0RST_SYS0H_IOMUX_PRESETN>;
+ interrupts = <57>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_sys0h 0 0 12>;
+ };
+
+ pinctrl_sys1: pinctrl@13081000 {
+ compatible = "starfive,jhb100-sys1-pinctrl";
+ reg = <0x0 0x13081000 0x0 0x1000>;
+ resets = <&sys1crg JHB100_SYS1RST_SYS1_IOMUX_PRESETN>;
+ interrupts = <58>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_sys1 0 0 8>;
+ };
+
+ pinctrl_sys2: pinctrl@13082000 {
+ compatible = "starfive,jhb100-sys2-pinctrl";
+ reg = <0x0 0x13082000 0x0 0x1000>;
+ interrupts = <59>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_sys2 0 0 37>;
+ };
};
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH v1 20/20] riscv: dts: starfive: jhb100: Add pinctrl nodes
2026-04-24 11:13 ` [PATCH v1 20/20] riscv: dts: starfive: jhb100: Add pinctrl nodes Changhuang Liang
@ 2026-04-24 17:01 ` Conor Dooley
2026-04-28 1:53 ` Changhuang Liang
0 siblings, 1 reply; 34+ messages in thread
From: Conor Dooley @ 2026-04-24 17:01 UTC (permalink / raw)
To: Changhuang Liang
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski, linux-gpio,
linux-kernel, devicetree, linux-riscv, Lianfeng Ouyang
[-- Attachment #1: Type: text/plain, Size: 8658 bytes --]
On Fri, Apr 24, 2026 at 04:13:30AM -0700, Changhuang Liang wrote:
> Add pinctrl nodes for starfive JHB100 SoC. They contain
> pinctrl_per0/pinctrl_per1/pinctrl_per2/pinctrl_per2pok/pinctrl_per3/
> pinctrl_sys0/pinctrl_sys0h/pinctrl_sys1/pinctrl_sys2.
>
> Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
What did Lianfeng do? A signoff alone suggests something is incorrectly
attributed here.
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
> .../boot/dts/starfive/jhb100-evb1-eth.dts | 27 +++++
> arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi | 4 +
> .../boot/dts/starfive/jhb100-pinctrl.dtsi | 19 ++++
> arch/riscv/boot/dts/starfive/jhb100.dtsi | 107 ++++++++++++++++++
> 4 files changed, 157 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> index 62cd046e1224..f7e82f9d0ff1 100644
> --- a/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> @@ -4,3 +4,30 @@
> */
>
> #include "jhb100-evb1.dtsi"
> +
> +&pinctrl_per0 {
> + gpioe-i3c0-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOB8-11, 32-33 */
> + gpioe-i3c1-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOB12-15, 34-35 */
> + gpioe-i3c2-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOB16-23 */
> + gpioe-i3c4-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOB36-43 */
> +};
> +
> +&pinctrl_per1 {
> + gpioe-spi-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOC0-4 */
> + gpioe-qspi0-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOC5-11 */
> + gpioe-qspi1-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOC12-19 */
> + gpioe-qspi2-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOC20-27 */
> +};
> +
> +&pinctrl_per2 {
> + gpionw-vref = <JHB100_PINVREF_1_8V>; /* VREF for GPIOD19-30 */
> +};
> +
> +&pinctrl_per3 {
> + gpios-vref = <JHB100_PINVREF_1_8V>; /* VREF for GPIOE0-10 */
> +};
> +
> +&pinctrl_sys2 {
> + gpiow-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOA36-39 */
> + gpiow-inner-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOA40-43 */
> +};
> diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi b/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
> index 462b6fb7953b..acd5949bcfdb 100644
> --- a/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
> @@ -3,7 +3,9 @@
> * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
> */
>
> +#include "jhb100-pinfunc.h"
> #include "jhb100.dtsi"
> +#include "jhb100-pinctrl.dtsi"
>
> / {
> model = "StarFive JHB100 EVB-1";
> @@ -29,4 +31,6 @@ memory@40000000 {
>
> &uart6 {
> status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart6_pins>;
> };
> diff --git a/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi b/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi
> new file mode 100644
> index 000000000000..d12b79376521
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (c) 2025-2026 StarFive Technology Co., Ltd.
> + */
> +
> +&pinctrl_sys2 {
> + uart6_pins: uart6-grp {
> + uart6-tx-pins {
> + pinmux = <PINMUX(PADNUM_SYS2_GPIO_A38,
> + FUNC_SYS2_UART6_TX)>;
> + };
> +
> + uart6-rx-pins {
> + pinmux = <PINMUX(PADNUM_SYS2_GPIO_A39,
> + FUNC_SYS2_UART6_RX)>;
> + input-enable;
> + };
> + };
> +};
Could we get some more examples, to exercise each pin controller?
Is that impossible without adding more peripherals other than uart?
Cheers,
Conor.
> diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
> index 700d00f800bc..74d427d7f2df 100644
> --- a/arch/riscv/boot/dts/starfive/jhb100.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
> @@ -425,6 +425,18 @@ per0crg: clock-controller@11a08000 {
> #reset-cells = <1>;
> };
>
> + pinctrl_per0: pinctrl@11a0a000 {
> + compatible = "starfive,jhb100-per0-pinctrl";
> + reg = <0x0 0x11a0a000 0x0 0x1000>;
> + resets = <&per0crg JHB100_PER0RST_GPIO_IOMUX_PRESETN>;
> + interrupts = <60>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl_per0 0 0 60>;
> + };
> +
> per1crg: clock-controller@11b40000 {
> compatible = "starfive,jhb100-per1crg";
> reg = <0x0 0x11b40000 0x0 0x1000>;
> @@ -440,6 +452,18 @@ per1crg: clock-controller@11b40000 {
> #reset-cells = <1>;
> };
>
> + pinctrl_per1: pinctrl@11b42000 {
> + compatible = "starfive,jhb100-per1-pinctrl";
> + reg = <0x0 0x11b42000 0x0 0x800>;
> + resets = <&per1crg JHB100_PER1RST_IOMUX_PRESETN>;
> + interrupts = <61>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl_per1 0 0 36>;
> + };
> +
> per2crg: clock-controller@11bc0000 {
> compatible = "starfive,jhb100-per2crg";
> reg = <0x0 0x11bc0000 0x0 0x1000>;
> @@ -461,6 +485,30 @@ per2crg: clock-controller@11bc0000 {
> #reset-cells = <1>;
> };
>
> + pinctrl_per2: pinctrl@11bc2000 {
> + compatible = "starfive,jhb100-per2-pinctrl";
> + reg = <0x0 0x11bc2000 0x0 0x400>;
> + resets = <&per2crg JHB100_PER2RST_IOMUX_PRESETN>;
> + interrupts = <62>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl_per2 0 0 31>;
> + };
> +
> + pinctrl_per2pok: pinctrl@11bc2400 {
> + compatible = "starfive,jhb100-per2pok-pinctrl";
> + reg = <0x0 0x11bc2400 0x0 0x400>;
> + resets = <&per2crg JHB100_PER2RST_POK_IOMUX_PRESETN>;
> + interrupts = <63>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl_per2pok 0 0 18>;
> + };
> +
> per3crg: clock-controller@11c40000 {
> compatible = "starfive,jhb100-per3crg";
> reg = <0x0 0x11c40000 0x0 0x1000>;
> @@ -480,6 +528,18 @@ per3crg: clock-controller@11c40000 {
> #reset-cells = <1>;
> };
>
> + pinctrl_per3: pinctrl@11c42000 {
> + compatible = "starfive,jhb100-per3-pinctrl";
> + reg = <0x0 0x11c42000 0x0 0x1000>;
> + resets = <&per3crg JHB100_PER3RST_IOMUX_PRESETN>;
> + interrupts = <64>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl_per3 0 0 11>;
> + };
> +
> sys0crg: clock-controller@13000000 {
> compatible = "starfive,jhb100-sys0crg";
> reg = <0x0 0x13000000 0x0 0x4000>;
> @@ -513,6 +573,53 @@ sys2crg: clock-controller@13008000 {
> #clock-cells = <1>;
> #reset-cells = <1>;
> };
> +
> + pinctrl_sys0: pinctrl@13080000 {
> + compatible = "starfive,jhb100-sys0-pinctrl";
> + reg = <0x0 0x13080000 0x0 0x800>;
> + resets = <&sys0crg JHB100_SYS0RST_SYS0_IOMUX_PRESETN>;
> + interrupts = <56>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl_sys0 0 0 4>;
> + };
> +
> + pinctrl_sys0h: pinctrl@13080800 {
> + compatible = "starfive,jhb100-sys0h-pinctrl";
> + reg = <0x0 0x13080800 0x0 0x800>;
> + resets = <&sys0crg JHB100_SYS0RST_SYS0H_IOMUX_PRESETN>;
> + interrupts = <57>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl_sys0h 0 0 12>;
> + };
> +
> + pinctrl_sys1: pinctrl@13081000 {
> + compatible = "starfive,jhb100-sys1-pinctrl";
> + reg = <0x0 0x13081000 0x0 0x1000>;
> + resets = <&sys1crg JHB100_SYS1RST_SYS1_IOMUX_PRESETN>;
> + interrupts = <58>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl_sys1 0 0 8>;
> + };
> +
> + pinctrl_sys2: pinctrl@13082000 {
> + compatible = "starfive,jhb100-sys2-pinctrl";
> + reg = <0x0 0x13082000 0x0 0x1000>;
> + interrupts = <59>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl_sys2 0 0 37>;
> + };
> };
> };
> };
> --
> 2.25.1
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH v1 20/20] riscv: dts: starfive: jhb100: Add pinctrl nodes
2026-04-24 17:01 ` Conor Dooley
@ 2026-04-28 1:53 ` Changhuang Liang
0 siblings, 0 replies; 34+ messages in thread
From: Changhuang Liang @ 2026-04-28 1:53 UTC (permalink / raw)
To: Conor Dooley
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski,
linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Lianfeng Ouyang
Hi, Conor
Thanks for the review.
> On Fri, Apr 24, 2026 at 04:13:30AM -0700, Changhuang Liang wrote:
> > Add pinctrl nodes for starfive JHB100 SoC. They contain
> > pinctrl_per0/pinctrl_per1/pinctrl_per2/pinctrl_per2pok/pinctrl_per3/
> > pinctrl_sys0/pinctrl_sys0h/pinctrl_sys1/pinctrl_sys2.
> >
> > Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
>
> What did Lianfeng do? A signoff alone suggests something is incorrectly
> attributed here.
We worked on this part together and will add the Co-developed-by tag.
>
> > Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> > ---
> > .../boot/dts/starfive/jhb100-evb1-eth.dts | 27 +++++
> > arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi | 4 +
> > .../boot/dts/starfive/jhb100-pinctrl.dtsi | 19 ++++
> > arch/riscv/boot/dts/starfive/jhb100.dtsi | 107
> ++++++++++++++++++
> > 4 files changed, 157 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > index 62cd046e1224..f7e82f9d0ff1 100644
> > --- a/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts
> > @@ -4,3 +4,30 @@
> > */
> >
> > #include "jhb100-evb1.dtsi"
> > +
> > +&pinctrl_per0 {
> > + gpioe-i3c0-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOB8-11,
> 32-33 */
> > + gpioe-i3c1-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOB12-15,
> 34-35 */
> > + gpioe-i3c2-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOB16-23 */
> > + gpioe-i3c4-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOB36-43 */
> > +};
> > +
> > +&pinctrl_per1 {
> > + gpioe-spi-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOC0-4 */
> > + gpioe-qspi0-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOC5-11 */
> > + gpioe-qspi1-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOC12-19
> */
> > + gpioe-qspi2-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOC20-27
> */
> > +};
> > +
> > +&pinctrl_per2 {
> > + gpionw-vref = <JHB100_PINVREF_1_8V>; /* VREF for GPIOD19-30 */ };
> > +
> > +&pinctrl_per3 {
> > + gpios-vref = <JHB100_PINVREF_1_8V>; /* VREF for GPIOE0-10 */ };
> > +
> > +&pinctrl_sys2 {
> > + gpiow-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOA36-39 */
> > + gpiow-inner-vref = <JHB100_PINVREF_3_3V>; /* VREF for GPIOA40-43
> */
> > +};
> > diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
> > b/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
> > index 462b6fb7953b..acd5949bcfdb 100644
> > --- a/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi
> > @@ -3,7 +3,9 @@
> > * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
> > */
> >
> > +#include "jhb100-pinfunc.h"
> > #include "jhb100.dtsi"
> > +#include "jhb100-pinctrl.dtsi"
> >
> > / {
> > model = "StarFive JHB100 EVB-1";
> > @@ -29,4 +31,6 @@ memory@40000000 {
> >
> > &uart6 {
> > status = "okay";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart6_pins>;
> > };
> > diff --git a/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi
> > b/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi
> > new file mode 100644
> > index 000000000000..d12b79376521
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi
> > @@ -0,0 +1,19 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (c) 2025-2026 StarFive Technology Co., Ltd.
> > + */
> > +
> > +&pinctrl_sys2 {
> > + uart6_pins: uart6-grp {
> > + uart6-tx-pins {
> > + pinmux = <PINMUX(PADNUM_SYS2_GPIO_A38,
> > + FUNC_SYS2_UART6_TX)>;
> > + };
> > +
> > + uart6-rx-pins {
> > + pinmux = <PINMUX(PADNUM_SYS2_GPIO_A39,
> > + FUNC_SYS2_UART6_RX)>;
> > + input-enable;
> > + };
> > + };
> > +};
>
> Could we get some more examples, to exercise each pin controller?
> Is that impossible without adding more peripherals other than uart?
>
Yes, providing more examples for each pin controller would require adding
other peripherals beyond UART. Currently, we only have UART available.
We can add more examples once other peripherals (like I2C, SPI, etc.) are
enabled in the DT.
Best Regards,
Changhuang
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC
2026-04-24 11:13 [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (19 preceding siblings ...)
2026-04-24 11:13 ` [PATCH v1 20/20] riscv: dts: starfive: jhb100: Add pinctrl nodes Changhuang Liang
@ 2026-04-28 10:11 ` Linus Walleij
2026-04-29 0:53 ` Changhuang Liang
20 siblings, 1 reply; 34+ messages in thread
From: Linus Walleij @ 2026-04-28 10:11 UTC (permalink / raw)
To: Changhuang Liang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski, linux-gpio,
linux-kernel, devicetree, linux-riscv, Lianfeng Ouyang
Hi Changhuang,
thanks for your patch!
On Fri, Apr 24, 2026 at 1:13 PM Changhuang Liang
<changhuang.liang@starfivetech.com> wrote:
> The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
> per2, per2pok, per3, adc0, adc1, emmc, and vga.
>
> In the current series, we will only add the following pinctrl:
> - sys0, sys0h, sys1, sys2
> - per0, per1, per2, per2pok, per3
>
> The remaining pinctrl will be implemented in future series.
>
> This series depends on the series:
> https://lore.kernel.org/all/20260402105523.447523-1-changhuang.liang@starfivetech.com/
(...)
> .../starfive/pinctrl-starfive-jhb100.c | 1821 +++++++++++++++++
Thats a big patch.
I need a motivation why the existing code in pinctrl-starfive-jh7110.c
and pinctrl-starfive-jh7100.c cannot be refactored, repurposed and
re-used of this hardware is related to the old hardware?
We don't want several copies of essentially the same driver, that
way we get maintenance overload.
So the first question about this patch set is if a completely new
driver is really needed.
A second question regards "banks" in the GPIO controller.
The callbacks offsets are exensively /32 %32 MOD:ed to clamp
to 32bit words. Should this rather be reflected in the device
tree model as a 3-cell GPIO <&gpio bank num flags> rather
than 2-cell <&gpio num flags>? Doing this makes it possible
to use gpiolib helpers.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC
2026-04-28 10:11 ` [PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC Linus Walleij
@ 2026-04-29 0:53 ` Changhuang Liang
0 siblings, 0 replies; 34+ messages in thread
From: Changhuang Liang @ 2026-04-29 0:53 UTC (permalink / raw)
To: Linus Walleij
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski,
linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Lianfeng Ouyang
Hi, linus
Thanks for the review.
> Hi Changhuang,
>
> thanks for your patch!
>
> On Fri, Apr 24, 2026 at 1:13 PM Changhuang Liang
> <changhuang.liang@starfivetech.com> wrote:
>
> > The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0,
> > per1, per2, per2pok, per3, adc0, adc1, emmc, and vga.
> >
> > In the current series, we will only add the following pinctrl:
> > - sys0, sys0h, sys1, sys2
> > - per0, per1, per2, per2pok, per3
> >
> > The remaining pinctrl will be implemented in future series.
> >
> > This series depends on the series:
> > https://lore.kernel.org/all/20260402105523.447523-1-changhuang.liang@s
> > tarfivetech.com/
>
> (...)
>
> > .../starfive/pinctrl-starfive-jhb100.c | 1821
> +++++++++++++++++
>
> Thats a big patch.
>
> I need a motivation why the existing code in pinctrl-starfive-jh7110.c and
> pinctrl-starfive-jh7100.c cannot be refactored, repurposed and re-used of this
> hardware is related to the old hardware?
>
> We don't want several copies of essentially the same driver, that way we get
> maintenance overload.
There are quite a few differences between the current jh7110 and JHB100 implementations.
Reusing the old code might also require extensive modifications, and I'm not sure if that
would introduce new issues.
> So the first question about this patch set is if a completely new driver is really
> needed.
>
> A second question regards "banks" in the GPIO controller.
> The callbacks offsets are exensively /32 %32 MOD:ed to clamp to 32bit words.
> Should this rather be reflected in the device tree model as a 3-cell GPIO
> <&gpio bank num flags> rather than 2-cell <&gpio num flags>? Doing this
> makes it possible to use gpiolib helpers.
This approach looks very good. I will attempt to implement the changes accordingly.
Best Regards,
Changhuang
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