Re: [PATCH v6 05/16] ASoC: rsnd: Add RZ/G3E SoC probing and register map

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Unmapped PIO data registers cause an IRQ storm and log spam if PIO fallback occurs on RZ/G3E.
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commit c024509f93a46087ccbea869fbbcef923ba14644
Author: John Madieu <john.madieu.xa@bp.renesas.com>

ASoC: rsnd: Add RZ/G3E SoC probing and register map

This commit adds support for the RZ/G3E audio subsystem, which has a different
register layout compared to R-Car generations. It introduces the new SoC's
register layouts and probe support.

> diff --git a/sound/soc/renesas/rcar/gen.c b/sound/soc/renesas/rcar/gen.c
> index d1f20cde66be1..05d5f656fb01c 100644
> --- a/sound/soc/renesas/rcar/gen.c
> +++ b/sound/soc/renesas/rcar/gen.c
[ ... ]
> +static int rsnd_rzg3e_probe(struct rsnd_priv *priv)
> +{
[ ... ]
> +	static const struct rsnd_regmap_field_conf conf_ssi[] = {
> +		RSND_GEN_M_REG(SSICR,			0x00,	0x40),
> +		RSND_GEN_M_REG(SSISR,			0x04,	0x40),
> +		RSND_GEN_M_REG(SSIWSR,			0x20,	0x40),
> +	};

If the RZ/G3E audio subsystem falls back to PIO mode (e.g., if DMA channel
allocation fails or the pio-transfer device tree property is set), will this
cause an interrupt storm?

The conf_ssi regmap for RZ/G3E intentionally omits the SSITDR and SSIRDR
data registers.

If PIO mode is engaged, rsnd_ssi_start() enables the Data Interrupt (DIEN).
When the interrupt fires, rsnd_ssi_pio_interrupt() will attempt to access
SSIRDR or SSITDR. Because they are missing from this regmap, the access will
be intercepted and skipped, returning an unsupported register access error.

Because the hardware FIFO is never serviced, the level-triggered DIRQ
condition is never cleared, resulting in an IRQ storm that hangs the CPU
and floods the kernel log.

A later commit in the series claims "SSI always operates in BUSIF mode
with no PIO fallback", but should this constraint be explicitly enforced
in the code to prevent this IRQ storm from occurring?

> +	int ret;

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Sashiko AI review · https://sashiko.dev/#/patchset/20260512182631.3842065-1-john.madieu.xa@bp.renesas.com?part=5