* Re: [PATCH v9 3/3] PCI: mediatek: Add support for EcoNet EN7528 SoC
From: sashiko-bot @ 2026-05-21 18:27 UTC (permalink / raw)
To: Caleb James DeLisle; +Cc: conor+dt, robh, linux-pci, devicetree
In-Reply-To: <20260521171951.1495781-4-cjd@cjdns.fr>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] The driver bypasses module export boundaries and locking encapsulation by using IS_BUILTIN() to access unexported PCI core functions and locks.
- [High] Retraining the PCIe link after `pci_host_probe()` causes the link to drop while endpoint drivers are actively probing and operating.
- [High] A failure to retrain one root port aborts the entire loop, leaving subsequent ports stuck at Gen1.
--
commit c15a1642adf464e152e3330bafda659a6425825d
Author: Caleb James DeLisle <cjd@cjdns.fr>
Subject: PCI: mediatek: Add support for EcoNet EN7528 SoC
This commit adds support for the PCIe controller present on the EcoNet EN7528
and EN751221 SoCs. It includes a quirk to retrain the link to Gen2 after
startup, as some Gen2-capable ports initially start in Gen1 mode.
> diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> index c503fbd774d09..30f8070967b82 100644
> --- a/drivers/pci/controller/pcie-mediatek.c
> +++ b/drivers/pci/controller/pcie-mediatek.c
[ ... ]
> +static int mtk_pcie_retrain(struct device *dev, struct pci_host_bridge *host)
> +{
> + struct pci_dev *rp;
> + int ret = -ENOENT;
> + u16 lnksta = 0;
> + u32 speed;
> +
> + /* Should already have been warned about during startup_port */
> + if (!IS_BUILTIN(CONFIG_PCIE_MEDIATEK))
> + return 0;
> +
> + guard(rwsem_read)(&pci_bus_sem);
[Severity: High]
Does using IS_BUILTIN() to conditionally access internal locks like pci_bus_sem
and unexported functions bypass module export boundaries?
When compiled as a module, does this silently break functionality by
completely skipping the Gen2 link retraining and leaving the ports permanently
degraded to Gen1?
> +
> + for_each_pci_bridge(rp, host->bus) {
> + if (pci_pcie_type(rp) != PCI_EXP_TYPE_ROOT_PORT)
> + continue;
> +
> +#if IS_BUILTIN(CONFIG_PCIE_MEDIATEK)
> + ret = pcie_retrain_link(rp, true);
> +#endif
> +
> + if (ret)
> + return dev_err_probe(&rp->dev, ret,
> + "failed to retrain port\n");
[Severity: High]
If pcie_retrain_link() fails for one root port, does returning immediately skip
retraining for all remaining root ports on the bus?
Since the caller explicitly ignores the return value of mtk_pcie_retrain(),
should this perhaps just log an error and continue to the next port instead?
> +
> + pcie_capability_read_word(rp, PCI_EXP_LNKSTA, &lnksta);
> + speed = lnksta & PCI_EXP_LNKSTA_CLS;
> +
> + pci_info(rp, "link retrained, speed %s\n",
> + pci_speed_string(pcie_link_speed[speed]));
> +
> + }
> +
> + return 0;
> +}
[ ... ]
> @@ -1159,6 +1298,13 @@ static int mtk_pcie_probe(struct platform_device *pdev)
> if (err)
> goto put_resources;
>
> + /*
> + * Ignore error because pci_host_probe() was already called, and in any
> + * case it is possible that the port will still work as Gen1.
> + */
> + if (pcie->soc->quirks & MTK_PCIE_RETRAIN)
> + mtk_pcie_retrain(dev, host);
[Severity: High]
Does retraining the link here cause it to drop while endpoint drivers are
already actively probing?
Because pci_host_probe() enumerates the bus and binds endpoint drivers,
taking the link down immediately after could cause concurrent MMIO or DMA
transactions to fail. Could this also result in endpoint drivers observing
incorrect Gen1 link speeds during their initialization?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260521171951.1495781-1-cjd@cjdns.fr?part=3
^ permalink raw reply
* Re: [PATCH v3 7/8] dt-bindings: iio: temperature: Add ADT7604 support to adi,ltc2983
From: sashiko-bot @ 2026-05-21 18:23 UTC (permalink / raw)
To: Liviu Stan; +Cc: devicetree, robh, conor+dt
In-Reply-To: <20260521164323.770626-8-liviu.stan@analog.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] The new compatible string 'adi,adt7604' is omitted from the existing conditional block that disables '^temp@' nodes, violating subsystem guidelines.
- [Low] The schema allows invalid 'adi,sensor-type' values in '^rtd@' and '^thermistor@' nodes for the ADT7604.
--
commit fbbcd3bcbfbb106e48a6545868dd2b27a56b39b5
Author: Liviu Stan <liviu.stan@analog.com>
dt-bindings: iio: temperature: Add ADT7604 support to adi,ltc2983
This commit adds support for the ADT7604 to the LTC2983 binding schema. It
introduces the adi,adt7604 compatible string and adds two new sensor node
types: copper-trace@ and leak-detector@. It also adds conditional checks to
restrict unsupported nodes for the ADT7604 device.
> diff --git a/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml b/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml
> index a22725f7619b7..14cfa28809edd 100644
> --- a/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml
> +++ b/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml
[ ... ]
> @@ -477,6 +597,22 @@ allOf:
> patternProperties:
> '^temp@': false
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: adi,adt7604
> + then:
> + patternProperties:
> + '^thermocouple@': false
> + '^diode@': false
> + '^adc@': false
> + '^temp@': false
[Severity: Low]
Since ADT7604 shares the ^temp@: false constraint with the existing devices,
should adi,adt7604 be added to the existing compatible enum block instead of
duplicating the ^temp@ restriction in this new conditional?
[Severity: Low]
The commit message mentions that ADT7604 repurposes the custom RTD sensor type
(18) and custom thermistor type (27).
However, the schema doesn't restrict adi,sensor-type = <18> inside ^rtd@ nodes
or adi,sensor-type = <27> inside ^thermistor@ nodes for the adi,adt7604
compatible.
Should these restrictions be added to this block to prevent invalid device
tree configurations from passing validation?
> + else:
> + patternProperties:
> + '^copper-trace@': false
> + '^leak-detector@': false
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260521164323.770626-1-liviu.stan@analog.com?part=7
^ permalink raw reply
* Re: [PATCH v3 6/8] iio: core: Add IIO_COVERAGE channel type
From: sashiko-bot @ 2026-05-21 18:10 UTC (permalink / raw)
To: Liviu Stan; +Cc: robh, devicetree, conor+dt
In-Reply-To: <20260521164323.770626-7-liviu.stan@analog.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The sysfs ABI documentation for IIO_COVERAGE incorrectly uses 'X' instead of 'Y' as the channel index wildcard.
--
commit 6217a0a065fdaa7ef3fffa525f2928d59a323a05
Author: Liviu Stan <liviu.stan@analog.com>
iio: core: Add IIO_COVERAGE channel type
This commit introduces a new channel type for sensors that report fractional
coverage as a percentage. It updates the core IIO structures and provides
the necessary sysfs ABI documentation for the new attributes.
> diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio
> index 4fc9f6bd42812..90fb8ef26de0e 100644
> --- a/Documentation/ABI/testing/sysfs-bus-iio
> +++ b/Documentation/ABI/testing/sysfs-bus-iio
> @@ -1959,6 +1959,23 @@ Description:
> Raw (unscaled no offset etc.) resistance reading.
> Units after application of scale and offset are ohms.
>
> +What: /sys/bus/iio/devices/iio:deviceX/in_coverageX_raw
[Severity: Low]
Should this use Y for the channel index wildcard instead of X? The IIO sysfs
ABI documentation typically uses X strictly for the device index and Y for the
channel index, which would make this in_coverageY_raw.
> +KernelVersion: 7.2
> +Contact: linux-iio@vger.kernel.org
> +Description:
> + Raw (unscaled no offset etc.) coverage reading. Used for sensors
> + that report fractional coverage as a percentage, such as leak
> + detectors where the value represents what portion of the sensing
> + element is wetted. Units after application of scale and offset are
> + percent.
> +
> +What: /sys/bus/iio/devices/iio:deviceX/in_coverageX_scale
[Severity: Low]
Does this attribute have the same naming consistency issue? Following the
standard convention, this would be in_coverageY_scale.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260521164323.770626-1-liviu.stan@analog.com?part=6
^ permalink raw reply
* Re: [PATCH 03/11] arm64: dts: qcom: sc8280xp-arcata: Enable the eDP display
From: Jérôme de Bretagne @ 2026-05-21 18:09 UTC (permalink / raw)
To: Konrad Dybcio, Douglas Anderson, Neil Armstrong, Jessica Zhang,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: dri-devel, linux-kernel, linux-arm-msm, devicetree,
Krzysztof Kozlowski
In-Reply-To: <cd5a8576-2f06-4620-bbf3-43b3f84de630@oss.qualcomm.com>
On 5/21/26 10:50, Konrad Dybcio wrote:
> On 5/20/26 6:40 PM, Jérôme de Bretagne via B4 Relay wrote:
>> From: Jérôme de Bretagne <jerome.debretagne@gmail.com>
>>
>> Add the vreg_edp_3p3, edp_reg_en and mdss0_dp3 nodes to enable the
>> Surface Pro 9 5G eDP-based LCD display (LG LP129WT232166).
>>
>> The enable GPIO 36 was found by decompiling AeoB dumps [1]:
>
> I'd like you to strip this from the commit message, as it
> doesn't add much value and makes the git log unreasonably long
I thought it could be useful for other people doing device bring-up
in the future. No problem to strip this in v2, the info is in the
mailing list from now on anyway.
> otherwise this lgtm
Thank you,
Jérôme
^ permalink raw reply
* Re: [PATCH 04/11] arm64: dts: qcom: sc8280xp-arcata: add USB-C orientation GPIOs
From: Jérôme de Bretagne @ 2026-05-21 18:04 UTC (permalink / raw)
To: Konrad Dybcio, Douglas Anderson, Neil Armstrong, Jessica Zhang,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: dri-devel, linux-kernel, linux-arm-msm, devicetree,
Krzysztof Kozlowski
In-Reply-To: <418efc2a-d7de-4c1d-98e1-634f08bc3a85@oss.qualcomm.com>
On 5/21/26 10:52, Konrad Dybcio wrote:
> On 5/20/26 6:40 PM, Jérôme de Bretagne via B4 Relay wrote:
>> From: Jérôme de Bretagne <jerome.debretagne@gmail.com>
>>
>> Define the USB-C orientation GPIOs so that the USB-C ports orientation
>> is known without having to resort to the alt mode notifications.
>>
>> Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com>
>> ---
>
> The commit message is slightly misleading - there is no orientation
> data otherwise
I will update it in v2.
Jérôme
^ permalink raw reply
* Re: [PATCH 05/11] arm64: dts: qcom: sc8280xp-arcata: Fix top USB-C DP alt mode
From: Jérôme de Bretagne @ 2026-05-21 17:59 UTC (permalink / raw)
To: Konrad Dybcio, Douglas Anderson, Neil Armstrong, Jessica Zhang,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: dri-devel, linux-kernel, linux-arm-msm, devicetree,
Krzysztof Kozlowski, Jens Glathe
In-Reply-To: <990a0d6b-ef5c-4d7b-ab63-e75c37825397@oss.qualcomm.com>
On 5/21/26 10:53, Konrad Dybcio wrote:
> On 5/20/26 6:40 PM, Jérôme de Bretagne via B4 Relay wrote:
>> From: Jérôme de Bretagne <jerome.debretagne@gmail.com>
>>
>> The top USB-C port (usb0) didn't switch to DP alt mode, as reusing the
>> same GPIO 101 as on the SC8280XP CRD or Lenovo ThinkPad X13s was not
>> working on the Surface Pro 9 5G.
>>
>> Investigation [1] by Jens on the Windows Dev Kit (WDK2023), the other
>> sc8280xp-based "blackrock" model from Microsoft, found a reference
>> to GPIO 100 in the DSDT in addition to 101. Switching to GPIO 100
>> fixed the issue on blackrock, as it does on arcata to enable
>> external screen when using the left-side top USB-C port.
>>
>> [1] https://lore.kernel.org/all/20250609-blackrock-usb0-mux-v1-1-7903c3b071e4@oldschoolsolutions.biz/
>>
>> Cc: Jens Glathe <jens.glathe@oldschoolsolutions.biz>
>> Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com>
>> Fixes: f6231a2eefd4 ("arm64: dts: qcom: sc8280xp: Add Microsoft Surface Pro 9 5G")
>
> Fixes should go before your sign-off
Sure, I will change this in v2.
> otherwise
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> Konrad
Thank you,
Jérôme
^ permalink raw reply
* Re: [PATCH 02/11] arm64: dts: qcom: sc8280xp-arcata: Enable backlight
From: Jérôme de Bretagne @ 2026-05-21 17:57 UTC (permalink / raw)
To: Konrad Dybcio, Douglas Anderson, Neil Armstrong, Jessica Zhang,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: dri-devel, linux-kernel, linux-arm-msm, devicetree,
Krzysztof Kozlowski
In-Reply-To: <624a780c-0b22-45e3-aec5-e61c319de901@oss.qualcomm.com>
On 5/21/26 10:48, Konrad Dybcio wrote:
> On 5/21/26 12:26 AM, Jérôme de Bretagne wrote:
>> On 5/20/26 18:40, Jérôme de Bretagne via B4 Relay wrote:
>>> From: Jérôme de Bretagne <jerome.debretagne@gmail.com>
>>>
>>> Add backlight nodes and enable backlight so that it can be controlled
>>> with the corresponding buttons found on Surface Pro Type Cover keyboards.
>>>
>>> The nodes are almost identical to the ones from the ThinkPad X13s with
>>> a different enable GPIO for the vreg_edp_bl node.
>>>
>>> The difference was found by looking at the output of /sys/kernel/debug/gpio
>>> on the ThinkPad X13s to see the properties of its enable gpio9:
>
> [...]
>
>> and ... backlight still works! It can also be enabled/disabled with:
>> /sys/class/backlight/backlight/bl_power
>> as expected.
>>
>> I have no clue why both gpio6 on pmc8280_2 and gpio6 on pmc8280c can enable and disable the backlight. Is it a common scenario?
>
> Could it be that one of them is an ENABLE_BL pin, while the other one
> enables the regulator?
>
> Konrad
I've looked at more device trees and seen that quite a few of them
simply don't have a "power-supply = <&vreg_edp_bl>" property in their
backlight node. Trying a similar approach, the backlight still works
so the gpio6 I was adding wasn't used (or even useful).
I will send a simpler patch in v2, removing the power-supply property
and the vreg_edp_bl & edp_bl_reg_en nodes.
Jérôme
^ permalink raw reply
* Re: [PATCH v4 4/4] regulator: Add regulator driver for Unisoc SC2730 PMIC
From: sashiko-bot @ 2026-05-21 17:57 UTC (permalink / raw)
To: Otto Pflüger; +Cc: devicetree, robh, conor+dt
In-Reply-To: <20260521-sc2730-regulators-v4-4-1ac8a3b5ed82@abscue.de>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The register offset for `SC2730_LDO_VDDCAMIO_VOL` is defined as `0x28`, which breaks the LDO register layout pattern and points to the DCDC/global control region. This is highly likely a typo and could cause silent corruption of another PMIC register when setting the LDO voltage.
--
commit 5c1a2f6397caa4ad7997b2f6f912d7c202d97041
Author: Otto Pflüger <otto.pflueger@abscue.de>
Subject: regulator: Add regulator driver for Unisoc SC2730 PMIC
This commit adds a regulator driver for the Spreadtrum/Unisoc SC2730 PMIC,
which is used with SoCs like the UMS512 and UMS9230. The new driver is
based on a downstream Unisoc driver and the existing SC2731 driver.
> diff --git a/drivers/regulator/sc2730-regulator.c b/drivers/regulator/sc2730-regulator.c
> new file mode 100644
> index 0000000000000..9e40c6eae4943
> --- /dev/null
> +++ b/drivers/regulator/sc2730-regulator.c
[ ... ]
> +/*
> + * SC2730 vsel register
> + */
> +#define SC2730_DCDC_CPU_VOL (SC2730_REGULATOR_BASE + 0x44)
[ ... ]
> +#define SC2730_LDO_AVDD18_VOL (SC2730_REGULATOR_BASE + 0x104)
> +#define SC2730_LDO_VDDRF18_VOL (SC2730_REGULATOR_BASE + 0x110)
> +#define SC2730_LDO_VDDCAMIO_VOL (SC2730_REGULATOR_BASE + 0x28)
[Severity: High]
Is 0x28 the correct offset for the VDDCAMIO voltage register?
All other LDO voltage and power-down registers are clustered in the 0x100
to 0x210 range. Defining this at 0x28 places it in the DCDC or global
control region.
Could writing voltage configurations to this offset fail to configure the
VDDCAMIO regulator and potentially corrupt another PMIC register instead?
> +#define SC2730_LDO_VDDWCN_VOL (SC2730_REGULATOR_BASE + 0x120)
> +#define SC2730_LDO_VDDCAMD1_VOL (SC2730_REGULATOR_BASE + 0x12c)
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260521-sc2730-regulators-v4-0-1ac8a3b5ed82@abscue.de?part=4
^ permalink raw reply
* Re: [PATCH v1 3/9] arm64: dts: agilex5: add Cadence SD6HC controller and SOCDK enablement
From: Kathpalia, Tanmay @ 2026-05-21 17:56 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-mmc, ulf.hansson, Dinh Nguyen, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel
In-Reply-To: <20260515-tuscan-spider-of-realization-ffafdf@quoll>
Hi K
Thanks for your feedback.
On 5/15/2026 2:08 PM, Krzysztof Kozlowski wrote:
> On Mon, May 11, 2026 at 01:21:25PM -0700, Tanmay Kathpalia wrote:
>> The Agilex5 SoC device tree gains an SD/MMC controller node backed by
>> the Cadence SD6HC, with IOMMU integration via the system SMMU. Card
>> power is supplied by a fixed 3.3V regulator and I/O voltage switching
>> between 1.8V and 3.3V is handled by a GPIO-controlled regulator.
>>
>> The SOCDK board enables the controller for SD-only operation in 4-bit
>> bus width with high-speed and SDR104 UHS-I modes at 200 MHz maximum
>> clock. SDHCI capability overrides clear the SDR50 tuning flag and
>> override the clock base mask to report 200 MHz.
>>
>> Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
>> ---
>> .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 38 +++++++++++++++++++
>> .../boot/dts/intel/socfpga_agilex5_socdk.dts | 26 +++++++++++++
>> 2 files changed, 64 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> index 352c96d144a8..7e080f13166f 100644
>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> @@ -300,6 +300,44 @@ portb: gpio-controller@0 {
>> };
>> };
>>
>> + sd_emmc_power: regulator-fixed-3p3v {
> NAK, this fails basic rules of organizing DTS/DTSI and the nodes. This
> is simple-bus, so how could you have here a regulator which is non MMIO?
>
> Plus, explain me how these regulators managed to appear on the SoC
> die/silicon?
>
> Best regards,
> Krzysztof
Apologies, you are right on both counts.
In v2 this will be fixed:
1. sd_emmc_power and sd_io_1v8_reg will be moved to the root level
of socfpga_agilex5_socdk.dts where they belong.
2. emmc_io_1v8_reg will be moved to the root level of
socfpga_agilex5_socdk_emmc.dts.
3. The shared socfpga_agilex5.dtsi will carry only the SoC-level
emmc controller node with no board-specific regulators.
Regards,
Tanmay
^ permalink raw reply
* Re: [PATCH v2 2/2] remoteproc: xlnx: enable auto boot feature
From: Mathieu Poirier @ 2026-05-21 17:48 UTC (permalink / raw)
To: Tanmay Shah
Cc: andersson, robh, krzk+dt, conor+dt, michal.simek, ben.levinsky,
linux-remoteproc, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20260501143707.1591110-3-tanmay.shah@amd.com>
Good morning,
I don't recal reviewing the first revision of this set. Can you provide a link
to it so that I can read the comments that were provided?
On Fri, May 01, 2026 at 07:37:07AM -0700, Tanmay Shah wrote:
> remoteproc framework has capability to start (or attach to) the remote
The remoteproc framework...
> processor automatically if auto boot flag is set by the driver during
> probe. If remote core is not started before the Linux boot, and linux is
> expected to start the remote core then it uses "firmware-name" property
> to load default firmware during auto boot.
>
> Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
> ---
> drivers/remoteproc/xlnx_r5_remoteproc.c | 48 +++++++++++++++++--------
> 1 file changed, 34 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/remoteproc/xlnx_r5_remoteproc.c b/drivers/remoteproc/xlnx_r5_remoteproc.c
> index 45a62cb98072..652030f9cea2 100644
> --- a/drivers/remoteproc/xlnx_r5_remoteproc.c
> +++ b/drivers/remoteproc/xlnx_r5_remoteproc.c
> @@ -899,17 +899,18 @@ static const struct rproc_ops zynqmp_r5_rproc_ops = {
> };
>
> /**
> - * zynqmp_r5_add_rproc_core() - Add core data to framework.
> - * Allocate and add struct rproc object for each r5f core
> + * zynqmp_r5_alloc_rproc_core() - alloc rproc core data structure
> + * Allocate struct rproc object for each r5f core
> * This is called for each individual r5f core
> *
> * @cdev: Device node of each r5 core
> *
> * Return: zynqmp_r5_core object for success else error code pointer
> */
> -static struct zynqmp_r5_core *zynqmp_r5_add_rproc_core(struct device *cdev)
> +static struct zynqmp_r5_core *zynqmp_r5_alloc_rproc_core(struct device *cdev)
Why is there a need to change the function's name?
> {
> struct zynqmp_r5_core *r5_core;
> + const char *fw_name = NULL;
> struct rproc *r5_rproc;
> int ret;
>
> @@ -918,10 +919,15 @@ static struct zynqmp_r5_core *zynqmp_r5_add_rproc_core(struct device *cdev)
> if (ret)
> return ERR_PTR(ret);
>
> + ret = rproc_of_parse_firmware(cdev, 0, &fw_name);
> + if (ret < 0 && ret != -EINVAL)
> + return ERR_PTR(dev_err_probe(cdev, ret,
> + "failed to parse firmware-name\n"));
> +
> /* Allocate remoteproc instance */
> r5_rproc = rproc_alloc(cdev, dev_name(cdev),
> &zynqmp_r5_rproc_ops,
> - NULL, sizeof(struct zynqmp_r5_core));
> + fw_name, sizeof(struct zynqmp_r5_core));
> if (!r5_rproc) {
> dev_err(cdev, "failed to allocate memory for rproc instance\n");
> return ERR_PTR(-ENOMEM);
> @@ -932,6 +938,11 @@ static struct zynqmp_r5_core *zynqmp_r5_add_rproc_core(struct device *cdev)
> r5_rproc->recovery_disabled = true;
> r5_rproc->has_iommu = false;
> r5_rproc->auto_boot = false;
> +
> + /* attempt to boot automatically if the firmware-name is provided */
> + if (fw_name)
> + r5_rproc->auto_boot = true;
> +
What happens when a firmware name needs to be provided in the DT but you don't
want to automatically boot the remote processor?
> r5_core = r5_rproc->priv;
> r5_core->dev = cdev;
> r5_core->np = dev_of_node(cdev);
> @@ -941,13 +952,6 @@ static struct zynqmp_r5_core *zynqmp_r5_add_rproc_core(struct device *cdev)
> goto free_rproc;
> }
>
> - /* Add R5 remoteproc core */
> - ret = rproc_add(r5_rproc);
> - if (ret) {
> - dev_err(cdev, "failed to add r5 remoteproc\n");
> - goto free_rproc;
> - }
> -
I'm not sure why there is a need to move this to zynqmp_r5_cluster_init()? Is
it simply to make the error path easier to handle? If so, please do that in a
separate patch.
> r5_core->rproc = r5_rproc;
> return r5_core;
>
> @@ -1280,6 +1284,7 @@ static int zynqmp_r5_core_init(struct zynqmp_r5_cluster *cluster,
> if (zynqmp_r5_get_rsc_table_va(r5_core))
> dev_dbg(r5_core->dev, "rsc tbl not found\n");
> r5_core->rproc->state = RPROC_DETACHED;
> + r5_core->rproc->auto_boot = true;
I thought this was done in zynqmp_r5_add_rproc_core() - what am I missing?
Thanks,
Mathieu
> }
> }
>
> @@ -1304,7 +1309,7 @@ static int zynqmp_r5_cluster_init(struct zynqmp_r5_cluster *cluster)
> enum rpu_oper_mode fw_reg_val;
> struct device **child_devs;
> enum rpu_tcm_comb tcm_mode;
> - int core_count, ret, i;
> + int core_count, ret, i, j;
> struct mbox_info *ipi;
>
> ret = of_property_read_u32(dev_node, "xlnx,cluster-mode", &cluster_mode);
> @@ -1390,7 +1395,7 @@ static int zynqmp_r5_cluster_init(struct zynqmp_r5_cluster *cluster)
> child_devs[i] = &child_pdev->dev;
>
> /* create and add remoteproc instance of type struct rproc */
> - r5_cores[i] = zynqmp_r5_add_rproc_core(&child_pdev->dev);
> + r5_cores[i] = zynqmp_r5_alloc_rproc_core(&child_pdev->dev);
> if (IS_ERR(r5_cores[i])) {
> ret = PTR_ERR(r5_cores[i]);
> r5_cores[i] = NULL;
> @@ -1435,16 +1440,31 @@ static int zynqmp_r5_cluster_init(struct zynqmp_r5_cluster *cluster)
> goto release_r5_cores;
> }
>
> + for (j = 0; j < cluster->core_count; j++) {
> + /* Add R5 remoteproc core */
> + ret = rproc_add(r5_cores[j]->rproc);
> + if (ret) {
> + dev_err_probe(r5_cores[j]->dev, ret,
> + "failed to add remoteproc\n");
> + goto delete_r5_cores;
> + }
> + }
> +
> kfree(child_devs);
> return 0;
>
> +delete_r5_cores:
> + i = core_count - 1;
> + /* delete previous added rproc */
> + while (--j >= 0)
> + rproc_del(r5_cores[j]->rproc);
> +
> release_r5_cores:
> while (i >= 0) {
> put_device(child_devs[i]);
> if (r5_cores[i]) {
> zynqmp_r5_free_mbox(r5_cores[i]->ipi);
> of_reserved_mem_device_release(r5_cores[i]->dev);
> - rproc_del(r5_cores[i]->rproc);
> rproc_free(r5_cores[i]->rproc);
> }
> i--;
> --
> 2.34.1
>
^ permalink raw reply
* Re: [PATCH V8 02/10] dt-bindings: iio: imu: icm42600: Add icm42607 binding
From: Chris Morgan @ 2026-05-21 17:43 UTC (permalink / raw)
To: Conor Dooley
Cc: Jonathan Cameron, Chris Morgan, linux-iio, andy, nuno.sa,
dlechner, jean-baptiste.maneyrol, linux-rockchip, devicetree,
heiko, conor+dt, krzk+dt, robh, andriy.shevchenko,
Krzysztof Kozlowski
In-Reply-To: <20260521-premium-afterlife-0d7a22b77517@spud>
On Thu, May 21, 2026 at 05:44:21PM +0100, Conor Dooley wrote:
> On Wed, May 20, 2026 at 05:42:17PM +0100, Jonathan Cameron wrote:
> > On Mon, 18 May 2026 15:05:17 -0500
> > Chris Morgan <macroalpha82@gmail.com> wrote:
> >
> > > From: Chris Morgan <macromorgan@hotmail.com>
> > >
> > > Add devicetree binding for the Invensense ICM42607 and Invensense
> > > ICM42607P inertial measurement unit. This unit is a combined
> > > accelerometer, gyroscope, and thermometer available via I2C or SPI.
> > >
> > > This device is functionally very similar to the icm42600 series with a
> > > very different register layout.
> > >
> > > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> > > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> > Note that Sashiko has highlighted that the binding this being added to
> > has a potential problem.
> >
> > interrupts are required but interrupt-names are not.
> > That would be fine but the binding doesn't say there is a default
> > ordering for the interrupts - so if we don't have names we have no
> > idea which interrupt it is.
> >
> > This needs fixing - probably by adding a default
>
> Worth pointing out that this isn't an issue with this particular patch,
> the problem exists in mainline.
The driver I lovingly borrowed this code from seems to have fallback
logic, basically picking the first interrupt if it couldn't find one
named "INT1". I was told early on not to do this that way, so in my
case the interrupt-names would be required (but not for the existing
driver because of this fallback).
Should I make the requirement conditional just to my compatible
strings?
Thank you,
Chris
^ permalink raw reply
* Re: [PATCH v4 3/4] mfd: sprd-sc27xx: Add SC2730 regulator cell
From: sashiko-bot @ 2026-05-21 17:33 UTC (permalink / raw)
To: Otto Pflüger; +Cc: robh, conor+dt, devicetree
In-Reply-To: <20260521-sc2730-regulators-v4-3-1ac8a3b5ed82@abscue.de>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] The existing MFD cells for `sc2731-regulator` and `sc2731-poweroff` fail to bind to their respective drivers due to naming mismatches.
--
commit 410bda683e83be6297ddc2d59ec5df1da8471eae
Author: Otto Pflüger <otto.pflueger@abscue.de>
mfd: sprd-sc27xx: Add SC2730 regulator cell
Add an MFD cell to register the SC2730 PMIC's regulators.
> diff --git a/drivers/mfd/sprd-sc27xx-spi.c b/drivers/mfd/sprd-sc27xx-spi.c
> index aa052f6466231..214bcbef0c271 100644
> --- a/drivers/mfd/sprd-sc27xx-spi.c
> +++ b/drivers/mfd/sprd-sc27xx-spi.c
> @@ -61,6 +61,7 @@ static const struct mfd_cell sc2730_devices[] = {
> MFD_CELL_OF("sc2730-efuse", NULL, NULL, 0, 0, "sprd,sc2730-efuse"),
> MFD_CELL_OF("sc2730-eic", NULL, NULL, 0, 0, "sprd,sc2730-eic"),
> MFD_CELL_OF("sc2730-fgu", NULL, NULL, 0, 0, "sprd,sc2730-fgu"),
> + MFD_CELL_NAME("sc2730-regulator"),
> MFD_CELL_OF("sc2730-rtc", NULL, NULL, 0, 0, "sprd,sc2730-rtc"),
> MFD_CELL_OF("sc2730-vibrator", NULL, NULL, 0, 0, "sprd,sc2730-vibrator"),
> };
[Severity: High]
This isn't a bug introduced by this patch, but do the existing MFD cells for
SC2731 regulators and poweroff fail to bind to their respective drivers due
to naming mismatches?
The sc2731_devices array creates MFD cells named "sc2731-regulator" and
"sc2731-poweroff". However, their corresponding platform drivers
(drivers/regulator/sc2731-regulator.c and
drivers/power/reset/sc27xx-poweroff.c) set their .name fields to
"sc27xx-regulator" and "sc27xx-poweroff", respectively.
Since neither driver provides a platform_device_id table to map the
SoC-specific names, does the platform_match() string comparison fail?
Would this leave the SC2731 hardware without regulator control and poweroff
functionality since the MFD core instantiates these platform devices, but
they never bind to their drivers?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260521-sc2730-regulators-v4-0-1ac8a3b5ed82@abscue.de?part=3
^ permalink raw reply
* Re: [PATCH v4 2/3] arm64: dts: freescale: add Aquila iMX95 support
From: sashiko-bot @ 2026-05-21 17:30 UTC (permalink / raw)
To: Franz Schnyder; +Cc: devicetree, Frank.Li, robh, conor+dt, imx
In-Reply-To: <20260521-add-aquila-imx95-v4-2-5a7f86c824f5@toradex.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The DisplayPort connector references a disabled DisplayPort bridge, leaving dangling references and rendering the connector non-functional while wasting power.
- [Medium] The dedicated power supply regulator for the disabled DSI-to-DP bridge is incorrectly marked as always-on, wasting power.
--
commit 3392fc6b669bcc9dccbd369d342a80d81c494ed6
Author: João Paulo Gonçalves <joao.goncalves@toradex.com>
arm64: dts: freescale: add Aquila iMX95 support
This commit adds support for the Toradex Aquila iMX95 computer-on-module
and its corresponding development carrier board.
Link: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95
Link: https://www.toradex.com/products/carrier-board/aquila-development-board-kit
> diff --git a/arch/arm64/boot/dts/freescale/imx95-aquila-dev.dts b/arch/arm64/boot/dts/freescale/imx95-aquila-dev.dts
> new file mode 100644
> index 0000000000000..3df17700b632f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx95-aquila-dev.dts
> @@ -0,0 +1,389 @@
[ ... ]
> + aliases {
> + eeprom1 = &carrier_eeprom;
> + };
> +
> + dp_1_connector: dp0-connector {
> + compatible = "dp-connector";
> + dp-pwr-supply = <®_dp_3p3v>;
> + type = "full-size";
> +
> + port {
> + dp_1_connector_in: endpoint {
> + remote-endpoint = <&dsi2dp_out>;
> + };
> + };
> + };
[Severity: Medium]
Since som_dsi2dp_bridge is disabled by default in imx95-aquila.dtsi and not
explicitly enabled in this device tree, does this connector node leave
dangling references?
Without status = "disabled" on this node, the display-connector driver will
probe successfully and unconditionally enable its dp-pwr-supply (reg_dp_3p3v),
wasting power on the carrier board for an unusable interface.
Should this connector be disabled by default or have the bridge enabled here?
> diff --git a/arch/arm64/boot/dts/freescale/imx95-aquila.dtsi b/arch/arm64/boot/dts/freescale/imx95-aquila.dtsi
> new file mode 100644
> index 0000000000000..69dc962a24a1d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx95-aquila.dtsi
> @@ -0,0 +1,1160 @@
[ ... ]
> + reg_dp_1p2v: regulator-dp-1p2v {
> + compatible = "regulator-fixed";
> + /* CTRL_DP_BRIDGE_EN */
> + gpios = <&som_gpio_expander_0 7 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-always-on;
> + regulator-max-microvolt = <1200000>;
> + regulator-min-microvolt = <1200000>;
> + regulator-name = "On-module +V1.2_DP";
> + vin-supply = <®_1p8v>;
> + };
[Severity: Medium]
Since this regulator is a dedicated power supply for som_dsi2dp_bridge which
is marked as status = "disabled" below, is it necessary to have the
regulator-always-on property here?
The always-on property bypasses the driver and forces the regulator core to
unconditionally assert the CTRL_DP_BRIDGE_EN GPIO at boot, continuously
powering the bridge chip on the module even when disabled.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260521-add-aquila-imx95-v4-0-5a7f86c824f5@toradex.com?part=2
^ permalink raw reply
* [PATCH v9 3/3] PCI: mediatek: Add support for EcoNet EN7528 SoC
From: Caleb James DeLisle @ 2026-05-21 17:19 UTC (permalink / raw)
To: linux-pci
Cc: linux-mips, naseefkm, ryder.lee, helgaas, lpieralisi, kwilczynski,
mani, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ansuelsmth, linux-mediatek, devicetree,
linux-kernel, Caleb James DeLisle
In-Reply-To: <20260521171951.1495781-1-cjd@cjdns.fr>
Add support for the PCIe present on the EcoNet EN7528 (and EN751221) SoCs.
These SoCs have a mix of Gen1 and Gen2 capable ports, but the Gen2 ports
require re-training after startup.
Co-developed-by: Ahmed Naseef <naseefkm@gmail.com>
Signed-off-by: Ahmed Naseef <naseefkm@gmail.com>
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
---
Before sending v9 I did some investigation to see if
pcie_failed_link_retrain() in quirks.c could be a suitable replacement
for mtk_pcie_retrain().
I discovered that it exits early on this hardware because the hardware
does not set PCI_EXP_LNKCAP_DLLLARC, and link_active_reporting is
tested.
The hardware has a register bit which claims to enable Data Link Layer
active reporting, but setting it during init does not cause
link_active_reporting to become true. Furthermore, skipping the check
in pcie_failed_link_retrain() makes the function run, but the port does
not upgrade to Gen2. Therefore I determined that it is most prudent to
keep with the mtk_pcie_retrain() logic which follows behavior of
reference code and is shown to work.
---
drivers/pci/controller/Kconfig | 2 +-
drivers/pci/controller/pcie-mediatek.c | 154 +++++++++++++++++++++++++
2 files changed, 155 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 2247709ef6d6..8a3a31b2bc12 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -209,7 +209,7 @@ config PCI_MVEBU
config PCIE_MEDIATEK
tristate "MediaTek PCIe controller"
- depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
+ depends on ARCH_AIROHA || ARCH_MEDIATEK || ECONET || COMPILE_TEST
depends on OF
depends on PCI_MSI
select IRQ_MSI_LIB
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index c503fbd774d0..30f8070967b8 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -9,11 +9,13 @@
#include <linux/clk.h>
#include <linux/delay.h>
+#include <linux/errno.h>
#include <linux/iopoll.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqchip/irq-msi-lib.h>
#include <linux/irqdomain.h>
+#include <linux/kconfig.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/msi.h>
@@ -77,6 +79,7 @@
#define PCIE_CONF_VEND_ID 0x100
#define PCIE_CONF_DEVICE_ID 0x102
+#define PCIE_CONF_REV_CLASS 0x104
#define PCIE_CONF_CLASS_ID 0x106
#define PCIE_INT_MASK 0x420
@@ -89,6 +92,11 @@
#define MSI_MASK BIT(23)
#define MTK_MSI_IRQS_NUM 32
+#define EN7528_HOST_MODE 0x00804201
+#define EN7528_LINKUP_REG 0x50
+#define EN7528_RC0_LINKUP BIT(1)
+#define EN7528_RC1_LINKUP BIT(2)
+
#define PCIE_AHB_TRANS_BASE0_L 0x438
#define PCIE_AHB_TRANS_BASE0_H 0x43c
#define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
@@ -148,12 +156,15 @@ struct mtk_pcie_port;
* @MTK_PCIE_FIX_DEVICE_ID: host's device ID needed to be fixed
* @MTK_PCIE_NO_MSI: Bridge has no MSI support, and relies on an external block
* @MTK_PCIE_SKIP_RSTB: Skip calling RSTB bits on PCIe probe
+ * @MTK_PCIE_RETRAIN: Retrain link to bridge after startup because some
+ * Gen2-capable devices start as Gen1.
*/
enum mtk_pcie_quirks {
MTK_PCIE_FIX_CLASS_ID = BIT(0),
MTK_PCIE_FIX_DEVICE_ID = BIT(1),
MTK_PCIE_NO_MSI = BIT(2),
MTK_PCIE_SKIP_RSTB = BIT(3),
+ MTK_PCIE_RETRAIN = BIT(4),
};
/**
@@ -755,6 +766,134 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
return 0;
}
+static int mtk_pcie_startup_port_en7528(struct mtk_pcie_port *port)
+{
+ struct mtk_pcie *pcie = port->pcie;
+ struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
+ struct resource *mem = NULL;
+ struct resource_entry *entry;
+ u32 val, link_mask;
+ int err;
+
+ entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
+ if (entry)
+ mem = entry->res;
+ if (!mem)
+ return -EINVAL;
+
+ if (!pcie->cfg) {
+ dev_err(pcie->dev, "EN7528: pciecfg syscon not available\n");
+ return -EINVAL;
+ }
+
+ /* Assert all reset signals */
+ writel(0, port->base + PCIE_RST_CTRL);
+
+ /*
+ * Enable PCIe link down reset, if link status changed from link up to
+ * link down, this will reset MAC control registers and configuration
+ * space.
+ */
+ writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
+
+ msleep(PCIE_T_PVPERL_MS);
+
+ /* De-assert PHY, PE, PIPE, MAC and configuration reset */
+ val = readl(port->base + PCIE_RST_CTRL);
+ val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
+ PCIE_MAC_SRSTB | PCIE_CRSTB;
+ writel(val, port->base + PCIE_RST_CTRL);
+
+ writel(PCIE_CLASS_CODE | PCIE_REVISION_ID,
+ port->base + PCIE_CONF_REV_CLASS);
+ writel(EN7528_HOST_MODE, port->base);
+
+ link_mask = (port->slot == 0) ? EN7528_RC0_LINKUP : EN7528_RC1_LINKUP;
+
+ /* 100ms timeout value should be enough for Gen1/2 training */
+ err = regmap_read_poll_timeout(pcie->cfg, EN7528_LINKUP_REG, val,
+ !!(val & link_mask), 20,
+ PCI_PM_D3COLD_WAIT * USEC_PER_MSEC);
+ if (err) {
+ dev_err(pcie->dev, "EN7528: port%d link timeout\n", port->slot);
+ return -ETIMEDOUT;
+ }
+
+ /* Activate INTx interrupts */
+ val = readl(port->base + PCIE_INT_MASK);
+ val &= ~INTX_MASK;
+ writel(val, port->base + PCIE_INT_MASK);
+
+ if (IS_ENABLED(CONFIG_PCI_MSI))
+ mtk_pcie_enable_msi(port);
+
+ /* Set AHB to PCIe translation windows */
+ val = lower_32_bits(mem->start) |
+ AHB2PCIE_SIZE(fls(resource_size(mem)));
+ writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
+
+ val = upper_32_bits(mem->start);
+ writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
+
+ writel(WIN_ENABLE, port->base + PCIE_AXI_WINDOW0);
+
+ if (!IS_BUILTIN(CONFIG_PCIE_MEDIATEK))
+ dev_info(pcie->dev,
+ "module not built-in, Gen2 unavailable even if supported\n");
+
+ return 0;
+}
+
+/**
+ * mtk_pcie_retrain - retrain the root bridge link if needed
+ * @dev: The device, for use in logging
+ * @host: The host bridge which contains the link
+ *
+ * Due to what is likely a hardware bug, some devices (notably EcoNet) start up
+ * as Gen1, and must be retrained once after initial configuration in order to
+ * reach Gen2.
+ *
+ * These devices always self-identify as Gen2 capable, but sometimes the PHY is
+ * only capable of Gen1 operation, and sometimes the PCIe card (e.g. wifi) is
+ * only Gen1 capable. Therefore it is most convenient to retrain every port
+ * after startup.
+ */
+static int mtk_pcie_retrain(struct device *dev, struct pci_host_bridge *host)
+{
+ struct pci_dev *rp;
+ int ret = -ENOENT;
+ u16 lnksta = 0;
+ u32 speed;
+
+ /* Should already have been warned about during startup_port */
+ if (!IS_BUILTIN(CONFIG_PCIE_MEDIATEK))
+ return 0;
+
+ guard(rwsem_read)(&pci_bus_sem);
+
+ for_each_pci_bridge(rp, host->bus) {
+ if (pci_pcie_type(rp) != PCI_EXP_TYPE_ROOT_PORT)
+ continue;
+
+#if IS_BUILTIN(CONFIG_PCIE_MEDIATEK)
+ ret = pcie_retrain_link(rp, true);
+#endif
+
+ if (ret)
+ return dev_err_probe(&rp->dev, ret,
+ "failed to retrain port\n");
+
+ pcie_capability_read_word(rp, PCI_EXP_LNKSTA, &lnksta);
+ speed = lnksta & PCI_EXP_LNKSTA_CLS;
+
+ pci_info(rp, "link retrained, speed %s\n",
+ pci_speed_string(pcie_link_speed[speed]));
+
+ }
+
+ return 0;
+}
+
static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
unsigned int devfn, int where)
{
@@ -1159,6 +1298,13 @@ static int mtk_pcie_probe(struct platform_device *pdev)
if (err)
goto put_resources;
+ /*
+ * Ignore error because pci_host_probe() was already called, and in any
+ * case it is possible that the port will still work as Gen1.
+ */
+ if (pcie->soc->quirks & MTK_PCIE_RETRAIN)
+ mtk_pcie_retrain(dev, host);
+
return 0;
put_resources:
@@ -1274,8 +1420,16 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
.quirks = MTK_PCIE_FIX_CLASS_ID | MTK_PCIE_FIX_DEVICE_ID,
};
+static const struct mtk_pcie_soc mtk_pcie_soc_en7528 = {
+ .ops = &mtk_pcie_ops_v2,
+ .startup = mtk_pcie_startup_port_en7528,
+ .setup_irq = mtk_pcie_setup_irq,
+ .quirks = MTK_PCIE_RETRAIN,
+};
+
static const struct of_device_id mtk_pcie_ids[] = {
{ .compatible = "airoha,an7583-pcie", .data = &mtk_pcie_soc_an7583 },
+ { .compatible = "econet,en7528-pcie", .data = &mtk_pcie_soc_en7528 },
{ .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
{ .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
{ .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
--
2.39.5
^ permalink raw reply related
* [PATCH v9 2/3] dt-bindings: PCI: mediatek: Add support for EcoNet EN7528
From: Caleb James DeLisle @ 2026-05-21 17:19 UTC (permalink / raw)
To: linux-pci
Cc: linux-mips, naseefkm, ryder.lee, helgaas, lpieralisi, kwilczynski,
mani, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ansuelsmth, linux-mediatek, devicetree,
linux-kernel, Caleb James DeLisle, Conor Dooley
In-Reply-To: <20260521171951.1495781-1-cjd@cjdns.fr>
Introduce EcoNet EN7528 SoC compatible in MediaTek PCIe controller
binding.
EcoNet PCIe controller has the same configuration model as
Mediatek v2 but is initialized more similarly to an MT7621
PCIe.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/pci/mediatek-pcie.yaml | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml
index 0b8c78ec4f91..c009a7a52bc6 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml
@@ -14,6 +14,7 @@ properties:
oneOf:
- enum:
- airoha,an7583-pcie
+ - econet,en7528-pcie
- mediatek,mt2712-pcie
- mediatek,mt7622-pcie
- mediatek,mt7629-pcie
@@ -226,6 +227,31 @@ allOf:
mediatek,pbus-csr: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: econet,en7528-pcie
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+ resets: false
+
+ reset-names: false
+
+ power-domains: false
+
+ mediatek,pbus-csr: false
+
+ required:
+ - phys
+ - phy-names
+
unevaluatedProperties: false
examples:
--
2.39.5
^ permalink raw reply related
* [PATCH v9 0/3] Add EcoNet EN7528 (and EN751221) PCIe support.
From: Caleb James DeLisle @ 2026-05-21 17:19 UTC (permalink / raw)
To: linux-pci
Cc: linux-mips, naseefkm, ryder.lee, helgaas, lpieralisi, kwilczynski,
mani, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ansuelsmth, linux-mediatek, devicetree,
linux-kernel, Caleb James DeLisle
Tested on TpLink Archer VR1200V-V2 (EN751221 with Gen2 device)
Changes since v8:
* guard(rwsem_read)(&pci_bus_sem); in mtk_pcie_retrain
* v8: https://lore.kernel.org/linux-mips/20260520183827.908243-1-cjd@cjdns.fr
Changes from v7:
* mtk_pcie_retrain retrain all root ports not just first
* Include fix from Manivannan Sadhasivam, wrong usage of virt_to_phys()
* v7: https://lore.kernel.org/linux-mips/20260514151318.3444959-1-cjd@cjdns.fr
Changes from v6:
* s/reset/resets/ in .yaml
* s/re-train/retrain/g
* s/Root bridge/Root port/
* If module not builtin, log at mtk_pcie_startup_port_en7528()
* Do not fail if error in mtk_pcie_retrain()
* v6: https://lore.kernel.org/linux-mips/20260513191652.3200607-1-cjd@cjdns.fr
Changes from v5:
* s/errno-base.h/errno.h/
* Breakout mtk_pcie_retrain() into a function
* Use for_each_pci_bridge() to find root bridge
* v5: https://lore.kernel.org/linux-mips/20260413140339.16238-1-cjd@cjdns.fr/
Changes from v4:
* Fixed missing Acked-by
* Rebased to commit 66672af7a095 ("Add linux-next specific files for 20260410")
* v4: https://lore.kernel.org/linux-mips/20260404182854.2183651-1-cjd@cjdns.fr/
Changes from v3:
* s/initiallized/initialized/
* Use PCIE_T_PVPERL_MS for sleep time
* Use PCI_PM_D3COLD_WAIT for startup wait time
* Clarify comment "Activate INTx interrupts"
* Add MTK_PCIE_RETRAIN quirk for devices which require link re-train
* Do not retrain *all* bridges, only root bridge
* Better comments and logging in retraining logic
* v3: https://lore.kernel.org/linux-mips/20260320094212.696671-1-cjd@cjdns.fr/
Changes from v2:
* mediatek-pcie.yaml -> s/power-domain/power-domains/ and drop example
* Patch 3 dropped as it has been applied (Thanks!)
* v2: https://lore.kernel.org/linux-mips/20260316155157.679533-1-cjd@cjdns.fr/
Changes from v1:
* mediatek-pcie.yaml slot0 needs device-type = "pci", fix dt_binding_check
Link: https://lore.kernel.org/linux-mips/177334026016.3889069.9474337544951486443.robh@kernel.org
* v1: https://lore.kernel.org/linux-mips/20260312165332.569772-1-cjd@cjdns.fr/
This was split from a larger PCIe patchset which crossed multiple
subsystems. I'm not labeling this a v3 because it's a new patchset, but
I'm keeping the historical record anyway.
Changes from econet-pcie v2:
* mediatek-pcie.yaml add missing constraints to PCI node properties
* econet-pcie v2: https://lore.kernel.org/linux-mips/20260309131818.74467-1-cjd@cjdns.fr
Changes from econet-pcie v1:
* pcie-mediatek.c Exclude pcie_retrain_link() when building as a module
* econet-pcie v1: https://lore.kernel.org/linux-mips/20260303190948.694783-1-cjd@cjdns.fr/
Caleb James DeLisle (2):
dt-bindings: PCI: mediatek: Add support for EcoNet EN7528
PCI: mediatek: Add support for EcoNet EN7528 SoC
Manivannan Sadhasivam (1):
PCI: mediatek: Use actual physical address instead of virt_to_phys()
.../bindings/pci/mediatek-pcie.yaml | 26 +++
drivers/pci/controller/Kconfig | 2 +-
drivers/pci/controller/pcie-mediatek.c | 170 +++++++++++++++++-
3 files changed, 194 insertions(+), 4 deletions(-)
base-commit: 687da68900cd1a46549f7d9430c7d40346cb86a0
--
2.39.5
^ permalink raw reply
* [PATCH v9 1/3] PCI: mediatek: Use actual physical address instead of virt_to_phys()
From: Caleb James DeLisle @ 2026-05-21 17:19 UTC (permalink / raw)
To: linux-pci
Cc: linux-mips, naseefkm, ryder.lee, helgaas, lpieralisi, kwilczynski,
mani, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, ansuelsmth, linux-mediatek, devicetree,
linux-kernel, Manivannan Sadhasivam, Caleb James DeLisle
In-Reply-To: <20260521171951.1495781-1-cjd@cjdns.fr>
From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
The driver previously used virt_to_phys() on the ioremapped register base
(port->base) to compute the MSI message address. Using virt_to_phys() on an
IO mapped address is incorrect because it expects a kernel virtual address.
To fix it, store the physical start of the I/O register region in
mtk_pcie_port->phys_base and use it to build the MSI address. This replaces
the incorrect virt_to_phys() usage and ensures MSI addresses are generated
correctly.
Fixes: 43e6409db64d ("PCI: mediatek: Add MSI support for MT2712 and MT7622")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Tested-by: Caleb James DeLisle <cjd@cjdns.fr>
---
drivers/pci/controller/pcie-mediatek.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index 75722524fe74..c503fbd774d0 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -175,6 +175,7 @@ struct mtk_pcie_soc {
/**
* struct mtk_pcie_port - PCIe port information
* @base: IO mapped register base
+ * @phys_base: Physical address of the I/O register base region
* @list: port list
* @pcie: pointer to PCIe host info
* @reset: pointer to port reset control
@@ -196,6 +197,7 @@ struct mtk_pcie_soc {
*/
struct mtk_pcie_port {
void __iomem *base;
+ phys_addr_t phys_base;
struct list_head list;
struct mtk_pcie *pcie;
struct reset_control *reset;
@@ -405,7 +407,7 @@ static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
phys_addr_t addr;
/* MT2712/MT7622 only support 32-bit MSI addresses */
- addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
+ addr = port->phys_base + PCIE_MSI_VECTOR;
msg->address_hi = 0;
msg->address_lo = lower_32_bits(addr);
@@ -520,7 +522,7 @@ static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
u32 val;
phys_addr_t msg_addr;
- msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
+ msg_addr = port->phys_base + PCIE_MSI_VECTOR;
val = lower_32_bits(msg_addr);
writel(val, port->base + PCIE_IMSI_ADDR);
@@ -953,6 +955,7 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
struct mtk_pcie_port *port;
struct device *dev = pcie->dev;
struct platform_device *pdev = to_platform_device(dev);
+ struct resource *res;
char name[20];
int err;
@@ -961,7 +964,14 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
return -ENOMEM;
snprintf(name, sizeof(name), "port%d", slot);
- port->base = devm_platform_ioremap_resource_byname(pdev, name);
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
+ if (!res) {
+ dev_err(dev, "failed to get port%d base\n", slot);
+ return -EINVAL;
+ }
+
+ port->phys_base = res->start;
+ port->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(port->base)) {
dev_err(dev, "failed to map port%d base\n", slot);
return PTR_ERR(port->base);
--
2.39.5
^ permalink raw reply related
* [PATCH v4] dt-bindings: iommu: riscv: Add bindings for Tenstorrent RISC-V IOMMU
From: Drew Fustini @ 2026-05-21 17:06 UTC (permalink / raw)
To: Tomasz Jeznach, Joerg Roedel, Will Deacon, Robin Murphy,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: iommu, linux-riscv, devicetree, linux-kernel, Drew Fustini,
Joel Stanley, Joerg Roedel, Nicholas Piggin
From: Nicholas Piggin <npiggin@gmail.com>
Extend the binding to cover details specific to the Tenstorrent RISC-V
IOMMU. In particular, a second register range is added which contains
M-privileged registers, e.g., PMAs and PMPs.
The RISC-V spec S-privileged registers remain in the first register
range and are compatible with "riscv,iommu" so the Linux driver does not
notice any difference, but the binding will be used by OpenSBI and
potentially other M-mode software.
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joerg Roedel <joerg.roedel@amd.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[fustini: fix dt_binding_check errors]
Signed-off-by: Drew Fustini <fustini@kernel.org>
---
v4 changes:
- Add minItems: 1 to reg-names so it is legal to for platforms other
than tenstorrent,riscv-iommu to use "base"
- Add reg-names constraints to the allOf: block
- Sashiko review:
https://lore.kernel.org/lkml/20260521070154.9CAA41F000E9@smtp.kernel.org/
- Link to v3:
https://lore.kernel.org/lkml/20260521064445.1740782-2-fustini@kernel.org/
v3 changes:
- Move tenstorrent,riscv-iommu to the enum with qemu,riscv-iommu
- Move descriptions out of the allOf:
- Add minItems: 2 for tenstorrent,riscv-iommu in allOf:
- Fix reg syntax in Example 5
- Link to v2:
https://lore.kernel.org/lkml/20260520061855.1623468-4-fustini@kernel.org/
v2 changes:
- Fix dt_binding_check errors
- Add the Acked-by: from Joerg
- Drop RFC prefix
- Link to v1:
https://lore.kernel.org/lkml/20260310003850.3837030-1-npiggin@gmail.com/
.../bindings/iommu/riscv,iommu.yaml | 59 ++++++++++++++++---
1 file changed, 51 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
index d4838c3b3741..f83efb3ee000 100644
--- a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
@@ -32,22 +32,35 @@ properties:
# should be specified along with 'reg' property providing MMIO location.
compatible:
oneOf:
- - items:
+ - description: Platform (non-PCIe) IOMMU implementations
+ items:
- enum:
- qemu,riscv-iommu
+ - tenstorrent,riscv-iommu
- const: riscv,iommu
- - items:
+ - description: PCIe IOMMU implementations
+ items:
- enum:
- pci1efd,edf1
- const: riscv,pci-iommu
reg:
- maxItems: 1
- description:
- For non-PCI devices this represents base address and size of for the
- IOMMU memory mapped registers interface.
- For PCI IOMMU hardware implementation this should represent an address
- of the IOMMU, as defined in the PCI Bus Binding reference.
+ minItems: 1
+ items:
+ - description:
+ For non-PCI devices, base address and size of the IOMMU memory
+ mapped registers interface. For PCI IOMMU hardware
+ implementation, an address of the IOMMU, as defined in the PCI
+ Bus Binding reference.
+ - description:
+ Region containing platform specific MMRs for machine-mode
+ configuration, such as PMA and PMP registers.
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: base
+ - const: machine
'#iommu-cells':
const: 1
@@ -75,6 +88,26 @@ required:
additionalProperties: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - tenstorrent,riscv-iommu
+ then:
+ properties:
+ reg:
+ minItems: 2
+ reg-names:
+ minItems: 2
+ else:
+ properties:
+ reg:
+ maxItems: 1
+ reg-names:
+ maxItems: 1
+
examples:
- |+
/* Example 1 (IOMMU device with wired interrupts) */
@@ -145,3 +178,13 @@ examples:
};
};
};
+
+ - |+
+ /* Example 5 (Tenstorrent IOMMU device with MSIs) */
+ iommu5: iommu@d2020000 {
+ compatible = "tenstorrent,riscv-iommu", "riscv,iommu";
+ reg = <0xd2020000 0x10000>, <0xaa000000 0x10000>;
+ reg-names = "base", "machine";
+ msi-parent = <&imsics_smode>;
+ #iommu-cells = <1>;
+ };
base-commit: 80dd246accce631c328ea43294e53b2b2dd2aa32
--
2.43.0
^ permalink raw reply related
* [PATCH v4 3/3] arm64: dts: freescale: imx95-aquila: Add Clover carrier board
From: Franz Schnyder @ 2026-05-21 17:11 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, linux-kernel, imx, linux-arm-kernel,
Francesco Dolcini, Franz Schnyder, Antoine Gouby
In-Reply-To: <20260521-add-aquila-imx95-v4-0-5a7f86c824f5@toradex.com>
From: Antoine Gouby <antoine.gouby@toradex.com>
Add support for the Aquila i.MX95 SoM mated with the Clover carrier
board. Clover is a low-cost carrier board for the Aquila family
featuring a small form factor (Nano-ITX 120mm x 120mm) and built for
volume production.
Link: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95
Link: https://www.toradex.com/products/carrier-board/clover
Signed-off-by: Antoine Gouby <antoine.gouby@toradex.com>
Signed-off-by: Franz Schnyder <franz.schnyder@toradex.com>
---
v4: Removed som_dsi2dp_bridge node since SoC's DSI controller is unsupported
v3: Deleted the cdns,* properties from flexspi1
v2: no changes
v1: https://lore.kernel.org/all/20260506-add-aquila-imx95-v1-3-69c8ee1c5413@toradex.com/
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../boot/dts/freescale/imx95-aquila-clover.dts | 285 +++++++++++++++++++++
2 files changed, 286 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index c8697b6ae01c5..3ce082c121036 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -523,6 +523,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-clover.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx95-aquila-clover.dts b/arch/arm64/boot/dts/freescale/imx95-aquila-clover.dts
new file mode 100644
index 0000000000000..fd93043314466
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-aquila-clover.dts
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95
+ * https://www.toradex.com/products/carrier-board/clover
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/usb/pd.h>
+#include "imx95-aquila.dtsi"
+
+/ {
+ model = "Aquila iMX95 on Aquila Clover Board";
+ compatible = "toradex,aquila-imx95-clover",
+ "toradex,aquila-imx95",
+ "fsl,imx95";
+
+ aliases {
+ eeprom1 = &carrier_eeprom;
+ };
+
+ dp_1_connector: dp0-connector {
+ compatible = "dp-connector";
+ dp-pwr-supply = <®_dp_3p3v>;
+ type = "full-size";
+
+ port {
+ dp_1_connector_in: endpoint {
+ remote-endpoint = <&dsi2dp_out>;
+ };
+ };
+ };
+
+ reg_dp_3p3v: regulator-dp-3p3v {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_21_dp>;
+ /* Aquila GPIO_21_DP */
+ gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "DP_3V3";
+ startup-delay-us = <10000>;
+ };
+};
+
+/* Aquila ADC_[1-4] */
+&adc1 {
+ status = "okay";
+};
+
+/* Aquila CTRL_WAKE1_MICO# */
+&aquila_key_wake {
+ status = "okay";
+};
+
+&dsi2dp_out {
+ remote-endpoint = <&dp_1_connector_in>;
+};
+
+/* Aquila ETH_1 */
+&enetc_port0 {
+ status = "okay";
+};
+
+/* Aquila CAN_1 */
+&flexcan1 {
+ status = "okay";
+};
+
+/* Aquila CAN_2 */
+&flexcan2 {
+ status = "okay";
+};
+
+/* Aquila CAN_3 */
+&flexcan3 {
+ status = "okay";
+};
+
+/* Aquila CAN_4 */
+&flexcan4 {
+ status = "okay";
+};
+
+/* Aquila QSPI_1 */
+&flexspi1 {
+ pinctrl-0 = <&pinctrl_flexspi1_4bit>,
+ <&pinctrl_qspi_cs1>;
+
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <66000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ };
+};
+
+&gpio4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_1>,
+ <&pinctrl_gpio_2>,
+ <&pinctrl_gpio_3>,
+ <&pinctrl_gpio_4>;
+};
+
+/* Aquila I2C_2 */
+&i3c2 {
+ status = "okay";
+};
+
+/* Aquila I2C_1 */
+&lpi2c2 {
+ status = "okay";
+
+ fan_controller: fan@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ #pwm-cells = <2>;
+
+ fan {
+ cooling-levels = <255>;
+ pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>;
+ };
+ };
+
+ temperature-sensor@4f {
+ compatible = "ti,tmp1075";
+ reg = <0x4f>;
+ };
+
+ /* USB-C OTG (TCPC USB PD PHY) */
+ tcpc@52 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x52>;
+ interrupt-parent = <&som_gpio_expander_1>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+
+ connector {
+ compatible = "usb-c-connector";
+ data-role = "dual";
+ op-sink-microwatt = <0>;
+ power-role = "dual";
+ self-powered;
+ sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ try-power-role = "sink";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ typec_con_hs: endpoint {
+ remote-endpoint = <&usb1_con_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ typec_con_ss: endpoint {
+ remote-endpoint = <&usb1_con_ss>;
+ };
+ };
+ };
+ };
+ };
+
+ carrier_eeprom: eeprom@57 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+/* Aquila I2C_6 */
+&lpi2c5 {
+ status = "okay";
+};
+
+/* Aquila SPI_1 */
+&lpspi6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi6 &pinctrl_gpio_5>;
+ cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>, <&gpio4 18 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+
+ tpm@1 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_6>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+ spi-max-frequency = <12000000>;
+ };
+};
+
+/* Aquila UART_3, used as the Linux Console */
+&lpuart1 {
+ status = "okay";
+};
+
+/* Aquila UART_4 */
+&lpuart2 {
+ status = "okay";
+};
+
+/* Aquila UART_1 */
+&lpuart3 {
+ status = "okay";
+};
+
+/* Aquila UART_2 */
+&lpuart7 {
+ status = "okay";
+};
+
+/* Aquila PCIE_1 */
+&pcie0 {
+ status = "okay";
+};
+
+/* Aquila PWM_1 */
+&tpm3 {
+ status = "okay";
+};
+
+/* Aquila PWM_3_DSI and PWM_4_DP */
+&tpm5 {
+ status = "okay";
+};
+
+/* Aquila PWM_2 */
+&tpm6 {
+ status = "okay";
+};
+
+/* Aquila USB_2, optional Bluetooth USB */
+&usb2 {
+ status = "okay";
+};
+
+/* Aquila USB_1 */
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc3 {
+ status = "okay";
+
+ port {
+ usb1_con_hs: endpoint {
+ remote-endpoint = <&typec_con_hs>;
+ };
+ };
+};
+
+&usb3_phy {
+ orientation-switch;
+
+ status = "okay";
+
+ port {
+ usb1_con_ss: endpoint {
+ remote-endpoint = <&typec_con_ss>;
+ };
+ };
+};
+
+/* Aquila SD_1 */
+&usdhc2 {
+ status = "okay";
+};
--
2.43.0
^ permalink raw reply related
* [PATCH v4 2/3] arm64: dts: freescale: add Aquila iMX95 support
From: Franz Schnyder @ 2026-05-21 17:11 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, linux-kernel, imx, linux-arm-kernel,
Francesco Dolcini, Franz Schnyder, João Paulo Gonçalves,
Emanuele Ghidoli, Francesco Dolcini, Antoine Gouby,
Ernest Van Hoecke
In-Reply-To: <20260521-add-aquila-imx95-v4-0-5a7f86c824f5@toradex.com>
From: João Paulo Gonçalves <joao.goncalves@toradex.com>
Add support for the Toradex Aquila iMX95 and its development carrier
board.
The module consists of an NXP i.MX95 family SoC, up to 16GB LPDDR5 RAM,
up to 128GB of storage, a USB 3.2 OTG and USB 2.0 Host, a Gigabit
Ethernet PHY, a 10 Gigabit Ethernet interface, an I2C EEPROM and
Temperature Sensor, an RX8130 RTC, one Quad lane CSI interface, one Quad
lane DSI or CSI interface, one LVDS interface (one or two channels), and
some optional addons: DisplayPort (through a DSI-DP bridge), TPM 2.0,
and a WiFi/BT module.
Link: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95
Link: https://www.toradex.com/products/carrier-board/aquila-development-board-kit
Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
Co-developed-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Co-developed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Co-developed-by: Antoine Gouby <antoine.gouby@toradex.com>
Signed-off-by: Antoine Gouby <antoine.gouby@toradex.com>
Co-developed-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
Co-developed-by: Franz Schnyder <franz.schnyder@toradex.com>
Signed-off-by: Franz Schnyder <franz.schnyder@toradex.com>
---
v4: Removed som_dsi2dp_bridge node from the dev board
since SoC's DSI controller is unsupported
v3: -Changed QSPI_1 4bit iomux node name to 'flexspi14bitgrp'
-Deleted the cdns,* properties from flexspi1
v2: -Reordered iomux alphanumerically by node name
-Changed Francesco's tags to have the Toradex mail address
v1: https://lore.kernel.org/all/20260506-add-aquila-imx95-v1-2-69c8ee1c5413@toradex.com/
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/imx95-aquila-dev.dts | 389 +++++++
arch/arm64/boot/dts/freescale/imx95-aquila.dtsi | 1160 ++++++++++++++++++++
3 files changed, 1550 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 513f61eb27b85..c8697b6ae01c5 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -523,6 +523,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx95-aquila-dev.dts b/arch/arm64/boot/dts/freescale/imx95-aquila-dev.dts
new file mode 100644
index 0000000000000..3df17700b632f
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-aquila-dev.dts
@@ -0,0 +1,389 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95
+ * https://www.toradex.com/products/carrier-board/aquila-development-board-kit
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/usb/pd.h>
+#include "imx95-aquila.dtsi"
+
+/ {
+ model = "Aquila iMX95 on Aquila Development Board";
+ compatible = "toradex,aquila-imx95-dev",
+ "toradex,aquila-imx95",
+ "fsl,imx95";
+
+ aliases {
+ eeprom1 = &carrier_eeprom;
+ };
+
+ dp_1_connector: dp0-connector {
+ compatible = "dp-connector";
+ dp-pwr-supply = <®_dp_3p3v>;
+ type = "full-size";
+
+ port {
+ dp_1_connector_in: endpoint {
+ remote-endpoint = <&dsi2dp_out>;
+ };
+ };
+ };
+
+ reg_carrier_1p8v: regulator-carrier-1p8v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "On-carrier 1V8";
+ };
+
+ reg_dp_3p3v: regulator-dp-3p3v {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_21_dp>;
+ /* Aquila GPIO_21_DP */
+ gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "DP_3V3";
+ startup-delay-us = <10000>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,bitclock-master = <&codec_dai>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&codec_dai>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "aquila-wm8904";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "IN2L", "Line In Jack",
+ "IN2R", "Line In Jack",
+ "Microphone Jack", "MICBIAS",
+ "IN1L", "Microphone Jack",
+ "IN1R", "Digital Mic";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Microphone", "Digital Mic",
+ "Headphone", "Headphone Jack",
+ "Line", "Line In Jack";
+
+ codec_dai: simple-audio-card,codec {
+ sound-dai = <&wm8904_1a>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ };
+ };
+};
+
+/* Aquila ADC_[1-4] */
+&adc1 {
+ status = "okay";
+};
+
+/* Aquila CTRL_WAKE1_MICO# */
+&aquila_key_wake {
+ status = "okay";
+};
+
+&dsi2dp_out {
+ remote-endpoint = <&dp_1_connector_in>;
+};
+
+/* Aquila ETH_1 */
+&enetc_port0 {
+ status = "okay";
+};
+
+/* Aquila CAN_1 */
+&flexcan1 {
+ status = "okay";
+};
+
+/* Aquila CAN_2 */
+&flexcan2 {
+ status = "okay";
+};
+
+/* Aquila CAN_3 */
+&flexcan3 {
+ status = "okay";
+};
+
+/* Aquila CAN_4 */
+&flexcan4 {
+ status = "okay";
+};
+
+/* Aquila QSPI_1 */
+&flexspi1 {
+ pinctrl-0 = <&pinctrl_flexspi1_4bit>,
+ <&pinctrl_qspi_cs1>;
+
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <66000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ };
+};
+
+&gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_8>;
+};
+
+&gpio4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_1>,
+ <&pinctrl_gpio_2>,
+ <&pinctrl_gpio_3>,
+ <&pinctrl_gpio_4>,
+ <&pinctrl_gpio_5>,
+ <&pinctrl_gpio_6>,
+ <&pinctrl_gpio_7>;
+};
+
+/* Aquila I2C_1 */
+&lpi2c2 {
+ status = "okay";
+
+ fan_controller: fan@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ #pwm-cells = <2>;
+
+ fan {
+ cooling-levels = <255>;
+ pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>;
+ };
+ };
+
+ wm8904_1a: audio-codec@1a {
+ compatible = "wlf,wm8904";
+ reg = <0x1a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2_mclk>;
+ clocks = <&scmi_clk IMX95_CLK_SAI2>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+ AVDD-supply = <®_carrier_1p8v>;
+ CPVDD-supply = <®_carrier_1p8v>;
+ DBVDD-supply = <®_carrier_1p8v>;
+ DCVDD-supply = <®_carrier_1p8v>;
+ MICVDD-supply = <®_carrier_1p8v>;
+ wlf,drc-cfg-names = "default", "peaklimiter";
+ /*
+ * Config registers per name, respectively:
+ * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
+ * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
+ */
+ wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
+ /bits/ 16 <0x04af 0x324b 0x0010 0x0408>;
+ /* GPIO1 = DMIC_CLK, don't touch others */
+ wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
+ wlf,in1r-as-dmicdat2;
+ };
+
+ /* Current measurement into module VCC */
+ hwmon@41 {
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+
+ temperature-sensor@4f {
+ compatible = "ti,tmp1075";
+ reg = <0x4f>;
+ };
+
+ /* USB-C OTG (TCPC USB PD PHY) */
+ tcpc@52 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x52>;
+ interrupt-parent = <&som_gpio_expander_1>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+
+ connector {
+ compatible = "usb-c-connector";
+ data-role = "dual";
+ op-sink-microwatt = <0>;
+ power-role = "dual";
+ self-powered;
+ sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ try-power-role = "sink";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ typec_con_hs: endpoint {
+ remote-endpoint = <&usb1_con_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ typec_con_ss: endpoint {
+ remote-endpoint = <&usb1_con_ss>;
+ };
+ };
+ };
+ };
+ };
+
+ carrier_eeprom: eeprom@57 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+/* Aquila I2C_2 */
+&i3c2 {
+ status = "okay";
+};
+
+/* Aquila I2C_4_CSI1 */
+&lpi2c4 {
+ status = "okay";
+};
+
+/* Aquila I2C_6 */
+&lpi2c5 {
+ status = "okay";
+};
+
+/* Aquila I2C_3_DSI1/I2C_5_CSI2 */
+&lpi2c8 {
+ status = "okay";
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9543";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* I2C on DSI Connector Pin #4 and #6 */
+ i2c_dsi_0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* I2C on DSI Connector Pin #52 and #54 */
+ i2c_dsi_1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+/* Aquila SPI_1 */
+&lpspi6 {
+ status = "okay";
+};
+
+/* Aquila UART_3, used as the Linux Console */
+&lpuart1 {
+ status = "okay";
+};
+
+/* Aquila UART_4 */
+&lpuart2 {
+ status = "okay";
+};
+
+/* Aquila UART_1 */
+&lpuart3 {
+ status = "okay";
+};
+
+/* Aquila UART_2 as RS485 */
+&lpuart7 {
+ linux,rs485-enabled-at-boot-time;
+ rs485-rts-active-low;
+ rs485-rx-during-tx;
+
+ status = "okay";
+};
+
+/* Aquila PCIE_1 */
+&pcie0 {
+ status = "okay";
+};
+
+/* Aquila I2S_1 */
+&sai2 {
+ status = "okay";
+};
+
+/* Aquila PWM_1 */
+&tpm3 {
+ status = "okay";
+};
+
+/* Aquila PWM_2 */
+&tpm6 {
+ status = "okay";
+};
+
+/* Aquila PWM_3_DSI and PWM_4_DP */
+&tpm5 {
+ status = "okay";
+};
+
+/* Aquila USB_2, optional Bluetooth USB */
+&usb2 {
+ status = "okay";
+};
+
+/* Aquila USB_1 */
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc3 {
+ status = "okay";
+
+ port {
+ usb1_con_hs: endpoint {
+ remote-endpoint = <&typec_con_hs>;
+ };
+ };
+};
+
+&usb3_phy {
+ orientation-switch;
+
+ status = "okay";
+
+ port {
+ usb1_con_ss: endpoint {
+ remote-endpoint = <&typec_con_ss>;
+ };
+ };
+};
+
+/* Aquila SD_1 */
+&usdhc2 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-aquila.dtsi b/arch/arm64/boot/dts/freescale/imx95-aquila.dtsi
new file mode 100644
index 0000000000000..69dc962a24a1d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-aquila.dtsi
@@ -0,0 +1,1160 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95
+ */
+
+#include <dt-bindings/net/ti-dp83867.h>
+#include "imx95.dtsi"
+
+/ {
+ aliases {
+ can0 = &flexcan1;
+ can1 = &flexcan2;
+ can2 = &flexcan3;
+ can3 = &flexcan4;
+ eeprom0 = &som_eeprom;
+ ethernet0 = &enetc_port0;
+ i2c0 = &lpi2c3;
+ i2c1 = &lpi2c2;
+ i2c2 = &i3c2;
+ i2c3 = &lpi2c8;
+ i2c4 = &lpi2c4;
+ i2c6 = &lpi2c5;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ rtc0 = &rtc_i2c;
+ rtc1 = &scmi_bbm;
+ serial0 = &lpuart3;
+ serial1 = &lpuart7;
+ serial2 = &lpuart1;
+ serial3 = &lpuart2;
+ usb0 = &usb3;
+ usb1 = &usb2;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ aquila_key_wake: gpio-key-wakeup {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_wake1_mico>;
+
+ status = "disabled";
+
+ key-wakeup {
+ /* Aquila CTRL_WAKE1_MICO# */
+ gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+ label = "Wake Up";
+ wakeup-source;
+ linux,code = <KEY_WAKEUP>;
+ };
+ };
+
+ clk_dsi2dp_refclk: clock-dsi2dp-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+
+ clk_dsi2dp_refclk_en: clock-dsi2dp-refclk-en {
+ compatible = "gpio-gate-clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_dp_clk_en>;
+ clocks = <&clk_dsi2dp_refclk>;
+ #clock-cells = <0>;
+ /* CTRL_DP_CLK_EN */
+ enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ clk_serdes_eth_ref: clock-serdes-eth-ref {
+ compatible = "gpio-gate-clock";
+ #clock-cells = <0>;
+ /* CTRL_ETH_REF_CLK_STBY */
+ enable-gpios = <&som_gpio_expander_0 6 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "On-module +V1.8";
+ };
+
+ reg_dp_1p2v: regulator-dp-1p2v {
+ compatible = "regulator-fixed";
+ /* CTRL_DP_BRIDGE_EN */
+ gpios = <&som_gpio_expander_0 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microvolt = <1200000>;
+ regulator-name = "On-module +V1.2_DP";
+ vin-supply = <®_1p8v>;
+ };
+
+ reg_usb1_vbus: regulator-usb1-vbus {
+ compatible = "regulator-fixed";
+ /* Aquila USB_1_EN */
+ gpios = <&som_gpio_expander_0 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-name = "USB_1_EN";
+ };
+
+ reg_usb2_vbus: regulator-usb2-vbus {
+ compatible = "regulator-fixed";
+ /* Aquila USB_2_EN */
+ gpios = <&som_gpio_expander_0 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-name = "USB_2_H_EN";
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sd1_pwr_en>;
+ /* Aquila SD_1_PWR_EN */
+ gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ off-on-delay-us = <100000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "SD_1_PWR_EN";
+ startup-delay-us = <20000>;
+ };
+
+ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
+ compatible = "regulator-gpio";
+ /* PMIC_SD_1_VSEL */
+ gpios = <&som_gpio_expander_1 9 GPIO_ACTIVE_HIGH>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "PMIC_SD_1_VSEL";
+ states = <1800000 0x1>,
+ <3300000 0x0>;
+ };
+
+ remoteproc-cm7 {
+ compatible = "fsl,imx95-cm7";
+ mboxes = <&mu7 0 1 &mu7 1 1 &mu7 3 1>;
+ mbox-names = "tx", "rx", "rxdb";
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux_cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0 0x3c000000>;
+ alloc-ranges = <0 0x80000000 0 0x7f000000>;
+ linux,cma-default;
+ };
+
+ m7_reserved: memory@80000000 {
+ reg = <0 0x80000000 0 0x1000000>;
+ no-map;
+ };
+
+ rsc_table: rsc-table@88220000 {
+ reg = <0 0x88220000 0 0x1000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@88000000 {
+ reg = <0 0x88000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@88008000 {
+ reg = <0 0x88008000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: vdev1vring0@88010000 {
+ reg = <0 0x88010000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: vdev1vring1@88018000 {
+ reg = <0 0x88018000 0 0x8000>;
+ no-map;
+ };
+
+ vdevbuffer: vdevbuffer@88020000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x88020000 0 0x100000>;
+ no-map;
+ };
+ };
+};
+
+/* Aquila ADC_[1-4] */
+&adc1 {
+ vref-supply = <®_1p8v>;
+};
+
+/* Aquila ETH_1 */
+&enetc_port0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enetc0>;
+ phy-handle = <ðphy1>;
+ phy-mode = "rgmii-id";
+};
+
+/* Aquila CAN_1 */
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+};
+
+/* Aquila CAN_2 */
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+};
+
+/* Aquila CAN_3 */
+&flexcan3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan3>;
+};
+
+/* Aquila CAN_4 */
+&flexcan4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan4>;
+};
+
+/* Aquila QSPI_1 */
+&flexspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi1_8bit>,
+ <&pinctrl_qspi_cs1>;
+};
+
+&gpio1 {
+ gpio-line-names = "", /* 0 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "AQUILA_C24", /* 10 */
+ "",
+ "AQUILA_B17",
+ "CTRL_GPIO_EXP_INT#",
+ "AQUILA_B18";
+
+ status = "okay";
+};
+
+&gpio2 {
+ gpio-line-names = "", /* 0 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "AQUILA_B42",
+ "",
+ "AQUILA_B43";
+};
+
+&gpio3 {
+ gpio-line-names = "", /* 0 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 10 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "AQUILA_A11",
+ "", /* 20 */
+ "AQUILA_B57",
+ "AQUILA_B19";
+};
+
+&gpio4 {
+ gpio-line-names = "", /* 0 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 10 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "AQUILA_C22",
+ "AQUILA_C21",
+ "AQUILA_C20",
+ "", /* 20 */
+ "",
+ "",
+ "AQUILA_C23",
+ "AQUILA_D23",
+ "AQUILA_D24",
+ "",
+ "AQUILA_D25";
+};
+
+&gpio5 {
+ gpio-line-names = "", /* 0 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 10 */
+ "",
+ "",
+ "AQUILA_B44",
+ "AQUILA_B45";
+};
+
+/* Aquila I2C_2 */
+&i3c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i3c2>;
+ i2c-scl-hz = <100000>;
+};
+
+/* Aquila I2C_1 */
+&lpi2c2 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ pinctrl-1 = <&pinctrl_lpi2c2_gpio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+/* On-module I2C - I2C_SOM */
+&lpi2c3 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_lpi2c3>, <&pinctrl_ctrl_gpio_exp_int>;
+ pinctrl-1 = <&pinctrl_lpi2c3_gpio>, <&pinctrl_ctrl_gpio_exp_int>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ status = "okay";
+
+ som_gpio_expander_0: gpio@20 {
+ compatible = "nxp,pcal6408";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names =
+ "AQUILA_C38", /* 0 */
+ "PCIE_2_RESET#",
+ "AQUILA_B77",
+ "USB_2_H_EN",
+ "BT_DISABLE#",
+ "WIFI_DISABLE#",
+ "CTRL_ETH_REF_CLK_STBY",
+ "CTRL_DP_BRIDGE_EN";
+ };
+
+ som_gpio_expander_1: gpio@21 {
+ compatible = "nxp,pcal6416";
+ reg = <0x21>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio1>;
+ interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names =
+ "AQUILA_C1", /* 0 */
+ "AQUILA_C2",
+ "AQUILA_C3",
+ "AQUILA_C4",
+ "AQUILA_C36",
+ "AQUILA_B74",
+ "AQUILA_B75",
+ "USB_2_H_OC#",
+ "AQUILA_B81",
+ "PMIC_SD_1_VSEL",
+ "ETH_1_INT#", /* 10 */
+ "CTRL_TPM_INT#",
+ "SPI_2_CS2_TPM",
+ "PCIE_WAKE_WIFI#",
+ "WIFI_WAKE_BT",
+ "WIFI_WAKEUP_HOST";
+ };
+
+ som_dsi2dp_bridge: bridge@2c {
+ compatible = "ti,sn65dsi86";
+ reg = <0x2c>;
+ clocks = <&clk_dsi2dp_refclk_en>;
+ clock-names = "refclk";
+ vcc-supply = <®_dp_1p2v>;
+ vcca-supply = <®_dp_1p2v>;
+ vccio-supply = <®_1p8v>;
+ vpll-supply = <®_1p8v>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dsi2dp_in: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ dsi2dp_out: endpoint {
+ data-lanes = <3 2 1 0>;
+ };
+ };
+ };
+ };
+
+ rtc_i2c: rtc@32 {
+ compatible = "epson,rx8130";
+ reg = <0x32>;
+ };
+
+ temperature-sensor@48 {
+ compatible = "ti,tmp1075";
+ reg = <0x48>;
+ };
+
+ som_eeprom: eeprom@50 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+/* Aquila I2C_4_CSI1 */
+&lpi2c4 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_lpi2c4>;
+ pinctrl-1 = <&pinctrl_lpi2c4_gpio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+/* Aquila I2C_6 */
+&lpi2c5 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_lpi2c5>;
+ pinctrl-1 = <&pinctrl_lpi2c5_gpio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+/* Aquila I2C_3_DSI1/I2C_5_CSI2 */
+&lpi2c8 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_lpi2c8>;
+ pinctrl-1 = <&pinctrl_lpi2c8_gpio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ scl-gpios = <&gpio2 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio2 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+/* Aquila SPI_2 */
+&lpspi4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi4>;
+ cs-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>,
+ <&som_gpio_expander_1 12 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+
+ som_tpm: tpm@1 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ interrupt-parent = <&som_gpio_expander_1>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ /*
+ * Maximum TPM-supported speed is 18.5 MHz, limited to 12 MHz
+ * here as lpspi4's per-clock (2x the max speed) is 24 MHz.
+ */
+ spi-max-frequency = <12000000>;
+ };
+};
+
+/* Aquila SPI_1 */
+&lpspi6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi6>;
+ cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+};
+
+/* Aquila UART_3, used as the Linux Console */
+&lpuart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+};
+
+/* Aquila UART_4 */
+&lpuart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+};
+
+/* Aquila UART_1 */
+&lpuart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ uart-has-rtscts;
+};
+
+/* Aquila UART_2 */
+&lpuart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart7>;
+ uart-has-rtscts;
+};
+
+&mu7 {
+ status = "okay";
+};
+
+/* Aquila ETH_2_XGMII_MDIO, shared between all ethernet ports */
+&netc_emdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emdio>;
+
+ status = "okay";
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ interrupt-parent = <&som_gpio_expander_1>;
+ interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ };
+};
+
+&netcmix_blk_ctrl {
+ status = "okay";
+};
+
+&netc_blk_ctrl {
+ status = "okay";
+};
+
+&netc_timer {
+ status = "okay";
+};
+
+/* Aquila PCIE_1 */
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpios = <&som_gpio_expander_0 0 GPIO_ACTIVE_LOW>;
+};
+
+/* On-module Wi-Fi or Aquila PCIE_2 */
+&pcie1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie1>;
+ reset-gpios = <&som_gpio_expander_0 1 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
+/* Aquila I2S_1 */
+&sai2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2>;
+ assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2>,
+ <&scmi_clk IMX95_CLK_SAI2>;
+ assigned-clock-parents = <0>, <0>, <0>, <0>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>;
+ assigned-clock-rates = <3932160000>,
+ <3612672000>, <393216000>,
+ <361267200>, <12288000>;
+ #sound-dai-cells = <0>;
+ fsl,sai-mclk-direction-output;
+};
+
+&scmi_bbm {
+ linux,code = <KEY_POWER>;
+};
+
+&thermal_zones {
+ /* PF09 Main PMIC */
+ pf09-thermal {
+ polling-delay = <2000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&scmi_sensor 2>;
+
+ trips {
+ trip0 {
+ hysteresis = <2000>;
+ temperature = <155000>;
+ type = "critical";
+ };
+ };
+ };
+
+ /* PF53 VDD_ARM PMIC */
+ pf53-arm-thermal {
+ polling-delay = <2000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&scmi_sensor 4>;
+
+ trips {
+ trip0 {
+ hysteresis = <2000>;
+ temperature = <155000>;
+ type = "critical";
+ };
+ };
+ };
+
+ /* PF53 VDD_SOC PMIC */
+ pf53-soc-thermal {
+ polling-delay = <2000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&scmi_sensor 3>;
+
+ trips {
+ trip0 {
+ hysteresis = <2000>;
+ temperature = <155000>;
+ type = "critical";
+ };
+ };
+ };
+};
+
+/* Aquila PWM_1 */
+&tpm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+};
+
+/* Aquila PWM_2 */
+&tpm6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+};
+
+/* Aquila PWM_3_DSI and PWM_4_DP */
+&tpm5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3_dsi>, <&pinctrl_pwm4_dp>;
+};
+
+/* Aquila USB_2, optional Bluetooth USB */
+&usb2 {
+ dr_mode = "host";
+ vbus-supply = <®_usb2_vbus>;
+};
+
+/* Aquila USB_1 */
+&usb3 {
+ fsl,disable-port-power-control;
+};
+
+&usb3_dwc3 {
+ dr_mode = "otg";
+ adp-disable;
+ hnp-disable;
+ srp-disable;
+ usb-role-switch;
+};
+
+&usb3_phy {
+ vbus-supply = <®_usb1_vbus>;
+};
+
+/* On-module eMMC */
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ no-sdio;
+ no-sd;
+
+ status = "okay";
+};
+
+/* Aquila SD_1 */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_sd1_cd_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_sd1_cd_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_sd1_cd_gpio>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_sd1_cd_gpio>;
+ cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ vqmmc-supply = <®_usdhc2_vqmmc>;
+};
+
+&wdog3 {
+ fsl,ext-reset-output;
+
+ status = "okay";
+};
+
+&scmi_iomuxc {
+ /* Aquila CTRL_WAKE1_MICO# */
+ pinctrl_ctrl_wake1_mico: ctrlwake1micogrp {
+ fsl,pins = <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x31e>; /* Aquila D6 */
+ };
+
+ pinctrl_ctrl_dp_clk_en: dpclkengrp {
+ fsl,pins = <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x11e>; /* CTRL_DP_CLK_EN */
+ };
+
+ /* Aquila ETH_2_XGMII_MDIO */
+ pinctrl_emdio: emdiogrp {
+ fsl,pins = <IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x57e>, /* Aquila B90 */
+ <IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e>; /* Aquila B89 */
+ };
+
+ /* Aquila ETH_1 */
+ pinctrl_enetc0: enetc0grp {
+ fsl,pins = <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e>, /* ENET1_TX_CTL */
+ <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e>, /* ENET1_TXC */
+ <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e>, /* ENET1_TDO */
+ <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e>, /* ENET1_TD1 */
+ <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e>, /* ENET1_TD2 */
+ <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e>, /* ENET1_TD3 */
+ <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e>, /* ENET1_RX_CTL */
+ <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e>, /* ENET1_RXC */
+ <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e>, /* ENET1_RD0 */
+ <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e>, /* ENET1_RD1 */
+ <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e>, /* ENET1_RD2 */
+ <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e>; /* ENET1_RD3 */
+ };
+
+ /* Aquila CAN_1 */
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e>, /* Aquila B48 */
+ <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e>; /* Aquila B49 */
+ };
+
+ /* Aquila CAN_2 */
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e>, /* Aquila B50 */
+ <IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e>; /* Aquila B51 */
+ };
+
+ /* Aquila CAN_3 */
+ pinctrl_flexcan3: flexcan3grp {
+ fsl,pins = <IMX95_PAD_CCM_CLKO3__CAN3_TX 0x39e>, /* Aquila B53 */
+ <IMX95_PAD_CCM_CLKO4__CAN3_RX 0x39e>; /* Aquila B54 */
+ };
+
+ /* Aquila CAN_4 */
+ pinctrl_flexcan4: flexcan4grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO04__CAN4_TX 0x39e>, /* Aquila B55 */
+ <IMX95_PAD_GPIO_IO05__CAN4_RX 0x39e>; /* Aquila B56 */
+ };
+
+ /* Aquila QSPI_1 (4 bit) */
+ pinctrl_flexspi1_4bit: flexspi14bitgrp {
+ fsl,pins = <IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe>, /* Aquila B65 */
+ <IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe>, /* Aquila B68 */
+ <IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe>, /* Aquila B67 */
+ <IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe>, /* Aquila B61 */
+ <IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe>, /* Aquila B60 */
+ <IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe>; /* Aquila B63 */
+ };
+
+ /* Aquila QSPI_1 (8 bit) */
+ pinctrl_flexspi1_8bit: flexspi18bitgrp {
+ fsl,pins = <IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe>, /* Aquila B65 */
+ <IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe>, /* Aquila B68 */
+ <IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe>, /* Aquila B67 */
+ <IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe>, /* Aquila B61 */
+ <IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe>, /* Aquila B60 */
+ <IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x3fe>, /* Aquila B70 */
+ <IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x3fe>, /* Aquila B71 */
+ <IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x3fe>, /* Aquila B72 */
+ <IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x3fe>, /* Aquila B73 */
+ <IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe>; /* Aquila B63 */
+ };
+
+ /* Aquila GPIO_01 */
+ pinctrl_gpio_1: gpio1grp {
+ fsl,pins = <IMX95_PAD_ENET2_RD0__GPIO4_IO_BIT24 0x31e>; /* Aquila D23 */
+ };
+
+ /* Aquila GPIO_02 */
+ pinctrl_gpio_2: gpio2grp {
+ fsl,pins = <IMX95_PAD_ENET2_RD1__GPIO4_IO_BIT25 0x31e>; /* Aquila D24 */
+ };
+
+ /* Aquila GPIO_03 */
+ pinctrl_gpio_3: gpio3grp {
+ fsl,pins = <IMX95_PAD_ENET2_RD3__GPIO4_IO_BIT27 0x31e>; /* Aquila D25 */
+ };
+
+ /* Aquila GPIO_04 */
+ pinctrl_gpio_4: gpio4grp {
+ fsl,pins = <IMX95_PAD_ENET2_TD0__GPIO4_IO_BIT19 0x31e>; /* Aquila C20 */
+ };
+
+ /* Aquila GPIO_05 */
+ pinctrl_gpio_5: gpio5grp {
+ fsl,pins = <IMX95_PAD_ENET2_TD1__GPIO4_IO_BIT18 0x31e>; /* Aquila C21 */
+ };
+
+ /* Aquila GPIO_06 */
+ pinctrl_gpio_6: gpio6grp {
+ fsl,pins = <IMX95_PAD_ENET2_TD2__GPIO4_IO_BIT17 0x31e>; /* Aquila C22 */
+ };
+
+ /* Aquila GPIO_07 */
+ pinctrl_gpio_7: gpio7grp {
+ fsl,pins = <IMX95_PAD_ENET2_RXC__GPIO4_IO_BIT23 0x31e>; /* Aquila C23 */
+ };
+
+ /* Aquila GPIO_08 */
+ pinctrl_gpio_8: gpio8grp {
+ fsl,pins = <IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x31e>; /* Aquila C24 */
+ };
+
+ /* Aquila GPIO_09_CSI_1 */
+ pinctrl_gpio_9_csi_1: gpio9csi1grp {
+ fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12 0x31e>; /* Aquila B17 */
+ };
+
+ /* Aquila GPIO_10_CSI_1 */
+ pinctrl_gpio_10_csi_1: gpio10csi1grp {
+ fsl,pins = <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x31e>; /* Aquila B18 */
+ };
+
+ /* Aquila GPIO_11_CSI_1 */
+ pinctrl_gpio_11_csi_1: gpio11csi1grp {
+ fsl,pins = <IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x31e>; /* Aquila A11*/
+ };
+
+ /* Aquila GPIO_12_CSI_1 */
+ pinctrl_gpio_12_csi_1: gpio12csi1grp {
+ fsl,pins = <IMX95_PAD_SD3_DATA0__GPIO3_IO_BIT22 0x31e>; /* Aquila B19 */
+ };
+
+ /* Aquila GPIO_17_DSI_1 */
+ pinctrl_gpio_17_dsi_1: gpio17dsi1grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7 0x31e>; /* Aquila B42 */
+ };
+
+ /* Aquila GPIO_18_DSI_1 */
+ pinctrl_gpio_18_dsi_1: gpio18dsi1grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9 0x31e>; /* Aquila B43 */
+ };
+
+ /* Aquila GPIO_19_DSI_1 */
+ pinctrl_gpio_19_dsi_1: gpio19dsi1grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e>; /* Aquila B44 */
+ };
+
+ /* Aquila GPIO_20_DSI_1 */
+ pinctrl_gpio_20_dsi_1: gpio20dsi1grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e>; /* Aquila B45 */
+ };
+
+ /* Aquila GPIO_21_DP */
+ pinctrl_gpio_21_dp: gpio21dpgrp {
+ fsl,pins = <IMX95_PAD_SD3_CMD__GPIO3_IO_BIT21 0x31e>; /* Aquila B57 */
+ };
+
+ pinctrl_ctrl_gpio_exp_int: gpioexpintgrp {
+ fsl,pins = <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x31e>; /* CTRL_GPIO_EXP_INT# */
+ };
+
+ /* Aquila I2C_2 */
+ pinctrl_i3c2: i3c2cgrp {
+ fsl,pins = <IMX95_PAD_ENET1_MDC__I3C2_SCL 0x40001186>, /* Aquila C17 */
+ <IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x40001186>; /* Aquila C16 */
+ };
+
+ /* Aquila I2C_1 as GPIOs */
+ pinctrl_lpi2c2_gpio: lpi2c2gpiogrp {
+ fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x40001b9e>, /* Aquila D8 */
+ <IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x40001b9e>; /* Aquila D7 */
+ };
+
+ /* Aquila I2C_1 */
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40001b9e>, /* Aquila D8 */
+ <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40001b9e>; /* Aquila D7 */
+ };
+
+ /* On-module I2C as GPIOs */
+ pinctrl_lpi2c3_gpio: lpi2c3gpiogrp {
+ fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x40001b9e>, /* I2C_SOM_SDA */
+ <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x40001b9e>; /* I2C_SOM_SCL */
+ };
+
+ /* On-module I2C */
+ pinctrl_lpi2c3: lpi2c3grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40001b9e>, /* I2C_SOM_SDA */
+ <IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40001b9e>; /* I2C_SOM_SCL */
+ };
+
+ /* Aquila I2C_4_CSI1 as GPIO */
+ pinctrl_lpi2c4_gpio: lpi2c4gpiogrp {
+ fsl,pins = <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x40001b9e>, /* Aquila A12 */
+ <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x40001b9e>; /* Aquila A13 */
+ };
+
+ /* Aquila I2C_4_CSI1 */
+ pinctrl_lpi2c4: lpi2c4grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40001b9e>, /* Aquila A12 */
+ <IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40001b9e>; /* Aquila A13 */
+ };
+
+ /* Aquila I2C_6 as GPIO */
+ pinctrl_lpi2c5_gpio: lpi2c5gpiogrp {
+ fsl,pins = <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x40001b9e>, /* Aquila C18 */
+ <IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x40001b9e>; /* Aquila C19 */
+ };
+
+ /* Aquila I2C_6 */
+ pinctrl_lpi2c5: lpi2c5grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40001b9e>, /* Aquila C18 */
+ <IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40001b9e>; /* Aquila C19 */
+ };
+
+ /* Aquila I2C_3_DSI1/I2C_5_CSI2 as GPIO */
+ pinctrl_lpi2c8_gpio: lpi2c8gpiogrp {
+ fsl,pins = <IMX95_PAD_GPIO_IO12__GPIO2_IO_BIT12 0x40001b9e>, /* Aquila C5/B40 */
+ <IMX95_PAD_GPIO_IO13__GPIO2_IO_BIT13 0x40001b9e>; /* Aquila C6/B41 */
+ };
+
+ /* Aquila I2C_3_DSI1/I2C_5_CSI2 */
+ pinctrl_lpi2c8: lpi2c8grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO12__LPI2C8_SDA 0x40001b9e>, /* Aquila C5/B40 */
+ <IMX95_PAD_GPIO_IO13__LPI2C8_SCL 0x40001b9e>; /* Aquila C6/B41 */
+ };
+
+ /* Aquila SPI_2 */
+ pinctrl_lpspi4: lpspi4grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x3fe>, /* Aquila D16 */
+ <IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x3fe>, /* Aquila D15 */
+ <IMX95_PAD_GPIO_IO20__LPSPI4_SOUT 0x3fe>, /* Aquila D17 */
+ <IMX95_PAD_GPIO_IO21__LPSPI4_SCK 0x3fe>; /* Aquila D14 */
+ };
+
+ /* Aquila SPI_1 */
+ pinctrl_lpspi6: lpspi6grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x3fe>, /* Aquila D9 */
+ <IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe>, /* Aquila D10 */
+ <IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe>, /* Aquila D11 */
+ <IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe>; /* Aquila D12 */
+ };
+
+ /* Aquila PCIE_1 */
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40001b1e>; /* Aquila C37 */
+ };
+
+ /* Aquila PCIE_2 */
+ pinctrl_pcie1: pcie1grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x40001b1e>; /* Aquila C34 */
+ };
+
+ /* Aquila QSPI_1_CS1# */
+ pinctrl_qspi_cs1: qspics1grp {
+ fsl,pins = <IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe>; /* Aquila B66 */
+ };
+
+ /* Aquila QSPI_1_CS2# as GPIO */
+ pinctrl_qspi_cs2_gpio: qspics2gpiogrp {
+ fsl,pins = <IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x3fe>; /* Aquila B62 */
+ };
+
+ /* Aquila I2S_1 */
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x11e>, /* Aquila B21 */
+ <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x11e>, /* Aquila B20 */
+ <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x11e>, /* Aquila B23 */
+ <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x11e>; /* Aquila B22 */
+ };
+
+ pinctrl_sai2_mclk: sai2mclkgrp {
+ fsl,pins = <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e>; /* Aquila B24 */
+ };
+
+ /* Aquila SD_1_CD# as GPIO */
+ pinctrl_sd1_cd_gpio: sd1cdgpiogrp {
+ fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>; /* Aquila A1 */
+ };
+
+ /* Aquila SD_1_PWR_EN */
+ pinctrl_sd1_pwr_en: sd1pwrengpiogrp {
+ fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>; /* Aquila A6 */
+ };
+
+ /* Aquila PWM_1 */
+ pinctrl_pwm1: tpm3ch3grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO24__TPM3_CH3 0x11e>; /* Aquila C25 */
+ };
+
+ /* Aquila PWM_3_DSI as GPIO */
+ pinctrl_pwm3_dsi_gpio: tpm5ch0gpiogrp {
+ fsl,pins = <IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x11e>; /* Aquila B46 */
+ };
+
+ /* Aquila PWM_3_DSI */
+ pinctrl_pwm3_dsi: tpm5ch0grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0 0x11e>; /* Aquila B46 */
+ };
+
+ /* Aquila PWM_4_DP */
+ pinctrl_pwm4_dp: tpm5ch3grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO26__TPM5_CH3 0x11e>; /* Aquila B58 */
+ };
+
+ /* Aquila PWM_2 */
+ pinctrl_pwm2: tpm6ch0grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO08__TPM6_CH0 0x11e>; /* Aquila C26 */
+ };
+
+ /* Aquila UART_3 */
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>, /* Aquila D20 */
+ <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e>; /* Aquila D19 */
+ };
+
+ /* Aquila UART_4 */
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e>, /* Aquila D22 */
+ <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x31e>; /* Aquila D21 */
+ };
+
+ /* Aquila UART_1 */
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO14__LPUART3_TX 0x31e>, /* Aquila B37 */
+ <IMX95_PAD_GPIO_IO15__LPUART3_RX 0x31e>, /* Aquila B35 */
+ <IMX95_PAD_GPIO_IO16__LPUART3_CTS_B 0x31e>, /* Aquila B36 */
+ <IMX95_PAD_GPIO_IO17__LPUART3_RTS_B 0x31e>; /* Aquila B38 */
+ };
+
+ /* Aquila UART_2 */
+ pinctrl_uart7: uart7grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO36__LPUART7_TX 0x31e>, /* Aquila B33 */
+ <IMX95_PAD_GPIO_IO37__LPUART7_RX 0x31e>, /* Aquila B31 */
+ <IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e>, /* Aquila B32 */
+ <IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e>; /* Aquila B34 */
+ };
+
+ /* On-module eMMC */
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, /* eMMC_CLK */
+ <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, /* eMMC_CMD */
+ <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, /* eMMC_DATA0 */
+ <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, /* eMMC_DATA1 */
+ <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, /* eMMC_DATA2 */
+ <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, /* eMMC_DATA3 */
+ <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, /* eMMC_DATA4 */
+ <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, /* eMMC_DATA5 */
+ <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, /* eMMC_DATA6 */
+ <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, /* eMMC_DATA7 */
+ <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; /* eMMC_STROBE */
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>, /* eMMC_CLK */
+ <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>, /* eMMC_CMD */
+ <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>, /* eMMC_DATA0 */
+ <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>, /* eMMC_DATA1 */
+ <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>, /* eMMC_DATA2 */
+ <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>, /* eMMC_DATA3 */
+ <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>, /* eMMC_DATA4 */
+ <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>, /* eMMC_DATA5 */
+ <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>, /* eMMC_DATA6 */
+ <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>, /* eMMC_DATA7 */
+ <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>; /* eMMC_STROBE */
+ };
+
+ /* Aquila SD_1 */
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>, /* Aquila A5 */
+ <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>, /* Aquila A7 */
+ <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, /* Aquila A3 */
+ <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, /* Aquila A2 */
+ <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, /* Aquila A10 */
+ <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>; /* Aquila A8 */
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>, /* Aquila A5 */
+ <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>, /* Aquila A7 */
+ <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>, /* Aquila A3 */
+ <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>, /* Aquila A2 */
+ <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>, /* Aquila A10 */
+ <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>; /* Aquila A8 */
+ };
+
+ pinctrl_usdhc2_sleep: usdhc2-sleepgrp {
+ fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x400>, /* Aquila A5 */
+ <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x400>, /* Aquila A7 */
+ <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x400>, /* Aquila A3 */
+ <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x400>, /* Aquila A2 */
+ <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x400>, /* Aquila A10 */
+ <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x400>; /* Aquila A8 */
+ };
+};
--
2.43.0
^ permalink raw reply related
* [PATCH v4 1/3] dt-bindings: arm: fsl: add Aquila iMX95
From: Franz Schnyder @ 2026-05-21 17:11 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, linux-kernel, imx, linux-arm-kernel,
Francesco Dolcini, Franz Schnyder, Conor Dooley
In-Reply-To: <20260521-add-aquila-imx95-v4-0-5a7f86c824f5@toradex.com>
From: Franz Schnyder <franz.schnyder@toradex.com>
Add DT compatible strings for the Aquila i.MX95 SoM and its supported
carrier boards: the Aquila Development Board and the Clover carrier
board.
Link: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95
Link: https://www.toradex.com/products/carrier-board/aquila-development-board-kit
Link: https://www.toradex.com/products/carrier-board/clover
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Franz Schnyder <franz.schnyder@toradex.com>
---
v4: No changes
v3: No changes
v2: Added Conor's acked-by
v1: https://lore.kernel.org/all/20260506-add-aquila-imx95-v1-1-69c8ee1c5413@toradex.com/
---
Documentation/devicetree/bindings/arm/fsl.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 59f7f168bf7c4..ea4cc98dadebc 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1507,6 +1507,14 @@ properties:
- const: phytec,imx95-phycore-fpsc # phyCORE-i.MX 95 FPSC
- const: fsl,imx95
+ - description: Toradex Boards with Aquila iMX95 Modules
+ items:
+ - enum:
+ - toradex,aquila-imx95-clover # Aquila iMX95 Module on Clover Board
+ - toradex,aquila-imx95-dev # Aquila iMX95 Module on Aquila Development Board
+ - const: toradex,aquila-imx95 # Aquila iMX95 Module
+ - const: fsl,imx95
+
- description: Toradex Boards with SMARC iMX95 Modules
items:
- const: toradex,smarc-imx95-dev # Toradex SMARC iMX95 on Toradex SMARC Development Board
--
2.43.0
^ permalink raw reply related
* [PATCH v4 0/3] arm64: dts: freescale: add Toradex Aquila iMX95
From: Franz Schnyder @ 2026-05-21 17:11 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, linux-kernel, imx, linux-arm-kernel,
Francesco Dolcini, Franz Schnyder, Conor Dooley,
João Paulo Gonçalves, Emanuele Ghidoli,
Francesco Dolcini, Antoine Gouby, Ernest Van Hoecke
This patch series adds support for the Toradex Aquila i.MX95 SoM and its
currently available carrier boards: the Aquila Development Board and the
Clover carrier board.
The module consists of an NXP i.MX95 family SoC, up to 16GB LPDDR5 RAM,
up to 128GB of storage, a USB 3.2 OTG and USB 2.0 Host, a Gigabit
Ethernet PHY, a 10 Gigabit Ethernet interface, an I2C EEPROM and
Temperature Sensor, an RX8130 RTC, one Quad lane CSI interface, one Quad
lane DSI or CSI interface, one LVDS interface (one or two channels), and
some optional addons: DisplayPort (through a DSI-DP bridge), TPM 2.0,
and a WiFi/BT module.
Link: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95
Link: https://www.toradex.com/products/carrier-board/aquila-development-board-kit
Link: https://www.toradex.com/products/carrier-board/clover
Signed-off-by: Franz Schnyder <franz.schnyder@toradex.com>
---
Changes in v4:
- Removed som_dsi2dp_bridge node from dev and clover board
since SoC's DSI controller is unsupported
- Link to v3: https://patch.msgid.link/20260521-add-aquila-imx95-v3-0-621843807def@toradex.com
Changes in v3:
- Changed QSPI_1 4bit iomux node name to 'flexspi14bitgrp'
- Deleted the cdns,* properties from flexspi1
- Link to v2: https://patch.msgid.link/20260520-add-aquila-imx95-v2-0-06424a51e33a@toradex.com
Changes in v2:
- Add 'acked-by' tag from Conor to the bindings patch
- Reordering iomux by node name
- Changed Francesco's tags to have the Toradex mail address
- Link to v1: https://lore.kernel.org/r/20260506-add-aquila-imx95-v1-0-69c8ee1c5413@toradex.com
---
Antoine Gouby (1):
arm64: dts: freescale: imx95-aquila: Add Clover carrier board
Franz Schnyder (1):
dt-bindings: arm: fsl: add Aquila iMX95
João Paulo Gonçalves (1):
arm64: dts: freescale: add Aquila iMX95 support
Documentation/devicetree/bindings/arm/fsl.yaml | 8 +
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../boot/dts/freescale/imx95-aquila-clover.dts | 285 +++++
arch/arm64/boot/dts/freescale/imx95-aquila-dev.dts | 389 +++++++
arch/arm64/boot/dts/freescale/imx95-aquila.dtsi | 1160 ++++++++++++++++++++
5 files changed, 1844 insertions(+)
---
base-commit: 596d0f9f4fefffbf783ab26cfa90cf50f5dd6bb0
change-id: 20260501-add-aquila-imx95-423256af3d21
Best regards,
--
Franz Schnyder <franz.schnyder@toradex.com>
^ permalink raw reply
* [PATCH v2] dt-bindings: clock: via,vt8500: Convert to DT Schema
From: Udaya Kiran Challa @ 2026-05-21 17:07 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt
Cc: skhan, me, linux-rtc, devicetree, linux-kernel,
Udaya Kiran Challa
Convert the VIA/Wondermedia VT8500 and Wondermedia WM8xxx series SoCs clock
controller binding from the legacy text format to DT schema.
Signed-off-by: Udaya Kiran Challa <challauday369@gmail.com>
---
Changelog:
Changes since v1:
- Add default value for divisor-mask
- Add required properties compatible and model
- Fix example node name
- Update example size cells and reg value
Link to v1:https://lore.kernel.org/all/20260520025131.17772-1-challauday369@gmail.com/
---
.../bindings/clock/via,vt8500-clock.yaml | 126 ++++++++++++++++++
.../devicetree/bindings/clock/vt8500.txt | 74 ----------
2 files changed, 126 insertions(+), 74 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/via,vt8500-clock.yaml
delete mode 100644 Documentation/devicetree/bindings/clock/vt8500.txt
diff --git a/Documentation/devicetree/bindings/clock/via,vt8500-clock.yaml b/Documentation/devicetree/bindings/clock/via,vt8500-clock.yaml
new file mode 100644
index 000000000000..9e19103866bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/via,vt8500-clock.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/via,vt8500-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: VIA/Wondermedia VT8500 Clock Controller
+
+maintainers:
+ - Michael Turquette <mturquette@baylibre.com>
+ - Stephen Boyd <sboyd@kernel.org>
+
+description: |
+ Clock controller bindings for VIA/Wondermedia VT8500 and Wondermedia WM8xxx
+ series SoCs.
+
+properties:
+ compatible:
+ enum:
+ - via,vt8500-pll-clock
+ - wm,wm8650-pll-clock
+ - wm,wm8750-pll-clock
+ - wm,wm8850-pll-clock
+ - via,vt8500-device-clock
+
+ reg:
+ maxItems: 1
+ description:
+ Offset of the PLL register within the PMC register space.
+
+ clocks:
+ maxItems: 1
+ description:
+ Parent reference clock.
+
+ "#clock-cells":
+ const: 0
+
+ enable-reg:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Offset of the clock enable register within the PMC register space.
+
+ enable-bit:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 31
+ description:
+ Bit index controlling clock enable.
+
+ divisor-reg:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Offset of the clock divisor register within the PMC register space.
+
+ divisor-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0x1f
+ description:
+ Bitmask describing the divisor field inside divisor-reg.
+
+required:
+ - compatible
+ - "#clock-cells"
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - via,vt8500-pll-clock
+ - wm,wm8650-pll-clock
+ - wm,wm8750-pll-clock
+ - wm,wm8850-pll-clock
+ then:
+ required:
+ - reg
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ const: via,vt8500-device-clock
+ then:
+ required:
+ - clocks
+ anyOf:
+ - required:
+ - enable-reg
+ - enable-bit
+ - required:
+ - divisor-reg
+
+additionalProperties: false
+
+examples:
+ - |
+ / {
+ compatible = "via,wm8650";
+ model = "Wondermedia WM8650";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ref25: clock-25000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ plla: clock@200 {
+ compatible = "wm,wm8650-pll-clock";
+ reg = <0x200 0x04>;
+ clocks = <&ref25>;
+ #clock-cells = <0>;
+ };
+
+ clksdhc: clock {
+ compatible = "via,vt8500-device-clock";
+ clocks = <&plla>;
+ divisor-reg = <0x328>;
+ divisor-mask = <0x3f>;
+ enable-reg = <0x254>;
+ enable-bit = <18>;
+ #clock-cells = <0>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/clock/vt8500.txt b/Documentation/devicetree/bindings/clock/vt8500.txt
deleted file mode 100644
index 91d71cc0314a..000000000000
--- a/Documentation/devicetree/bindings/clock/vt8500.txt
+++ /dev/null
@@ -1,74 +0,0 @@
-Device Tree Clock bindings for arch-vt8500
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible : shall be one of the following:
- "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
- "wm,wm8650-pll-clock" - for a WM8650 PLL clock
- "wm,wm8750-pll-clock" - for a WM8750 PLL clock
- "wm,wm8850-pll-clock" - for a WM8850 PLL clock
- "via,vt8500-device-clock" - for a VT/WM device clock
-
-Required properties for PLL clocks:
-- reg : shall be the control register offset from PMC base for the pll clock.
-- clocks : shall be the input parent clock phandle for the clock. This should
- be the reference clock.
-- #clock-cells : from common clock binding; shall be set to 0.
-
-Required properties for device clocks:
-- clocks : shall be the input parent clock phandle for the clock. This should
- be a pll output.
-- #clock-cells : from common clock binding; shall be set to 0.
-
-
-Device Clocks
-
-Device clocks are required to have one or both of the following sets of
-properties:
-
-
-Gated device clocks:
-
-Required properties:
-- enable-reg : shall be the register offset from PMC base for the enable
- register.
-- enable-bit : shall be the bit within enable-reg to enable/disable the clock.
-
-
-Divisor device clocks:
-
-Required property:
-- divisor-reg : shall be the register offset from PMC base for the divisor
- register.
-Optional property:
-- divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
- if not specified.
-
-
-For example:
-
-ref25: ref25M {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <25000000>;
-};
-
-plla: plla {
- #clock-cells = <0>;
- compatible = "wm,wm8650-pll-clock";
- clocks = <&ref25>;
- reg = <0x200>;
-};
-
-sdhc: sdhc {
- #clock-cells = <0>;
- compatible = "via,vt8500-device-clock";
- clocks = <&pllb>;
- divisor-reg = <0x328>;
- divisor-mask = <0x3f>;
- enable-reg = <0x254>;
- enable-bit = <18>;
-};
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v1 13/15] dt-bindings: display: panel-lvds: Add dual-channel LVDS support
From: Conor Dooley @ 2026-05-21 16:59 UTC (permalink / raw)
To: Vitor Soares
Cc: Laurent Pinchart, Neil Armstrong, Jessica Zhang,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Lad Prabhakar,
Thierry Reding, Sam Ravnborg, Vitor Soares, dri-devel, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <20260521150038.103538-30-ivitro@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1362 bytes --]
On Thu, May 21, 2026 at 04:00:49PM +0100, Vitor Soares wrote:
> From: Vitor Soares <vitor.soares@toradex.com>
>
> The panel-lvds binding only supports single-channel panels.
> Extend it to support dual-channel LVDS panels by referencing the
> lvds-dual-ports schema when a ports container is present.
>
> Assisted-by: Claude:claude-sonnet-4.6
> Signed-off-by: Vitor Soares <vitor.soares@toradex.com>
Ah, this is part of what sashiko was talking about I guess.
nvm that email so.
Why can't your new device go into panel-simple-lvds-dual-ports?
> ---
> .../bindings/display/panel/panel-lvds.yaml | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml b/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml
> index 7ed0c486870b..45183a1439ce 100644
> --- a/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml
> +++ b/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml
> @@ -82,6 +82,17 @@ required:
> - width-mm
> - height-mm
> - panel-timing
> - - port
> +
> +oneOf:
> + - required:
> + - port
> + - required:
> + - ports
> +
> +if:
> + required:
> + - ports
> +then:
> + $ref: /schemas/display/lvds-dual-ports.yaml#
>
> ...
> --
> 2.54.0
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v1 05/15] dt-bindings: display: panel-lvds: Add Riverdi RVT70HSLNWCA0 and RVT101HVLNWC00
From: Conor Dooley @ 2026-05-21 16:57 UTC (permalink / raw)
To: Vitor Soares
Cc: Laurent Pinchart, Neil Armstrong, Jessica Zhang,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Lad Prabhakar,
Thierry Reding, Sam Ravnborg, Vitor Soares, dri-devel, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <20260521150038.103538-22-ivitro@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 75 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
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