[PATCH V3 2/3] dt-binding: i2c: nvidia,tegra20-i2c: Add register-setting support

[Rajesh Gumasta <rgumasta@nvidia.com>]

Add register setting support for the NVIDIA Tegra20 I2C controllers. An
i2c-controller-common.yaml binding document has been added a top-level
binding document so that all I2C controllers can use this binding. This
new binding document defines some generic register setting properties
for I2C and some standard I2C operating modes that the register settings
need to be programmed for. This new binding document is used by the
NVIDIA Tegra20 I2C binding to enable the use of the 'reg-settings'
binding for this device.

Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
---
 .../bindings/i2c/i2c-controller-common.yaml   | 73 +++++++++++++++++++
 .../bindings/i2c/nvidia,tegra20-i2c.yaml      | 64 +++++++++++++++-
 2 files changed, 134 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-controller-common.yaml

diff --git a/Documentation/devicetree/bindings/i2c/i2c-controller-common.yaml b/Documentation/devicetree/bindings/i2c/i2c-controller-common.yaml
new file mode 100644
index 000000000000..3b5b75d4b98a
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-controller-common.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-controller-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: I2C Controller Common Properties
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Krishna Yarlagadda <kyarlagadda@nvidia.com>
+  - Rajesh Gumasta <rgumasta@nvidia.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+description:
+  These properties are common to multiple I2C controllers.
+
+definitions:
+  reg-settings:
+    properties:
+      scl-low-period-cycles:
+        $ref: /schemas/types.yaml#/definitions/uint8
+        description: Low period of the SCL clock in parent clock cycles.
+      scl-high-period-cycles:
+        $ref: /schemas/types.yaml#/definitions/uint8
+        description: High period of the SCL clock in parent clock cycles.
+      bus-free-time-cycles:
+        $ref: /schemas/types.yaml#/definitions/uint8
+        description: Bus free time between STOP and START conditions in parent
+          clock cycles.
+      start-setup-time-cycles:
+        $ref: /schemas/types.yaml#/definitions/uint8
+        description: Set-up time for START condition in parent clock cycles.
+      stop-setup-time-cycles:
+        $ref: /schemas/types.yaml#/definitions/uint8
+        description: Set-up time for STOP condition in parent clock cycles.
+      start-hold-time-cycles:
+        $ref: /schemas/types.yaml#/definitions/uint8
+        description: Hold time for STOP condition in parent clock cycles.
+
+properties:
+  reg-settings:
+    $ref: /schemas/regset/register-settings.yaml
+
+    properties:
+      default-setting:
+        type: object
+        $ref: "#/definitions/reg-settings"
+        description:
+          Default register settings.
+
+      fast:
+        type: object
+        $ref: "#/definitions/reg-settings"
+        description:
+          Register settings for I2C fast operating mode.
+
+      fastplus:
+        type: object
+        $ref: "#/definitions/reg-settings"
+        description:
+          Register settings for I2C fastplus operating mode.
+
+      standard:
+        type: object
+        $ref: "#/definitions/reg-settings"
+        description:
+          Register settings for I2C standard operating mode.
+
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
index 6b6f6762d122..695ce5ada7d5 100644
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
@@ -119,6 +119,28 @@ properties:
       - const: rx
       - const: tx
 
+  reg-settings:
+    $ref: /schemas/i2c/i2c-controller-common.yaml#/properties/reg-settings
+
+    properties:
+      default-setting:
+        $ref: /schemas/i2c/i2c-controller-common.yaml#/definitions/reg-settings
+        unevaluatedProperties: false
+
+      fast:
+        $ref: /schemas/i2c/i2c-controller-common.yaml#/definitions/reg-settings
+        unevaluatedProperties: false
+
+      fastplus:
+        $ref: /schemas/i2c/i2c-controller-common.yaml#/definitions/reg-settings
+        unevaluatedProperties: false
+
+      standard:
+        $ref: /schemas/i2c/i2c-controller-common.yaml#/definitions/reg-settings
+        unevaluatedProperties: false
+
+    unevaluatedProperties: false
+
 required:
   - compatible
   - reg
@@ -127,7 +149,7 @@ required:
   - clock-names
 
 allOf:
-  - $ref: /schemas/i2c/i2c-controller.yaml
+  - $ref: /schemas/i2c/i2c-controller-common.yaml
   - if:
       properties:
         compatible:
@@ -206,6 +228,42 @@ examples:
         dmas = <&apbdma 16>, <&apbdma 16>;
         dma-names = "rx", "tx";
 
-        #address-cells = <1>;
-        #size-cells = <0>;
+        i2c-bus {
+            #address-cells = <1>;
+            #size-cells = <0>;
+        };
+
+        reg-settings {
+            default-setting {
+                scl-high-period-cycles = /bits/ 8 <3>;
+                scl-low-period-cycles = /bits/ 8 <8>;
+            };
+
+            fast {
+                scl-high-period-cycles = /bits/ 8 <2>;
+                scl-low-period-cycles = /bits/ 8 <2>;
+                bus-free-time-cycles = /bits/ 8 <2>;
+                stop-setup-time-cycles = /bits/ 8 <2>;
+                start-hold-time-cycles = /bits/ 8 <2>;
+                start-setup-time-cycles = /bits/ 8 <2>;
+            };
+
+            fastplus {
+                scl-high-period-cycles = /bits/ 8 <2>;
+                scl-low-period-cycles = /bits/ 8 <2>;
+                bus-free-time-cycles = /bits/ 8 <2>;
+                stop-setup-time-cycles = /bits/ 8 <2>;
+                start-hold-time-cycles = /bits/ 8 <2>;
+                start-setup-time-cycles = /bits/ 8 <2>;
+            };
+
+            standard {
+                scl-high-period-cycles = /bits/ 8 <7>;
+                scl-low-period-cycles = /bits/ 8 <8>;
+                bus-free-time-cycles = /bits/ 8 <8>;
+                stop-setup-time-cycles = /bits/ 8 <8>;
+                start-hold-time-cycles = /bits/ 8 <8>;
+                start-setup-time-cycles = /bits/ 8 <8>;
+            };
+        };
     };
-- 
2.50.1