Re: [PATCH v2 01/11] media: ccs-pll: Start OP pre-PLL multiplier search from correct value

[Laurent Pinchart <laurent.pinchart@ideasonboard.com>]

Hi Sakari,

Thank you for the patch.

On Thu, Apr 17, 2025 at 09:53:44AM +0300, Sakari Ailus wrote:
> The ccs_pll_calculate() function does a search over possible PLL
> configurations to find the "best" one. If the sensor did not support odd

s/did not/does not/

> pre-PLL divisors and the minimum value (with constraints) wasn't 1, other

s/wasn't/isn't/

> even values could have errorneously searched (and selected) for the

s/could have errorneously searched/
s/could be erroneously searched/

Do you mean "other odd values" ?

> pre-PLL divisor. Fix this.
> 
> Fixes: 415ddd993978 ("media: ccs-pll: Split limits and PLL configuration into front and back parts")
> Cc: stable@vger.kernel.org
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> ---
>  drivers/media/i2c/ccs-pll.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
> index 34ccda666524..e516ed23e899 100644
> --- a/drivers/media/i2c/ccs-pll.c
> +++ b/drivers/media/i2c/ccs-pll.c
> @@ -815,6 +815,8 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
>  			      one_or_more(
>  				      DIV_ROUND_UP(op_lim_fr->max_pll_op_clk_freq_hz,
>  						   pll->ext_clk_freq_hz))));
> +	if (!(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER))
> +		min_op_pre_pll_clk_div = clk_div_even(min_op_pre_pll_clk_div);
>  	dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n",
>  		min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);
>  

Is my understanding correct that the problem can only occur during the
first iteration of the loop just below ? If so, with the commit message
fixed,

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

If not, there's something I don't get :-)

-- 
Regards,

Laurent Pinchart