From: Sakari Ailus <sakari.ailus@linux.intel.com>
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-media@vger.kernel.org, dongcheng.yan@intel.com
Subject: Re: [PATCH v2 08/11] media: ccs-pll: Add a flag for even PLL multipliers
Date: Wed, 23 Apr 2025 10:19:46 +0000 [thread overview]
Message-ID: <aAi-wiwZrmLiXUlR@kekkonen.localdomain> (raw)
In-Reply-To: <20250421201924.GI17813@pendragon.ideasonboard.com>
Hi Laurent,
On Mon, Apr 21, 2025 at 11:19:24PM +0300, Laurent Pinchart wrote:
> Hi Sakari,
>
> Thank you for the patch.
Thank you for the review!
>
> On Thu, Apr 17, 2025 at 09:53:51AM +0300, Sakari Ailus wrote:
> > Some devices (not entirely CCS compliant) only support even PLL
> > multipliers. Add support for this through a PLL flag.
> >
> > Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> > ---
> > drivers/media/i2c/ccs-pll.c | 11 ++++++++++-
> > drivers/media/i2c/ccs-pll.h | 1 +
> > 2 files changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
> > index ebbc5e323244..3f8153fb4af0 100644
> > --- a/drivers/media/i2c/ccs-pll.c
> > +++ b/drivers/media/i2c/ccs-pll.c
> > @@ -124,9 +124,10 @@ static void print_pll(struct device *dev, const struct ccs_pll *pll)
> > dev_dbg(dev, "pixel rate on CSI-2 bus:\t%u\n",
> > pll->pixel_rate_csi);
> >
> > - dev_dbg(dev, "flags%s%s%s%s%s%s%s%s%s%s\n",
> > + dev_dbg(dev, "flags%s%s%s%s%s%s%s%s%s%s%s\n",
> > pll->flags & PLL_FL(OP_PIX_CLOCK_PER_LANE) ? " op-pix-clock-per-lane" : "",
> > pll->flags & PLL_FL(NO_OP_CLOCKS) ? " no-op-clocks" : "",
> > + pll->flags & PLL_FL(EVEN_PLL_MULTIPLIER) ? " even-pll-multiplier" : "",
> > pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "",
> > pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ?
> > " ext-ip-pll-divider" : "",
> > @@ -312,6 +313,10 @@ __ccs_pll_calculate_vt_tree(struct device *dev,
> > more_mul *= DIV_ROUND_UP(lim_fr->min_pll_multiplier, mul * more_mul);
> > dev_dbg(dev, "more_mul2: %u\n", more_mul);
> >
> > + if (pll->flags & CCS_PLL_FLAG_EVEN_PLL_MULTIPLIER &&
> > + mul & 1 && more_mul & 1)
>
> Even if not mandated by the C standard, I'd write
>
> (mul & 1) && (more_mul & 1))
>
> to make the code easier to read.
I'll address this in v3.
>
> > + more_mul <<= 1;
>
> I'm not sure to get the logic behind this :-/
Multiplying an odd number with an even number results in an even number,
this is what we need if the above flag is set.
>
> > +
> > pll_fr->pll_multiplier = mul * more_mul;
> > if (pll_fr->pll_multiplier > lim_fr->max_pll_multiplier) {
> > dev_dbg(dev, "pll multiplier %u too high\n",
> > @@ -668,6 +673,10 @@ ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim,
> > if (!is_one_or_even(i))
> > i <<= 1;
> >
> > + if (pll->flags & CCS_PLL_FLAG_EVEN_PLL_MULTIPLIER &&
> > + mul & 1 && i & 1)
>
> Same here.
>
> > + i <<= 1;
> > +
> > dev_dbg(dev, "final more_mul: %u\n", i);
> > if (i > more_mul_max) {
> > dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max);
> > diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
> > index ee206e5b287b..e8297db45460 100644
> > --- a/drivers/media/i2c/ccs-pll.h
> > +++ b/drivers/media/i2c/ccs-pll.h
> > @@ -31,6 +31,7 @@
> > #define CCS_PLL_FLAG_DUAL_PLL BIT(8)
> > #define CCS_PLL_FLAG_OP_SYS_DDR BIT(9)
> > #define CCS_PLL_FLAG_OP_PIX_DDR BIT(10)
> > +#define CCS_PLL_FLAG_EVEN_PLL_MULTIPLIER BIT(11)
>
> You could reuse bit 3, as it got dropped in patch 06/11.
I'll move it there, also for the reason that this isn't a CCS flag.
>
> >
> > /**
> > * struct ccs_pll_branch_fr - CCS PLL configuration (front)
>
--
Regards,
Sakari Ailus
next prev parent reply other threads:[~2025-04-23 10:19 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-17 6:53 [PATCH v2 00/11] CCS PLL fixes and improvements Sakari Ailus
2025-04-17 6:53 ` [PATCH v2 01/11] media: ccs-pll: Start OP pre-PLL multiplier search from correct value Sakari Ailus
2025-04-21 19:50 ` Laurent Pinchart
2025-04-22 11:43 ` Sakari Ailus
2025-04-22 11:50 ` Laurent Pinchart
2025-04-22 12:07 ` Sakari Ailus
2025-04-17 6:53 ` [PATCH v2 02/11] media: ccs-pll: Start VT " Sakari Ailus
2025-04-21 19:53 ` Laurent Pinchart
2025-04-17 6:53 ` [PATCH v2 03/11] media: ccs-pll: Check for too high VT PLL multiplier in dual PLL case Sakari Ailus
2025-04-21 19:56 ` Laurent Pinchart
2025-04-17 6:53 ` [PATCH v2 04/11] media: ccs-pll: Correctly the upper limit of maximum op_pre_pll_clk_div Sakari Ailus
2025-04-21 20:01 ` Laurent Pinchart
2025-04-23 11:55 ` Sakari Ailus
2025-04-17 6:53 ` [PATCH v2 05/11] media: ccs-pll: Print a debug message on too high VT PLL OP clock Sakari Ailus
2025-04-21 20:02 ` Laurent Pinchart
2025-04-17 6:53 ` [PATCH v2 06/11] media: ccs-pll: Drop LINK_DECOUPLED flag Sakari Ailus
2025-04-21 20:03 ` Laurent Pinchart
2025-04-23 12:04 ` Sakari Ailus
2025-04-23 12:22 ` Laurent Pinchart
2025-04-17 6:53 ` [PATCH v2 07/11] media: ccs-pll: Print missing PLL flags Sakari Ailus
2025-04-21 20:05 ` Laurent Pinchart
2025-04-17 6:53 ` [PATCH v2 08/11] media: ccs-pll: Add a flag for even PLL multipliers Sakari Ailus
2025-04-21 20:19 ` Laurent Pinchart
2025-04-23 10:19 ` Sakari Ailus [this message]
2025-04-17 6:53 ` [PATCH v2 09/11] media: ccs-pll: Better validate VT PLL branch Sakari Ailus
2025-04-21 20:24 ` Laurent Pinchart
2025-04-23 10:26 ` Sakari Ailus
2025-04-17 6:53 ` [PATCH v2 10/11] media: ccs-pll: Print PLL calculator flags in the beginning Sakari Ailus
2025-04-21 20:25 ` Laurent Pinchart
2025-04-17 6:53 ` [PATCH v2 11/11] media: ccs-pll: Document the CCS PLL flags Sakari Ailus
2025-04-21 20:29 ` Laurent Pinchart
2025-04-22 11:49 ` Sakari Ailus
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