Re: [PATCH v6 1/9] PCI: tegra194: Drive CLKREQ signal low explicitly

[Vidya Sagar <vidyas@nvidia.com>]

On 24/02/26 00:15, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> Currently, the default setting is that CLKREQ signal of a Root Port
> is internally overridden to '0' to enable REFCLK to flow out to the slot.
> It is observed that one of the PCIe switches (case in point Broadcom PCIe
> Gen4 switch) is propagating the CLKREQ signal of the root port to the
> downstream side of the switch and expecting the endpoints to pull it low
> so that it (PCIe switch) can give out the REFCLK although the Switch as
> such doesn't support CLK-PM or ASPM-L1SS. So, as a workaround, this patch
> drives the CLKREQ of the Root Port itself low to avoid link up issues
> between PCIe switch downstream port and endpoints. This is not a wrong
> thing to do after all the CLKREQ is anyway being overridden to '0'
> internally and now it is just that the same is being propagated outside
> also.
> 
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V1 -> V6: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 9883d14f7f97..f026af7c2ce0 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -44,6 +44,7 @@
>  #define APPL_PINMUX_CLKREQ_OVERRIDE		BIT(3)
>  #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN	BIT(4)
>  #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE	BIT(5)
> +#define APPL_PINMUX_CLKREQ_DEFAULT_VALUE	BIT(13)
>  
>  #define APPL_CTRL				0x4
>  #define APPL_CTRL_SYS_PRE_DET_STATE		BIT(6)
> @@ -1415,6 +1416,7 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
>  		val = appl_readl(pcie, APPL_PINMUX);
>  		val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;
>  		val &= ~APPL_PINMUX_CLKREQ_OVERRIDE;
> +		val &= ~APPL_PINMUX_CLKREQ_DEFAULT_VALUE;
>  		appl_writel(pcie, val, APPL_PINMUX);
>  	}
>  

Reviewed-by: Vidya Sagar <vidyas@nvidia.com>