Re: [PATCH v6 8/9] PCI: tegra194: Add core monitor clock support

[Vidya Sagar <vidyas@nvidia.com>]

On 24/02/26 00:15, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> Tegra supports PCIe core clock monitoring for any rate changes that may be
> happening because of the link speed changes. This is useful in tracking
> any changes in the core clock that are not initiated by the software. This
> patch adds support to parse the monitor clock info from device-tree and
> enable it if present.
> 
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V1 -> V6: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 96581fcd8693..82e9ef172de1 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -253,6 +253,7 @@ struct tegra_pcie_dw {
>  	struct resource *atu_dma_res;
>  	void __iomem *appl_base;
>  	struct clk *core_clk;
> +	struct clk *core_clk_m;
>  	struct reset_control *core_apb_rst;
>  	struct reset_control *core_rst;
>  	struct dw_pcie pci;
> @@ -949,6 +950,8 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
>  	}
>  
>  	clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
> +	if (clk_prepare_enable(pcie->core_clk_m))
> +		dev_err(pci->dev, "Failed to enable core monitor clock\n");
>  
>  	return 0;
>  }
> @@ -1021,6 +1024,12 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
>  		val &= ~PCI_DLF_EXCHANGE_ENABLE;
>  		dw_pcie_writel_dbi(pci, offset + PCI_DLF_CAP, val);
>  
> +		/*
> +		 * core_clk_m is enabled as part of host_init callback in
> +		 * dw_pcie_host_init(). Disable the clock since below
> +		 * tegra_pcie_dw_host_init() will enable it again.
> +		 */
> +		clk_disable_unprepare(pcie->core_clk_m);
>  		tegra_pcie_dw_host_init(pp);
>  		dw_pcie_setup_rc(pp);
>  
> @@ -1613,6 +1622,7 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
>  
>  static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
>  {
> +	clk_disable_unprepare(pcie->core_clk_m);
>  	dw_pcie_host_deinit(&pcie->pci.pp);
>  	tegra_pcie_dw_pme_turnoff(pcie);
>  	tegra_pcie_unconfig_controller(pcie);
> @@ -2160,6 +2170,13 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
>  		return PTR_ERR(pcie->core_clk);
>  	}
>  
> +	pcie->core_clk_m = devm_clk_get_optional(dev, "core_m");
> +	if (IS_ERR(pcie->core_clk_m)) {
> +		dev_err(dev, "Failed to get monitor clock: %ld\n",
> +			PTR_ERR(pcie->core_clk_m));
> +		return PTR_ERR(pcie->core_clk_m);
> +	}
> +
>  	pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
>  						      "appl");
>  	if (!pcie->appl_res) {
> @@ -2356,6 +2373,7 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev)
>  	if (!pcie->link_state)
>  		return 0;
>  
> +	clk_disable_unprepare(pcie->core_clk_m);
>  	tegra_pcie_dw_pme_turnoff(pcie);
>  	tegra_pcie_unconfig_controller(pcie);
>  

Reviewed-by: Vidya Sagar <vidyas@nvidia.com>