Re: [PATCH v6 6/9] PCI: tegra194: Disable L1.2 capability of Tegra234 EP

[Vidya Sagar <vidyas@nvidia.com>]

On 24/02/26 00:15, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> When Tegra234 is operating in the endpoint mode with L1.2 enabled, PCIe
> link goes down during L1.2 exit. This is because Tegra234 is powering up
> UPHY PLL immediately without making sure that the REFCLK is stable.
> This is causing UPHY PLL to not lock to the correct frequency and leading
> to link going down. There is no hardware fix for this, hence do not
> advertise the L1.2 capability in the endpoint mode.
> 
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V1 -> V6: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index f6305a880cad..96581fcd8693 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -240,6 +240,7 @@ struct tegra_pcie_dw_of_data {
>  	bool has_sbr_reset_fix;
>  	bool has_l1ss_exit_fix;
>  	bool has_ltr_req_fix;
> +	bool disable_l1_2;
>  	u32 cdm_chk_int_en_bit;
>  	u32 gen4_preset_vec;
>  	u8 n_fts[2];
> @@ -692,6 +693,22 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
>  	if (pcie->supports_clkreq)
>  		pci->l1ss_support = true;
>  
> +	/*
> +	 * Disable L1.2 capability advertisement for Tegra234 Endpoint mode.
> +	 * Tegra234 has a hardware bug where during L1.2 exit, the UPHY PLL is
> +	 * powered up immediately without waiting for REFCLK to stabilize. This
> +	 * causes the PLL to fail to lock to the correct frequency, resulting in
> +	 * PCIe link loss. Since there is no hardware fix available, we prevent
> +	 * the Endpoint from advertising L1.2 support by clearing the L1.2 bits
> +	 * in the L1 PM Substates Capabilities register. This ensures the host
> +	 * will not attempt to enter L1.2 state with this Endpoint.
> +	 */
> +	if (pcie->of_data->disable_l1_2 && pcie->of_data->mode == DW_PCIE_EP_TYPE) {
> +		val = dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP);
> +		val &= ~(PCI_L1SS_CAP_PCIPM_L1_2 | PCI_L1SS_CAP_ASPM_L1_2);
> +		dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, val);
> +	}
> +
>  	/* Program L0s and L1 entrance latencies */
>  	val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
>  	val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
> @@ -2464,6 +2481,7 @@ static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_ep_of_data = {
>  	.mode = DW_PCIE_EP_TYPE,
>  	.has_l1ss_exit_fix = true,
>  	.has_ltr_req_fix = true,
> +	.disable_l1_2 = true,
>  	.cdm_chk_int_en_bit = BIT(18),
>  	/* Gen4 - 6, 8 and 9 presets enabled */
>  	.gen4_preset_vec = 0x340,

Reviewed-by: Vidya Sagar <vidyas@nvidia.com>