Re: [PATCH v6 4/9] PCI: tegra194: Enable DMA interrupt

[Vidya Sagar <vidyas@nvidia.com>]

On 24/02/26 00:15, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> Enable DMA interrupt to support Tegra PCIe DMA in both Root port and
> Endpoint modes.
> 
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V1 -> V6: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index aeec5f8b9842..110f2adb74d2 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -91,6 +91,7 @@
>  #define APPL_INTR_EN_L1_8_0			0x44
>  #define APPL_INTR_EN_L1_8_BW_MGT_INT_EN		BIT(2)
>  #define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN	BIT(3)
> +#define APPL_INTR_EN_L1_8_EDMA_INT_EN		BIT(6)
>  #define APPL_INTR_EN_L1_8_INTX_EN		BIT(11)
>  #define APPL_INTR_EN_L1_8_AER_INT_EN		BIT(15)
>  
> @@ -547,6 +548,13 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
>  		spurious = 0;
>  	}
>  
> +	if (status_l0 & APPL_INTR_STATUS_L0_INT_INT) {
> +		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);
> +		/* Interrupt is handled by dma driver, don't treat it as spurious */
> +		if (status_l1 & APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK)
> +			spurious = 0;
> +	}
> +
>  	if (spurious) {
>  		dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n",
>  			 status_l0);
> @@ -766,6 +774,7 @@ static void tegra_pcie_enable_intx_interrupts(struct dw_pcie_rp *pp)
>  	val |= APPL_INTR_EN_L1_8_INTX_EN;
>  	val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN;
>  	val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN;
> +	val |= APPL_INTR_EN_L1_8_EDMA_INT_EN;
>  	if (IS_ENABLED(CONFIG_PCIEAER))
>  		val |= APPL_INTR_EN_L1_8_AER_INT_EN;
>  	appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
> @@ -1789,6 +1798,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>  	val |= APPL_INTR_EN_L0_0_SYS_INTR_EN;
>  	val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN;
>  	val |= APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN;
> +	val |= APPL_INTR_EN_L0_0_INT_INT_EN;
>  	appl_writel(pcie, val, APPL_INTR_EN_L0_0);
>  
>  	val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
> @@ -1796,6 +1806,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>  	val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN;
>  	appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
>  
> +	val = appl_readl(pcie, APPL_INTR_EN_L1_8_0);
> +	val |= APPL_INTR_EN_L1_8_EDMA_INT_EN;
> +	appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
> +
>  	/* 110us for both snoop and no-snoop */
>  	val = 110 | (2 << PCI_LTR_SCALE_SHIFT) | LTR_MSG_REQ;
>  	val |= (val << LTR_MST_NO_SNOOP_SHIFT);

Reviewed-by: Vidya Sagar <vidyas@nvidia.com>