Re: [PATCH v6 9/9] PCI: tegra194: Add ASPM L1 entrance latency config

[Vidya Sagar <vidyas@nvidia.com>]

On 24/02/26 00:15, Manikanta Maddireddy wrote:
> For Tegra234, the HW PHY team conducted experiments and determined the
> optimal ASPM L1 entrance latency values: 8 us for Root Port mode and
> 16 us for Endpoint mode. Update the default ASPM L1 entrance latency
> configuration accordingly.
> 
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V1 -> V6: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 82e9ef172de1..1b4fc6a9bed1 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -244,6 +244,8 @@ struct tegra_pcie_dw_of_data {
>  	u32 cdm_chk_int_en_bit;
>  	u32 gen4_preset_vec;
>  	u8 n_fts[2];
> +	/* L1 Latency entrance values(Rest/Prod) */
> +	u32 aspm_l1_enter_lat;
>  };
>  
>  struct tegra_pcie_dw {
> @@ -714,6 +716,8 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
>  	val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
>  	val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
>  	val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
> +	val &= ~PORT_AFR_L1_ENTRANCE_LAT_MASK;
> +	val |= (pcie->of_data->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT);
>  	val |= PORT_AFR_ENTER_ASPM;
>  	dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
>  }
> @@ -2471,6 +2475,7 @@ static const struct tegra_pcie_dw_of_data tegra194_pcie_dw_rc_of_data = {
>  	/* Gen4 - 5, 6, 8 and 9 presets enabled */
>  	.gen4_preset_vec = 0x360,
>  	.n_fts = { 52, 52 },
> +	.aspm_l1_enter_lat = 3,
>  };
>  
>  static const struct tegra_pcie_dw_of_data tegra194_pcie_dw_ep_of_data = {
> @@ -2480,6 +2485,7 @@ static const struct tegra_pcie_dw_of_data tegra194_pcie_dw_ep_of_data = {
>  	/* Gen4 - 5, 6, 8 and 9 presets enabled */
>  	.gen4_preset_vec = 0x360,
>  	.n_fts = { 52, 52 },
> +	.aspm_l1_enter_lat = 3,
>  };
>  
>  static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_rc_of_data = {
> @@ -2492,6 +2498,7 @@ static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_rc_of_data = {
>  	/* Gen4 - 6, 8 and 9 presets enabled */
>  	.gen4_preset_vec = 0x340,
>  	.n_fts = { 52, 80 },
> +	.aspm_l1_enter_lat = 4,
>  };
>  
>  static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_ep_of_data = {
> @@ -2504,6 +2511,7 @@ static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_ep_of_data = {
>  	/* Gen4 - 6, 8 and 9 presets enabled */
>  	.gen4_preset_vec = 0x340,
>  	.n_fts = { 52, 80 },
> +	.aspm_l1_enter_lat = 5,
>  };
>  
>  static const struct of_device_id tegra_pcie_dw_of_match[] = {

Reviewed-by: Vidya Sagar <vidyas@nvidia.com>