Re: [patch V5 05/15] x86/irq: Suppress unlikely interrupt stats by default

Re: [patch V5 05/15] x86/irq: Suppress unlikely interrupt stats by default

[Thomas Gleixner]

On Thu, Apr 02 2026 at 12:39, Radu Rendec wrote:
>> -	inc_irq_stat(SPURIOUS);
>> +	irq_stat_inc_and_enable(IRQ_COUNT_SPURIOUS);
>
> This is just a matter of style but for symmetry with inc_irq_stat(), I
> would prepend '__' to the function name and create a wrapper macro that
> adds the 'IRQ_COUNT_' prefix.
>
> And for consistency (you also have inc_perf_irq_stat()) I would call it
> inc_and_enable_irq_stat().

I fundamentaly despise these constructs which do not have a proper name
space prefix. They make it just hard to grep for. Yes, inc_irq_stat()
exists already, but that does not mean we need to proliferate it.

Thanks,

        tglx

RE: [patch V5 00/15] Improve /proc/interrupts further

[Thomas Gleixner]

On Thu, Apr 02 2026 at 02:32, Michael Kelley wrote:
> On x86, the leftmost column now correctly aligns the "VPMI:" label.
> But the rightmost column does not correctly align the text
> "Perf Guest Mediated PMI". It needs one additional space. Here's my
> output (with some CPU columns removed so it's not so wide):
>
> root@mhkubun:~# cat /proc/interrupts | cut -b 1-30,64-
>             CPU0       CPU1       CPU5       CPU6       CPU7
>  PIW:          0          0          0          0          0  Posted-interrupt wakeup event
> VPMI:          0          0          0          0          0 Perf Guest Mediated PMI

Right. There is a missing space in the VPMI text.

> On arm64, the leftmost column doesn't align the IPI<n> entries.
> Neither does the rightmost column for the IPI<n> entries. Here's some
> of my output:
>
>  45:          0           0         80          0          0  HV-PCI-MSIX-0817:00:02.0  14 Edge      mlx5_comp13@pci:0817:00:02.0
>  46:          0           0          0         10          0  HV-PCI-MSIX-0817:00:02.0  15 Edge      mlx5_comp14@pci:0817:00:02.0
>  47:          0           0          0          0         45  HV-PCI-MSIX-0817:00:02.0  16 Edge      mlx5_comp15@pci:0817:00:02.0
> IPI0:       906         536        649        495        606       Rescheduling interrupts
> IPI1:     28844       12457      14770      55242      39175       Function call interrupts
> IPI2:         0           0          0          0          0       CPU stop interrupts
> IPI3:         0           0          0          0          0       CPU stop NMIs
> IPI4:         0           0          0          0          0       Timer broadcast interrupts
> IPI5:        11           1          5          0          2       IRQ work interrupts
> IPI6:         0           0          0          0          0       CPU backtrace interrupts
> IPI7:         0           0          0          0          0       KGDB roundup interrupts

That means total_nr_irqs is < 1000, which makes it use precision of
3. That obiously is not enough for the IPIn output and already an issue
today. The IPI text is misaligned on ARM64 already today in pretty much
the same way as with the patches applied. That's trivial to fix.

As a bonus ARM(64) has quite some interrupt chips which have their own
print routine to show the interupt chip name. That makes it even more
randomly aligned. That's also an existing problem and a larger
effort to mop up and as it's already a mess. I leave it so.

x86 suffers from the leftmost column issue as well when you make NR_CPUS
small enough in case that VPMI is emitted because the default precision
in the core is 3 digits.

Thanks,

        tglx