[RFC PATCH net-next v2 0/5] net: dsa: qca8k: add a QCA8337 CPU PHY consumer

[RFC PATCH net-next v2 0/5] net: dsa: qca8k: add a QCA8337 CPU PHY consumer

[Yongzhao Chen]

Following Andrew's feedback on the v1 RFC, shared-port PHY flag plumbing
now includes its consumer within the same series. To clarify a prior
misunderstanding, the qca83xx PHY driver already exists upstream; patch
5 supplies the new flag consumer alongside internal CPU-PHY selection in
qca8k.

The minimal topology has one CPU link: a conduit PHY connects through
MDI to QCA8337 PHY4, belonging to switch port 5. The two sides have
distinct phy-handles. A user port provides the data path; ports 0 and 6
are unused. The existing binding accepts an ethernet phandle, phy-mode
and phy-handle on port 5. A reduced fixture based on the documented
Redmi AX5400 wiring passes dtc and the complete net-next schema set. It
is a binding fixture, not a bootable board port.

The pinned net-next base lacks an IPQ5018 Ethernet MAC driver and an
RA74 DTS description. Consequently, this series cannot demonstrate a
runnable RA74 platform upstream, though this does not preclude other
hardware implementations. We would appreciate review of whether this
code-level qca83xx consumer is sufficient scope for the RFC while the
board and MAC support remain downstream.

In this revision:
- Patch 3 serializes MTU updates with phylink link-up/down and port
  enable/disable. It restores each CPU port's original TXMAC/RXMAC
  state, so a link-down port stays down while LINK_AUTO is preserved.
  Failed status reads or MAC pauses abort before the frame-size write;
  restoration failures are logged even if the original operation failed.
- Patch 4 defines the shared switch-to-PHY flag and marks QCA8337
  internal CPU PHYs for SmartSpeed suppression.
- Patch 5 consumes the flag in qca8337_soft_reset() and before the resume
  BMCR reset. It clears enable and bypass-timer bits, preserves other
  register bits and returns an MDIO error without issuing the reset.

Validation:
- All five exported patches pass checkpatch --strict and git mailinfo;
  each parsed commit message retains its DCO sign-off. Independent
  sequential application reproduces the tree.
- ASan and UBSan function-model suites pass 7,189 CPU-selection, MDIO
  and MTU cases plus four resume cases, with 14 negative controls.
- The current qca8k-common.o, qca8k-8xxx.o and qca83xx.o pass x86_64
  and ARM64 allyesconfig/allmodconfig W=1 builds without KCFLAGS overrides.
- Physical hardware testing on upstream net-next has not been performed
  due to the absence of upstream IPQ5018 MAC driver and board DTS.

Changes from v1:
- Clarified that qca83xx is already present upstream; patch 5 provides
  the SmartSpeed flag consumer.
- Added internal CPU-PHY support (retaining Ziyang Huang's authorship).
- Serialized MTU reconfiguration with MAC link-state changes and restored
  each port's original TXMAC/RXMAC bits while preserving LINK_AUTO.
- Narrowed MDIO address filtering to preserve external user-port
  behavior.

Original RFC:
https://lore.kernel.org/netdev/20260919085406.1395-1-yongzhao.derek@gmail.com/

Maintainer response:
https://lore.kernel.org/netdev/59975387-5539-47e7-bcca-4a5ed0a84bad@lunn.ch/

Yongzhao Chen (4):
  net: dsa: pass PHY flags when connecting shared ports
  net: dsa: qca8k: serialize CPU MAC pause during MTU changes
  net: dsa: qca8k: flag QCA8337 internal CPU PHYs for SmartSpeed
  net: phy: qca83xx: disable SmartSpeed before resetting CPU PHYs

Ziyang Huang (1):
  net: dsa: qca8k: support an internal PHY as the CPU port

 Documentation/networking/dsa/dsa.rst |  2 +
 MAINTAINERS                          |  1 +
 drivers/net/dsa/bcm_sf2.c            |  4 ++
 drivers/net/dsa/microchip/ksz8.c     |  4 ++
 drivers/net/dsa/qca/qca8k-8xxx.c     | 37 ++++++++++-------
 drivers/net/dsa/qca/qca8k-common.c   | 79 +++++++++++++++++++++++++++++-------
 drivers/net/dsa/qca/qca8k.h          |  2 +
 drivers/net/phy/qcom/qca83xx.c       | 32 +++++++++++++--
 include/linux/qca83xx.h              | 11 ++++++
 net/dsa/port.c                       |  6 ++-
 10 files changed, 144 insertions(+), 34 deletions(-)
 create mode 100644 include/linux/qca83xx.h

base-commit: 8830e65ed46de41f849eefb8ba227d4852c460f6
-- 
2.43.0

[RFC PATCH net-next v2 1/5] net: dsa: pass PHY flags when connecting shared ports

[Yongzhao Chen]

DSA calls get_phy_flags() for user ports, but passes zero when connecting
CPU or DSA port PHYs. Pass the callback result before PHY initialization
for shared ports too. Drivers without the callback still pass zero.

Keep bcm_sf2 and ksz88xx shared-port flags at zero, preserving their
existing behavior. Document the extended callback scope.

This lets qca8k pass revision information and a SmartSpeed quirk to an
internal PHY used as a CPU link. The remaining patches supply that user.

Assisted-by: LLM
Signed-off-by: Yongzhao Chen <yongzhao.derek@gmail.com>
---
 Documentation/networking/dsa/dsa.rst | 2 ++
 drivers/net/dsa/bcm_sf2.c            | 4 ++++
 drivers/net/dsa/microchip/ksz8.c     | 4 ++++
 net/dsa/port.c                       | 6 +++++-
 4 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/Documentation/networking/dsa/dsa.rst b/Documentation/networking/dsa/dsa.rst
index 7edfdd555..647f952e3 100644
--- a/Documentation/networking/dsa/dsa.rst
+++ b/Documentation/networking/dsa/dsa.rst
@@ -668,6 +668,8 @@ PHY devices and link management
   on its own (e.g.: coming from switch memory mapped registers), this function
   should return a 32-bit bitmask of "flags" that is private between the switch
   driver and the Ethernet PHY driver in ``drivers/net/phy/\*``.
+  It is called when connecting PHYs for user, CPU and DSA ports. Drivers
+  should return zero for ports that do not need switch-specific PHY flags.
 
 - ``phy_read``: Function invoked by the DSA user MDIO bus when attempting to read
   the switch port MDIO registers. If unavailable, return 0xffff for each read.
diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c
index 9e5713015..f516fc396 100644
--- a/drivers/net/dsa/bcm_sf2.c
+++ b/drivers/net/dsa/bcm_sf2.c
@@ -709,6 +709,10 @@ static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
 {
 	struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
 
+	/* Shared ports previously received no PHY flags. */
+	if (!dsa_is_user_port(ds, port))
+		return 0;
+
 	/* The BCM7xxx PHY driver expects to find the integrated PHY revision
 	 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
 	 * the REG_PHY_REVISION register layout is.
diff --git a/drivers/net/dsa/microchip/ksz8.c b/drivers/net/dsa/microchip/ksz8.c
index d74981320..be8861a7a 100644
--- a/drivers/net/dsa/microchip/ksz8.c
+++ b/drivers/net/dsa/microchip/ksz8.c
@@ -3076,6 +3076,10 @@ static u32 ksz88xx_get_phy_flags(struct dsa_switch *ds, int port)
 {
 	struct ksz_device *dev = ds->priv;
 
+	/* Shared ports previously received no PHY flags. */
+	if (!dsa_is_user_port(ds, port))
+		return 0;
+
 	switch (dev->chip_id) {
 	case KSZ88X3_CHIP_ID:
 		/* Silicon Errata Sheet (DS80000830A):
diff --git a/net/dsa/port.c b/net/dsa/port.c
index 1f5536c0d..4db7e6f9c 100644
--- a/net/dsa/port.c
+++ b/net/dsa/port.c
@@ -1666,6 +1666,7 @@ static int dsa_shared_port_phylink_register(struct dsa_port *dp)
 {
 	struct dsa_switch *ds = dp->ds;
 	struct device_node *port_dn = dp->dn;
+	u32 phy_flags = 0;
 	int err;
 
 	dp->pl_config.dev = ds->dev;
@@ -1675,7 +1676,10 @@ static int dsa_shared_port_phylink_register(struct dsa_port *dp)
 	if (err)
 		return err;
 
-	err = phylink_of_phy_connect(dp->pl, port_dn, 0);
+	if (ds->ops->get_phy_flags)
+		phy_flags = ds->ops->get_phy_flags(ds, dp->index);
+
+	err = phylink_of_phy_connect(dp->pl, port_dn, phy_flags);
 	if (err && err != -ENODEV) {
 		pr_err("could not attach to PHY: %d\n", err);
 		goto err_phy_connect;
-- 
2.43.0

[RFC PATCH net-next v2 2/5] net: dsa: qca8k: support an internal PHY as the CPU port

[Yongzhao Chen]

From: Ziyang Huang <hzyitc@outlook.com>

A PHY-to-PHY CPU link connects the SoC PHY to an internal switch PHY.
QCA8337 supports header mode on these ports, and the existing phylink
callbacks already support their internal interfaces.

Allow CPU port selection to find ports 1 through 5 after checking the
MAC-only ports. Include internal CPU PHYs when deciding how to access
the PHYs, without changing the treatment of MAC-only or user ports.

This supports a single internal CPU PHY with an explicit phy-handle and
phy-mode = "internal". The conduit uses its own PHY at the other end of
the MDI connection. Existing single-CPU forwarding then uses the selected
port for flooding and port membership without additional routing changes.

Adapted from the OpenWrt PHY-to-PHY CPU link patch; narrow the MDIO
filter change to retain existing external user-port handling.

[yongzhao: preserve external user-port handling on port 6]
Assisted-by: LLM
Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
Signed-off-by: Yongzhao Chen <yongzhao.derek@gmail.com>
---
 drivers/net/dsa/qca/qca8k-8xxx.c | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8xxx.c
index 60f2a615a..17704cb53 100644
--- a/drivers/net/dsa/qca/qca8k-8xxx.c
+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
@@ -1014,7 +1014,8 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv)
 			return ret;
 		}
 
-		if (!dsa_is_user_port(priv->ds, reg))
+		if (!dsa_is_user_port(priv->ds, reg) &&
+		    !(reg > 0 && reg < 6 && dsa_is_cpu_port(priv->ds, reg)))
 			continue;
 
 		of_get_phy_mode(port, &mode);
@@ -1089,17 +1090,19 @@ qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
 
 static int qca8k_find_cpu_port(struct dsa_switch *ds)
 {
-	struct qca8k_priv *priv = ds->priv;
+	int port;
 
-	/* Find the connected cpu port. Valid port are 0 or 6 */
 	if (dsa_is_cpu_port(ds, 0))
 		return 0;
 
-	dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6");
-
 	if (dsa_is_cpu_port(ds, 6))
 		return 6;
 
+	/* An internal PHY can provide a PHY-to-PHY CPU link. */
+	for (port = 1; port < 6; port++)
+		if (dsa_is_cpu_port(ds, port))
+			return port;
+
 	return -EINVAL;
 }
 
@@ -1849,7 +1852,7 @@ qca8k_setup(struct dsa_switch *ds)
 
 	cpu_port = qca8k_find_cpu_port(ds);
 	if (cpu_port < 0) {
-		dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6");
+		dev_err(priv->dev, "No CPU port configured");
 		return cpu_port;
 	}
 
-- 
2.43.0

[RFC PATCH net-next v2 3/5] net: dsa: qca8k: serialize CPU MAC pause during MTU changes

[Yongzhao Chen]

The global maximum frame size must be changed with CPU MACs disabled.
The old sequence only handled ports 0 and 6, leaving an internal PHY CPU
port enabled while the register was updated.

Include enabled internal CPU ports in the pause. Serialize the whole MTU
update with port enable/disable and phylink link-up/down callbacks, so a
link-up cannot re-enable a CPU MAC during the frame-size write. Read and
restore each port's original TXMAC/RXMAC bits instead of enabling both
unconditionally; a link-down port remains down and LINK_AUTO is preserved.

Abort before updating the frame size if a status read or MAC pause fails,
attempt to restore any port already touched, and report a restore error
when the frame-size write itself succeeded.

Keep the existing treatment of ports 0 and 6, including when either is a
user port.

Assisted-by: LLM
Signed-off-by: Yongzhao Chen <yongzhao.derek@gmail.com>
---
 drivers/net/dsa/qca/qca8k-8xxx.c   |  3 ++
 drivers/net/dsa/qca/qca8k-common.c | 79 ++++++++++++++++++++++++------
 drivers/net/dsa/qca/qca8k.h        |  2 +
 3 files changed, 69 insertions(+), 15 deletions(-)

diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8xxx.c
index 17704cb53..787f30495 100644
--- a/drivers/net/dsa/qca/qca8k-8xxx.c
+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
@@ -1486,7 +1486,9 @@ qca8k_phylink_mac_link_up(struct phylink_config *config,
 
 	reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
 
+	mutex_lock(&priv->port_status_mutex);
 	qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
+	mutex_unlock(&priv->port_status_mutex);
 }
 
 static struct qca8k_pcs *pcs_to_qca8k_pcs(struct phylink_pcs *pcs)
@@ -2119,6 +2121,7 @@ qca8k_sw_probe(struct mdio_device *mdiodev)
 	priv->ds->ops = &qca8k_switch_ops;
 	priv->ds->phylink_mac_ops = &qca8k_phylink_mac_ops;
 	mutex_init(&priv->reg_mutex);
+	mutex_init(&priv->port_status_mutex);
 	dev_set_drvdata(&mdiodev->dev, priv);
 
 	return dsa_register_switch(priv->ds);
diff --git a/drivers/net/dsa/qca/qca8k-common.c b/drivers/net/dsa/qca/qca8k-common.c
index 13005f10e..a584ddf72 100644
--- a/drivers/net/dsa/qca/qca8k-common.c
+++ b/drivers/net/dsa/qca/qca8k-common.c
@@ -463,7 +463,8 @@ int qca8k_mib_init(struct qca8k_priv *priv)
 	return ret;
 }
 
-void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
+static void qca8k_port_set_status_locked(struct qca8k_priv *priv, int port,
+					 int enable)
 {
 	u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
 
@@ -477,6 +478,13 @@ void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
 		regmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);
 }
 
+void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
+{
+	mutex_lock(&priv->port_status_mutex);
+	qca8k_port_set_status_locked(priv, port, enable);
+	mutex_unlock(&priv->port_status_mutex);
+}
+
 void qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset,
 		       uint8_t *data)
 {
@@ -751,8 +759,10 @@ int qca8k_port_enable(struct dsa_switch *ds, int port,
 {
 	struct qca8k_priv *priv = ds->priv;
 
-	qca8k_port_set_status(priv, port, 1);
+	mutex_lock(&priv->port_status_mutex);
+	qca8k_port_set_status_locked(priv, port, 1);
 	priv->port_enabled_map |= BIT(port);
+	mutex_unlock(&priv->port_status_mutex);
 
 	if (dsa_is_user_port(ds, port))
 		phy_support_asym_pause(phy);
@@ -764,14 +774,20 @@ void qca8k_port_disable(struct dsa_switch *ds, int port)
 {
 	struct qca8k_priv *priv = ds->priv;
 
-	qca8k_port_set_status(priv, port, 0);
+	mutex_lock(&priv->port_status_mutex);
+	qca8k_port_set_status_locked(priv, port, 0);
 	priv->port_enabled_map &= ~BIT(port);
+	mutex_unlock(&priv->port_status_mutex);
 }
 
 int qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
 {
 	struct qca8k_priv *priv = ds->priv;
-	int ret;
+	u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
+	u32 status[QCA8K_NUM_PORTS] = { 0 };
+	u32 ports;
+	u32 stopped = 0;
+	int ret, restore_ret, i;
 
 	/* We have only have a general MTU setting.
 	 * DSA always set the CPU port's MTU to the largest MTU of the user
@@ -784,25 +800,58 @@ int qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
 
 	/* To change the MAX_FRAME_SIZE the cpu ports must be off or
 	 * the switch panics.
-	 * Turn off both cpu ports before applying the new value to prevent
-	 * this.
+	 * Include internal PHY CPU ports as well as the two MAC-only ports.
+	 * Toggle only MAC enables, preserving the phylink link-control mode.
 	 */
-	if (priv->port_enabled_map & BIT(0))
-		qca8k_port_set_status(priv, 0, 0);
+	ports = BIT(0) | BIT(6);
+	for (i = 1; i < 6; i++)
+		if (dsa_is_cpu_port(ds, i))
+			ports |= BIT(i);
 
-	if (priv->port_enabled_map & BIT(6))
-		qca8k_port_set_status(priv, 6, 0);
+	mutex_lock(&priv->port_status_mutex);
+	ports &= priv->port_enabled_map;
+
+	for (i = 0; i < QCA8K_NUM_PORTS; i++) {
+		if (!(ports & BIT(i)))
+			continue;
+
+		ret = regmap_read(priv->regmap, QCA8K_REG_PORT_STATUS(i),
+				  &status[i]);
+		if (ret)
+			goto unlock;
+	}
+
+	for (i = 0; i < QCA8K_NUM_PORTS; i++) {
+		if (!(ports & BIT(i)) || !(status[i] & mask))
+			continue;
+
+		stopped |= BIT(i);
+		ret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(i),
+					mask);
+		if (ret)
+			goto restore;
+	}
 
 	/* Include L2 header / FCS length */
 	ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, new_mtu +
 			  ETH_HLEN + ETH_FCS_LEN);
 
-	if (priv->port_enabled_map & BIT(0))
-		qca8k_port_set_status(priv, 0, 1);
-
-	if (priv->port_enabled_map & BIT(6))
-		qca8k_port_set_status(priv, 6, 1);
+restore:
+	for (i = 0; i < QCA8K_NUM_PORTS; i++)
+		if (stopped & BIT(i)) {
+			restore_ret = regmap_update_bits(priv->regmap,
+							 QCA8K_REG_PORT_STATUS(i),
+							 mask, status[i] & mask);
+			if (restore_ret) {
+				dev_err(priv->dev, "failed to restore MAC state on port %d: %d\n",
+					i, restore_ret);
+				if (!ret)
+					ret = restore_ret;
+			}
+		}
 
+unlock:
+	mutex_unlock(&priv->port_status_mutex);
 	return ret;
 }
 
diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h
index 956338893..6cb060204 100644
--- a/drivers/net/dsa/qca/qca8k.h
+++ b/drivers/net/dsa/qca/qca8k.h
@@ -459,6 +459,8 @@ struct qca8k_priv {
 	struct mii_bus *internal_mdio_bus;
 	struct dsa_switch *ds;
 	struct mutex reg_mutex;
+	/* Serializes port MAC state changes with global MTU updates. */
+	struct mutex port_status_mutex;
 	struct device *dev;
 	struct gpio_desc *reset_gpio;
 	struct net_device *mgmt_conduit; /* Track if mdio/mib Ethernet is available */
-- 
2.43.0

[RFC PATCH net-next v2 4/5] net: dsa: qca8k: flag QCA8337 internal CPU PHYs for SmartSpeed

[Yongzhao Chen]

Mark QCA8337 internal PHYs used as CPU links for SmartSpeed suppression.
These links can wait for the conduit PHY during boot, causing SmartSpeed
to remove Gigabit advertisement before the conduit starts.

Use a shared switch-to-PHY flag definition, preserving the revision
bits already consumed by the PHY driver. Only QCA8337 CPU ports 1
through 5 receive the new flag; MAC-only ports and other roles do not.

Assisted-by: LLM
Signed-off-by: Yongzhao Chen <yongzhao.derek@gmail.com>
---
 MAINTAINERS                      |  1 +
 drivers/net/dsa/qca/qca8k-8xxx.c | 19 ++++++++++---------
 drivers/net/phy/qcom/qca83xx.c   |  3 +--
 include/linux/qca83xx.h          | 11 +++++++++++
 4 files changed, 23 insertions(+), 11 deletions(-)
 create mode 100644 include/linux/qca83xx.h

diff --git a/MAINTAINERS b/MAINTAINERS
index df8ab9b82..fa1da8031 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22336,6 +22336,7 @@ L:	netdev@vger.kernel.org
 S:	Maintained
 F:	Documentation/devicetree/bindings/net/dsa/qca8k.yaml
 F:	drivers/net/dsa/qca/qca8k*
+F:	include/linux/qca83xx.h
 F:	net/dsa/tag_qca.c
 
 QUALCOMM ATHEROS QCA7K ETHERNET DRIVER
diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8xxx.c
index 787f30495..4ed1ce660 100644
--- a/drivers/net/dsa/qca/qca8k-8xxx.c
+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
@@ -8,6 +8,7 @@
 
 #include <linux/module.h>
 #include <linux/phy.h>
+#include <linux/qca83xx.h>
 #include <linux/netdevice.h>
 #include <linux/bitfield.h>
 #include <linux/regmap.h>
@@ -1744,17 +1745,17 @@ qca8k_get_ethtool_stats_eth(struct dsa_switch *ds, int port, u64 *data)
 static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port)
 {
 	struct qca8k_priv *priv = ds->priv;
+	u32 flags;
 
-	/* Communicate to the phy internal driver the switch revision.
-	 * Based on the switch revision different values needs to be
-	 * set to the dbg and mmd reg on the phy.
-	 * The first 2 bit are used to communicate the switch revision
-	 * to the phy driver.
-	 */
-	if (port > 0 && port < 6)
-		return priv->switch_revision;
+	if (port <= 0 || port >= 6)
+		return 0;
 
-	return 0;
+	/* The PHY driver uses the switch revision for analog initialization. */
+	flags = priv->switch_revision;
+	if (priv->switch_id == QCA8K_ID_QCA8337 && dsa_is_cpu_port(ds, port))
+		flags |= QCA8K_DEVFLAGS_NO_SMARTSPEED;
+
+	return flags;
 }
 
 static enum dsa_tag_protocol
diff --git a/drivers/net/phy/qcom/qca83xx.c b/drivers/net/phy/qcom/qca83xx.c
index bc70ed8ef..0f484cdfe 100644
--- a/drivers/net/phy/qcom/qca83xx.c
+++ b/drivers/net/phy/qcom/qca83xx.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 
 #include <linux/phy.h>
+#include <linux/qca83xx.h>
 #include <linux/module.h>
 
 #include "qcom.h"
@@ -16,8 +17,6 @@
 #define QCA8327_B_PHY_ID			0x004dd034
 #define QCA8337_PHY_ID				0x004dd036
 
-#define QCA8K_DEVFLAGS_REVISION_MASK		GENMASK(2, 0)
-
 static struct at803x_hw_stat qca83xx_hw_stats[] = {
 	{ "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
 	{ "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
diff --git a/include/linux/qca83xx.h b/include/linux/qca83xx.h
new file mode 100644
index 000000000..f90ed80fb
--- /dev/null
+++ b/include/linux/qca83xx.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef _LINUX_QCA83XX_H
+#define _LINUX_QCA83XX_H
+
+#include <linux/bits.h>
+
+/* QCA8K switch-to-PHY flags, carried through phy_device::dev_flags. */
+#define QCA8K_DEVFLAGS_REVISION_MASK	GENMASK(2, 0)
+#define QCA8K_DEVFLAGS_NO_SMARTSPEED	BIT(3)
+
+#endif
-- 
2.43.0

[RFC PATCH net-next v2 5/5] net: phy: qca83xx: disable SmartSpeed before resetting CPU PHYs

[Yongzhao Chen]

Consume the qca8k flag on QCA8337 by clearing SmartSpeed enable and
bypass-timer bits before genphy_soft_reset(). Read-modify-write preserves
the remaining register bits, and a failed update prevents reset.

The same clear runs before the resume BMCR reset. If MDIO access fails,
resume returns the error without issuing that reset.

The downstream Redmi AX5400 experiment observed Gigabit advertisement
being removed while the conduit was not yet running. Applying this
sequence before the initial reset preserved advertisement in that
experiment. This series does not add the board support used there.

Unflagged QCA8337 PHYs retain their reset sequence. QCA8327 drivers
continue to use genphy_soft_reset() directly.

Link: https://github.com/openwrt/openwrt/issues/24696

Assisted-by: LLM
Signed-off-by: Yongzhao Chen <yongzhao.derek@gmail.com>
---
 drivers/net/phy/qcom/qca83xx.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/qcom/qca83xx.c b/drivers/net/phy/qcom/qca83xx.c
index 0f484cdfe..21ab015f6 100644
--- a/drivers/net/phy/qcom/qca83xx.c
+++ b/drivers/net/phy/qcom/qca83xx.c
@@ -91,6 +91,28 @@ static int qca83xx_probe(struct phy_device *phydev)
 	return 0;
 }
 
+static int qca8337_disable_smartspeed(struct phy_device *phydev)
+{
+	if (!(phydev->dev_flags & QCA8K_DEVFLAGS_NO_SMARTSPEED))
+		return 0;
+
+	/* SmartSpeed settings take effect at software reset. */
+	return phy_clear_bits(phydev, AT803X_SMART_SPEED,
+			      AT803X_SMART_SPEED_ENABLE |
+			      AT803X_SMART_SPEED_BYPASS_TIMER);
+}
+
+static int qca8337_soft_reset(struct phy_device *phydev)
+{
+	int ret;
+
+	ret = qca8337_disable_smartspeed(phydev);
+	if (ret)
+		return ret;
+
+	return genphy_soft_reset(phydev);
+}
+
 static int qca83xx_config_init(struct phy_device *phydev)
 {
 	u8 switch_revision;
@@ -160,6 +182,11 @@ static int qca83xx_resume(struct phy_device *phydev)
 	/* Reinit the port, reset values set by suspend */
 	qca83xx_config_init(phydev);
 
+	/* Reapply the CPU PHY quirk before the resume reset. */
+	ret = qca8337_disable_smartspeed(phydev);
+	if (ret)
+		return ret;
+
 	/* Reset the port on port resume */
 	phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 
@@ -218,7 +245,7 @@ static struct phy_driver qca83xx_driver[] = {
 	.probe			= qca83xx_probe,
 	.flags			= PHY_IS_INTERNAL,
 	.config_init		= qca83xx_config_init,
-	.soft_reset		= genphy_soft_reset,
+	.soft_reset		= qca8337_soft_reset,
 	.get_sset_count		= qca83xx_get_sset_count,
 	.get_strings		= qca83xx_get_strings,
 	.get_stats		= qca83xx_get_stats,
-- 
2.43.0

Re: [RFC PATCH net-next v2 3/5] net: dsa: qca8k: serialize CPU MAC pause during MTU changes

[Andrew Lunn]

>  	mutex_init(&priv->reg_mutex);
> +	mutex_init(&priv->port_status_mutex);

Why not use the existing reg_mutex?

>  int qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
>  {
>  	struct qca8k_priv *priv = ds->priv;
> -	int ret;
> +	u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
> +	u32 status[QCA8K_NUM_PORTS] = { 0 };
> +	u32 ports;
> +	u32 stopped = 0;
> +	int ret, restore_ret, i;

Reverse Christmas tree.

	Andrew

Re: [RFC PATCH net-next v2 4/5] net: dsa: qca8k: flag QCA8337 internal CPU PHYs for SmartSpeed

[Andrew Lunn]

On Tue, Sep 22, 2026 at 10:26:52PM +0200, Yongzhao Chen wrote:
> Mark QCA8337 internal PHYs used as CPU links for SmartSpeed suppression.
> These links can wait for the conduit PHY during boot, causing SmartSpeed
> to remove Gigabit advertisement before the conduit starts.

You need to explain in more detail what smart speed suppression is.

Maybe it is in the next patch?

      Andrew

Re: [RFC PATCH net-next v2 5/5] net: phy: qca83xx: disable SmartSpeed before resetting CPU PHYs

[Andrew Lunn]

On Tue, Sep 22, 2026 at 10:26:53PM +0200, Yongzhao Chen wrote:
> Consume the qca8k flag on QCA8337 by clearing SmartSpeed enable and
> bypass-timer bits before genphy_soft_reset(). Read-modify-write preserves
> the remaining register bits, and a failed update prevents reset.
> 
> The same clear runs before the resume BMCR reset. If MDIO access fails,
> resume returns the error without issuing that reset.
> 
> The downstream Redmi AX5400 experiment observed Gigabit advertisement
> being removed while the conduit was not yet running.

Does this happen after .config_aneg() has been called on the PHY
driver?

Is this another name for downshift, where the PHY detects there is a
broken pair and so reduces the link to 100Mbps which only requires 2
working pairs?

	Andrew

Re: [RFC PATCH net-next v2 1/5] net: dsa: pass PHY flags when connecting shared ports

[Florian Fainelli]

On 9/22/26 13:26, Yongzhao Chen wrote:
> DSA calls get_phy_flags() for user ports, but passes zero when connecting
> CPU or DSA port PHYs. Pass the callback result before PHY initialization
> for shared ports too. Drivers without the callback still pass zero.
> 
> Keep bcm_sf2 and ksz88xx shared-port flags at zero, preserving their
> existing behavior. Document the extended callback scope.
> 
> This lets qca8k pass revision information and a SmartSpeed quirk to an
> internal PHY used as a CPU link. The remaining patches supply that user.
> 
> Assisted-by: LLM
> Signed-off-by: Yongzhao Chen <yongzhao.derek@gmail.com>

Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
-- 
Florian

Re: [RFC PATCH net-next v2 3/5] net: dsa: qca8k: serialize CPU MAC pause during MTU changes

[Yongzhao Chen]

Hi Andrew,

V3 patch 2 uses the existing reg_mutex across the CPU MAC pause,
frame-size update, and state restoration. The link and port-status paths
use the same lock, and the internal helpers do not reacquire it. I also
reordered the declarations in reverse Christmas-tree order.

Thanks,
Yongzhao Chen

Re: [RFC PATCH net-next v2 4/5] net: dsa: qca8k: flag QCA8337 internal CPU PHYs for SmartSpeed

[Yongzhao Chen]

Hi Andrew,

SmartSpeed is the Qualcomm PHY driver's downshift feature. Suppressing
it means clearing the enable and bypass-timer bits in register 0x14,
then resetting the PHY. Patch 4 marks QCA8337 internal CPU PHYs for this
treatment; patch 5 performs the register update before reset.

The v2 commit message claimed that waiting for the conduit PHY caused
the loss of Gigabit advertisement. I have not established that cause, so
v3 removes the claim.

Thanks,
Yongzhao Chen

Re: [RFC PATCH net-next v2 5/5] net: phy: qca83xx: disable SmartSpeed before resetting CPU PHYs

[Yongzhao Chen]

Hi Andrew,

Yes. In the RA74 trace, generic config_aneg() returned successfully with
CTRL1000 at 0x0600. A later read found 0x0400, so 1000BASE-T full-duplex
advertisement had been cleared by then. I did not capture when it
changed. The instrumented Clause 22 BMCR/CTRL1000 path showed no
intervening write; other paths were not ruled out.

SmartSpeed is the downshift feature. I have no evidence of a broken pair
or a successful fallback to 100 Mb/s. The 0x0400 value describes
advertised capability, not the negotiated speed. Clearing SmartSpeed
before the initial reset kept the internal link at 1 Gb/s during the
tested RA74 boot sequence. The trigger remains unknown.

Thanks,
Yongzhao Chen

Re: [RFC PATCH net-next v2 5/5] net: phy: qca83xx: disable SmartSpeed before resetting CPU PHYs

[Andrew Lunn]

On Wed, Sep 23, 2026 at 11:57:35PM +0200, Yongzhao Chen wrote:
> Hi Andrew,
> 
> Yes. In the RA74 trace, generic config_aneg() returned successfully with
> CTRL1000 at 0x0600. A later read found 0x0400, so 1000BASE-T full-duplex
> advertisement had been cleared by then. I did not capture when it
> changed. The instrumented Clause 22 BMCR/CTRL1000 path showed no
> intervening write; other paths were not ruled out.
> 
> SmartSpeed is the downshift feature. I have no evidence of a broken pair
> or a successful fallback to 100 Mb/s. The 0x0400 value describes
> advertised capability, not the negotiated speed. Clearing SmartSpeed
> before the initial reset kept the internal link at 1 Gb/s during the
> tested RA74 boot sequence. The trigger remains unknown.

It is operating different to most devices implementing downshift.

All the other PHYs don't change the contents of the standard
registers, LPA still indicates the link partner can do 1G, BMSR
indicate the link is running at 1G because that is what the
negotiation resolved to, but a vendor register indicates the link is
actually running at 100Mbps.

Now, downshift is not part of 802.3, so vendors are free to implement
it however they want.

But back to this patchset. We have to consider, is downshift in
general broken? If so, we can just disable it in the PHY driver, and
add a comment it is broken. The flag is not needed. We could also
implement the tuning API, but have it disabled by default. Again the
flag is not needed.

I would prefer not to add the flag, but we can if we must. I suggest
you reach out to the vendor and see if there is any errata.

    Andrew

Re: [RFC PATCH net-next v2 5/5] net: phy: qca83xx: disable SmartSpeed before resetting CPU PHYs

[Yongzhao Chen]

Hi Andrew,

I agree that if downshift is broken more generally, disabling it in the
PHY driver, possibly with a default-off tunable, would avoid the need
for this flag. I have not established that. I ran into this on my own
home router and don't have a way to force a downshift, such as a
two-pair cable, so I have not tested user ports. If anyone with
QCA8337 hardware can try a user port with a two-pair cable, that would
answer the general question. Disabling it in qca83xx without a flag
would also remove downshift from user ports, where I have no evidence
that it misbehaves.

On how it differs from other PHYs: in the failing state there was no
link at any layer. BMSR read 0x7949 with link and AN-complete clear,
0x11 was 0x1030 with resolved and link clear, and the conduit had no
carrier. So I have not observed a downshifted link, only the 1000BASE-T
advertisement in CTRL1000 being cleared by a path I have not
identified. The 0x11 value does have bit 5 set, which the QCA8337N
datasheet I have describes as downgrade, but bit 4, documented as
reserved/always 0, is also set, so I am not relying on that decoding.

For the next RFC I would keep the flag, limited to QCA8337 internal CPU
ports. qca8k knows the switch model and port role, qca83xx owns the
registers and reset/resume, and get_phy_flags() delivers the
requirement before the first reset without the PHY driver inspecting
DSA topology. phydev->is_internal also covers user ports. The
workaround has only been tested on CPU PHY4 on RA74, and that result
does not by itself show that a flag is the right selection mechanism.

I have not found a verified erratum for this revision, and as a home
user I do not have a Qualcomm support channel, so I have added Jie Luo,
who has worked on the Qualcomm PHY drivers, to Cc.

Jie, could you forward this to someone at Qualcomm who can check
whether there is a SmartSpeed erratum for the QCA8337 internal PHYs?
If you have seen SmartSpeed problems on an internal PHY used as a CPU
link, or have a recommended way to handle it, that would also help.

Christian, as the qca8k maintainer, have you seen SmartSpeed cause
link problems on QCA8337 PHYs, either on CPU links or on user ports?
That would help answer whether this is specific to the CPU link.

Would you consider this CPU-link scope and get_phy_flags() approach
reasonable for the next RFC, or suggest a different way to select the
workaround?

Thanks,
Yongzhao Chen