* [PATCH 58/74] drm/amd/display: Flip dml2_core_utils_get_segment_horizontal_contiguous() Inputs
[not found] <20261111014100.3596072-1-Wayne.Lin@amd.com>
@ 2026-11-11 1:29 ` Wayne Lin
2026-11-11 1:29 ` [PATCH 61/74] drm/amd/display: Read DRAM channel width from SMU init table Wayne Lin
` (3 subsequent siblings)
4 siblings, 0 replies; 5+ messages in thread
From: Wayne Lin @ 2026-11-11 1:29 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Austin Zheng, Dillon Varone,
Mario Limonciello, Alex Deucher, stable, Wayne Lin
From: Austin Zheng <Austin.Zheng@amd.com>
[Why/How]
Parameters for dml2_core_utils_get_segment_horizontal_contiguous() should be flipped.
Should be swizzle mode then bytes per pixel.
Cc: Dillon Varone <dillon.varone@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
---
.../dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c
index 09cfb5046c81..569ab02ea080 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c
@@ -836,7 +836,7 @@ void dcn5_calculate_swath_and_det_configuration(struct dml2_core_internal_scratc
p->SwathHeightC[k] = MaximumSwathHeightC[k];
RoundedUpSwathSizeBytesY[k] = p->full_swath_bytes_l[k] / 2;
RoundedUpSwathSizeBytesC[k] = p->full_swath_bytes_c[k];
- p->request_size_bytes_luma[k] = dml2_core_utils_get_segment_horizontal_contiguous(p->BytePerPixY[k], p->display_cfg->plane_descriptors[k].surface.tiling)
+ p->request_size_bytes_luma[k] = dml2_core_utils_get_segment_horizontal_contiguous(p->display_cfg->plane_descriptors[k].surface.tiling, p->BytePerPixY[k])
== dml2_core_utils_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle) ? 64 : 128;
p->request_size_bytes_chroma[k] = 256;
@@ -846,7 +846,7 @@ void dcn5_calculate_swath_and_det_configuration(struct dml2_core_internal_scratc
RoundedUpSwathSizeBytesY[k] = p->full_swath_bytes_l[k];
RoundedUpSwathSizeBytesC[k] = p->full_swath_bytes_c[k] / 2;
p->request_size_bytes_luma[k] = 256;
- p->request_size_bytes_chroma[k] = dml2_core_utils_get_segment_horizontal_contiguous(p->BytePerPixC[k], p->display_cfg->plane_descriptors[k].surface.tiling)
+ p->request_size_bytes_chroma[k] = dml2_core_utils_get_segment_horizontal_contiguous(p->display_cfg->plane_descriptors[k].surface.tiling, p->BytePerPixC[k])
== dml2_core_utils_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle) ? 64 : 128;
} else {
@@ -854,9 +854,9 @@ void dcn5_calculate_swath_and_det_configuration(struct dml2_core_internal_scratc
p->SwathHeightC[k] = MaximumSwathHeightC[k] / 2;
RoundedUpSwathSizeBytesY[k] = p->full_swath_bytes_l[k] / 2;
RoundedUpSwathSizeBytesC[k] = p->full_swath_bytes_c[k] / 2;
- p->request_size_bytes_luma[k] = dml2_core_utils_get_segment_horizontal_contiguous(p->BytePerPixY[k], p->display_cfg->plane_descriptors[k].surface.tiling)
+ p->request_size_bytes_luma[k] = dml2_core_utils_get_segment_horizontal_contiguous(p->display_cfg->plane_descriptors[k].surface.tiling, p->BytePerPixY[k])
== dml2_core_utils_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle) ? 64 : 128;
- p->request_size_bytes_chroma[k] = dml2_core_utils_get_segment_horizontal_contiguous(p->BytePerPixC[k], p->display_cfg->plane_descriptors[k].surface.tiling)
+ p->request_size_bytes_chroma[k] = dml2_core_utils_get_segment_horizontal_contiguous(p->display_cfg->plane_descriptors[k].surface.tiling, p->BytePerPixC[k])
== dml2_core_utils_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle) ? 64 : 128;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 61/74] drm/amd/display: Read DRAM channel width from SMU init table
[not found] <20261111014100.3596072-1-Wayne.Lin@amd.com>
2026-11-11 1:29 ` [PATCH 58/74] drm/amd/display: Flip dml2_core_utils_get_segment_horizontal_contiguous() Inputs Wayne Lin
@ 2026-11-11 1:29 ` Wayne Lin
2026-11-11 1:29 ` [PATCH 62/74] drm/amd/display: Update DCN42B stutter latency to match DCN42 Wayne Lin
` (2 subsequent siblings)
4 siblings, 0 replies; 5+ messages in thread
From: Wayne Lin @ 2026-11-11 1:29 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Wenjing Liu, Dillon Varone,
Mario Limonciello, Alex Deucher, stable, Wayne Lin
From: Wenjing Liu <wenjing.liu@amd.com>
[Why]
The channel count came from the SMU init table but the channel
width came from VBIOS vram info. Both values need to describe the
same memory type.
[How]
Add DramChannelWidthBytes to MemoryConfig_t, using a reserved slot
so the layout is unchanged. Populate the channel width in bw_params
from the init table instead of VBIOS vram info.
Cc: Dillon Varone <dillon.varone@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h | 3 ++-
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c | 3 +--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h
index 234777bdd183..ea3927223117 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h
@@ -77,7 +77,8 @@ typedef struct {
typedef struct {
uint32_t NumUmcChannels;
- uint32_t Reserved[3];
+ uint32_t DramChannelWidthBytes;
+ uint32_t Reserved[2];
} MemoryConfig_t;
/**
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
index 8eee54c7d5d5..c5d56757eafd 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
@@ -747,8 +747,7 @@ static bool dcn60_fetch_dal_init_table(struct clk_mgr_internal *clk_mgr)
//dcn60_populate_dc_mode_limit(&bw_params->dc_mode_limit, init_table);
bw_params->num_channels = init_table->MemoryConfig.NumUmcChannels;
- bw_params->dram_channel_width_bytes =
- clk_mgr->base.ctx->dc_bios->vram_info.dram_channel_width_bytes;
+ bw_params->dram_channel_width_bytes = init_table->MemoryConfig.DramChannelWidthBytes;
dcn60_populate_utm_qos_model(clk_mgr, &bw_params->utm_qos_model, init_table);
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 62/74] drm/amd/display: Update DCN42B stutter latency to match DCN42
[not found] <20261111014100.3596072-1-Wayne.Lin@amd.com>
2026-11-11 1:29 ` [PATCH 58/74] drm/amd/display: Flip dml2_core_utils_get_segment_horizontal_contiguous() Inputs Wayne Lin
2026-11-11 1:29 ` [PATCH 61/74] drm/amd/display: Read DRAM channel width from SMU init table Wayne Lin
@ 2026-11-11 1:29 ` Wayne Lin
2026-11-11 1:29 ` [PATCH 64/74] drm/amd/display: Report QoS latency bounds and request Wayne Lin
2026-11-11 1:29 ` [PATCH 68/74] drm/amd/display: Seed boot clocks to avoid lowering pre-OS display clocks Wayne Lin
4 siblings, 0 replies; 5+ messages in thread
From: Wayne Lin @ 2026-11-11 1:29 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Allen Pan, Dillon Varone,
Charlene Liu, Mario Limonciello, Alex Deucher, stable, Wayne Lin
From: Allen Pan <Allen.Pan@amd.com>
[Why]
The DCN42B stutter latencies do not match DCN42, which can lead to
underflow and stutter issues.
[How]
Update the DCN42B LPDDR5/LPCAMM2 stutter latencies to the same
values DCN42 already uses.
Cc: Dillon Varone <dillon.varone@amd.com>
Cc: Charlene Liu <charlene.liu@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Allen Pan <Allen.Pan@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
---
.../dc/dml2_0/dml21/inc/bounding_boxes/dcn42b_soc_bb.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42b_soc_bb.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42b_soc_bb.h
index e83a9ac018db..07f1bffc75ca 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42b_soc_bb.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42b_soc_bb.h
@@ -188,8 +188,8 @@ static const struct dml2_soc_bb dml2_socbb_dcn42b = {
.dram_clk_change_blackout_us = 36,
.fclk_change_blackout_us = 0,
.g7_ppt_blackout_us = 0,
- .stutter_enter_plus_exit_latency_us = 14,
- .stutter_exit_latency_us = 12,
+ .stutter_enter_plus_exit_latency_us = 15.5,
+ .stutter_exit_latency_us = 13.5,
.z8_stutter_enter_plus_exit_latency_us = 300,
.z8_stutter_exit_latency_us = 200,
},
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 64/74] drm/amd/display: Report QoS latency bounds and request
[not found] <20261111014100.3596072-1-Wayne.Lin@amd.com>
` (2 preceding siblings ...)
2026-11-11 1:29 ` [PATCH 62/74] drm/amd/display: Update DCN42B stutter latency to match DCN42 Wayne Lin
@ 2026-11-11 1:29 ` Wayne Lin
2026-11-11 1:29 ` [PATCH 68/74] drm/amd/display: Seed boot clocks to avoid lowering pre-OS display clocks Wayne Lin
4 siblings, 0 replies; 5+ messages in thread
From: Wayne Lin @ 2026-11-11 1:29 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Wenjing Liu, Alvin Lee,
Mario Limonciello, Alex Deucher, stable, Wayne Lin
From: Wenjing Liu <wenjing.liu@amd.com>
[Why]
The requested QoS values returned by the QoS query read zero. The
latency upper bounds and the calculated average bandwidth were never
filled, and clearing the memory bandwidth override zeroed the
bandwidth request instead of restoring the request of the committed
mode.
[How]
Fill the avg and max nominal latency upper bounds from the DML
qos_bound, converting from microseconds to nanoseconds. Fill the
average active bandwidth from the DML informative qos output,
converting from MBps to KBps. Report these from the committed state
in dc_get_qos_info(). Restore the bandwidth lower bounds from the
committed state when the override is cleared.
Cc: Alvin Lee <alvin.lee2@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
---
.../drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c | 7 +++++--
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +++++---
.../dml21_wrapper/dml21_translation_helper.c | 11 +++++++++++
3 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
index c5d56757eafd..f801f3337e5d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
@@ -1619,8 +1619,11 @@ static unsigned int dcn60_override_memory_bandwidth_request(
memcpy(&new_clocks, &clk_mgr_base->clks, sizeof(struct dc_clocks));
if (bw_kbps == 0) {
- new_clocks.utm_nominal_bandwidth_lb_KBps = 0;
- new_clocks.utm_urgent_bandwidth_lb_KBps = 0;
+ /* Clearing the override restores the request of the committed mode. */
+ new_clocks.utm_nominal_bandwidth_lb_KBps =
+ dc->current_state->bw_ctx.bw.dcn.clk.utm_nominal_bandwidth_lb_KBps;
+ new_clocks.utm_urgent_bandwidth_lb_KBps =
+ dc->current_state->bw_ctx.bw.dcn.clk.utm_urgent_bandwidth_lb_KBps;
} else {
max_bw_kbps = dcn60_get_max_active_utm_bandwidth_kbps(clk_mgr_base);
capped_bw_kbps = (bw_kbps > max_bw_kbps) ? max_bw_kbps : bw_kbps;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 656a941b1ba0..8a02bcbb9649 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -8105,12 +8105,14 @@ bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info)
if (dc->clk_mgr && dc->clk_mgr->funcs->get_requested_memory_qos) {
dc->clk_mgr->funcs->get_requested_memory_qos(dc->clk_mgr, &requested);
info->qos_bandwidth_lb_in_mbps = requested.bandwidth_lb_in_mbps;
- info->calculated_avg_bw_in_mbps = requested.calculated_avg_bw_in_mbps;
- info->qos_max_latency_ub_in_ns = requested.max_latency_ub_in_ns;
- info->qos_avg_latency_ub_in_ns = requested.avg_latency_ub_in_ns;
info->qos_max_bw_budget_in_mbps = requested.max_bw_budget_in_mbps;
}
+ /* The clk_mgr does not track these, so report the ones of the committed state. */
+ info->calculated_avg_bw_in_mbps = clk->required_avg_active_bandwidth_KBps / 1000;
+ info->qos_max_latency_ub_in_ns = clk->utm_nominal_max_latency_ub_ns;
+ info->qos_avg_latency_ub_in_ns = clk->utm_nominal_avg_latency_ub_ns;
+
return true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c
index a7d6ff59870a..31292a70a84e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c
@@ -1036,6 +1036,14 @@ void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state
context->bw_ctx.bw.dcn.clk.utm_latency_ub_index = 0; /* TODO - derive from qos model */
context->bw_ctx.bw.dcn.clk.utm_nominal_bandwidth_lb_KBps = (unsigned int) in_ctx->v21.mode_programming.programming->qos_bound.bandwidth_lb.dcn5.non_urgent_bandwidth_kbps;
context->bw_ctx.bw.dcn.clk.utm_urgent_bandwidth_lb_KBps = (unsigned int) in_ctx->v21.mode_programming.programming->qos_bound.bandwidth_lb.dcn5.urgent_bandwidth_kbps;
+ /* DML latency upper bounds are in microseconds, the dc clocks fields are in nanoseconds. */
+ context->bw_ctx.bw.dcn.clk.utm_nominal_avg_latency_ub_ns = (unsigned int)(
+ in_ctx->v21.mode_programming.programming->qos_bound.latency_ub.dcn5.avg_req_latency_non_urg * 1000);
+ context->bw_ctx.bw.dcn.clk.utm_nominal_max_latency_ub_ns = (unsigned int)(
+ in_ctx->v21.mode_programming.programming->qos_bound.latency_ub.dcn5.max_req_latency_non_urg * 1000);
+ /* The average bandwidth DML calculated for the active state, converted from MBps to KBps. */
+ context->bw_ctx.bw.dcn.clk.required_avg_active_bandwidth_KBps = (unsigned int)(
+ in_ctx->v21.mode_programming.programming->informative.qos.avg_bw_required.sys_active.sdp_bw_mbps * 1000);
context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = (uint8_t)in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency;
context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = (uint8_t)in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency;
context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_efficiency = (uint8_t)in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_efficiency;
@@ -1177,6 +1185,9 @@ void dml21_init_min_clocks_for_dc_state(struct dml2_context *in_ctx, struct dc_s
min_clocks->utm_latency_ub_index = 0; /* TODO - derive from qos model */
min_clocks->utm_nominal_bandwidth_lb_KBps = 0;
min_clocks->utm_urgent_bandwidth_lb_KBps = 0;
+ min_clocks->utm_nominal_max_latency_ub_ns = 0;
+ min_clocks->utm_nominal_avg_latency_ub_ns = 0;
+ min_clocks->required_avg_active_bandwidth_KBps = 0;
min_clocks->stutter_efficiency.base_efficiency = 1;
min_clocks->stutter_efficiency.low_power_efficiency = 1;
min_clocks->stutter_efficiency.z8_stutter_efficiency = 1;
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 68/74] drm/amd/display: Seed boot clocks to avoid lowering pre-OS display clocks
[not found] <20261111014100.3596072-1-Wayne.Lin@amd.com>
` (3 preceding siblings ...)
2026-11-11 1:29 ` [PATCH 64/74] drm/amd/display: Report QoS latency bounds and request Wayne Lin
@ 2026-11-11 1:29 ` Wayne Lin
4 siblings, 0 replies; 5+ messages in thread
From: Wayne Lin @ 2026-11-11 1:29 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Jing Zhou, Nicholas Kazlauskas,
Charlene Liu, Mario Limonciello, Alex Deucher, stable, Wayne Lin
From: Jing Zhou <Jing.Zhou@amd.com>
[WHY]
USB4 DPIA HPD can arrive early in boot, before the first stream commit.
Its link detection runs prepare_phy_clocks(), which goes through
clk_mgr_exit_optimized_pwr_state() and clk_mgr_optimize_pwr_state()
and calls update_clocks(dc->current_state).
At that point both dc->current_state->bw_ctx.bw.dcn.clk and
clk_mgr->clks are still zero, because init_clocks() memsets them. On the
safe_to_lower path, dcn42_update_clocks() clamps the requested DPPCLK to
the 100MHz floor and programs it. This drops DPPCLK below what the
GOP-lit eDP pipe needs, and the panel flashes white.
[HOW]
1. In dcn42_init_clocks() and dcn42b_init_clocks(), seed clk_mgr->clks
dispclk/dppclk from the boot snapshot(10kHz units, x10).
2. Add a DC core helper, sync_current_state_clocks_from_clk_mgr().
After every hwss.init_hw() call (legacy_hardware_init, D0 entry in
dc_set_power_state, and dc_reinitialize_hardware), it copies
clk_mgr->clks into dc->current_state->bw_ctx.bw.dcn.clk for DCN.
A later update_clocks() before the first commit then sees the real
pre-OS clocks and does not lower them. Raising clocks is still
allowed and does not cause a flash.
Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Cc: Charlene Liu <charlene.liu@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Jing Zhou <Jing.Zhou@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
---
.../amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 3 +++
.../display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c | 4 ++++
drivers/gpu/drm/amd/display/dc/core/dc.c | 16 +++++++++++++++-
3 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
index b1fbadd0d885..054eab1e0cb9 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
@@ -643,6 +643,9 @@ DC_LOGGER_INIT(clk_mgr_base->ctx->logger);
DC_LOG_SMU("dp_dto_source_clock %d, dprefclk %d\n", clk_mgr_base->dp_dto_source_clock_in_khz, clk_mgr_base->dprefclk_khz);
dcn42_dump_clk_registers(&clk_mgr_base->boot_snapshot, clk_mgr);
+ /* Snapshot is in 10kHz units; seed clks so update_clocks() does not lower the pre-OS clocks */
+ clk_mgr_base->clks.dispclk_khz = clk_mgr_base->boot_snapshot.dispclk * 10;
+ clk_mgr_base->clks.dppclk_khz = clk_mgr_base->boot_snapshot.dppclk * 10;
clk_mgr_base->clks.ref_dtbclk_khz = clk_mgr_base->boot_snapshot.dtbclk * 10;
clk_mgr_base->clks.dtbclk_en = clk_mgr_base->boot_snapshot.dtbclk > 59000;
}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c
index 57291c10c917..5e8a65f1ee68 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c
@@ -251,6 +251,10 @@ DC_LOGGER_INIT(clk_mgr_base->ctx->logger);
DC_LOG_SMU("dp_dto_source_clock %d, dprefclk %d\n", clk_mgr_base->dp_dto_source_clock_in_khz, clk_mgr_base->dprefclk_khz);
dcn42b_dump_clk_registers(&clk_mgr_base->boot_snapshot, clk_mgr);
+
+ /* Snapshot is in 10kHz units; seed clks so update_clocks() does not lower the pre-OS clocks */
+ clk_mgr_base->clks.dispclk_khz = clk_mgr_base->boot_snapshot.dispclk * 10;
+ clk_mgr_base->clks.dppclk_khz = clk_mgr_base->boot_snapshot.dppclk * 10;
}
static struct clk_bw_params dcn42b_bw_params = {
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 8a02bcbb9649..463a3fc2d8c2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1728,12 +1728,25 @@ static void detect_edp_presence(struct dc *dc)
}
}
+static void sync_current_state_clocks_from_clk_mgr(struct dc *dc)
+{
+ if (!dc->current_state || !dc->clk_mgr)
+ return;
+
+ if (!(dc->ctx->dce_version == DCN_VERSION_4_2 || dc->ctx->dce_version == DCN_VERSION_4_2B))
+ return;
+
+ dc->current_state->bw_ctx.bw.dcn.clk = dc->clk_mgr->clks;
+}
+
void legacy_hardware_init(struct dc *dc)
{
detect_edp_presence(dc);
- if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
+ if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW) {
dc->hwss.init_hw(dc);
+ sync_current_state_clocks_from_clk_mgr(dc);
+ }
dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
}
@@ -6435,6 +6448,7 @@ void dc_set_power_state(struct dc *dc, enum dc_acpi_cm_power_state power_state)
dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state);
dc->hwss.init_hw(dc);
+ sync_current_state_clocks_from_clk_mgr(dc);
invalidate_drr_adjust(dc);
--
2.43.0
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