[U-Boot] [PATCH v5 11/26] clk: sunxi: Implement UART clocks

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From: Jagan Teki <jagan@amarulasolutions.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v5 11/26] clk: sunxi: Implement UART clocks
Date: Mon, 31 Dec 2018 22:29:12 +0530	[thread overview]
Message-ID: <20181231165927.13803-12-jagan@amarulasolutions.com> (raw)
In-Reply-To: <20181231165927.13803-1-jagan@amarulasolutions.com>

Implement UART clocks for all Allwinner SoC
clock drivers via ccu clock gate table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/clk/sunxi/clk_a10.c  | 9 +++++++++
 drivers/clk/sunxi/clk_a10s.c | 5 +++++
 drivers/clk/sunxi/clk_a23.c  | 6 ++++++
 drivers/clk/sunxi/clk_a31.c  | 7 +++++++
 drivers/clk/sunxi/clk_a64.c  | 6 ++++++
 drivers/clk/sunxi/clk_a83t.c | 6 ++++++
 drivers/clk/sunxi/clk_h3.c   | 5 +++++
 drivers/clk/sunxi/clk_r40.c  | 9 +++++++++
 drivers/clk/sunxi/clk_v3s.c  | 4 ++++
 9 files changed, 57 insertions(+)

diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index 59d9d90a19..1b074e3872 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -19,6 +19,15 @@ static struct ccu_clk_gate a10_gates[] = {
 	[CLK_AHB_EHCI1]		= GATE(0x060, BIT(3)),
 	[CLK_AHB_OHCI1]		= GATE(0x060, BIT(4)),
 
+	[CLK_APB1_UART0]	= GATE(0x06c, BIT(16)),
+	[CLK_APB1_UART1]	= GATE(0x06c, BIT(17)),
+	[CLK_APB1_UART2]	= GATE(0x06c, BIT(18)),
+	[CLK_APB1_UART3]	= GATE(0x06c, BIT(19)),
+	[CLK_APB1_UART4]	= GATE(0x06c, BIT(20)),
+	[CLK_APB1_UART5]	= GATE(0x06c, BIT(21)),
+	[CLK_APB1_UART6]	= GATE(0x06c, BIT(22)),
+	[CLK_APB1_UART7]	= GATE(0x06c, BIT(23)),
+
 	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(6)),
 	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(7)),
 	[CLK_USB_PHY]		= GATE(0x0cc, BIT(8)),
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index 474f37d607..a50c6e3f7f 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -17,6 +17,11 @@ static struct ccu_clk_gate a10s_gates[] = {
 	[CLK_AHB_EHCI]		= GATE(0x060, BIT(1)),
 	[CLK_AHB_OHCI]		= GATE(0x060, BIT(2)),
 
+	[CLK_APB1_UART0]	= GATE(0x06c, BIT(16)),
+	[CLK_APB1_UART1]	= GATE(0x06c, BIT(17)),
+	[CLK_APB1_UART2]	= GATE(0x06c, BIT(18)),
+	[CLK_APB1_UART3]	= GATE(0x06c, BIT(19)),
+
 	[CLK_USB_OHCI]		= GATE(0x0cc, BIT(6)),
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index 0fc8a5821c..63004b881d 100644
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -17,6 +17,12 @@ static struct ccu_clk_gate a23_gates[] = {
 	[CLK_BUS_EHCI]		= GATE(0x060, BIT(26)),
 	[CLK_BUS_OHCI]		= GATE(0x060, BIT(29)),
 
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
 	[CLK_USB_HSIC]		= GATE(0x0cc, BIT(10)),
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index 03dd9ae913..c01d2a3549 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -20,6 +20,13 @@ static struct ccu_clk_gate a31_gates[] = {
 	[CLK_AHB1_OHCI1]	= GATE(0x060, BIT(30)),
 	[CLK_AHB1_OHCI2]	= GATE(0x060, BIT(31)),
 
+	[CLK_APB2_UART0]	= GATE(0x06c, BIT(16)),
+	[CLK_APB2_UART1]	= GATE(0x06c, BIT(17)),
+	[CLK_APB2_UART2]	= GATE(0x06c, BIT(18)),
+	[CLK_APB2_UART3]	= GATE(0x06c, BIT(19)),
+	[CLK_APB2_UART4]	= GATE(0x06c, BIT(20)),
+	[CLK_APB2_UART5]	= GATE(0x06c, BIT(21)),
+
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
 	[CLK_USB_PHY2]		= GATE(0x0cc, BIT(10)),
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 28bda1f497..b427e3adda 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -19,6 +19,12 @@ static const struct ccu_clk_gate a64_gates[] = {
 	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(28)),
 	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(29)),
 
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
 	[CLK_USB_HSIC]		= GATE(0x0cc, BIT(10)),
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index 45faef2f11..fbffa3bf5f 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -18,6 +18,12 @@ static struct ccu_clk_gate a83t_gates[] = {
 	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(27)),
 	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(29)),
 
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
 	[CLK_USB_HSIC]		= GATE(0x0cc, BIT(10)),
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index 283fc31b01..f706e77dee 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -23,6 +23,11 @@ static struct ccu_clk_gate h3_gates[] = {
 	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(30)),
 	[CLK_BUS_OHCI3]		= GATE(0x060, BIT(31)),
 
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
 	[CLK_USB_PHY2]		= GATE(0x0cc, BIT(10)),
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index 2a6000f4dc..3405b39c46 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -21,6 +21,15 @@ static struct ccu_clk_gate r40_gates[] = {
 	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(30)),
 	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(31)),
 
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+	[CLK_BUS_UART5]		= GATE(0x06c, BIT(21)),
+	[CLK_BUS_UART6]		= GATE(0x06c, BIT(22)),
+	[CLK_BUS_UART7]		= GATE(0x06c, BIT(23)),
+
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
 	[CLK_USB_PHY2]		= GATE(0x0cc, BIT(10)),
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index 0eeea84c1a..a662bc3e93 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -15,6 +15,10 @@
 static struct ccu_clk_gate v3s_gates[] = {
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
 
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+
 	[CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
 };
 
-- 
2.18.0.321.gffc6fa0e3

next prev parent reply	other threads:[~2018-12-31 16:59 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-31 16:59 [U-Boot] [PATCH v5 00/26] clk: Add Allwinner CLK, RESET support Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 01/26] clk: Add Allwinner A64 CLK driver Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 02/26] reset: Add Allwinner RESET driver Jagan Teki
2019-01-10  0:50   ` André Przywara
2018-12-31 16:59 ` [U-Boot] [PATCH v5 03/26] clk: sunxi: Add Allwinner H3/H5 CLK driver Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 04/26] clk: sunxi: Add Allwinner A10/A20 " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 05/26] clk: sunxi: Add Allwinner A10s/A13 " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 06/26] clk: sunxi: Add Allwinner A31 " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 07/26] clk: sunxi: Add Allwinner A23/A33 " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 08/26] clk: sunxi: Add Allwinner A83T " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 09/26] clk: sunxi: Add Allwinner R40 " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 10/26] clk: sunxi: Add Allwinner V3S " Jagan Teki
2018-12-31 16:59 ` Jagan Teki [this message]
2018-12-31 16:59 ` [U-Boot] [PATCH v5 12/26] clk: sunxi: Implement UART resets Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 13/26] clk: sunxi: Add Allwinner H6 CLK driver Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 14/26] sunxi: A64: Update sun50i-a64-ccu.h Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 15/26] clk: sunxi: Add ccu clock tree support Jagan Teki
2019-01-07  1:03   ` André Przywara
2019-01-07 13:01     ` Maxime Ripard
2019-01-07 14:09       ` Andre Przywara
2019-01-07 18:25         ` Maxime Ripard
2019-01-08 10:57     ` Jagan Teki
2019-01-08 11:39       ` Andre Przywara
2019-01-08 19:12         ` Jagan Teki
2019-01-10  0:50           ` André Przywara
2019-01-10 18:31             ` Jagan Teki
2019-01-08 11:25     ` Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 16/26] sunxi: Enable CLK Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 17/26] phy: sun4i-usb: Use CLK and RESET support Jagan Teki
2018-12-31 18:29   ` Marek Vasut
2018-12-31 18:38     ` Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 18/26] reset: Add reset valid Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 19/26] musb-new: sunxi: Use CLK and RESET support Jagan Teki
2018-12-31 18:30   ` Marek Vasut
2018-12-31 16:59 ` [U-Boot] [PATCH v5 20/26] sunxi: usb: Switch to Generic host controllers Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 21/26] usb: host: Drop [e-o]hci-sunxi drivers Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 22/26] clk: sunxi: Implement SPI clocks Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 23/26] spi: sun4i: Add CLK support Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 24/26] clk: sunxi: Implement A64 SPI clocks, resets Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 25/26] spi: Add Allwinner A31 SPI driver Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 26/26] board: sopine: Enable SPI/SPI-FLASH Jagan Teki
2019-01-07 13:04   ` Maxime Ripard
2019-01-22 16:32   ` Alexander Graf
2019-01-22 16:40     ` Andre Przywara
2019-01-22 16:47       ` Tom Rini
2019-01-06  9:39 ` [U-Boot] [PATCH v5 00/26] clk: Add Allwinner CLK, RESET support Jagan Teki
2019-01-06 13:17 ` André Przywara
2019-01-06 19:22   ` Jagan Teki
2019-01-07  1:21     ` André Przywara

find likely ancestor, descendant, or conflicting patches for this message:
( dfblob:59d9d90a1 dfblob:1b074e387 dfblob:474f37d60 dfblob:a50c6e3f7
dfblob:0fc8a5821 dfblob:63004b881 dfblob:03dd9ae91 dfblob:c01d2a354
dfblob:28bda1f49 dfblob:b427e3add dfblob:45faef2f1 dfblob:fbffa3bf5
dfblob:283fc31b0 dfblob:f706e77de dfblob:2a6000f4d dfblob:3405b39c4
dfblob:0eeea84c1 dfblob:a662bc3e9 )
 OR (
bs:"[U-Boot] [PATCH v5 11/26] clk: sunxi: Implement UART clocks" )
	(help)

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