[U-Boot] [PATCH v5 06/26] clk: sunxi: Add Allwinner A31 CLK driver

[Jagan Teki <jagan@amarulasolutions.com>]

Add initial clock driver for Allwinner A31.

- Implement USB ahb1 and USB clocks via ccu_clk_gate table
  for A31, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement USB ahb1 and USB resets via ccu_reset table
  for A31, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
 drivers/clk/sunxi/Kconfig   |  7 ++++
 drivers/clk/sunxi/Makefile  |  1 +
 drivers/clk/sunxi/clk_a31.c | 68 +++++++++++++++++++++++++++++++++++++
 3 files changed, 76 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_a31.c

diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index b228c2fa3a..535b0dc02c 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -23,6 +23,13 @@ config CLK_SUN5I_A10S
 	  This enables common clock driver support for platforms based
 	  on Allwinner A10s/A13 SoC.
 
+config CLK_SUN6I_A31
+	bool "Clock driver for Allwinner A31/A31s"
+	default MACH_SUN6I
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A31/A31s SoC.
+
 config CLK_SUN8I_H3
 	bool "Clock driver for Allwinner H3/H5"
 	default MACH_SUNXI_H3_H5
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 466d4b79d6..3cf0071b0c 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -8,5 +8,6 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
 
 obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
 obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
+obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
new file mode 100644
index 0000000000..03dd9ae913
--- /dev/null
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions B.V.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun6i-a31-ccu.h>
+#include <dt-bindings/reset/sun6i-a31-ccu.h>
+
+static struct ccu_clk_gate a31_gates[] = {
+	[CLK_AHB1_OTG]		= GATE(0x060, BIT(24)),
+	[CLK_AHB1_EHCI0]	= GATE(0x060, BIT(26)),
+	[CLK_AHB1_EHCI1]	= GATE(0x060, BIT(27)),
+	[CLK_AHB1_OHCI0]	= GATE(0x060, BIT(29)),
+	[CLK_AHB1_OHCI1]	= GATE(0x060, BIT(30)),
+	[CLK_AHB1_OHCI2]	= GATE(0x060, BIT(31)),
+
+	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
+	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
+	[CLK_USB_PHY2]		= GATE(0x0cc, BIT(10)),
+	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
+	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
+	[CLK_USB_OHCI2]		= GATE(0x0cc, BIT(18)),
+};
+
+static struct ccu_reset a31_resets[] = {
+	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
+	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
+	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
+
+	[RST_AHB1_OTG]		= RESET(0x2c0, BIT(24)),
+	[RST_AHB1_EHCI0]	= RESET(0x2c0, BIT(26)),
+	[RST_AHB1_EHCI1]	= RESET(0x2c0, BIT(27)),
+	[RST_AHB1_OHCI0]	= RESET(0x2c0, BIT(29)),
+	[RST_AHB1_OHCI1]	= RESET(0x2c0, BIT(30)),
+	[RST_AHB1_OHCI2]	= RESET(0x2c0, BIT(31)),
+};
+
+static const struct ccu_desc a31_ccu_desc = {
+	.gates = a31_gates,
+	.resets = a31_resets,
+};
+
+static int a31_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, 56);
+}
+
+static const struct udevice_id a31_clk_ids[] = {
+	{ .compatible = "allwinner,sun6i-a31-ccu",
+	  .data = (ulong)&a31_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun6i_a31) = {
+	.name		= "sun6i_a31_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= a31_clk_ids,
+	.priv_auto_alloc_size	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= a31_clk_bind,
+};
-- 
2.18.0.321.gffc6fa0e3