From: "André Przywara" <andre.przywara@arm.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v5 02/26] reset: Add Allwinner RESET driver
Date: Thu, 10 Jan 2019 00:50:55 +0000 [thread overview]
Message-ID: <3be791c3-bb58-e4ec-53e0-a9a80ec8e218@arm.com> (raw)
In-Reply-To: <20181231165927.13803-3-jagan@amarulasolutions.com>
On 31/12/2018 16:59, Jagan Teki wrote:
> Add common reset driver for all Allwinner SoC's.
>
> Since CLK and RESET share common DT compatible, it is CLK driver
> job is to bind the reset driver. So add CLK bind call on respective
> SoC driver by passing ccu map descriptor so-that reset deassert,
> deassert operations held based on ccu reset table defined from
> CLK driver.
>
> Select DM_RESET via CLK_SUNXI, this make hidden section of RESET
> since CLK and RESET share common DT compatible and code.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
> ---
> arch/arm/include/asm/arch-sunxi/ccu.h | 29 ++++++
> drivers/clk/sunxi/Kconfig | 1 +
> drivers/clk/sunxi/clk_a64.c | 20 +++++
> drivers/reset/Kconfig | 8 ++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-sunxi.c | 125 ++++++++++++++++++++++++++
> 6 files changed, 184 insertions(+)
> create mode 100644 drivers/reset/reset-sunxi.c
>
> diff --git a/arch/arm/include/asm/arch-sunxi/ccu.h b/arch/arm/include/asm/arch-sunxi/ccu.h
> index db69c8f0d5..3fdc26978d 100644
> --- a/arch/arm/include/asm/arch-sunxi/ccu.h
> +++ b/arch/arm/include/asm/arch-sunxi/ccu.h
> @@ -34,13 +34,33 @@ struct ccu_clk_gate {
> .flags = CCU_CLK_F_INIT_DONE, \
> }
>
> +/**
> + * struct ccu_reset - ccu reset
> + * @off: reset offset
> + * @bit: reset bit
> + * @flags: reset flags
> + */
> +struct ccu_reset {
> + u16 off;
> + u32 bit;
> + enum ccu_clk_flags flags;
> +};
> +
> +#define RESET(_off, _bit) { \
> + .off = _off, \
> + .bit = _bit, \
> + .flags = CCU_CLK_F_INIT_DONE, \
> +}
> +
> /**
> * struct ccu_desc - clock control unit descriptor
> *
> * @gates: clock gates
> + * @resets: reset unit
> */
> struct ccu_desc {
> const struct ccu_clk_gate *gates;
> + const struct ccu_reset *resets;
> };
>
> /**
> @@ -62,4 +82,13 @@ int sunxi_clk_probe(struct udevice *dev);
>
> extern struct clk_ops sunxi_clk_ops;
>
> +/**
> + * sunxi_reset_bind() - reset binding
> + *
> + * @dev: reset device
> + * @count: reset count
> + * @return 0 success, or error value
> + */
> +int sunxi_reset_bind(struct udevice *dev, ulong count);
> +
> #endif /* _ASM_ARCH_CCU_H */
> diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
> index bf5ecb3801..041d711e58 100644
> --- a/drivers/clk/sunxi/Kconfig
> +++ b/drivers/clk/sunxi/Kconfig
> @@ -1,6 +1,7 @@
> config CLK_SUNXI
> bool "Clock support for Allwinner SoCs"
> depends on CLK && ARCH_SUNXI
> + select DM_RESET
> default y
> help
> This enables support for common clock driver API on Allwinner
> diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
> index 803a2f711d..28bda1f497 100644
> --- a/drivers/clk/sunxi/clk_a64.c
> +++ b/drivers/clk/sunxi/clk_a64.c
> @@ -10,6 +10,7 @@
> #include <errno.h>
> #include <asm/arch/ccu.h>
> #include <dt-bindings/clock/sun50i-a64-ccu.h>
> +#include <dt-bindings/reset/sun50i-a64-ccu.h>
>
> static const struct ccu_clk_gate a64_gates[] = {
> [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
> @@ -26,10 +27,28 @@ static const struct ccu_clk_gate a64_gates[] = {
> [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
> };
>
> +static const struct ccu_reset a64_resets[] = {
> + [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
> + [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
> + [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
> +
> + [RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
> + [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
> + [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
> + [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
> + [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
> +};
> +
> static const struct ccu_desc a64_ccu_desc = {
> .gates = a64_gates,
> + .resets = a64_resets,
> };
>
> +static int a64_clk_bind(struct udevice *dev)
> +{
> + return sunxi_reset_bind(dev, 50);
The second parameter is count, so it should be 51. But this is wrong
either way, so just use ARRAY_SIZE(a64_reset), as this is what you are
after with the check later on.
Same for the other SoCs, of course.
> +}
> +
> static const struct udevice_id a64_ccu_ids[] = {
> { .compatible = "allwinner,sun50i-a64-ccu",
> .data = (ulong)&a64_ccu_desc },
> @@ -43,4 +62,5 @@ U_BOOT_DRIVER(clk_sun50i_a64) = {
> .priv_auto_alloc_size = sizeof(struct ccu_priv),
> .ops = &sunxi_clk_ops,
> .probe = sunxi_clk_probe,
> + .bind = a64_clk_bind,
> };
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 9c5208b7da..b6b40b6ce9 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -106,4 +106,12 @@ config RESET_SOCFPGA
> help
> Support for reset controller on SoCFPGA platform.
>
> +config RESET_SUNXI
> + bool "RESET support for Allwinner SoCs"
> + depends on DM_RESET && ARCH_SUNXI
> + default y
> + help
> + This enables support for common reset driver for
> + Allwinner SoCs.
> +
> endmenu
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index f4520878b7..377c038163 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -17,3 +17,4 @@ obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
> obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
> obj-$(CONFIG_RESET_MESON) += reset-meson.o
> obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
> +obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
> diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c
> new file mode 100644
> index 0000000000..af63cac64e
> --- /dev/null
> +++ b/drivers/reset/reset-sunxi.c
> @@ -0,0 +1,125 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2018 Amarula Solutions.
> + * Author: Jagan Teki <jagan@amarulasolutions.com>
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <reset-uclass.h>
> +#include <asm/io.h>
> +#include <dm/lists.h>
> +#include <linux/log2.h>
> +#include <asm/arch/ccu.h>
> +
> +struct sunxi_reset_priv {
> + void *base;
> + ulong count;
> + const struct ccu_desc *desc;
> +};
> +
> +static const struct ccu_reset *priv_to_reset(struct sunxi_reset_priv *priv,
> + unsigned long id)
> +{
> + return &priv->desc->resets[id];
> +}
> +
> +static int sunxi_reset_request(struct reset_ctl *reset_ctl)
> +{
> + struct sunxi_reset_priv *priv = dev_get_priv(reset_ctl->dev);
> +
> + debug("%s: (RST#%ld)\n", __func__, reset_ctl->id);
> +
> + /* check dt-bindings/reset/sun8i-h3-ccu.h for max id */
File name should be generic, but the comment is not correct anyway,
since we are limited by the array size, not by the DT.
So please just remove this comment.
Cheers,
Andre.
> + if (reset_ctl->id >= priv->count)
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +static int sunxi_reset_free(struct reset_ctl *reset_ctl)
> +{
> + debug("%s: (RST#%ld)\n", __func__, reset_ctl->id);
> +
> + return 0;
> +}
> +
> +static int sunxi_set_reset(struct reset_ctl *reset_ctl, bool on)
> +{
> + struct sunxi_reset_priv *priv = dev_get_priv(reset_ctl->dev);
> + const struct ccu_reset *reset = priv_to_reset(priv, reset_ctl->id);
> + u32 reg;
> +
> + if (!(reset->flags & CCU_CLK_F_INIT_DONE)) {
> + printf("%s: (RST#%ld) unhandled\n", __func__, reset_ctl->id);
> + return 0;
> + }
> +
> + debug("%s: (RST#%ld) off#0x%x, BIT(%d)\n", __func__,
> + reset_ctl->id, reset->off, ilog2(reset->bit));
> +
> + reg = readl(priv->base + reset->off);
> + if (on)
> + reg |= reset->bit;
> + else
> + reg &= ~reset->bit;
> +
> + writel(reg, priv->base + reset->off);
> +
> + return 0;
> +}
> +
> +static int sunxi_reset_assert(struct reset_ctl *reset_ctl)
> +{
> + return sunxi_set_reset(reset_ctl, false);
> +}
> +
> +static int sunxi_reset_deassert(struct reset_ctl *reset_ctl)
> +{
> + return sunxi_set_reset(reset_ctl, true);
> +}
> +
> +struct reset_ops sunxi_reset_ops = {
> + .request = sunxi_reset_request,
> + .free = sunxi_reset_free,
> + .rst_assert = sunxi_reset_assert,
> + .rst_deassert = sunxi_reset_deassert,
> +};
> +
> +static int sunxi_reset_probe(struct udevice *dev)
> +{
> + struct sunxi_reset_priv *priv = dev_get_priv(dev);
> +
> + priv->base = dev_read_addr_ptr(dev);
> +
> + return 0;
> +}
> +
> +int sunxi_reset_bind(struct udevice *dev, ulong count)
> +{
> + struct udevice *rst_dev;
> + struct sunxi_reset_priv *priv;
> + int ret;
> +
> + ret = device_bind_driver_to_node(dev, "sunxi_reset", "reset",
> + dev_ofnode(dev), &rst_dev);
> + if (ret) {
> + debug("failed to bind sunxi_reset driver (ret=%d)\n", ret);
> + return ret;
> + }
> + priv = malloc(sizeof(struct sunxi_reset_priv));
> + priv->count = count;
> + priv->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
> + rst_dev->priv = priv;
> +
> + return 0;
> +}
> +
> +U_BOOT_DRIVER(sunxi_reset) = {
> + .name = "sunxi_reset",
> + .id = UCLASS_RESET,
> + .ops = &sunxi_reset_ops,
> + .probe = sunxi_reset_probe,
> + .priv_auto_alloc_size = sizeof(struct sunxi_reset_priv),
> +};
>
next prev parent reply other threads:[~2019-01-10 0:50 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-31 16:59 [U-Boot] [PATCH v5 00/26] clk: Add Allwinner CLK, RESET support Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 01/26] clk: Add Allwinner A64 CLK driver Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 02/26] reset: Add Allwinner RESET driver Jagan Teki
2019-01-10 0:50 ` André Przywara [this message]
2018-12-31 16:59 ` [U-Boot] [PATCH v5 03/26] clk: sunxi: Add Allwinner H3/H5 CLK driver Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 04/26] clk: sunxi: Add Allwinner A10/A20 " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 05/26] clk: sunxi: Add Allwinner A10s/A13 " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 06/26] clk: sunxi: Add Allwinner A31 " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 07/26] clk: sunxi: Add Allwinner A23/A33 " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 08/26] clk: sunxi: Add Allwinner A83T " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 09/26] clk: sunxi: Add Allwinner R40 " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 10/26] clk: sunxi: Add Allwinner V3S " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 11/26] clk: sunxi: Implement UART clocks Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 12/26] clk: sunxi: Implement UART resets Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 13/26] clk: sunxi: Add Allwinner H6 CLK driver Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 14/26] sunxi: A64: Update sun50i-a64-ccu.h Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 15/26] clk: sunxi: Add ccu clock tree support Jagan Teki
2019-01-07 1:03 ` André Przywara
2019-01-07 13:01 ` Maxime Ripard
2019-01-07 14:09 ` Andre Przywara
2019-01-07 18:25 ` Maxime Ripard
2019-01-08 10:57 ` Jagan Teki
2019-01-08 11:39 ` Andre Przywara
2019-01-08 19:12 ` Jagan Teki
2019-01-10 0:50 ` André Przywara
2019-01-10 18:31 ` Jagan Teki
2019-01-08 11:25 ` Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 16/26] sunxi: Enable CLK Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 17/26] phy: sun4i-usb: Use CLK and RESET support Jagan Teki
2018-12-31 18:29 ` Marek Vasut
2018-12-31 18:38 ` Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 18/26] reset: Add reset valid Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 19/26] musb-new: sunxi: Use CLK and RESET support Jagan Teki
2018-12-31 18:30 ` Marek Vasut
2018-12-31 16:59 ` [U-Boot] [PATCH v5 20/26] sunxi: usb: Switch to Generic host controllers Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 21/26] usb: host: Drop [e-o]hci-sunxi drivers Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 22/26] clk: sunxi: Implement SPI clocks Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 23/26] spi: sun4i: Add CLK support Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 24/26] clk: sunxi: Implement A64 SPI clocks, resets Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 25/26] spi: Add Allwinner A31 SPI driver Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 26/26] board: sopine: Enable SPI/SPI-FLASH Jagan Teki
2019-01-07 13:04 ` Maxime Ripard
2019-01-22 16:32 ` Alexander Graf
2019-01-22 16:40 ` Andre Przywara
2019-01-22 16:47 ` Tom Rini
2019-01-06 9:39 ` [U-Boot] [PATCH v5 00/26] clk: Add Allwinner CLK, RESET support Jagan Teki
2019-01-06 13:17 ` André Przywara
2019-01-06 19:22 ` Jagan Teki
2019-01-07 1:21 ` André Przywara
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