From: Jagan Teki <jagan@amarulasolutions.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v5 12/26] clk: sunxi: Implement UART resets
Date: Mon, 31 Dec 2018 22:29:13 +0530 [thread overview]
Message-ID: <20181231165927.13803-13-jagan@amarulasolutions.com> (raw)
In-Reply-To: <20181231165927.13803-1-jagan@amarulasolutions.com>
Implement UART resets for all relevant Allwinner SoC
clock drivers via ccu reset table.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/clk/sunxi/clk_a23.c | 6 ++++++
drivers/clk/sunxi/clk_a31.c | 7 +++++++
drivers/clk/sunxi/clk_a64.c | 6 ++++++
drivers/clk/sunxi/clk_a83t.c | 6 ++++++
drivers/clk/sunxi/clk_h3.c | 5 +++++
drivers/clk/sunxi/clk_r40.c | 9 +++++++++
drivers/clk/sunxi/clk_v3s.c | 4 ++++
7 files changed, 43 insertions(+)
diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index 63004b881d..4661a33191 100644
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -38,6 +38,12 @@ static struct ccu_reset a23_resets[] = {
[RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
[RST_BUS_EHCI] = RESET(0x2c0, BIT(26)),
[RST_BUS_OHCI] = RESET(0x2c0, BIT(29)),
+
+ [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
+ [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
+ [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
+ [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
+ [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
};
static const struct ccu_desc a23_ccu_desc = {
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index c01d2a3549..b05bea5b82 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -46,6 +46,13 @@ static struct ccu_reset a31_resets[] = {
[RST_AHB1_OHCI0] = RESET(0x2c0, BIT(29)),
[RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)),
[RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)),
+
+ [RST_APB2_UART0] = RESET(0x2d8, BIT(16)),
+ [RST_APB2_UART1] = RESET(0x2d8, BIT(17)),
+ [RST_APB2_UART2] = RESET(0x2d8, BIT(18)),
+ [RST_APB2_UART3] = RESET(0x2d8, BIT(19)),
+ [RST_APB2_UART4] = RESET(0x2d8, BIT(20)),
+ [RST_APB2_UART5] = RESET(0x2d8, BIT(21)),
};
static const struct ccu_desc a31_ccu_desc = {
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index b427e3adda..162ec769d6 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -43,6 +43,12 @@ static const struct ccu_reset a64_resets[] = {
[RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
[RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
[RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
+
+ [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
+ [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
+ [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
+ [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
+ [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
};
static const struct ccu_desc a64_ccu_desc = {
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index fbffa3bf5f..3fe96ccd84 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -40,6 +40,12 @@ static struct ccu_reset a83t_resets[] = {
[RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
[RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
[RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
+
+ [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
+ [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
+ [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
+ [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
+ [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
};
static const struct ccu_desc a83t_ccu_desc = {
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index f706e77dee..89f59dbea3 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -53,6 +53,11 @@ static struct ccu_reset h3_resets[] = {
[RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
[RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)),
[RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)),
+
+ [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
+ [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
+ [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
+ [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
};
static const struct ccu_desc h3_ccu_desc = {
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index 3405b39c46..a95017f12e 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -50,6 +50,15 @@ static struct ccu_reset r40_resets[] = {
[RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
[RST_BUS_OHCI1] = RESET(0x2c0, BIT(30)),
[RST_BUS_OHCI2] = RESET(0x2c0, BIT(31)),
+
+ [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
+ [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
+ [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
+ [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
+ [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
+ [RST_BUS_UART5] = RESET(0x2d8, BIT(21)),
+ [RST_BUS_UART6] = RESET(0x2d8, BIT(22)),
+ [RST_BUS_UART7] = RESET(0x2d8, BIT(23)),
};
static const struct ccu_desc r40_ccu_desc = {
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index a662bc3e93..867b029172 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -26,6 +26,10 @@ static struct ccu_reset v3s_resets[] = {
[RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
[RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
+
+ [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
+ [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
+ [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
};
static const struct ccu_desc v3s_ccu_desc = {
--
2.18.0.321.gffc6fa0e3
next prev parent reply other threads:[~2018-12-31 16:59 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-31 16:59 [U-Boot] [PATCH v5 00/26] clk: Add Allwinner CLK, RESET support Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 01/26] clk: Add Allwinner A64 CLK driver Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 02/26] reset: Add Allwinner RESET driver Jagan Teki
2019-01-10 0:50 ` André Przywara
2018-12-31 16:59 ` [U-Boot] [PATCH v5 03/26] clk: sunxi: Add Allwinner H3/H5 CLK driver Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 04/26] clk: sunxi: Add Allwinner A10/A20 " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 05/26] clk: sunxi: Add Allwinner A10s/A13 " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 06/26] clk: sunxi: Add Allwinner A31 " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 07/26] clk: sunxi: Add Allwinner A23/A33 " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 08/26] clk: sunxi: Add Allwinner A83T " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 09/26] clk: sunxi: Add Allwinner R40 " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 10/26] clk: sunxi: Add Allwinner V3S " Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 11/26] clk: sunxi: Implement UART clocks Jagan Teki
2018-12-31 16:59 ` Jagan Teki [this message]
2018-12-31 16:59 ` [U-Boot] [PATCH v5 13/26] clk: sunxi: Add Allwinner H6 CLK driver Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 14/26] sunxi: A64: Update sun50i-a64-ccu.h Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 15/26] clk: sunxi: Add ccu clock tree support Jagan Teki
2019-01-07 1:03 ` André Przywara
2019-01-07 13:01 ` Maxime Ripard
2019-01-07 14:09 ` Andre Przywara
2019-01-07 18:25 ` Maxime Ripard
2019-01-08 10:57 ` Jagan Teki
2019-01-08 11:39 ` Andre Przywara
2019-01-08 19:12 ` Jagan Teki
2019-01-10 0:50 ` André Przywara
2019-01-10 18:31 ` Jagan Teki
2019-01-08 11:25 ` Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 16/26] sunxi: Enable CLK Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 17/26] phy: sun4i-usb: Use CLK and RESET support Jagan Teki
2018-12-31 18:29 ` Marek Vasut
2018-12-31 18:38 ` Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 18/26] reset: Add reset valid Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 19/26] musb-new: sunxi: Use CLK and RESET support Jagan Teki
2018-12-31 18:30 ` Marek Vasut
2018-12-31 16:59 ` [U-Boot] [PATCH v5 20/26] sunxi: usb: Switch to Generic host controllers Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 21/26] usb: host: Drop [e-o]hci-sunxi drivers Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 22/26] clk: sunxi: Implement SPI clocks Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 23/26] spi: sun4i: Add CLK support Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 24/26] clk: sunxi: Implement A64 SPI clocks, resets Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 25/26] spi: Add Allwinner A31 SPI driver Jagan Teki
2018-12-31 16:59 ` [U-Boot] [PATCH v5 26/26] board: sopine: Enable SPI/SPI-FLASH Jagan Teki
2019-01-07 13:04 ` Maxime Ripard
2019-01-22 16:32 ` Alexander Graf
2019-01-22 16:40 ` Andre Przywara
2019-01-22 16:47 ` Tom Rini
2019-01-06 9:39 ` [U-Boot] [PATCH v5 00/26] clk: Add Allwinner CLK, RESET support Jagan Teki
2019-01-06 13:17 ` André Przywara
2019-01-06 19:22 ` Jagan Teki
2019-01-07 1:21 ` André Przywara
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20181231165927.13803-13-jagan@amarulasolutions.com \
--to=jagan@amarulasolutions.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox