* [Qemu-devel] [v2 01/13] Abandon GEN_VSX_* macros
2013-10-11 12:53 [Qemu-devel] [v2 00/13] Stage 2 VSX Support Tom Musta
@ 2013-10-11 12:55 ` Tom Musta
2013-10-22 6:23 ` Paolo Bonzini
2013-10-11 12:57 ` [Qemu-devel] [v2 02/13] Add lxsdx Tom Musta
` (12 subsequent siblings)
13 siblings, 1 reply; 30+ messages in thread
From: Tom Musta @ 2013-10-11 12:55 UTC (permalink / raw)
To: qemu-ppc; +Cc: Tom Musta, qemu-devel
This patch eliminates the GEN_VSX_LXVNX/GEN_VSX_STXVNX macros which
did not provide significant value above the general GEN_HANDLER_E
macro.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 12 ++----------
1 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 66fcd80..bd5e89d 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9518,17 +9518,9 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
GEN_VAFORM_PAIRED(vsel, vperm, 21),
GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
-#undef GEN_VSX_LXVNX
-#define GEN_VSX_LXVNX(name, opc2, opc3) \
- GEN_HANDLER_E(lxv##name, 0x1F, opc2, opc3, 0x00000000, PPC_NONE, PPC2_VSX)
+GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
-GEN_VSX_LXVNX(d2x, 0x0C, 0x1A),
-
-#undef GEN_VSX_STXVNX
-#define GEN_VSX_STXVNX(name, opc2, opc3) \
- GEN_HANDLER_E(stxv##name, 0x1F, opc2, opc3, 0x00000000, PPC_NONE, PPC2_VSX)
-
-GEN_VSX_STXVNX(d2x, 0x0C, 0x1E),
+GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
#undef GEN_XX3FORM_DM
#define GEN_XX3FORM_DM(name, opc2, opc3) \
--
1.7.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [v2 01/13] Abandon GEN_VSX_* macros
2013-10-11 12:55 ` [Qemu-devel] [v2 01/13] Abandon GEN_VSX_* macros Tom Musta
@ 2013-10-22 6:23 ` Paolo Bonzini
0 siblings, 0 replies; 30+ messages in thread
From: Paolo Bonzini @ 2013-10-22 6:23 UTC (permalink / raw)
To: Tom Musta; +Cc: qemu-ppc, qemu-devel
Il 11/10/2013 13:55, Tom Musta ha scritto:
> This patch eliminates the GEN_VSX_LXVNX/GEN_VSX_STXVNX macros which
> did not provide significant value above the general GEN_HANDLER_E
> macro.
>
> Signed-off-by: Tom Musta <tommusta@gmail.com>
> ---
> target-ppc/translate.c | 12 ++----------
> 1 files changed, 2 insertions(+), 10 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 66fcd80..bd5e89d 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -9518,17 +9518,9 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
> GEN_VAFORM_PAIRED(vsel, vperm, 21),
> GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
>
> -#undef GEN_VSX_LXVNX
> -#define GEN_VSX_LXVNX(name, opc2,
> opc3) \
> - GEN_HANDLER_E(lxv##name, 0x1F, opc2, opc3, 0x00000000, PPC_NONE,
> PPC2_VSX)
> +GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
>
> -GEN_VSX_LXVNX(d2x, 0x0C, 0x1A),
> -
> -#undef GEN_VSX_STXVNX
> -#define GEN_VSX_STXVNX(name, opc2,
> opc3) \
> - GEN_HANDLER_E(stxv##name, 0x1F, opc2, opc3, 0x00000000, PPC_NONE,
> PPC2_VSX)
> -
> -GEN_VSX_STXVNX(d2x, 0x0C, 0x1E),
> +GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
>
> #undef GEN_XX3FORM_DM
> #define GEN_XX3FORM_DM(name, opc2, opc3) \
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Qemu-devel] [v2 02/13] Add lxsdx
2013-10-11 12:53 [Qemu-devel] [v2 00/13] Stage 2 VSX Support Tom Musta
2013-10-11 12:55 ` [Qemu-devel] [v2 01/13] Abandon GEN_VSX_* macros Tom Musta
@ 2013-10-11 12:57 ` Tom Musta
2013-10-22 6:24 ` Paolo Bonzini
2013-10-31 22:58 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2013-10-11 12:58 ` [Qemu-devel] [v2 03/13] Add lxvdsx Tom Musta
` (11 subsequent siblings)
13 siblings, 2 replies; 30+ messages in thread
From: Tom Musta @ 2013-10-11 12:57 UTC (permalink / raw)
To: qemu-ppc; +Cc: Tom Musta, qemu-devel
This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
instruction.
The lower 8 bytes of the target register are undefined; this
implementation leaves those bytes unaltered.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 16 ++++++++++++++++
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index bd5e89d..6ee0d80 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7007,6 +7007,21 @@ static inline TCGv_i64 cpu_vsrl(int n)
}
}
+static void gen_lxsdx(DisasContext *ctx)
+{
+ TCGv EA;
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
+ /* NOTE: cpu_vsrl is undefined */
+ tcg_temp_free(EA);
+}
+
static void gen_lxvd2x(DisasContext *ctx)
{
TCGv EA;
@@ -9518,6 +9533,7 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
GEN_VAFORM_PAIRED(vsel, vperm, 21),
GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
+GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
--
1.7.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [v2 02/13] Add lxsdx
2013-10-11 12:57 ` [Qemu-devel] [v2 02/13] Add lxsdx Tom Musta
@ 2013-10-22 6:24 ` Paolo Bonzini
2013-10-31 22:58 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
1 sibling, 0 replies; 30+ messages in thread
From: Paolo Bonzini @ 2013-10-22 6:24 UTC (permalink / raw)
To: Tom Musta; +Cc: qemu-ppc, qemu-devel
Il 11/10/2013 13:57, Tom Musta ha scritto:
> This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
> instruction.
>
> The lower 8 bytes of the target register are undefined; this
> implementation leaves those bytes unaltered.
>
> Signed-off-by: Tom Musta <tommusta@gmail.com>
> ---
> target-ppc/translate.c | 16 ++++++++++++++++
> 1 files changed, 16 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index bd5e89d..6ee0d80 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -7007,6 +7007,21 @@ static inline TCGv_i64 cpu_vsrl(int n)
> }
> }
>
> +static void gen_lxsdx(DisasContext *ctx)
> +{
> + TCGv EA;
> + if (unlikely(!ctx->vsx_enabled)) {
> + gen_exception(ctx, POWERPC_EXCP_VSXU);
> + return;
> + }
> + gen_set_access_type(ctx, ACCESS_INT);
> + EA = tcg_temp_new();
> + gen_addr_reg_index(ctx, EA);
> + gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
> + /* NOTE: cpu_vsrl is undefined */
> + tcg_temp_free(EA);
> +}
> +
> static void gen_lxvd2x(DisasContext *ctx)
> {
> TCGv EA;
> @@ -9518,6 +9533,7 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
> GEN_VAFORM_PAIRED(vsel, vperm, 21),
> GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
>
> +GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
> GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
>
> GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [Qemu-ppc] [v2 02/13] Add lxsdx
2013-10-11 12:57 ` [Qemu-devel] [v2 02/13] Add lxsdx Tom Musta
2013-10-22 6:24 ` Paolo Bonzini
@ 2013-10-31 22:58 ` Alexander Graf
2013-11-01 12:31 ` Tom Musta
1 sibling, 1 reply; 30+ messages in thread
From: Alexander Graf @ 2013-10-31 22:58 UTC (permalink / raw)
To: Tom Musta; +Cc: open list:PReP, QEMU Developers
On 11.10.2013, at 05:57, Tom Musta <tommusta@gmail.com> wrote:
> This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
> instruction.
>
> The lower 8 bytes of the target register are undefined; this
> implementation leaves those bytes unaltered.
>
> Signed-off-by: Tom Musta <tommusta@gmail.com>
The diff seems to be broken. Patchworks and my mail client show 2 spaces in "already existing code" parts of the patch.
Alex
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index bd5e89d..6ee0d80 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7007,6 +7007,21 @@ static inline TCGv_i64 cpu_vsrl(int n)
}
}
+static void gen_lxsdx(DisasContext *ctx)
+{
+ TCGv EA;
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
+ /* NOTE: cpu_vsrl is undefined */
+ tcg_temp_free(EA);
+}
+
static void gen_lxvd2x(DisasContext *ctx)
{
TCGv EA;
@@ -9518,6 +9533,7 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
GEN_VAFORM_PAIRED(vsel, vperm, 21),
GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
+GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [Qemu-ppc] [v2 02/13] Add lxsdx
2013-10-31 22:58 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
@ 2013-11-01 12:31 ` Tom Musta
0 siblings, 0 replies; 30+ messages in thread
From: Tom Musta @ 2013-11-01 12:31 UTC (permalink / raw)
To: Alexander Graf; +Cc: PReP, QEMU Developers
On 10/31/2013 5:58 PM, Alexander Graf wrote:
>
> On 11.10.2013, at 05:57, Tom Musta <tommusta@gmail.com> wrote:
>
>> This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
>> instruction.
>>
>> The lower 8 bytes of the target register are undefined; this
>> implementation leaves those bytes unaltered.
>>
>> Signed-off-by: Tom Musta <tommusta@gmail.com>
>
> The diff seems to be broken. Patchworks and my mail client show 2 spaces in "already existing code" parts of the patch.
>
>
> Alex
Arrgh. Sorry about that.
I am still fighting with my email client. But I have also now installed and configured git send-email. So I will resubmit the entire patch series.
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Qemu-devel] [v2 03/13] Add lxvdsx
2013-10-11 12:53 [Qemu-devel] [v2 00/13] Stage 2 VSX Support Tom Musta
2013-10-11 12:55 ` [Qemu-devel] [v2 01/13] Abandon GEN_VSX_* macros Tom Musta
2013-10-11 12:57 ` [Qemu-devel] [v2 02/13] Add lxsdx Tom Musta
@ 2013-10-11 12:58 ` Tom Musta
2013-10-22 6:24 ` Paolo Bonzini
2013-10-11 12:59 ` [Qemu-devel] [v2 04/13] Add lxvw4x Tom Musta
` (10 subsequent siblings)
13 siblings, 1 reply; 30+ messages in thread
From: Tom Musta @ 2013-10-11 12:58 UTC (permalink / raw)
To: qemu-ppc; +Cc: Tom Musta, qemu-devel
This patch adds the Load VSX Vector Doubleword & Splat Indexed
(lxvdsx) instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 16 ++++++++++++++++
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 6ee0d80..e5021cf 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7038,6 +7038,21 @@ static void gen_lxvd2x(DisasContext *ctx)
tcg_temp_free(EA);
}
+static void gen_lxvdsx(DisasContext *ctx)
+{
+ TCGv EA;
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
+ tcg_gen_mov_tl(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
+ tcg_temp_free(EA);
+}
+
static void gen_stxvd2x(DisasContext *ctx)
{
TCGv EA;
@@ -9535,6 +9550,7 @@ GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
--
1.7.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [v2 03/13] Add lxvdsx
2013-10-11 12:58 ` [Qemu-devel] [v2 03/13] Add lxvdsx Tom Musta
@ 2013-10-22 6:24 ` Paolo Bonzini
0 siblings, 0 replies; 30+ messages in thread
From: Paolo Bonzini @ 2013-10-22 6:24 UTC (permalink / raw)
To: Tom Musta; +Cc: qemu-ppc, qemu-devel
Il 11/10/2013 13:58, Tom Musta ha scritto:
> This patch adds the Load VSX Vector Doubleword & Splat Indexed
> (lxvdsx) instruction.
>
> Signed-off-by: Tom Musta <tommusta@gmail.com>
> ---
> target-ppc/translate.c | 16 ++++++++++++++++
> 1 files changed, 16 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 6ee0d80..e5021cf 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -7038,6 +7038,21 @@ static void gen_lxvd2x(DisasContext *ctx)
> tcg_temp_free(EA);
> }
>
> +static void gen_lxvdsx(DisasContext *ctx)
> +{
> + TCGv EA;
> + if (unlikely(!ctx->vsx_enabled)) {
> + gen_exception(ctx, POWERPC_EXCP_VSXU);
> + return;
> + }
> + gen_set_access_type(ctx, ACCESS_INT);
> + EA = tcg_temp_new();
> + gen_addr_reg_index(ctx, EA);
> + gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
> + tcg_gen_mov_tl(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
> + tcg_temp_free(EA);
> +}
> +
> static void gen_stxvd2x(DisasContext *ctx)
> {
> TCGv EA;
> @@ -9535,6 +9550,7 @@ GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
>
> GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
> GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
> +GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
>
> GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Qemu-devel] [v2 04/13] Add lxvw4x
2013-10-11 12:53 [Qemu-devel] [v2 00/13] Stage 2 VSX Support Tom Musta
` (2 preceding siblings ...)
2013-10-11 12:58 ` [Qemu-devel] [v2 03/13] Add lxvdsx Tom Musta
@ 2013-10-11 12:59 ` Tom Musta
2013-10-22 6:28 ` Paolo Bonzini
2013-10-11 13:00 ` [Qemu-devel] [v2 05/13] Add stxsdx Tom Musta
` (9 subsequent siblings)
13 siblings, 1 reply; 30+ messages in thread
From: Tom Musta @ 2013-10-11 12:59 UTC (permalink / raw)
To: qemu-ppc; +Cc: Tom Musta, qemu-devel
This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x)
instruction.
V2: changed to use deposit_i64 per Richard Henderson's review.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 29 +++++++++++++++++++++++++++++
1 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e5021cf..064cfa1 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7053,6 +7053,34 @@ static void gen_lxvdsx(DisasContext *ctx)
tcg_temp_free(EA);
}
+static void gen_lxvw4x(DisasContext *ctx)
+{
+ TCGv EA, tmp;
+ TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
+ TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+ tmp = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ gen_qemu_ld32u(ctx, tmp, EA);
+ tcg_gen_addi_tl(EA, EA, 4);
+ gen_qemu_ld32u(ctx, xth, EA);
+ tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
+
+ tcg_gen_addi_tl(EA, EA, 4);
+ gen_qemu_ld32u(ctx, tmp, EA);
+ tcg_gen_addi_tl(EA, EA, 4);
+ gen_qemu_ld32u(ctx, xtl, EA);
+ tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
+
+ tcg_temp_free(EA);
+ tcg_temp_free(tmp);
+}
+
static void gen_stxvd2x(DisasContext *ctx)
{
TCGv EA;
@@ -9551,6 +9579,7 @@ GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
--
1.7.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [v2 04/13] Add lxvw4x
2013-10-11 12:59 ` [Qemu-devel] [v2 04/13] Add lxvw4x Tom Musta
@ 2013-10-22 6:28 ` Paolo Bonzini
0 siblings, 0 replies; 30+ messages in thread
From: Paolo Bonzini @ 2013-10-22 6:28 UTC (permalink / raw)
To: Tom Musta; +Cc: qemu-ppc, qemu-devel
Il 11/10/2013 13:59, Tom Musta ha scritto:
> This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x)
> instruction.
>
> V2: changed to use deposit_i64 per Richard Henderson's review.
>
> Signed-off-by: Tom Musta <tommusta@gmail.com>
> ---
> target-ppc/translate.c | 29 +++++++++++++++++++++++++++++
> 1 files changed, 29 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index e5021cf..064cfa1 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -7053,6 +7053,34 @@ static void gen_lxvdsx(DisasContext *ctx)
> tcg_temp_free(EA);
> }
>
> +static void gen_lxvw4x(DisasContext *ctx)
> +{
> + TCGv EA, tmp;
> + TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
> + TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
> + if (unlikely(!ctx->vsx_enabled)) {
> + gen_exception(ctx, POWERPC_EXCP_VSXU);
> + return;
> + }
> + gen_set_access_type(ctx, ACCESS_INT);
> + EA = tcg_temp_new();
> + tmp = tcg_temp_new();
> + gen_addr_reg_index(ctx, EA);
> + gen_qemu_ld32u(ctx, tmp, EA);
> + tcg_gen_addi_tl(EA, EA, 4);
> + gen_qemu_ld32u(ctx, xth, EA);
> + tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
> +
> + tcg_gen_addi_tl(EA, EA, 4);
> + gen_qemu_ld32u(ctx, tmp, EA);
> + tcg_gen_addi_tl(EA, EA, 4);
> + gen_qemu_ld32u(ctx, xtl, EA);
> + tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
> +
> + tcg_temp_free(EA);
> + tcg_temp_free(tmp);
> +}
> +
> static void gen_stxvd2x(DisasContext *ctx)
> {
> TCGv EA;
> @@ -9551,6 +9579,7 @@ GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
> GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
> GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
> GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
> +GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
>
> GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Qemu-devel] [v2 05/13] Add stxsdx
2013-10-11 12:53 [Qemu-devel] [v2 00/13] Stage 2 VSX Support Tom Musta
` (3 preceding siblings ...)
2013-10-11 12:59 ` [Qemu-devel] [v2 04/13] Add lxvw4x Tom Musta
@ 2013-10-11 13:00 ` Tom Musta
2013-10-22 6:29 ` Paolo Bonzini
2013-10-11 13:01 ` [Qemu-devel] [v2 06/13] Add stxvw4x Tom Musta
` (8 subsequent siblings)
13 siblings, 1 reply; 30+ messages in thread
From: Tom Musta @ 2013-10-11 13:00 UTC (permalink / raw)
To: qemu-ppc; +Cc: Tom Musta, qemu-devel
This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx)
instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 15 +++++++++++++++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 064cfa1..46b8380 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7081,6 +7081,20 @@ static void gen_lxvw4x(DisasContext *ctx)
tcg_temp_free(tmp);
}
+static void gen_stxsdx(DisasContext *ctx)
+{
+ TCGv EA;
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
+ tcg_temp_free(EA);
+}
+
static void gen_stxvd2x(DisasContext *ctx)
{
TCGv EA;
@@ -9581,6 +9595,7 @@ GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
#undef GEN_XX3FORM_DM
--
1.7.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [v2 05/13] Add stxsdx
2013-10-11 13:00 ` [Qemu-devel] [v2 05/13] Add stxsdx Tom Musta
@ 2013-10-22 6:29 ` Paolo Bonzini
0 siblings, 0 replies; 30+ messages in thread
From: Paolo Bonzini @ 2013-10-22 6:29 UTC (permalink / raw)
To: Tom Musta; +Cc: qemu-ppc, qemu-devel
Il 11/10/2013 14:00, Tom Musta ha scritto:
> This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx)
> instruction.
>
> Signed-off-by: Tom Musta <tommusta@gmail.com>
> ---
> target-ppc/translate.c | 15 +++++++++++++++
> 1 files changed, 15 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 064cfa1..46b8380 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -7081,6 +7081,20 @@ static void gen_lxvw4x(DisasContext *ctx)
> tcg_temp_free(tmp);
> }
>
> +static void gen_stxsdx(DisasContext *ctx)
> +{
> + TCGv EA;
> + if (unlikely(!ctx->vsx_enabled)) {
> + gen_exception(ctx, POWERPC_EXCP_VSXU);
> + return;
> + }
> + gen_set_access_type(ctx, ACCESS_INT);
> + EA = tcg_temp_new();
> + gen_addr_reg_index(ctx, EA);
> + gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
> + tcg_temp_free(EA);
> +}
> +
> static void gen_stxvd2x(DisasContext *ctx)
> {
> TCGv EA;
> @@ -9581,6 +9595,7 @@ GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0,
> PPC_NONE, PPC2_VSX),
> GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
> GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
>
> +GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
> GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
>
> #undef GEN_XX3FORM_DM
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Qemu-devel] [v2 06/13] Add stxvw4x
2013-10-11 12:53 [Qemu-devel] [v2 00/13] Stage 2 VSX Support Tom Musta
` (4 preceding siblings ...)
2013-10-11 13:00 ` [Qemu-devel] [v2 05/13] Add stxsdx Tom Musta
@ 2013-10-11 13:01 ` Tom Musta
2013-10-22 6:29 ` Paolo Bonzini
2013-10-11 13:02 ` [Qemu-devel] [v2 07/13] Add VSX Scalar Move Instructions Tom Musta
` (7 subsequent siblings)
13 siblings, 1 reply; 30+ messages in thread
From: Tom Musta @ 2013-10-11 13:01 UTC (permalink / raw)
To: qemu-ppc; +Cc: Tom Musta, qemu-devel
This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x)
instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 28 ++++++++++++++++++++++++++++
1 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 46b8380..8d53cb5 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7111,6 +7111,33 @@ static void gen_stxvd2x(DisasContext *ctx)
tcg_temp_free(EA);
}
+static void gen_stxvw4x(DisasContext *ctx)
+{
+ TCGv EA, tmp;
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ tmp = tcg_temp_new();
+
+ tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
+ gen_qemu_st32(ctx, tmp, EA);
+ tcg_gen_addi_tl(EA, EA, 4);
+ gen_qemu_st32(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
+
+ tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
+ tcg_gen_addi_tl(EA, EA, 4);
+ gen_qemu_st32(ctx, tmp, EA);
+ tcg_gen_addi_tl(EA, EA, 4);
+ gen_qemu_st32(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
+
+ tcg_temp_free(EA);
+ tcg_temp_free(tmp);
+}
+
static void gen_xxpermdi(DisasContext *ctx)
{
TCGv_i64 xh, xl;
@@ -9597,6 +9624,7 @@ GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
#undef GEN_XX3FORM_DM
#define GEN_XX3FORM_DM(name, opc2, opc3) \
--
1.7.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [v2 06/13] Add stxvw4x
2013-10-11 13:01 ` [Qemu-devel] [v2 06/13] Add stxvw4x Tom Musta
@ 2013-10-22 6:29 ` Paolo Bonzini
0 siblings, 0 replies; 30+ messages in thread
From: Paolo Bonzini @ 2013-10-22 6:29 UTC (permalink / raw)
To: Tom Musta; +Cc: qemu-ppc, qemu-devel
Il 11/10/2013 14:01, Tom Musta ha scritto:
> This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x)
> instruction.
>
> Signed-off-by: Tom Musta <tommusta@gmail.com>
> ---
> target-ppc/translate.c | 28 ++++++++++++++++++++++++++++
> 1 files changed, 28 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 46b8380..8d53cb5 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -7111,6 +7111,33 @@ static void gen_stxvd2x(DisasContext *ctx)
> tcg_temp_free(EA);
> }
>
> +static void gen_stxvw4x(DisasContext *ctx)
> +{
> + TCGv EA, tmp;
> + if (unlikely(!ctx->vsx_enabled)) {
> + gen_exception(ctx, POWERPC_EXCP_VSXU);
> + return;
> + }
> + gen_set_access_type(ctx, ACCESS_INT);
> + EA = tcg_temp_new();
> + gen_addr_reg_index(ctx, EA);
> + tmp = tcg_temp_new();
> +
> + tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
> + gen_qemu_st32(ctx, tmp, EA);
> + tcg_gen_addi_tl(EA, EA, 4);
> + gen_qemu_st32(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
> +
> + tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
> + tcg_gen_addi_tl(EA, EA, 4);
> + gen_qemu_st32(ctx, tmp, EA);
> + tcg_gen_addi_tl(EA, EA, 4);
> + gen_qemu_st32(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
> +
> + tcg_temp_free(EA);
> + tcg_temp_free(tmp);
> +}
> +
> static void gen_xxpermdi(DisasContext *ctx)
> {
> TCGv_i64 xh, xl;
> @@ -9597,6 +9624,7 @@ GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0,
> PPC_NONE, PPC2_VSX),
>
> GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
> GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
> +GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
>
> #undef GEN_XX3FORM_DM
> #define GEN_XX3FORM_DM(name, opc2, opc3) \
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Qemu-devel] [v2 07/13] Add VSX Scalar Move Instructions
2013-10-11 12:53 [Qemu-devel] [v2 00/13] Stage 2 VSX Support Tom Musta
` (5 preceding siblings ...)
2013-10-11 13:01 ` [Qemu-devel] [v2 06/13] Add stxvw4x Tom Musta
@ 2013-10-11 13:02 ` Tom Musta
2013-10-22 6:31 ` Paolo Bonzini
2013-10-11 13:03 ` [Qemu-devel] [v2 08/13] Add VSX Vector " Tom Musta
` (6 subsequent siblings)
13 siblings, 1 reply; 30+ messages in thread
From: Tom Musta @ 2013-10-11 13:02 UTC (permalink / raw)
To: qemu-ppc; +Cc: Tom Musta, qemu-devel
This patch adds the VSX scalar move instructions:
- xsabsdp (Scalar Absolute Value Double-Precision)
- xsnabspd (Scalar Negative Absolute Value Double-Precision)
- xsnegdp (Scalar Negate Double-Precision)
- xscpsgndp (Scalar Copy Sign Double-Precision)
A common generator macro (VSX_SCALAR_MOVE) is added since these
instructions vary only slightly from each other.
Macros to support VSX XX2 and XX3 form opcodes are also added.
These macros handle the overloading of "opcode 2" space (instruction
bits 26:30) caused by AX and BX bits (29 and 30, respectively).
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 66 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 8d53cb5..36e04b0 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7167,6 +7167,55 @@ static void gen_xxpermdi(DisasContext *ctx)
tcg_temp_free(xh);
tcg_temp_free(xl);
}
+#define OP_ABS 1
+#define OP_NABS 2
+#define OP_NEG 3
+#define OP_CPSGN 4
+#define SGN_MASK_DP 0x8000000000000000ul
+#define SGN_MASK_SP 0x8000000080000000ul
+
+#define VSX_SCALAR_MOVE(name, op, sgn_mask) \
+static void glue(gen_, name)(DisasContext * ctx) \
+ { \
+ TCGv_i64 xb; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ xb = tcg_temp_new(); \
+ tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
+ switch (op) { \
+ case OP_ABS: { \
+ tcg_gen_andi_i64(xb, xb, ~(sgn_mask)); \
+ break; \
+ } \
+ case OP_NABS: { \
+ tcg_gen_ori_i64(xb, xb, (sgn_mask)); \
+ break; \
+ } \
+ case OP_NEG: { \
+ tcg_gen_xori_i64(xb, xb, (sgn_mask)); \
+ break; \
+ } \
+ case OP_CPSGN: { \
+ TCGv_i64 xa = tcg_temp_new(); \
+ tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
+ tcg_gen_andi_i64(xa, xa, (sgn_mask)); \
+ tcg_gen_andi_i64(xb, xb, ~(sgn_mask)); \
+ tcg_gen_or_i64(xb, xb, xa); \
+ tcg_temp_free(xa); \
+ break; \
+ } \
+ } \
+ tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
+ tcg_temp_free(xb); \
+ }
+
+VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
+VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
+VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
+VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
+
/*** SPE extension ***/
/* Register moves */
@@ -9626,6 +9675,18 @@ GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
+#undef GEN_XX2FORM
+#define GEN_XX2FORM(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
+
+#undef GEN_XX3FORM
+#define GEN_XX3FORM(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
+
#undef GEN_XX3FORM_DM
#define GEN_XX3FORM_DM(name, opc2, opc3) \
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
@@ -9645,6 +9706,11 @@ GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE,
PPC2_VSX),\
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
+GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
+GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
+GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
+GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
+
GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
#undef GEN_SPE
--
1.7.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [v2 07/13] Add VSX Scalar Move Instructions
2013-10-11 13:02 ` [Qemu-devel] [v2 07/13] Add VSX Scalar Move Instructions Tom Musta
@ 2013-10-22 6:31 ` Paolo Bonzini
2013-10-22 12:57 ` Tom Musta
2013-10-22 15:15 ` [Qemu-devel] [V3 " Tom Musta
0 siblings, 2 replies; 30+ messages in thread
From: Paolo Bonzini @ 2013-10-22 6:31 UTC (permalink / raw)
To: Tom Musta; +Cc: qemu-ppc, qemu-devel
Il 11/10/2013 14:02, Tom Musta ha scritto:
>
> + case OP_CPSGN: { \
> + TCGv_i64 xa = tcg_temp_new(); \
> + tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
> + tcg_gen_andi_i64(xa, xa, (sgn_mask)); \
> + tcg_gen_andi_i64(xb, xb, ~(sgn_mask)); \
> + tcg_gen_or_i64(xb, xb, xa); \
> + tcg_temp_free(xa); \
> + break; \
You might get slightly better generated code if you move the sgn_mask
immediate to a temporary and then use and+andc.
Paolo
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [v2 07/13] Add VSX Scalar Move Instructions
2013-10-22 6:31 ` Paolo Bonzini
@ 2013-10-22 12:57 ` Tom Musta
2013-10-22 15:15 ` [Qemu-devel] [V3 " Tom Musta
1 sibling, 0 replies; 30+ messages in thread
From: Tom Musta @ 2013-10-22 12:57 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-ppc, qemu-devel
On 10/22/2013 1:31 AM, Paolo Bonzini wrote:
> Il 11/10/2013 14:02, Tom Musta ha scritto:
>>
>> + case OP_CPSGN: { \
>> + TCGv_i64 xa = tcg_temp_new(); \
>> + tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
>> + tcg_gen_andi_i64(xa, xa, (sgn_mask)); \
>> + tcg_gen_andi_i64(xb, xb, ~(sgn_mask)); \
>> + tcg_gen_or_i64(xb, xb, xa); \
>> + tcg_temp_free(xa); \
>> + break; \
>
> You might get slightly better generated code if you move the sgn_mask
> immediate to a temporary and then use and+andc.
>
> Paolo
>
Thank you for the suggestion, Paolo. I will recode, retest and resubmit this one and patch 8.
^ permalink raw reply [flat|nested] 30+ messages in thread* [Qemu-devel] [V3 07/13] Add VSX Scalar Move Instructions
2013-10-22 6:31 ` Paolo Bonzini
2013-10-22 12:57 ` Tom Musta
@ 2013-10-22 15:15 ` Tom Musta
1 sibling, 0 replies; 30+ messages in thread
From: Tom Musta @ 2013-10-22 15:15 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel; +Cc: qemu-ppc
From 37b74a6ca422e62b349692188c457bf6127a3a83 Mon Sep 17 00:00:00 2001
From: Tom Musta <tommusta@gmail.com>
Date: Thu, 3 Oct 2013 10:09:50 -0500
Subject: [PATCH 07/13] Add VSX Scalar Move Instructions
To: qemu-ppc@nongnu.org
This patch adds the VSX scalar move instructions:
- xsabsdp (Scalar Absolute Value Double-Precision)
- xsnabspd (Scalar Negative Absolute Value Double-Precision)
- xsnegdp (Scalar Negate Double-Precision)
- xscpsgndp (Scalar Copy Sign Double-Precision)
A common generator macro (VSX_SCALAR_MOVE) is added since these
instructions vary only slightly from each other.
Macros to support VSX XX2 and XX3 form opcodes are also added.
These macros handle the overloading of "opcode 2" space (instruction
bits 26:30) caused by AX and BX bits (29 and 30, respectively).
V3: Per feedback from Paolo Bonzini, moved the sign mask into a
temporary and used andc.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 69 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 047e876..7409f77 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7163,6 +7163,58 @@ static void gen_xxpermdi(DisasContext *ctx)
tcg_temp_free(xh);
tcg_temp_free(xl);
}
+#define OP_ABS 1
+#define OP_NABS 2
+#define OP_NEG 3
+#define OP_CPSGN 4
+#define SGN_MASK_DP 0x8000000000000000ul
+#define SGN_MASK_SP 0x8000000080000000ul
+
+#define VSX_SCALAR_MOVE(name, op, sgn_mask) \
+static void glue(gen_, name)(DisasContext * ctx) \
+ { \
+ TCGv_i64 xb, sgm; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ xb = tcg_temp_new(); \
+ sgm = tcg_temp_new(); \
+ tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
+ tcg_gen_movi_i64(sgm, sgn_mask); \
+ switch (op) { \
+ case OP_ABS: { \
+ tcg_gen_andc_i64(xb, xb, sgm); \
+ break; \
+ } \
+ case OP_NABS: { \
+ tcg_gen_or_i64(xb, xb, sgm); \
+ break; \
+ } \
+ case OP_NEG: { \
+ tcg_gen_xor_i64(xb, xb, sgm); \
+ break; \
+ } \
+ case OP_CPSGN: { \
+ TCGv_i64 xa = tcg_temp_new(); \
+ tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
+ tcg_gen_and_i64(xa, xa, sgm); \
+ tcg_gen_andc_i64(xb, xb, sgm); \
+ tcg_gen_or_i64(xb, xb, xa); \
+ tcg_temp_free(xa); \
+ break; \
+ } \
+ } \
+ tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
+ tcg_temp_free(xb); \
+ tcg_temp_free(sgm); \
+ }
+
+VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
+VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
+VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
+VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
+
/*** SPE extension ***/
/* Register moves */
@@ -9622,6 +9674,18 @@ GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
+#undef GEN_XX2FORM
+#define GEN_XX2FORM(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
+
+#undef GEN_XX3FORM
+#define GEN_XX3FORM(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
+
#undef GEN_XX3FORM_DM
#define GEN_XX3FORM_DM(name, opc2, opc3) \
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
@@ -9641,6 +9705,11 @@ GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
+GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
+GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
+GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
+GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
+
GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
#undef GEN_SPE
--
1.7.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [v2 08/13] Add VSX Vector Move Instructions
2013-10-11 12:53 [Qemu-devel] [v2 00/13] Stage 2 VSX Support Tom Musta
` (6 preceding siblings ...)
2013-10-11 13:02 ` [Qemu-devel] [v2 07/13] Add VSX Scalar Move Instructions Tom Musta
@ 2013-10-11 13:03 ` Tom Musta
2013-10-22 6:34 ` Paolo Bonzini
2013-10-11 13:04 ` [Qemu-devel] [v2 09/13] Add Power7 VSX Logical Instructions Tom Musta
` (5 subsequent siblings)
13 siblings, 1 reply; 30+ messages in thread
From: Tom Musta @ 2013-10-11 13:03 UTC (permalink / raw)
To: qemu-ppc; +Cc: Tom Musta, qemu-devel
This patch adds the vector move instructions:
- xvabsdp - Vector Absolute Value Double-Precision
- xvnabsdp - Vector Negative Absolute Value Double-Precision
- xvnegdp - Vector Negate Double-Precision
- xvcpsgndp - Vector Copy Sign Double-Precision
- xvabssp - Vector Absolute Value Single-Precision
- xvnabssp - Vector Negative Absolute Value Single-Precision
- xvnegsp - Vector Negate Single-Precision
- xvcpsgnsp - Vector Copy Sign Single-Precision
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 68 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 36e04b0..03a352d 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7216,6 +7216,66 @@ VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
+#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
+static void glue(gen_, name)(DisasContext * ctx) \
+ { \
+ TCGv_i64 xbh, xbl; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ xbh = tcg_temp_new(); \
+ xbl = tcg_temp_new(); \
+ tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
+ tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
+ switch (op) { \
+ case OP_ABS: { \
+ tcg_gen_andi_i64(xbh, xbh, ~(sgn_mask)); \
+ tcg_gen_andi_i64(xbl, xbl, ~(sgn_mask)); \
+ break; \
+ } \
+ case OP_NABS: { \
+ tcg_gen_ori_i64(xbh, xbh, (sgn_mask)); \
+ tcg_gen_ori_i64(xbl, xbl, (sgn_mask)); \
+ break; \
+ } \
+ case OP_NEG: { \
+ tcg_gen_xori_i64(xbh, xbh, (sgn_mask)); \
+ tcg_gen_xori_i64(xbl, xbl, (sgn_mask)); \
+ break; \
+ } \
+ case OP_CPSGN: { \
+ TCGv_i64 xah = tcg_temp_new(); \
+ TCGv_i64 xal = tcg_temp_new(); \
+ tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
+ tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
+ tcg_gen_andi_i64(xah, xah, (sgn_mask)); \
+ tcg_gen_andi_i64(xal, xal, (sgn_mask)); \
+ tcg_gen_andi_i64(xbh, xbh, ~(sgn_mask)); \
+ tcg_gen_andi_i64(xbl, xbl, ~(sgn_mask)); \
+ tcg_gen_or_i64(xbh, xbh, xah); \
+ tcg_gen_or_i64(xbl, xbl, xal); \
+ tcg_temp_free(xah); \
+ tcg_temp_free(xal); \
+ break; \
+ } \
+ } \
+ tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
+ tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
+ tcg_temp_free(xbh); \
+ tcg_temp_free(xbl); \
+ }
+
+VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
+VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
+VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
+VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
+
+
/*** SPE extension ***/
/* Register moves */
@@ -9711,6 +9771,14 @@ GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
+GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
+GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
+GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
+GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
+GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
+GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
+GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
+GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
#undef GEN_SPE
--
1.7.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [v2 08/13] Add VSX Vector Move Instructions
2013-10-11 13:03 ` [Qemu-devel] [v2 08/13] Add VSX Vector " Tom Musta
@ 2013-10-22 6:34 ` Paolo Bonzini
2013-10-22 15:16 ` [Qemu-devel] [V3 " Tom Musta
0 siblings, 1 reply; 30+ messages in thread
From: Paolo Bonzini @ 2013-10-22 6:34 UTC (permalink / raw)
To: Tom Musta; +Cc: qemu-ppc, qemu-devel
Il 11/10/2013 14:03, Tom Musta ha scritto:
> This patch adds the vector move instructions:
>
> - xvabsdp - Vector Absolute Value Double-Precision
> - xvnabsdp - Vector Negative Absolute Value Double-Precision
> - xvnegdp - Vector Negate Double-Precision
> - xvcpsgndp - Vector Copy Sign Double-Precision
> - xvabssp - Vector Absolute Value Single-Precision
> - xvnabssp - Vector Negative Absolute Value Single-Precision
> - xvnegsp - Vector Negate Single-Precision
> - xvcpsgnsp - Vector Copy Sign Single-Precision
>
> Signed-off-by: Tom Musta <tommusta@gmail.com>
> ---
> target-ppc/translate.c | 68
> ++++++++++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 68 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 36e04b0..03a352d 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -7216,6 +7216,66 @@ VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
> VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
> VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
>
> +#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
> +static void glue(gen_, name)(DisasContext * ctx) \
> + { \
> + TCGv_i64 xbh, xbl; \
> + if (unlikely(!ctx->vsx_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_VSXU); \
> + return; \
> + } \
> + xbh = tcg_temp_new(); \
> + xbl = tcg_temp_new(); \
> + tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
> + tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
> + switch (op) { \
> + case OP_ABS: { \
> + tcg_gen_andi_i64(xbh, xbh, ~(sgn_mask)); \
> + tcg_gen_andi_i64(xbl, xbl, ~(sgn_mask)); \
> + break; \
> + } \
> + case OP_NABS: { \
> + tcg_gen_ori_i64(xbh, xbh, (sgn_mask)); \
> + tcg_gen_ori_i64(xbl, xbl, (sgn_mask)); \
> + break; \
> + } \
> + case OP_NEG: { \
> + tcg_gen_xori_i64(xbh, xbh, (sgn_mask)); \
> + tcg_gen_xori_i64(xbl, xbl, (sgn_mask)); \
> + break; \
> + } \
> + case OP_CPSGN: { \
> + TCGv_i64 xah = tcg_temp_new(); \
> + TCGv_i64 xal = tcg_temp_new(); \
> + tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
> + tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
> + tcg_gen_andi_i64(xah, xah, (sgn_mask)); \
> + tcg_gen_andi_i64(xal, xal, (sgn_mask)); \
> + tcg_gen_andi_i64(xbh, xbh, ~(sgn_mask)); \
> + tcg_gen_andi_i64(xbl, xbl, ~(sgn_mask)); \
> + tcg_gen_or_i64(xbh, xbh, xah); \
> + tcg_gen_or_i64(xbl, xbl, xal); \
> + tcg_temp_free(xah); \
> + tcg_temp_free(xal); \
> + break; \
Same as before. Also, you may want to use a temporary for the other
cases as well, so that the constant is reused. Using andc for OP_ABS
also makes sense, since on some RISC machines 0x80000... is cheaper than
0x7FFFF... On target that lack andc, you'll just get the same code
you're generating now.
Paolo
> + } \
> + } \
> + tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
> + tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
> + tcg_temp_free(xbh); \
> + tcg_temp_free(xbl); \
> + }
> +
> +VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
> +VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
> +VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
> +VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
> +VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
> +VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
> +VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
> +VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
> +
> +
>
> /*** SPE
> extension ***/
> /* Register moves */
> @@ -9711,6 +9771,14 @@ GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
> GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
> GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
>
> +GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
> +GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
> +GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
> +GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
> +GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
> +GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
> +GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
> +GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
> GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
>
> #undef GEN_SPE
^ permalink raw reply [flat|nested] 30+ messages in thread* [Qemu-devel] [V3 08/13] Add VSX Vector Move Instructions
2013-10-22 6:34 ` Paolo Bonzini
@ 2013-10-22 15:16 ` Tom Musta
0 siblings, 0 replies; 30+ messages in thread
From: Tom Musta @ 2013-10-22 15:16 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel; +Cc: qemu-ppc
This patch adds the vector move instructions:
- xvabsdp - Vector Absolute Value Double-Precision
- xvnabsdp - Vector Negative Absolute Value Double-Precision
- xvnegdp - Vector Negate Double-Precision
- xvcpsgndp - Vector Copy Sign Double-Precision
- xvabssp - Vector Absolute Value Single-Precision
- xvnabssp - Vector Negative Absolute Value Single-Precision
- xvnegsp - Vector Negate Single-Precision
- xvcpsgnsp - Vector Copy Sign Single-Precision
V3: Per Paolo Bonzini's suggestion, used a temporary for the
sign mask and andc.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 71 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7409f77..e7d40a4 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7215,6 +7215,69 @@ VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
+#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
+static void glue(gen_, name)(DisasContext * ctx) \
+ { \
+ TCGv_i64 xbh, xbl, sgm; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ xbh = tcg_temp_new(); \
+ xbl = tcg_temp_new(); \
+ sgm = tcg_temp_new(); \
+ tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
+ tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
+ tcg_gen_movi_i64(sgm, sgn_mask); \
+ switch (op) { \
+ case OP_ABS: { \
+ tcg_gen_andc_i64(xbh, xbh, sgm); \
+ tcg_gen_andc_i64(xbl, xbl, sgm); \
+ break; \
+ } \
+ case OP_NABS: { \
+ tcg_gen_or_i64(xbh, xbh, sgm); \
+ tcg_gen_or_i64(xbl, xbl, sgm); \
+ break; \
+ } \
+ case OP_NEG: { \
+ tcg_gen_xor_i64(xbh, xbh, sgm); \
+ tcg_gen_xor_i64(xbl, xbl, sgm); \
+ break; \
+ } \
+ case OP_CPSGN: { \
+ TCGv_i64 xah = tcg_temp_new(); \
+ TCGv_i64 xal = tcg_temp_new(); \
+ tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
+ tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
+ tcg_gen_and_i64(xah, xah, sgm); \
+ tcg_gen_and_i64(xal, xal, sgm); \
+ tcg_gen_andc_i64(xbh, xbh, sgm); \
+ tcg_gen_andc_i64(xbl, xbl, sgm); \
+ tcg_gen_or_i64(xbh, xbh, xah); \
+ tcg_gen_or_i64(xbl, xbl, xal); \
+ tcg_temp_free(xah); \
+ tcg_temp_free(xal); \
+ break; \
+ } \
+ } \
+ tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
+ tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
+ tcg_temp_free(xbh); \
+ tcg_temp_free(xbl); \
+ tcg_temp_free(sgm); \
+ }
+
+VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
+VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
+VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
+VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
+
+
/*** SPE extension ***/
/* Register moves */
@@ -9710,6 +9773,14 @@ GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
+GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
+GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
+GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
+GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
+GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
+GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
+GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
+GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
#undef GEN_SPE
--
1.7.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Qemu-devel] [v2 09/13] Add Power7 VSX Logical Instructions
2013-10-11 12:53 [Qemu-devel] [v2 00/13] Stage 2 VSX Support Tom Musta
` (7 preceding siblings ...)
2013-10-11 13:03 ` [Qemu-devel] [v2 08/13] Add VSX Vector " Tom Musta
@ 2013-10-11 13:04 ` Tom Musta
2013-10-22 6:34 ` Paolo Bonzini
2013-10-11 13:05 ` [Qemu-devel] [v2 10/13] Add xxmrgh/xxmrgl Tom Musta
` (4 subsequent siblings)
13 siblings, 1 reply; 30+ messages in thread
From: Tom Musta @ 2013-10-11 13:04 UTC (permalink / raw)
To: qemu-ppc; +Cc: Tom Musta, qemu-devel
This patch adds the VSX logical instructions that are defined
by the Version 2.06 Power ISA (aka Power7):
- xxland
- xxlandc
- xxlor
- xxlxor
- xxlnor
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 29 +++++++++++++++++++++++++++++
1 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 03a352d..5056ec9 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7276,6 +7276,24 @@ VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
+#define VSX_LOGICAL(name, tcg_op) \
+static void glue(gen_, name)(DisasContext * ctx) \
+ { \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
+ cpu_vsrh(xB(ctx->opcode))); \
+ tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
+ cpu_vsrl(xB(ctx->opcode))); \
+ }
+
+VSX_LOGICAL(xxland, tcg_gen_and_tl)
+VSX_LOGICAL(xxlandc, tcg_gen_andc_tl)
+VSX_LOGICAL(xxlor, tcg_gen_or_tl)
+VSX_LOGICAL(xxlxor, tcg_gen_xor_tl)
+VSX_LOGICAL(xxlnor, tcg_gen_nor_tl)
/*** SPE extension ***/
/* Register moves */
@@ -9779,6 +9797,17 @@ GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
+
+#undef VSX_LOGICAL
+#define VSX_LOGICAL(name, opc2, opc3, fl2) \
+GEN_XX3FORM(name, opc2, opc3, fl2)
+
+VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
+VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
+VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
+VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
+VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
+
GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
#undef GEN_SPE
--
1.7.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [v2 09/13] Add Power7 VSX Logical Instructions
2013-10-11 13:04 ` [Qemu-devel] [v2 09/13] Add Power7 VSX Logical Instructions Tom Musta
@ 2013-10-22 6:34 ` Paolo Bonzini
0 siblings, 0 replies; 30+ messages in thread
From: Paolo Bonzini @ 2013-10-22 6:34 UTC (permalink / raw)
To: Tom Musta; +Cc: qemu-ppc, qemu-devel
Il 11/10/2013 14:04, Tom Musta ha scritto:
> This patch adds the VSX logical instructions that are defined
> by the Version 2.06 Power ISA (aka Power7):
>
> - xxland
> - xxlandc
> - xxlor
> - xxlxor
> - xxlnor
>
> Signed-off-by: Tom Musta <tommusta@gmail.com>
> ---
> target-ppc/translate.c | 29 +++++++++++++++++++++++++++++
> 1 files changed, 29 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 03a352d..5056ec9 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -7276,6 +7276,24 @@ VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
> VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
>
>
> +#define VSX_LOGICAL(name, tcg_op) \
> +static void glue(gen_, name)(DisasContext * ctx) \
> + { \
> + if (unlikely(!ctx->vsx_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_VSXU); \
> + return; \
> + } \
> + tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
> + cpu_vsrh(xB(ctx->opcode))); \
> + tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
> + cpu_vsrl(xB(ctx->opcode))); \
> + }
> +
> +VSX_LOGICAL(xxland, tcg_gen_and_tl)
> +VSX_LOGICAL(xxlandc, tcg_gen_andc_tl)
> +VSX_LOGICAL(xxlor, tcg_gen_or_tl)
> +VSX_LOGICAL(xxlxor, tcg_gen_xor_tl)
> +VSX_LOGICAL(xxlnor, tcg_gen_nor_tl)
>
> /*** SPE
> extension ***/
> /* Register moves */
> @@ -9779,6 +9797,17 @@ GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
> GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
> GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
> GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
> +
> +#undef VSX_LOGICAL
> +#define VSX_LOGICAL(name, opc2, opc3, fl2) \
> +GEN_XX3FORM(name, opc2, opc3, fl2)
> +
> +VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
> +VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
> +VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
> +VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
> +VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
> +
> GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
>
> #undef GEN_SPE
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Qemu-devel] [v2 10/13] Add xxmrgh/xxmrgl
2013-10-11 12:53 [Qemu-devel] [v2 00/13] Stage 2 VSX Support Tom Musta
` (8 preceding siblings ...)
2013-10-11 13:04 ` [Qemu-devel] [v2 09/13] Add Power7 VSX Logical Instructions Tom Musta
@ 2013-10-11 13:05 ` Tom Musta
2013-10-22 6:35 ` Paolo Bonzini
2013-10-11 13:06 ` [Qemu-devel] [v2 11/13] Add xxsel Tom Musta
` (3 subsequent siblings)
13 siblings, 1 reply; 30+ messages in thread
From: Tom Musta @ 2013-10-11 13:05 UTC (permalink / raw)
To: qemu-ppc; +Cc: Tom Musta, qemu-devel
This patch adds the VSX Merge High Word and VSX Merge Low Word
instructions.
V2: Now implemented using deposit (per Richard Henderson's comment)
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 41 +++++++++++++++++++++++++++++++++++++++++
1 files changed, 41 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 5056ec9..e6e8b02 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7295,6 +7295,45 @@ VSX_LOGICAL(xxlor, tcg_gen_or_tl)
VSX_LOGICAL(xxlxor, tcg_gen_xor_tl)
VSX_LOGICAL(xxlnor, tcg_gen_nor_tl)
+#define VSX_XXMRG(name, high) \
+static void glue(gen_, name)(DisasContext * ctx) \
+ { \
+ TCGv_i64 a0, a1, b0, b1; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ a0 = tcg_temp_new(); \
+ a1 = tcg_temp_new(); \
+ b0 = tcg_temp_new(); \
+ b1 = tcg_temp_new(); \
+ if (high) { \
+ tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
+ tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
+ tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
+ tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
+ } else { \
+ tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
+ tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
+ tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
+ tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
+ } \
+ tcg_gen_shri_i64(a0, a0, 32); \
+ tcg_gen_shri_i64(b0, b0, 32); \
+ tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
+ b0, a0, 32, 32); \
+ tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
+ b1, a1, 32, 32); \
+ tcg_temp_free(a0); \
+ tcg_temp_free(a1); \
+ tcg_temp_free(b0); \
+ tcg_temp_free(b1); \
+ }
+
+VSX_XXMRG(xxmrghw, 1)
+VSX_XXMRG(xxmrglw, 0)
+
+
/*** SPE extension ***/
/* Register moves */
@@ -9807,6 +9846,8 @@ VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
+GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
+GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
--
1.7.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [v2 10/13] Add xxmrgh/xxmrgl
2013-10-11 13:05 ` [Qemu-devel] [v2 10/13] Add xxmrgh/xxmrgl Tom Musta
@ 2013-10-22 6:35 ` Paolo Bonzini
0 siblings, 0 replies; 30+ messages in thread
From: Paolo Bonzini @ 2013-10-22 6:35 UTC (permalink / raw)
To: Tom Musta; +Cc: qemu-ppc, qemu-devel
Il 11/10/2013 14:05, Tom Musta ha scritto:
> This patch adds the VSX Merge High Word and VSX Merge Low Word
> instructions.
>
> V2: Now implemented using deposit (per Richard Henderson's comment)
>
> Signed-off-by: Tom Musta <tommusta@gmail.com>
> ---
> target-ppc/translate.c | 41 +++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 41 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 5056ec9..e6e8b02 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -7295,6 +7295,45 @@ VSX_LOGICAL(xxlor, tcg_gen_or_tl)
> VSX_LOGICAL(xxlxor, tcg_gen_xor_tl)
> VSX_LOGICAL(xxlnor, tcg_gen_nor_tl)
>
> +#define VSX_XXMRG(name, high) \
> +static void glue(gen_, name)(DisasContext * ctx) \
> + { \
> + TCGv_i64 a0, a1, b0, b1; \
> + if (unlikely(!ctx->vsx_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_VSXU); \
> + return; \
> + } \
> + a0 = tcg_temp_new(); \
> + a1 = tcg_temp_new(); \
> + b0 = tcg_temp_new(); \
> + b1 = tcg_temp_new(); \
> + if (high) { \
> + tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
> + tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
> + tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
> + tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
> + } else { \
> + tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
> + tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
> + tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
> + tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
> + } \
> + tcg_gen_shri_i64(a0, a0, 32); \
> + tcg_gen_shri_i64(b0, b0, 32); \
> + tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
> + b0, a0, 32, 32); \
> + tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
> + b1, a1, 32, 32); \
> + tcg_temp_free(a0); \
> + tcg_temp_free(a1); \
> + tcg_temp_free(b0); \
> + tcg_temp_free(b1); \
> + }
> +
> +VSX_XXMRG(xxmrghw, 1)
> +VSX_XXMRG(xxmrglw, 0)
> +
> +
> /*** SPE
> extension ***/
> /* Register moves */
>
> @@ -9807,6 +9846,8 @@ VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
> VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
> VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
> VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
> +GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
> +GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
>
> GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Qemu-devel] [v2 11/13] Add xxsel
2013-10-11 12:53 [Qemu-devel] [v2 00/13] Stage 2 VSX Support Tom Musta
` (9 preceding siblings ...)
2013-10-11 13:05 ` [Qemu-devel] [v2 10/13] Add xxmrgh/xxmrgl Tom Musta
@ 2013-10-11 13:06 ` Tom Musta
2013-10-11 13:07 ` [Qemu-devel] [v2 12/13] Add xxspltw Tom Musta
` (2 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Tom Musta @ 2013-10-11 13:06 UTC (permalink / raw)
To: qemu-ppc; +Cc: Tom Musta, qemu-devel
This patch adds the VSX Select (xxsel) instruction.
The xxsel instruction has four VSR operands. Thus the xC
instruction decoder is added.
The xxsel instruction is massively overloaded in the opcode
table since only bits 26 and 27 are opcode bits. This
overloading is done in matrix fashion with two macros
(GEN_XXSEL_ROW and GEN_XX_SEL).
V2: (1) eliminated unecessary XXSEL macro (2) tighter implementation
using tcg_gen_andc_i64.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 76 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e6e8b02..fd34b93 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -501,6 +501,7 @@ EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
+EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
EXTRACT_HELPER(DM, 8, 2);
/*****************************************************************************/
/* PowerPC instructions table */
@@ -7333,6 +7334,38 @@ static void glue(gen_, name)(DisasContext * ctx) \
VSX_XXMRG(xxmrghw, 1)
VSX_XXMRG(xxmrglw, 0)
+static void gen_xxsel(DisasContext * ctx)
+{
+ TCGv_i64 a, b, c;
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ a = tcg_temp_new();
+ b = tcg_temp_new();
+ c = tcg_temp_new();
+
+ tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
+ tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
+ tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
+
+ tcg_gen_and_i64(b, b, c);
+ tcg_gen_andc_i64(a, a, c);
+ tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
+
+ tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
+ tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
+ tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
+
+ tcg_gen_and_i64(b, b, c);
+ tcg_gen_andc_i64(a, a, c);
+ tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
+
+ tcg_temp_free(a);
+ tcg_temp_free(b);
+ tcg_temp_free(c);
+}
+
/*** SPE extension ***/
/* Register moves */
@@ -9849,6 +9882,49 @@ VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
+#define GEN_XXSEL_ROW(opc3) \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
+
+GEN_XXSEL_ROW(0x00)
+GEN_XXSEL_ROW(0x01)
+GEN_XXSEL_ROW(0x02)
+GEN_XXSEL_ROW(0x03)
+GEN_XXSEL_ROW(0x04)
+GEN_XXSEL_ROW(0x05)
+GEN_XXSEL_ROW(0x06)
+GEN_XXSEL_ROW(0x07)
+GEN_XXSEL_ROW(0x08)
+GEN_XXSEL_ROW(0x09)
+GEN_XXSEL_ROW(0x0A)
+GEN_XXSEL_ROW(0x0B)
+GEN_XXSEL_ROW(0x0C)
+GEN_XXSEL_ROW(0x0D)
+GEN_XXSEL_ROW(0x0E)
+GEN_XXSEL_ROW(0x0F)
+GEN_XXSEL_ROW(0x10)
+GEN_XXSEL_ROW(0x11)
+GEN_XXSEL_ROW(0x12)
+GEN_XXSEL_ROW(0x13)
+GEN_XXSEL_ROW(0x14)
+GEN_XXSEL_ROW(0x15)
+GEN_XXSEL_ROW(0x16)
+GEN_XXSEL_ROW(0x17)
+GEN_XXSEL_ROW(0x18)
+GEN_XXSEL_ROW(0x19)
+GEN_XXSEL_ROW(0x1A)
+GEN_XXSEL_ROW(0x1B)
+GEN_XXSEL_ROW(0x1C)
+GEN_XXSEL_ROW(0x1D)
+GEN_XXSEL_ROW(0x1E)
+GEN_XXSEL_ROW(0x1F)
+
GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
#undef GEN_SPE
--
1.7.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Qemu-devel] [v2 12/13] Add xxspltw
2013-10-11 12:53 [Qemu-devel] [v2 00/13] Stage 2 VSX Support Tom Musta
` (10 preceding siblings ...)
2013-10-11 13:06 ` [Qemu-devel] [v2 11/13] Add xxsel Tom Musta
@ 2013-10-11 13:07 ` Tom Musta
2013-10-11 13:08 ` [Qemu-devel] [v2 13/13] Add xxsldwi Tom Musta
2013-10-11 15:53 ` [Qemu-devel] [v2 00/13] Stage 2 VSX Support Richard Henderson
13 siblings, 0 replies; 30+ messages in thread
From: Tom Musta @ 2013-10-11 13:07 UTC (permalink / raw)
To: qemu-ppc; +Cc: Tom Musta, qemu-devel
This patch adds the VSX Splat Word (xxsplatw) instruction.
This is the first instruction to use the UIM immediate field
and consequently a decoder is also added.
V2: reworked implementation per Richard Henderson's comments.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 31 +++++++++++++++++++++++++++++++
1 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index fd34b93..a56b303 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -503,6 +503,7 @@ EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
EXTRACT_HELPER(DM, 8, 2);
+EXTRACT_HELPER(UIM, 16, 2);
/*****************************************************************************/
/* PowerPC instructions table */
@@ -7366,6 +7367,35 @@ static void gen_xxsel(DisasContext * ctx)
tcg_temp_free(c);
}
+static void gen_xxspltw(DisasContext *ctx)
+{
+ TCGv_i64 b, b2;
+ TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
+ cpu_vsrl(xB(ctx->opcode)) :
+ cpu_vsrh(xB(ctx->opcode));
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+
+ b = tcg_temp_new();
+ b2 = tcg_temp_new();
+
+ if (UIM(ctx->opcode) & 1) {
+ tcg_gen_ext32u_i64(b, vsr);
+ } else {
+ tcg_gen_shri_i64(b, vsr, 32);
+ }
+
+ tcg_gen_shli_i64(b2, b, 32);
+ tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
+ tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
+
+ tcg_temp_free(b);
+ tcg_temp_free(b2);
+}
+
/*** SPE extension ***/
/* Register moves */
@@ -9881,6 +9911,7 @@ VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
+GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
#define GEN_XXSEL_ROW(opc3) \
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
1.7.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Qemu-devel] [v2 13/13] Add xxsldwi
2013-10-11 12:53 [Qemu-devel] [v2 00/13] Stage 2 VSX Support Tom Musta
` (11 preceding siblings ...)
2013-10-11 13:07 ` [Qemu-devel] [v2 12/13] Add xxspltw Tom Musta
@ 2013-10-11 13:08 ` Tom Musta
2013-10-11 15:53 ` [Qemu-devel] [v2 00/13] Stage 2 VSX Support Richard Henderson
13 siblings, 0 replies; 30+ messages in thread
From: Tom Musta @ 2013-10-11 13:08 UTC (permalink / raw)
To: qemu-ppc; +Cc: Tom Musta, qemu-devel
This patch adds the VSX Shift Left Double by Word Immediate
(xxsldwi) instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 62 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a56b303..ef57bae 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -504,6 +504,7 @@ EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
EXTRACT_HELPER(DM, 8, 2);
EXTRACT_HELPER(UIM, 16, 2);
+EXTRACT_HELPER(SHW, 8, 2);
/*****************************************************************************/
/* PowerPC instructions table */
@@ -7396,6 +7397,66 @@ static void gen_xxspltw(DisasContext *ctx)
tcg_temp_free(b2);
}
+static void gen_xxsldwi(DisasContext *ctx)
+{
+ TCGv_i64 xth, xtl;
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ xth = tcg_temp_new();
+ xtl = tcg_temp_new();
+
+ switch (SHW(ctx->opcode)) {
+ case 0: {
+ tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
+ tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
+ break;
+ }
+ case 1: {
+ TCGv_i64 t0 = tcg_temp_new();
+ tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
+ tcg_gen_shli_i64(xth, xth, 32);
+ tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
+ tcg_gen_shri_i64(t0, t0, 32);
+ tcg_gen_or_i64(xth, xth, t0);
+ tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
+ tcg_gen_shli_i64(xtl, xtl, 32);
+ tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
+ tcg_gen_shri_i64(t0, t0, 32);
+ tcg_gen_or_i64(xtl, xtl, t0);
+ tcg_temp_free(t0);
+ break;
+ }
+ case 2: {
+ tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
+ tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
+ break;
+ }
+ case 3: {
+ TCGv_i64 t0 = tcg_temp_new();
+ tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
+ tcg_gen_shli_i64(xth, xth, 32);
+ tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
+ tcg_gen_shri_i64(t0, t0, 32);
+ tcg_gen_or_i64(xth, xth, t0);
+ tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
+ tcg_gen_shli_i64(xtl, xtl, 32);
+ tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
+ tcg_gen_shri_i64(t0, t0, 32);
+ tcg_gen_or_i64(xtl, xtl, t0);
+ tcg_temp_free(t0);
+ break;
+ }
+ }
+
+ tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
+ tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
+
+ tcg_temp_free(xth);
+ tcg_temp_free(xtl);
+}
+
/*** SPE extension ***/
/* Register moves */
@@ -9912,6 +9973,7 @@ VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
+GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
#define GEN_XXSEL_ROW(opc3) \
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
1.7.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Qemu-devel] [v2 00/13] Stage 2 VSX Support
2013-10-11 12:53 [Qemu-devel] [v2 00/13] Stage 2 VSX Support Tom Musta
` (12 preceding siblings ...)
2013-10-11 13:08 ` [Qemu-devel] [v2 13/13] Add xxsldwi Tom Musta
@ 2013-10-11 15:53 ` Richard Henderson
13 siblings, 0 replies; 30+ messages in thread
From: Richard Henderson @ 2013-10-11 15:53 UTC (permalink / raw)
To: Tom Musta, qemu-ppc; +Cc: qemu-devel
On 10/11/2013 05:53 AM, Tom Musta wrote:
>
> This patch series continues adding support for the PowerPC Vector Scalar Extension
> (VSX). Patches are relative to the Stage 1 delivery (see
> http://lists.nongnu.org/archive/html/qemu-ppc/2013-09/msg00231.html).
>
> This series adds the following:
>
> a) all remaining load and store instructions defined by the V2.06 Power ISA
> (aka Power7).
> b) The vector and scalar move instructions.
> c) The logical instructions defined by V2.06.
> d) Assorted permute and select instructions.
>
> V2: reworked patches 4, 10, 11 and 12 per comments from Richard Henderson
> (thanks, Richard!)
Reviewed-by: Richard Henderson <rth@twiddle.net>
r~
>
> Tom Musta (13):
> Abandon GEN_VSX_* macros
> Add lxsdx
> Add lxvdsx
> Add lxvw4x
> Add stxsdx
> Add stxvw4x
> Add VSX Scalar Move Instructions
> Add VSX Vector Move Instructions
> Add Power7 VSX Logical Instructions
> Add xxmrgh/xxmrgl
> Add xxsel
> Add xxspltw
> Add xxsldwi
>
> target-ppc/translate.c | 485 +++++++++++++++++++++++++++++++++++++++++++++++-
> 1 files changed, 477 insertions(+), 8 deletions(-)
>
^ permalink raw reply [flat|nested] 30+ messages in thread