[PATCH v6 00/20] single-binary: Make hw/arm/ common

[PATCH v6 00/20] single-binary: Make hw/arm/ common

[Philippe Mathieu-Daudé]

Since v5:
- Unify 'max' CPU type (rth, pm215)

Since v4:
- Add DEFINE_MACHINE_WITH_INTERFACES (Zoltan)
- Use GPtrArray for get_valid_cpu_type (Richard)
- Define InterfaceInfo[] arrays (Richard)
- Collect R-b tags

Since v3:
- QAPI structure renamed as QemuTargetInfo
- MachineClass::get_valid_cpu_types() runtime
- target_aarch64() checking SysEmuTarget value
- Remove CONFIG_TCG #ifdef'ry in hw/arm/

Since v2:
- More comments from Pierrick addressed
- Use GList to register valid CPUs list
- Remove all TARGET_AARCH64 uses in hw/arm/

Since v1:
- Dropped unrelated / irrelevant patches
- Addressed Pierrick comments
- Added R-b tag
- Only considering machines, not CPUs.

Available here, based on my pending patch queue:
https://gitlab.com/philmd/qemu/-/tags/single-binary-hw-arm-rfc-v5

Philippe Mathieu-Daudé (20):
  hw/arm: Build ARM/HVF GICv3 stub once
  hw/arm/raspi: Initialize 64-bit CPU types during DeviceRealize()
  hw/arm/raspi: Build objects once
  hw/arm/aspeed: Initialize 64-bit CPU types during DeviceRealize()
  hw/arm/aspeed: Build objects once
  hw/arm/meson: Remove now unused arm_ss[] source set
  target/arm: Introduce common system/user meson source set
  target/arm: Build gdbstub64.o as common object
  target/arm: Build cpu64.o as common object
  target/arm: Restrict IDAU interface to TCG namespace
  target/arm: Rename Aarch64-specific methods
  target/arm: Extract common code related to 'max' CPU
  target/arm: Use make_ccsidr(LEGACY) in 32 bit 'max' CPU type
  target/arm: Implement DBGDEVID* registers in max AArch32 CPU
  target/arm: Only set %kvm_target when KVM is enabled
  target/arm: Factor aarch64_aa32_a57_init() out
  target/arm: Re-use common aarch64_aa32_a57_init() helper
  target/arm: Define 'max' CPU type in cpu-max.c
  target/arm: Build cpu32-system.o as common object
  target/arm: Build cpu-max.c once

 include/hw/arm/armv7m.h                    |   2 +-
 include/hw/misc/tz-msc.h                   |   2 +-
 target/arm/internals.h                     |  10 +-
 target/arm/{ => tcg}/idau.h                |   4 +-
 hw/arm/armv7m.c                            |   2 +-
 hw/arm/aspeed_ast27x0.c                    |   7 +-
 hw/arm/bcm2836.c                           |  14 +-
 hw/arm/raspi.c                             |   4 -
 target/arm/cpu-max.c                       | 241 +++++++++++++++++++++
 target/arm/cpu.c                           |  10 +-
 target/arm/cpu32-stubs.c                   |   8 +-
 target/arm/cpu64.c                         |  92 +-------
 target/arm/ptw.c                           |   2 +-
 target/arm/tcg/cpu-v7m.c                   |  11 +
 target/arm/tcg/{cpu32.c => cpu32-system.c} | 191 +---------------
 target/arm/tcg/stubs32.c                   |  10 +
 hw/arm/meson.build                         |  15 +-
 hw/intc/meson.build                        |   2 +-
 target/arm/meson.build                     |  26 ++-
 target/arm/tcg/meson.build                 |  60 ++---
 20 files changed, 349 insertions(+), 364 deletions(-)
 rename target/arm/{ => tcg}/idau.h (97%)
 create mode 100644 target/arm/cpu-max.c
 rename target/arm/tcg/{cpu32.c => cpu32-system.c} (80%)

-- 
2.53.0

[PATCH v6 01/20] hw/arm: Build ARM/HVF GICv3 stub once

[Philippe Mathieu-Daudé]

Move arm_gicv3_hvf_stub.c, introduced in commit 48396ad6ce9
("hw/intc: arm_gicv3_hvf: save/restore Apple GIC state"), to
the global stub_ss[] source set which holds stub files being
built once for all binaries, instead of one time per system
binary. This prevents symbol clash when trying to build a
single QEMU system binary:

  clang: error: linker command failed with exit code 1 (use -v to see invocation)
  duplicate symbol '_vmstate_gicv3_hvf' in:
      libqemu-aarch64-softmmu.a.p/hw_intc_arm_gicv3_hvf_stub.c.o
      libqemu-arm-softmmu.a.p/hw_intc_arm_gicv3_hvf_stub.c.o
  ld: 1 duplicate symbols

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Mohamed Mediouni <mohamed@unpredictable.fr>
---
 hw/intc/meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index d7db99ce354..fac2d228f9b 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -47,7 +47,7 @@ arm_common_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files('arm_gicv3_cpuif.c'))
 specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'))
 specific_ss.add(when: ['CONFIG_WHPX', 'TARGET_AARCH64'], if_true: files('arm_gicv3_whpx.c'))
 specific_ss.add(when: ['CONFIG_HVF', 'CONFIG_ARM_GICV3'], if_true: files('arm_gicv3_hvf.c'))
-specific_ss.add(when: ['CONFIG_HVF', 'CONFIG_ARM_GICV3'], if_false: files('arm_gicv3_hvf_stub.c'))
+stub_ss.add(files('arm_gicv3_hvf_stub.c'))
 specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
 arm_common_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
 specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c'))
-- 
2.53.0

[PATCH v6 02/20] hw/arm/raspi: Initialize 64-bit CPU types during DeviceRealize()

[Philippe Mathieu-Daudé]

bcm2836.c models 3 similar SoC: BCM2835, BCM2836 and BCM2837.
The BCM2837 is a 64-bit only SoC (Cortex-A53), only available
in the 64-bit binary.

If we build this file as common object, all BCM SoCs become
available in both 32 and 64-bit binaries; however when running
the introspection test on the 32-bit binary, the BCM2837 init()
method tries to init the Cortex-A53 type -- although not
realizing it -- which is not available. This can be avoided by
deferring the CPU type initialization to the SoC DeviceRealize
step (this is safe because nothing uses the CPU type before,
only the GIC access them, just after their realization).

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/bcm2836.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index ee2f44debd1..03825e69d06 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -25,12 +25,7 @@ static void bcm283x_base_init(Object *obj)
 {
     BCM283XBaseState *s = BCM283X_BASE(obj);
     BCM283XBaseClass *bc = BCM283X_BASE_GET_CLASS(obj);
-    int n;
 
-    for (n = 0; n < bc->core_count; n++) {
-        object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
-                                bc->cpu_type);
-    }
     if (bc->core_count > 1) {
         qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property);
         qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count);
@@ -65,6 +60,11 @@ bool bcm283x_common_realize(DeviceState *dev, BCMSocPeripheralBaseState *ps,
     BCM283XBaseClass *bc = BCM283X_BASE_GET_CLASS(dev);
     Object *obj;
 
+    for (int n = 0; n < bc->core_count; n++) {
+        object_initialize_child(OBJECT(dev), "cpu[*]", &s->cpu[n].core,
+                                bc->cpu_type);
+    }
+
     /* common peripherals from bcm2835 */
 
     obj = object_property_get_link(OBJECT(dev), "ram", &error_abort);
-- 
2.53.0

[PATCH v6 03/20] hw/arm/raspi: Build objects once

[Philippe Mathieu-Daudé]

Now than Raspi machines can be filtered when running a
qemu-system-arm or qemu-system-aarch64 binary, we can
remove the TARGET_AARCH64 #ifdef'ry and compile the
aspeed.c file once, moving it from arm_ss[] source set
to arm_common_ss[]. Note, we expose the TYPE_BCM2837
and TYPE_BCM2838 types to qemu-system-arm, but they are
not user-creatable, so not an issue.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/arm/bcm2836.c   | 4 ----
 hw/arm/raspi.c     | 4 ----
 hw/arm/meson.build | 8 ++++++--
 3 files changed, 6 insertions(+), 10 deletions(-)

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index 03825e69d06..f4ecea908bd 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -195,7 +195,6 @@ static void bcm2836_class_init(ObjectClass *oc, const void *data)
     dc->realize = bcm2836_realize;
 };
 
-#ifdef TARGET_AARCH64
 static void bcm2837_class_init(ObjectClass *oc, const void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
@@ -208,7 +207,6 @@ static void bcm2837_class_init(ObjectClass *oc, const void *data)
     bc->clusterid = 0x0;
     dc->realize = bcm2836_realize;
 };
-#endif
 
 static const TypeInfo bcm283x_types[] = {
     {
@@ -219,12 +217,10 @@ static const TypeInfo bcm283x_types[] = {
         .name           = TYPE_BCM2836,
         .parent         = TYPE_BCM283X,
         .class_init     = bcm2836_class_init,
-#ifdef TARGET_AARCH64
     }, {
         .name           = TYPE_BCM2837,
         .parent         = TYPE_BCM283X,
         .class_init     = bcm2837_class_init,
-#endif
     }, {
         .name           = TYPE_BCM283X,
         .parent         = TYPE_BCM283X_BASE,
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 00e4a10466a..3f99e87428c 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -367,7 +367,6 @@ static void raspi2b_machine_class_init(ObjectClass *oc, const void *data)
     raspi_machine_class_init(mc, rmc->board_rev);
 };
 
-#ifdef TARGET_AARCH64
 static void raspi3ap_machine_class_init(ObjectClass *oc, const void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
@@ -387,7 +386,6 @@ static void raspi3b_machine_class_init(ObjectClass *oc, const void *data)
     rmc->board_rev = 0xa02082;
     raspi_machine_class_init(mc, rmc->board_rev);
 };
-#endif /* TARGET_AARCH64 */
 
 static const TypeInfo raspi_machine_types[] = {
     {
@@ -405,7 +403,6 @@ static const TypeInfo raspi_machine_types[] = {
         .parent         = TYPE_RASPI_MACHINE,
         .class_init     = raspi2b_machine_class_init,
         .interfaces     = arm_machine_interfaces,
-#ifdef TARGET_AARCH64
     }, {
         .name           = MACHINE_TYPE_NAME("raspi3ap"),
         .parent         = TYPE_RASPI_MACHINE,
@@ -416,7 +413,6 @@ static const TypeInfo raspi_machine_types[] = {
         .parent         = TYPE_RASPI_MACHINE,
         .class_init     = raspi3b_machine_class_init,
         .interfaces     = aarch64_machine_interfaces,
-#endif
     }, {
         .name           = TYPE_RASPI_MACHINE,
         .parent         = TYPE_RASPI_BASE_MACHINE,
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 80068f70bb9..144e4827660 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -27,8 +27,12 @@ arm_common_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c'
 arm_common_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
 arm_common_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c', 'bananapi_m2u.c'))
 arm_common_ss.add(when: 'CONFIG_MAX78000_SOC', if_true: files('max78000_soc.c'))
-arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c'))
-arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c'))
+arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files(
+  'bcm2836.c',
+  'bcm2838.c',
+  'raspi.c',
+  'raspi4b.c'
+))
 arm_common_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
 arm_common_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
 arm_common_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
-- 
2.53.0

[PATCH v6 04/20] hw/arm/aspeed: Initialize 64-bit CPU types during DeviceRealize()

[Philippe Mathieu-Daudé]

aspeed_ast27x0.c models 2 similar SoC based on a 64-bit only
CPU (Cortex-A35), only available in the 64-bit binary.

If we build this file as common object, these SoCs become
available in both 32 and 64-bit binaries; however when running
the introspection test on the 32-bit binary, the init() method
tries to init the Cortex-A35 type -- although not realizing it
-- which is not available. This can be avoided by deferring the
CPU type initialization to the SoC DeviceRealize step (this is
safe because nothing uses the CPU type before, only the GIC
access them, just after their realization).

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/aspeed_ast27x0.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 87dcb82e1b0..e50125bfeec 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -418,11 +418,6 @@ static void aspeed_soc_ast2700_init(Object *obj)
         g_assert_not_reached();
     }
 
-    for (i = 0; i < sc->num_cpus; i++) {
-        object_initialize_child(obj, "cpu[*]", &a->cpu[i],
-                                aspeed_soc_cpu_type(sc->valid_cpu_types));
-    }
-
     object_initialize_child(obj, "gic", &a->gic, gicv3_class_name());
 
     object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
@@ -701,6 +696,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
 
     /* CPU */
     for (i = 0; i < sc->num_cpus; i++) {
+        object_initialize_child(OBJECT(dev), "cpu[*]", &a->cpu[i],
+                                aspeed_soc_cpu_type(sc->valid_cpu_types));
         object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
                                 aspeed_calc_affinity(i), &error_abort);
 
-- 
2.53.0

[PATCH v6 05/20] hw/arm/aspeed: Build objects once

[Philippe Mathieu-Daudé]

Commit 064f1ce95fe ("hw/arm/aspeed: Split AST2700 EVB
machine into a separate source file for maintainability")
remove the last TARGET_AARCH64 use.

Now than Aspeed machines can be filtered when running a
qemu-system-arm or qemu-system-aarch64 binary, we can
compile the aspeed.c file once, moving it from arm_ss[]
source set to arm_common_ss[].

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/arm/meson.build | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 144e4827660..7c3d66f4378 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -43,7 +43,7 @@ arm_common_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'x
 arm_common_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'))
 arm_common_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
 arm_common_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
-arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
+arm_common_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
   'aspeed.c',
   'aspeed_soc_common.c',
   'aspeed_ast2400.c',
@@ -66,8 +66,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
   'aspeed_ast2600_gb200nvl.c',
   'aspeed_ast2600_rainier.c',
   'aspeed_ast10x0.c',
-  'aspeed_ast10x0_evb.c'))
-arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
+  'aspeed_ast10x0_evb.c',
   'aspeed_ast1700.c',
   'aspeed_ast27x0.c',
   'aspeed_ast27x0_evb.c',
-- 
2.53.0

[PATCH v6 06/20] hw/arm/meson: Remove now unused arm_ss[] source set

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
 hw/arm/meson.build | 2 --
 1 file changed, 2 deletions(-)

diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 7c3d66f4378..88e7ad1a3ed 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -1,4 +1,3 @@
-arm_ss = ss.source_set()
 arm_common_ss = ss.source_set()
 arm_common_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
 arm_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
@@ -108,5 +107,4 @@ arm_common_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
 
 arm_common_ss.add(files('boot.c'))
 
-hw_arch += {'arm': arm_ss}
 hw_common_arch += {'arm': arm_common_ss}
-- 
2.53.0

[PATCH v6 07/20] target/arm: Introduce common system/user meson source set

[Philippe Mathieu-Daudé]

Introduce a source set common to system / user.
No logical change intended.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/meson.build     | 21 +++++++++--------
 target/arm/tcg/meson.build | 48 ++++++++++++--------------------------
 2 files changed, 26 insertions(+), 43 deletions(-)

diff --git a/target/arm/meson.build b/target/arm/meson.build
index 4723f9f170a..e56fc943bdf 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -1,6 +1,7 @@
 arm_ss = ss.source_set()
 arm_common_ss = ss.source_set()
 arm_common_system_ss = ss.source_set()
+arm_common_user_system_ss = ss.source_set()
 arm_system_ss = ss.source_set()
 arm_stubs_ss = ss.source_set()
 arm_user_ss = ss.source_set()
@@ -16,6 +17,13 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
 arm_common_ss.add(files(
   'mmuidx.c',
 ))
+arm_common_user_system_ss.add(files(
+  'cpregs-gcs.c',
+  'cpregs-pmu.c',
+  'debug_helper.c',
+  'helper.c',
+  'vfp_fpscr.c',
+))
 
 arm_common_system_ss.add(files(
   'arm-qmp-cmds.c',
@@ -26,11 +34,6 @@ arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c'))
 arm_user_ss.add(files('cpu.c'))
 arm_stubs_ss.add(files('cpu32-stubs.c'))
 arm_user_ss.add(files(
-  'cpregs-gcs.c',
-  'cpregs-pmu.c',
-  'debug_helper.c',
-  'helper.c',
-  'vfp_fpscr.c',
   'el2-stubs.c',
   'cpregs-omap-stub.c',
 ))
@@ -45,15 +48,10 @@ arm_common_system_ss.add(files(
   'arch_dump.c',
   'arm-powerctl.c',
   'cortex-regs.c',
-  'cpregs-gcs.c',
   'cpregs-omap.c',
-  'cpregs-pmu.c',
   'cpu-irq.c',
-  'debug_helper.c',
-  'helper.c',
   'machine.c',
   'ptw.c',
-  'vfp_fpscr.c',
 ))
 
 subdir('hvf')
@@ -65,6 +63,9 @@ else
     arm_common_system_ss.add(files('tcg-stubs.c'))
 endif
 
+arm_user_ss.add_all(arm_common_user_system_ss)
+arm_common_system_ss.add_all(arm_common_user_system_ss)
+
 target_arch += {'arm': arm_ss}
 target_system_arch += {'arm': arm_system_ss}
 target_user_arch += {'arm': arm_user_ss}
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index 4fb2c15f7e0..9eeccb2adca 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -52,59 +52,41 @@ arm_common_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c'))
 arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c'))
 
 arm_common_ss.add(zlib)
-
 arm_common_ss.add(files(
   'arith_helper.c',
   'crypto_helper.c',
 ))
 
-arm_common_system_ss.add(
+arm_common_user_system_ss.add(
   m_nocp_d,
   mve_d,
   neon_d,
   translate32_d,
   vfp_d,
   files(
-  'cpregs-at.c',
   'debug.c',
-  'gicv5-cpuif.c',
-  'hflags.c',
   'gengvec.c',
+  'hflags.c',
   'm_helper.c',
   'mve_helper.c',
   'neon_helper.c',
   'op_helper.c',
+  'translate.c',
+  'translate-m-nocp.c',
+  'translate-mve.c',
+  'translate-neon.c',
+  'translate-vfp.c',
+  'vec_helper.c',
+  'vfp_helper.c',
+))
+
+arm_common_system_ss.add(files(
+  'cpregs-at.c',
+  'gicv5-cpuif.c',
   'psci.c',
   'tlb_helper.c',
   'tlb-insns.c',
-  'translate.c',
-  'translate-m-nocp.c',
-  'translate-mve.c',
-  'translate-neon.c',
-  'translate-vfp.c',
-  'vec_helper.c',
-  'vfp_helper.c',
 ))
-arm_user_ss.add(
-  m_nocp_d,
-  mve_d,
-  neon_d,
-  translate32_d,
-  vfp_d,
-  files(
-  'debug.c',
-  'gengvec.c',
-  'hflags.c',
-  'm_helper.c',
-  'mve_helper.c',
-  'neon_helper.c',
-  'op_helper.c',
+arm_user_ss.add(files(
   'tlb_helper.c',
-  'translate.c',
-  'translate-m-nocp.c',
-  'translate-mve.c',
-  'translate-neon.c',
-  'translate-vfp.c',
-  'vec_helper.c',
-  'vfp_helper.c',
 ))
-- 
2.53.0

[PATCH v6 08/20] target/arm: Build gdbstub64.o as common object

[Philippe Mathieu-Daudé]

While gdbstub64.o is already built once, build it as
common object, reducing target-specific set in arm_ss[].

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/meson.build | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/arm/meson.build b/target/arm/meson.build
index e56fc943bdf..5376be2e3bc 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -11,7 +11,6 @@ arm_user_ss.add(files('gdbstub.c'))
 
 arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
   'cpu64.c',
-  'gdbstub64.c'
 ))
 
 arm_common_ss.add(files(
@@ -24,6 +23,9 @@ arm_common_user_system_ss.add(files(
   'helper.c',
   'vfp_fpscr.c',
 ))
+arm_common_user_system_ss.add(when: 'TARGET_AARCH64', if_true: files(
+  'gdbstub64.c'
+))
 
 arm_common_system_ss.add(files(
   'arm-qmp-cmds.c',
-- 
2.53.0

[PATCH v6 09/20] target/arm: Build cpu64.o as common object

[Philippe Mathieu-Daudé]

While gdbstub64.o is already built once, build it as
common object, reducing target-specific set in arm_ss[].

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/tcg/meson.build | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index 9eeccb2adca..f821331fbee 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -27,15 +27,13 @@ translate32_d = [
   decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']),
 ]
 
-arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64)
 arm_stubs_ss.add(files('stubs32.c'))
 
 arm_ss.add(files(
   'cpu32.c',
 ))
 
-arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
-  'cpu64.c',
+arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64 + files(
   'gengvec64.c',
   'translate-a64.c',
   'translate-sve.c',
@@ -79,6 +77,9 @@ arm_common_user_system_ss.add(
   'vec_helper.c',
   'vfp_helper.c',
 ))
+arm_common_user_system_ss.add(when: 'TARGET_AARCH64', if_true: files(
+  'cpu64.c',
+))
 
 arm_common_system_ss.add(files(
   'cpregs-at.c',
-- 
2.53.0

[PATCH v6 10/20] target/arm: Restrict IDAU interface to TCG namespace

[Philippe Mathieu-Daudé]

Emphasis the IDAU interface is restricted to TCG by
moving the header under target/arm/tcg/. Move the
definition to cpu-v7m.c which also contains v7/v8
hardware (NVIC), keeping only CPU types in cpu32.c.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/arm/armv7m.h     |  2 +-
 include/hw/misc/tz-msc.h    |  2 +-
 target/arm/{ => tcg}/idau.h |  4 ++--
 hw/arm/armv7m.c             |  2 +-
 target/arm/cpu.c            |  2 +-
 target/arm/ptw.c            |  2 +-
 target/arm/tcg/cpu-v7m.c    | 11 +++++++++++
 target/arm/tcg/cpu32.c      |  8 --------
 8 files changed, 18 insertions(+), 15 deletions(-)
 rename target/arm/{ => tcg}/idau.h (97%)

diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
index 98ad08db036..70555962bb9 100644
--- a/include/hw/arm/armv7m.h
+++ b/include/hw/arm/armv7m.h
@@ -13,7 +13,7 @@
 #include "hw/core/sysbus.h"
 #include "hw/intc/armv7m_nvic.h"
 #include "hw/misc/armv7m_ras.h"
-#include "target/arm/idau.h"
+#include "target/arm/tcg/idau.h"
 #include "qom/object.h"
 #include "hw/core/clock.h"
 
diff --git a/include/hw/misc/tz-msc.h b/include/hw/misc/tz-msc.h
index 07112d8caa3..6cf4c6b09eb 100644
--- a/include/hw/misc/tz-msc.h
+++ b/include/hw/misc/tz-msc.h
@@ -51,7 +51,7 @@
 #define TZ_MSC_H
 
 #include "hw/core/sysbus.h"
-#include "target/arm/idau.h"
+#include "target/arm/tcg/idau.h"
 #include "qom/object.h"
 
 #define TYPE_TZ_MSC "tz-msc"
diff --git a/target/arm/idau.h b/target/arm/tcg/idau.h
similarity index 97%
rename from target/arm/idau.h
rename to target/arm/tcg/idau.h
index 0ef5251971d..e5736ad848d 100644
--- a/target/arm/idau.h
+++ b/target/arm/tcg/idau.h
@@ -25,8 +25,8 @@
  * connected to the CPU using a link property.
  */
 
-#ifndef TARGET_ARM_IDAU_H
-#define TARGET_ARM_IDAU_H
+#ifndef TARGET_ARM_TCG_IDAU_H
+#define TARGET_ARM_TCG_IDAU_H
 
 #include "qom/object.h"
 
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index a29eab6c915..68a1cbd6316 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -20,7 +20,7 @@
 #include "qemu/error-report.h"
 #include "qemu/module.h"
 #include "qemu/log.h"
-#include "target/arm/idau.h"
+#include "target/arm/tcg/idau.h"
 #include "target/arm/cpu.h"
 #include "target/arm/cpu-features.h"
 #include "target/arm/cpu-qom.h"
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 31e0a12a986..76f5909e902 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -24,7 +24,6 @@
 #include "qemu/log.h"
 #include "exec/page-vary.h"
 #include "system/whpx.h"
-#include "target/arm/idau.h"
 #include "qemu/module.h"
 #include "qapi/error.h"
 #include "cpu.h"
@@ -42,6 +41,7 @@
 #include "hw/intc/arm_gicv5_stream.h"
 #ifdef CONFIG_TCG
 #include "hw/intc/armv7m_nvic.h"
+#include "target/arm/tcg/idau.h"
 #endif /* CONFIG_TCG */
 #endif /* !CONFIG_USER_ONLY */
 #include "system/tcg.h"
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 8706dd59dd6..a4842a4b62b 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -17,7 +17,7 @@
 #include "cpu.h"
 #include "internals.h"
 #include "cpu-features.h"
-#include "idau.h"
+#include "target/arm/tcg/idau.h"
 
 typedef struct S1Translate {
     /*
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index dc249ce1f14..02abd831e6a 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -11,6 +11,7 @@
 #include "qemu/osdep.h"
 #include "cpu.h"
 #include "accel/tcg/cpu-ops.h"
+#include "target/arm/tcg/idau.h"
 #include "internals.h"
 
 #if !defined(CONFIG_USER_ONLY)
@@ -40,6 +41,16 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
     return ret;
 }
 
+static const TypeInfo arm_v8m_types[] = {
+    {
+        .name = TYPE_IDAU_INTERFACE,
+        .parent = TYPE_INTERFACE,
+        .class_size = sizeof(IDAUInterfaceClass),
+    }
+};
+
+DEFINE_TYPES(arm_v8m_types)
+
 #endif /* !CONFIG_USER_ONLY */
 
 static void cortex_m0_initfn(Object *obj)
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 2127d456ad6..73d21c6cf7d 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -12,7 +12,6 @@
 #include "cpu.h"
 #include "accel/tcg/cpu-ops.h"
 #include "internals.h"
-#include "target/arm/idau.h"
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/core/boards.h"
 #endif
@@ -899,17 +898,10 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
 #endif
 };
 
-static const TypeInfo idau_interface_type_info = {
-    .name = TYPE_IDAU_INTERFACE,
-    .parent = TYPE_INTERFACE,
-    .class_size = sizeof(IDAUInterfaceClass),
-};
-
 static void arm_tcg_cpu_register_types(void)
 {
     size_t i;
 
-    type_register_static(&idau_interface_type_info);
     for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
         arm_cpu_register(&arm_tcg_cpus[i]);
     }
-- 
2.53.0

[PATCH v6 11/20] target/arm: Rename Aarch64-specific methods

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 target/arm/internals.h   |  8 ++++----
 target/arm/cpu.c         |  8 ++++----
 target/arm/cpu32-stubs.c |  8 ++++----
 target/arm/cpu64.c       | 12 ++++++------
 4 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index 3edc15c7b4a..00830b17248 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1750,10 +1750,10 @@ int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg);
 int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg);
 int aarch64_gdb_get_tls_reg(CPUState *cs, GByteArray *buf, int reg);
 int aarch64_gdb_set_tls_reg(CPUState *cs, uint8_t *buf, int reg);
-void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
-void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
-void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
-void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
+void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
+void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
+void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
+void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
 void aarch64_max_tcg_initfn(Object *obj);
 void aarch64_add_pauth_properties(Object *obj);
 void aarch64_add_sve_properties(Object *obj);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 76f5909e902..31e1fd6cd51 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1707,25 +1707,25 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
     Error *local_err = NULL;
 
     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
-        arm_cpu_sve_finalize(cpu, &local_err);
+        aarch64_cpu_sve_finalize(cpu, &local_err);
         if (local_err != NULL) {
             error_propagate(errp, local_err);
             return;
         }
 
-        arm_cpu_sme_finalize(cpu, &local_err);
+        aarch64_cpu_sme_finalize(cpu, &local_err);
         if (local_err != NULL) {
             error_propagate(errp, local_err);
             return;
         }
 
-        arm_cpu_pauth_finalize(cpu, &local_err);
+        aarch64_cpu_pauth_finalize(cpu, &local_err);
         if (local_err != NULL) {
             error_propagate(errp, local_err);
             return;
         }
 
-        arm_cpu_lpa2_finalize(cpu, &local_err);
+        aarch64_cpu_lpa2_finalize(cpu, &local_err);
         if (local_err != NULL) {
             error_propagate(errp, local_err);
             return;
diff --git a/target/arm/cpu32-stubs.c b/target/arm/cpu32-stubs.c
index 9e50bb1b0b5..d42b1a5d6a6 100644
--- a/target/arm/cpu32-stubs.c
+++ b/target/arm/cpu32-stubs.c
@@ -4,22 +4,22 @@
 #include "target/arm/cpu.h"
 #include "target/arm/internals.h"
 
-void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
+void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
 {
     g_assert_not_reached();
 }
 
-void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
+void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
 {
     g_assert_not_reached();
 }
 
-void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
+void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
 {
     g_assert_not_reached();
 }
 
-void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
+void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
 {
     g_assert_not_reached();
 }
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index a93ad2da5ad..b38a78aac3f 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -60,7 +60,7 @@ int get_sysreg_idx(ARMSysRegs sysreg)
 
 #undef DEF
 
-void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
+void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
 {
     /*
      * If any vector lengths are explicitly enabled with sve<N> properties,
@@ -121,7 +121,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
              * Disable all SVE extensions as well. Note that some ZFR0
              * fields are used also by SME so must not be wiped in
              * an SME-no-SVE config. We will clear the rest in
-             * arm_cpu_sme_finalize() if necessary.
+             * aarch_cpu_sme_finalize() if necessary.
              */
             FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F64MM, 0);
             FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F32MM, 0);
@@ -336,7 +336,7 @@ static void cpu_arm_set_sve(Object *obj, bool value, Error **errp)
     FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, SVE, value);
 }
 
-void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
+void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
 {
     uint32_t vq_map = cpu->sme_vq.map;
     uint32_t vq_init = cpu->sme_vq.init;
@@ -408,7 +408,7 @@ static void cpu_arm_set_sme(Object *obj, bool value, Error **errp)
     /*
      * For now, write 0 for "off" and 1 for "on" into the PFR1 field.
      * We will correct this value to report the right SME
-     * level (SME vs SME2) in arm_cpu_sme_finalize() later.
+     * level (SME vs SME2) in aarch_cpu_sme_finalize() later.
      */
     FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, value);
 }
@@ -548,7 +548,7 @@ void aarch64_add_sme_properties(Object *obj)
 #endif
 }
 
-void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
+void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
 {
     ARMPauthFeature features = cpu_isar_feature(pauth_feature, cpu);
     ARMISARegisters *isar = &cpu->isar;
@@ -666,7 +666,7 @@ void aarch64_add_pauth_properties(Object *obj)
     }
 }
 
-void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
+void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
 {
     uint64_t t;
 
-- 
2.53.0

[PATCH v6 12/20] target/arm: Extract common code related to 'max' CPU

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/cpu-max.c   | 106 +++++++++++++++++++++++++++++++++++++++++
 target/arm/tcg/cpu32.c |  96 -------------------------------------
 target/arm/meson.build |   1 +
 3 files changed, 107 insertions(+), 96 deletions(-)
 create mode 100644 target/arm/cpu-max.c

diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c
new file mode 100644
index 00000000000..9fd48ce46e2
--- /dev/null
+++ b/target/arm/cpu-max.c
@@ -0,0 +1,106 @@
+/*
+ * QEMU ARM 'max' CPU
+ *
+ * Copyright (c) 2018 Linaro Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "target/arm/internals.h"
+
+/* Share AArch32 -cpu max features with AArch64. */
+void aa32_max_features(ARMCPU *cpu)
+{
+    uint32_t t;
+    ARMISARegisters *isar = &cpu->isar;
+
+    /* Add additional features supported by QEMU */
+    t = GET_IDREG(isar, ID_ISAR5);
+    t = FIELD_DP32(t, ID_ISAR5, AES, 2);          /* FEAT_PMULL */
+    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);         /* FEAT_SHA1 */
+    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);         /* FEAT_SHA256 */
+    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
+    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);          /* FEAT_RDM */
+    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);         /* FEAT_FCMA */
+    SET_IDREG(isar, ID_ISAR5, t);
+
+    t = GET_IDREG(isar, ID_ISAR6);
+    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);        /* FEAT_JSCVT */
+    t = FIELD_DP32(t, ID_ISAR6, DP, 1);           /* Feat_DotProd */
+    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);          /* FEAT_FHM */
+    t = FIELD_DP32(t, ID_ISAR6, SB, 1);           /* FEAT_SB */
+    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);      /* FEAT_SPECRES */
+    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);         /* FEAT_AA32BF16 */
+    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);         /* FEAT_AA32I8MM */
+    SET_IDREG(isar, ID_ISAR6, t);
+
+    t = cpu->isar.mvfr1;
+    t = FIELD_DP32(t, MVFR1, FPHP, 3);            /* FEAT_FP16 */
+    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);          /* FEAT_FP16 */
+    cpu->isar.mvfr1 = t;
+
+    t = cpu->isar.mvfr2;
+    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3);        /* SIMD MaxNum */
+    t = FIELD_DP32(t, MVFR2, FPMISC, 4);          /* FP MaxNum */
+    cpu->isar.mvfr2 = t;
+
+    FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2);          /* FEAT_PAN2 */
+
+    t = GET_IDREG(isar, ID_MMFR4);
+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 2);         /* FEAT_HPDS2 */
+    t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
+    t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
+    t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
+    t = FIELD_DP32(t, ID_MMFR4, EVT, 2);          /* FEAT_EVT */
+    SET_IDREG(isar, ID_MMFR4, t);
+
+    FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2);          /* FEAT_ETS2 */
+
+    t = GET_IDREG(isar, ID_PFR0);
+    t = FIELD_DP32(t, ID_PFR0, CSV2, 2);          /* FEAT_CSV2 */
+    t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
+    t = FIELD_DP32(t, ID_PFR0, RAS, 1);           /* FEAT_RAS */
+    SET_IDREG(isar, ID_PFR0, t);
+
+    t = GET_IDREG(isar, ID_PFR2);
+    t = FIELD_DP32(t, ID_PFR2, CSV3, 1);          /* FEAT_CSV3 */
+    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
+    SET_IDREG(isar, ID_PFR2, t);
+
+    t = GET_IDREG(isar, ID_DFR0);
+    t = FIELD_DP32(t, ID_DFR0, COPDBG, 10);       /* FEAT_Debugv8p8 */
+    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10);      /* FEAT_Debugv8p8 */
+    t = FIELD_DP32(t, ID_DFR0, PERFMON, 6);       /* FEAT_PMUv3p5 */
+    SET_IDREG(isar, ID_DFR0, t);
+
+    /* Debug ID registers. */
+
+    /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */
+    t = 0x00008000;
+    t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
+    t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
+    t = FIELD_DP32(t, DBGDIDR, VERSION, 10);      /* FEAT_Debugv8p8 */
+    t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
+    t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
+    t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
+    cpu->isar.dbgdidr = t;
+
+    t = 0;
+    t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3);
+    t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1);
+    t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15);
+    t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0);
+    t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1);
+    t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1);
+    t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0);
+    t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0);
+    cpu->isar.dbgdevid = t;
+
+    /* Bits[31:4] are RES0. */
+    t = 0;
+    t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
+    cpu->isar.dbgdevid1 = t;
+
+    FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1);         /* FEAT_HPMN0 */
+}
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 73d21c6cf7d..919ed8a6cf8 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -18,102 +18,6 @@
 #include "cpregs.h"
 
 
-/* Share AArch32 -cpu max features with AArch64. */
-void aa32_max_features(ARMCPU *cpu)
-{
-    uint32_t t;
-    ARMISARegisters *isar = &cpu->isar;
-
-    /* Add additional features supported by QEMU */
-    t = GET_IDREG(isar, ID_ISAR5);
-    t = FIELD_DP32(t, ID_ISAR5, AES, 2);          /* FEAT_PMULL */
-    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);         /* FEAT_SHA1 */
-    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);         /* FEAT_SHA256 */
-    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);          /* FEAT_RDM */
-    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);         /* FEAT_FCMA */
-    SET_IDREG(isar, ID_ISAR5, t);
-
-    t = GET_IDREG(isar, ID_ISAR6);
-    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);        /* FEAT_JSCVT */
-    t = FIELD_DP32(t, ID_ISAR6, DP, 1);           /* Feat_DotProd */
-    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);          /* FEAT_FHM */
-    t = FIELD_DP32(t, ID_ISAR6, SB, 1);           /* FEAT_SB */
-    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);      /* FEAT_SPECRES */
-    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);         /* FEAT_AA32BF16 */
-    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);         /* FEAT_AA32I8MM */
-    SET_IDREG(isar, ID_ISAR6, t);
-
-    t = cpu->isar.mvfr1;
-    t = FIELD_DP32(t, MVFR1, FPHP, 3);            /* FEAT_FP16 */
-    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);          /* FEAT_FP16 */
-    cpu->isar.mvfr1 = t;
-
-    t = cpu->isar.mvfr2;
-    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3);        /* SIMD MaxNum */
-    t = FIELD_DP32(t, MVFR2, FPMISC, 4);          /* FP MaxNum */
-    cpu->isar.mvfr2 = t;
-
-    FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2);          /* FEAT_PAN2 */
-
-    t = GET_IDREG(isar, ID_MMFR4);
-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 2);         /* FEAT_HPDS2 */
-    t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
-    t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
-    t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
-    t = FIELD_DP32(t, ID_MMFR4, EVT, 2);          /* FEAT_EVT */
-    SET_IDREG(isar, ID_MMFR4, t);
-
-    FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2);          /* FEAT_ETS2 */
-
-    t = GET_IDREG(isar, ID_PFR0);
-    t = FIELD_DP32(t, ID_PFR0, CSV2, 2);          /* FEAT_CSV2 */
-    t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
-    t = FIELD_DP32(t, ID_PFR0, RAS, 1);           /* FEAT_RAS */
-    SET_IDREG(isar, ID_PFR0, t);
-
-    t = GET_IDREG(isar, ID_PFR2);
-    t = FIELD_DP32(t, ID_PFR2, CSV3, 1);          /* FEAT_CSV3 */
-    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
-    SET_IDREG(isar, ID_PFR2, t);
-
-    t = GET_IDREG(isar, ID_DFR0);
-    t = FIELD_DP32(t, ID_DFR0, COPDBG, 10);       /* FEAT_Debugv8p8 */
-    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10);      /* FEAT_Debugv8p8 */
-    t = FIELD_DP32(t, ID_DFR0, PERFMON, 6);       /* FEAT_PMUv3p5 */
-    SET_IDREG(isar, ID_DFR0, t);
-
-    /* Debug ID registers. */
-
-    /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */
-    t = 0x00008000;
-    t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
-    t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
-    t = FIELD_DP32(t, DBGDIDR, VERSION, 10);      /* FEAT_Debugv8p8 */
-    t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
-    t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
-    t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
-    cpu->isar.dbgdidr = t;
-
-    t = 0;
-    t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3);
-    t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1);
-    t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15);
-    t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0);
-    t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1);
-    t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1);
-    t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0);
-    t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0);
-    cpu->isar.dbgdevid = t;
-
-    /* Bits[31:4] are RES0. */
-    t = 0;
-    t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
-    cpu->isar.dbgdevid1 = t;
-
-    FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1);         /* FEAT_HPMN0 */
-}
-
 /* CPU models. These are not needed for the AArch64 linux-user build. */
 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 5376be2e3bc..3e02941d0d5 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -9,6 +9,7 @@ arm_user_ss = ss.source_set()
 arm_common_system_ss.add(files('gdbstub.c'))
 arm_user_ss.add(files('gdbstub.c'))
 
+arm_ss.add(files('cpu-max.c'))
 arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
   'cpu64.c',
 ))
-- 
2.53.0

[PATCH v6 13/20] target/arm: Use make_ccsidr(LEGACY) in 32 bit 'max' CPU type

[Philippe Mathieu-Daudé]

Commit 676624d757a ("target/arm/tcg: refine cache descriptions
with a wrapper") added the make_ccsidr() helper. Use it. Besides
being simpler to review, it also makes arm_max_initfn() more in
line which aarch64_a57_initfn(), which it almost duplicates.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/tcg/cpu32.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 919ed8a6cf8..cf643ce43b1 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -9,6 +9,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/units.h"
 #include "cpu.h"
 #include "accel/tcg/cpu-ops.h"
 #include "internals.h"
@@ -756,9 +757,12 @@ static void arm_max_initfn(Object *obj)
     SET_IDREG(isar, ID_ISAR6, 0);
     cpu->isar.reset_pmcr_el0 = 0x41013000;
     SET_IDREG(isar, CLIDR, 0x0a200023);
-    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
-    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
-    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
+    /* 32KB L1 dcache */
+    cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
+    /* 48KB L1 icache */
+    cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
+    /* 2048KB L2 cache */
+    cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
     define_cortex_a72_a57_a53_cp_reginfo(cpu);
 
     aa32_max_features(cpu);
-- 
2.53.0

[PATCH v6 14/20] target/arm: Implement DBGDEVID* registers in max AArch32 CPU

[Philippe Mathieu-Daudé]

32-bit ARM max CPU is a 'Cortex-A57 advertising none of the AArch64
features'. Keep it as close as possible as the A57, by implementing
the debug ID registers, following the changes in aarch64_a57_initfn
added by commits 48eb3ae64b3 ("target-arm: Adjust debug ID registers
per-CPU") and 09754ca867f ("target/arm: Implement AArch32 DBGDEVID,
DBGDEVID1, DBGDEVID2").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/tcg/cpu32.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index cf643ce43b1..2e8afc28602 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -755,6 +755,9 @@ static void arm_max_initfn(Object *obj)
     SET_IDREG(isar, ID_ISAR4, 0x00011142);
     SET_IDREG(isar, ID_ISAR5, 0x00011121);
     SET_IDREG(isar, ID_ISAR6, 0);
+    cpu->isar.dbgdidr = 0x3516d000;
+    cpu->isar.dbgdevid = 0x01110f13;
+    cpu->isar.dbgdevid1 = 0x2;
     cpu->isar.reset_pmcr_el0 = 0x41013000;
     SET_IDREG(isar, CLIDR, 0x0a200023);
     /* 32KB L1 dcache */
-- 
2.53.0

[PATCH v6 15/20] target/arm: Only set %kvm_target when KVM is enabled

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/cpu64.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index b38a78aac3f..7b2f09cf8ec 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -701,7 +701,9 @@ static void aarch64_a57_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_EL2);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
     set_feature(&cpu->env, ARM_FEATURE_PMU);
-    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
+    if (kvm_enabled()) {
+        cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
+    }
     cpu->midr = 0x411fd070;
     cpu->revidr = 0x00000000;
     cpu->reset_fpsid = 0x41034070;
-- 
2.53.0

[PATCH v6 16/20] target/arm: Factor aarch64_aa32_a57_init() out

[Philippe Mathieu-Daudé]

In order to make the following commit easier to review,
factor aarch64_aa32_a57_init() out of aarch64_a57_initfn()
as a preliminary step. We only add a %aa32_only argument
to restrict AArch64 features.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/cpu64.c | 36 ++++++++++++++++++++++++------------
 1 file changed, 24 insertions(+), 12 deletions(-)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 7b2f09cf8ec..7dce17fdb20 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -686,17 +686,20 @@ void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
     SET_IDREG(&cpu->isar, ID_AA64MMFR0, t);
 }
 
-static void aarch64_a57_initfn(Object *obj)
+static void aarch64_aa32_a57_init(Object *obj, bool aa32_only)
 {
     ARMCPU *cpu = ARM_CPU(obj);
     ARMISARegisters *isar = &cpu->isar;
+    const bool aarch64_enabled = !aa32_only;
 
     cpu->dtb_compatible = "arm,cortex-a57";
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
     set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
-    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    if (aarch64_enabled) {
+        set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    }
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
@@ -727,10 +730,12 @@ static void aarch64_a57_initfn(Object *obj)
     SET_IDREG(isar, ID_ISAR4, 0x00011142);
     SET_IDREG(isar, ID_ISAR5, 0x00011121);
     SET_IDREG(isar, ID_ISAR6, 0);
-    SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
-    SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
-    SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
-    SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
+    if (aarch64_enabled) {
+        SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
+        SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
+        SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
+        SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
+    }
     cpu->isar.dbgdidr = 0x3516d000;
     cpu->isar.dbgdevid = 0x01110f13;
     cpu->isar.dbgdevid1 = 0x2;
@@ -742,14 +747,21 @@ static void aarch64_a57_initfn(Object *obj)
     cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
     /* 2048KB L2 cache */
     cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
-    set_dczid_bs(cpu, 4); /* 64 bytes */
-    cpu->gic_num_lrs = 4;
-    cpu->gic_vpribits = 5;
-    cpu->gic_vprebits = 5;
-    cpu->gic_pribits = 5;
+    if (aarch64_enabled) {
+        set_dczid_bs(cpu, 4); /* 64 bytes */
+        cpu->gic_num_lrs = 4;
+        cpu->gic_vpribits = 5;
+        cpu->gic_vprebits = 5;
+        cpu->gic_pribits = 5;
+    }
     define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
+static void aarch64_a57_initfn(Object *obj)
+{
+    aarch64_aa32_a57_init(obj, false);
+}
+
 static void aarch64_a53_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -886,7 +898,7 @@ static void aarch64_max_initfn(Object *obj)
     }
 
     if (tcg_enabled() || qtest_enabled()) {
-        aarch64_a57_initfn(obj);
+        aarch64_aa32_a57_init(obj, false);
     }
 
     /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
-- 
2.53.0

[PATCH v6 17/20] target/arm: Re-use common aarch64_aa32_a57_init() helper

[Philippe Mathieu-Daudé]

Make aarch64_aa32_a57_init() common by exposing its prototype
and defining it in cpu-max.c. Call it in arm_max_initfn()
restricted to AArch32.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/internals.h |  1 +
 target/arm/cpu-max.c   | 74 ++++++++++++++++++++++++++++++++++++++++++
 target/arm/cpu64.c     | 71 ----------------------------------------
 target/arm/tcg/cpu32.c | 48 ++-------------------------
 4 files changed, 77 insertions(+), 117 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index 00830b17248..c95f3d63138 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1758,6 +1758,7 @@ void aarch64_max_tcg_initfn(Object *obj);
 void aarch64_add_pauth_properties(Object *obj);
 void aarch64_add_sve_properties(Object *obj);
 void aarch64_add_sme_properties(Object *obj);
+void aarch64_aa32_a57_init(Object *obj, bool aa32_only);
 
 /* Return true if the gdbstub is presenting an AArch64 CPU */
 static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu)
diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c
index 9fd48ce46e2..6fc54ebe74e 100644
--- a/target/arm/cpu-max.c
+++ b/target/arm/cpu-max.c
@@ -7,7 +7,81 @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "system/kvm.h"
 #include "target/arm/internals.h"
+#include "target/arm/cpregs.h"
+
+void aarch64_aa32_a57_init(Object *obj, bool aa32_only)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    ARMISARegisters *isar = &cpu->isar;
+    const bool aarch64_enabled = !aa32_only;
+
+    cpu->dtb_compatible = "arm,cortex-a57";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
+    if (aarch64_enabled) {
+        set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    }
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+    if (kvm_enabled()) {
+        cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
+    }
+    cpu->midr = 0x411fd070;
+    cpu->revidr = 0x00000000;
+    cpu->reset_fpsid = 0x41034070;
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x12111111;
+    cpu->isar.mvfr2 = 0x00000043;
+    cpu->ctr = 0x8444c004;
+    cpu->reset_sctlr = 0x00c50838;
+    SET_IDREG(isar, ID_PFR0, 0x00000131);
+    SET_IDREG(isar, ID_PFR1, 0x00011011);
+    SET_IDREG(isar, ID_DFR0, 0x03010066);
+    SET_IDREG(isar, ID_AFR0, 0x00000000);
+    SET_IDREG(isar, ID_MMFR0, 0x10101105);
+    SET_IDREG(isar, ID_MMFR1, 0x40000000);
+    SET_IDREG(isar, ID_MMFR2, 0x01260000);
+    SET_IDREG(isar, ID_MMFR3, 0x02102211);
+    SET_IDREG(isar, ID_ISAR0, 0x02101110);
+    SET_IDREG(isar, ID_ISAR1, 0x13112111);
+    SET_IDREG(isar, ID_ISAR2, 0x21232042);
+    SET_IDREG(isar, ID_ISAR3, 0x01112131);
+    SET_IDREG(isar, ID_ISAR4, 0x00011142);
+    SET_IDREG(isar, ID_ISAR5, 0x00011121);
+    SET_IDREG(isar, ID_ISAR6, 0);
+    if (aarch64_enabled) {
+        SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
+        SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
+        SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
+        SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
+    }
+    cpu->isar.dbgdidr = 0x3516d000;
+    cpu->isar.dbgdevid = 0x01110f13;
+    cpu->isar.dbgdevid1 = 0x2;
+    cpu->isar.reset_pmcr_el0 = 0x41013000;
+    SET_IDREG(isar, CLIDR, 0x0a200023);
+    /* 32KB L1 dcache */
+    cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
+    /* 48KB L1 icache */
+    cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
+    /* 2048KB L2 cache */
+    cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
+    if (aarch64_enabled) {
+        set_dczid_bs(cpu, 4); /* 64 bytes */
+        cpu->gic_num_lrs = 4;
+        cpu->gic_vpribits = 5;
+        cpu->gic_vprebits = 5;
+        cpu->gic_pribits = 5;
+    }
+    define_cortex_a72_a57_a53_cp_reginfo(cpu);
+}
 
 /* Share AArch32 -cpu max features with AArch64. */
 void aa32_max_features(ARMCPU *cpu)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 7dce17fdb20..499d154dace 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -686,77 +686,6 @@ void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
     SET_IDREG(&cpu->isar, ID_AA64MMFR0, t);
 }
 
-static void aarch64_aa32_a57_init(Object *obj, bool aa32_only)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-    ARMISARegisters *isar = &cpu->isar;
-    const bool aarch64_enabled = !aa32_only;
-
-    cpu->dtb_compatible = "arm,cortex-a57";
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
-    if (aarch64_enabled) {
-        set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-    }
-    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-    set_feature(&cpu->env, ARM_FEATURE_EL2);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    set_feature(&cpu->env, ARM_FEATURE_PMU);
-    if (kvm_enabled()) {
-        cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
-    }
-    cpu->midr = 0x411fd070;
-    cpu->revidr = 0x00000000;
-    cpu->reset_fpsid = 0x41034070;
-    cpu->isar.mvfr0 = 0x10110222;
-    cpu->isar.mvfr1 = 0x12111111;
-    cpu->isar.mvfr2 = 0x00000043;
-    cpu->ctr = 0x8444c004;
-    cpu->reset_sctlr = 0x00c50838;
-    SET_IDREG(isar, ID_PFR0, 0x00000131);
-    SET_IDREG(isar, ID_PFR1, 0x00011011);
-    SET_IDREG(isar, ID_DFR0, 0x03010066);
-    SET_IDREG(isar, ID_AFR0, 0x00000000);
-    SET_IDREG(isar, ID_MMFR0, 0x10101105);
-    SET_IDREG(isar, ID_MMFR1, 0x40000000);
-    SET_IDREG(isar, ID_MMFR2, 0x01260000);
-    SET_IDREG(isar, ID_MMFR3, 0x02102211);
-    SET_IDREG(isar, ID_ISAR0, 0x02101110);
-    SET_IDREG(isar, ID_ISAR1, 0x13112111);
-    SET_IDREG(isar, ID_ISAR2, 0x21232042);
-    SET_IDREG(isar, ID_ISAR3, 0x01112131);
-    SET_IDREG(isar, ID_ISAR4, 0x00011142);
-    SET_IDREG(isar, ID_ISAR5, 0x00011121);
-    SET_IDREG(isar, ID_ISAR6, 0);
-    if (aarch64_enabled) {
-        SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
-        SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
-        SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
-        SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
-    }
-    cpu->isar.dbgdidr = 0x3516d000;
-    cpu->isar.dbgdevid = 0x01110f13;
-    cpu->isar.dbgdevid1 = 0x2;
-    cpu->isar.reset_pmcr_el0 = 0x41013000;
-    SET_IDREG(isar, CLIDR, 0x0a200023);
-    /* 32KB L1 dcache */
-    cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
-    /* 48KB L1 icache */
-    cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
-    /* 2048KB L2 cache */
-    cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
-    if (aarch64_enabled) {
-        set_dczid_bs(cpu, 4); /* 64 bytes */
-        cpu->gic_num_lrs = 4;
-        cpu->gic_vpribits = 5;
-        cpu->gic_vprebits = 5;
-        cpu->gic_pribits = 5;
-    }
-    define_cortex_a72_a57_a53_cp_reginfo(cpu);
-}
-
 static void aarch64_a57_initfn(Object *obj)
 {
     aarch64_aa32_a57_init(obj, false);
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 2e8afc28602..a2f730451fb 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -720,53 +720,9 @@ static void sa1110_initfn(Object *obj)
 static void arm_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
-    ARMISARegisters *isar = &cpu->isar;
 
-    /* aarch64_a57_initfn, advertising none of the aarch64 features */
-    cpu->dtb_compatible = "arm,cortex-a57";
-    set_feature(&cpu->env, ARM_FEATURE_V8);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
-    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-    set_feature(&cpu->env, ARM_FEATURE_EL2);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    set_feature(&cpu->env, ARM_FEATURE_PMU);
-    cpu->midr = 0x411fd070;
-    cpu->revidr = 0x00000000;
-    cpu->reset_fpsid = 0x41034070;
-    cpu->isar.mvfr0 = 0x10110222;
-    cpu->isar.mvfr1 = 0x12111111;
-    cpu->isar.mvfr2 = 0x00000043;
-    cpu->ctr = 0x8444c004;
-    cpu->reset_sctlr = 0x00c50838;
-    SET_IDREG(isar, ID_PFR0, 0x00000131);
-    SET_IDREG(isar, ID_PFR1, 0x00011011);
-    SET_IDREG(isar, ID_DFR0, 0x03010066);
-    SET_IDREG(isar, ID_AFR0, 0x00000000);
-    SET_IDREG(isar, ID_MMFR0, 0x10101105);
-    SET_IDREG(isar, ID_MMFR1, 0x40000000);
-    SET_IDREG(isar, ID_MMFR2, 0x01260000);
-    SET_IDREG(isar, ID_MMFR3, 0x02102211);
-    SET_IDREG(isar, ID_ISAR0, 0x02101110);
-    SET_IDREG(isar, ID_ISAR1, 0x13112111);
-    SET_IDREG(isar, ID_ISAR2, 0x21232042);
-    SET_IDREG(isar, ID_ISAR3, 0x01112131);
-    SET_IDREG(isar, ID_ISAR4, 0x00011142);
-    SET_IDREG(isar, ID_ISAR5, 0x00011121);
-    SET_IDREG(isar, ID_ISAR6, 0);
-    cpu->isar.dbgdidr = 0x3516d000;
-    cpu->isar.dbgdevid = 0x01110f13;
-    cpu->isar.dbgdevid1 = 0x2;
-    cpu->isar.reset_pmcr_el0 = 0x41013000;
-    SET_IDREG(isar, CLIDR, 0x0a200023);
-    /* 32KB L1 dcache */
-    cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
-    /* 48KB L1 icache */
-    cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
-    /* 2048KB L2 cache */
-    cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
-    define_cortex_a72_a57_a53_cp_reginfo(cpu);
+    /* Cortex-A57 advertising none of the aarch64 features */
+    aarch64_aa32_a57_init(obj, true);
 
     aa32_max_features(cpu);
 
-- 
2.53.0

[PATCH v6 18/20] target/arm: Define 'max' CPU type in cpu-max.c

[Philippe Mathieu-Daudé]

Rather than having the 32-bit 'max' CPU type defined in
cpu32.c and the 64-bit counter part in cpu64.c, unify the
code in a single place in cpu-max.c. Define stubs for
aarch64_host_initfn() and aarch64_max_tcg_initfn() in the
32-bit binary.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/internals.h   |  1 +
 target/arm/cpu-max.c     | 65 ++++++++++++++++++++++++++++++++++++++++
 target/arm/cpu64.c       | 21 +------------
 target/arm/tcg/cpu32.c   | 29 ------------------
 target/arm/tcg/stubs32.c | 10 +++++++
 5 files changed, 77 insertions(+), 49 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index c95f3d63138..ccada1c9018 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1759,6 +1759,7 @@ void aarch64_add_pauth_properties(Object *obj);
 void aarch64_add_sve_properties(Object *obj);
 void aarch64_add_sme_properties(Object *obj);
 void aarch64_aa32_a57_init(Object *obj, bool aa32_only);
+void aarch64_host_initfn(Object *obj);
 
 /* Return true if the gdbstub is presenting an AArch64 CPU */
 static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu)
diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c
index 6fc54ebe74e..8cf8edc6535 100644
--- a/target/arm/cpu-max.c
+++ b/target/arm/cpu-max.c
@@ -8,7 +8,10 @@
 
 #include "qemu/osdep.h"
 #include "qemu/units.h"
+#include "system/hw_accel.h"
 #include "system/kvm.h"
+#include "system/qtest.h"
+#include "system/tcg.h"
 #include "target/arm/internals.h"
 #include "target/arm/cpregs.h"
 
@@ -178,3 +181,65 @@ void aa32_max_features(ARMCPU *cpu)
 
     FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1);         /* FEAT_HPMN0 */
 }
+
+/*
+ * -cpu max: a CPU with as many features enabled as our emulation supports.
+ * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
+ * this only needs to handle 32 bits, and need not care about KVM.
+ */
+static void cpu_max_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+#ifdef TARGET_AARCH64
+    const bool aarch64_enabled = true;
+#else
+    const bool aarch64_enabled = false;
+#endif /* !TARGET_AARCH64 */
+
+    if (hwaccel_enabled()) {
+        assert(aarch64_enabled);
+        /*
+         * When hardware acceleration enabled, '-cpu max' is
+         * identical to '-cpu host'
+         */
+        aarch64_host_initfn(obj);
+        return;
+    }
+
+    if (tcg_enabled() || qtest_enabled()) {
+        aarch64_aa32_a57_init(obj, !aarch64_enabled);
+    }
+
+    if (!aarch64_enabled) {
+        aa32_max_features(cpu);
+#ifdef CONFIG_USER_ONLY
+        /*
+         * Break with true ARMv8 and add back old-style VFP short-vector
+         * support. Only do this for user-mode, where -cpu max is the default,
+         * so that older v6 and v7 programs are more likely to work without
+         * adjustment.
+         */
+        cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+#endif
+    } else if (tcg_enabled()) {
+        assert(aarch64_enabled);
+        /*
+         * '-cpu max' for TCG: we currently do this as
+         * "A57 with extra things"
+         */
+        aarch64_max_tcg_initfn(obj);
+    }
+}
+
+static const ARMCPUInfo arm_max_cpu = {
+    .name = "max",
+    .initfn = cpu_max_initfn,
+};
+
+static void arm_max_cpu_register_types(void)
+{
+    arm_cpu_register(&arm_max_cpu);
+}
+
+type_init(arm_max_cpu_register_types)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 499d154dace..28167355773 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -791,7 +791,7 @@ static void kvm_arm_set_cpreg_mig_tolerances(ARMCPU *cpu)
 }
 #endif
 
-static void aarch64_host_initfn(Object *obj)
+void aarch64_host_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
 
@@ -818,28 +818,9 @@ static void aarch64_host_initfn(Object *obj)
     }
 }
 
-static void aarch64_max_initfn(Object *obj)
-{
-    if (hwaccel_enabled()) {
-        /* When hardware acceleration enabled, '-cpu max' is identical to '-cpu host' */
-        aarch64_host_initfn(obj);
-        return;
-    }
-
-    if (tcg_enabled() || qtest_enabled()) {
-        aarch64_aa32_a57_init(obj, false);
-    }
-
-    /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
-    if (tcg_enabled()) {
-        aarch64_max_tcg_initfn(obj);
-    }
-}
-
 static const ARMCPUInfo aarch64_cpus[] = {
     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
-    { .name = "max",                .initfn = aarch64_max_initfn },
 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) || defined(CONFIG_WHPX)
     { .name = "host",               .initfn = aarch64_host_initfn },
 #endif
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index a2f730451fb..8220d785f5b 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -711,32 +711,6 @@ static void sa1110_initfn(Object *obj)
     cpu->reset_sctlr = 0x00000070;
 }
 
-#ifndef TARGET_AARCH64
-/*
- * -cpu max: a CPU with as many features enabled as our emulation supports.
- * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
- * this only needs to handle 32 bits, and need not care about KVM.
- */
-static void arm_max_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    /* Cortex-A57 advertising none of the aarch64 features */
-    aarch64_aa32_a57_init(obj, true);
-
-    aa32_max_features(cpu);
-
-#ifdef CONFIG_USER_ONLY
-    /*
-     * Break with true ARMv8 and add back old-style VFP short-vector support.
-     * Only do this for user-mode, where -cpu max is the default, so that
-     * older v6 and v7 programs are more likely to work without adjustment.
-     */
-    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
-#endif
-}
-#endif /* !TARGET_AARCH64 */
-
 static const ARMCPUInfo arm_tcg_cpus[] = {
     { .name = "arm926",      .initfn = arm926_initfn },
     { .name = "arm946",      .initfn = arm946_initfn },
@@ -760,9 +734,6 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
     { .name = "ti925t",      .initfn = ti925t_initfn },
     { .name = "sa1100",      .initfn = sa1100_initfn },
     { .name = "sa1110",      .initfn = sa1110_initfn },
-#ifndef TARGET_AARCH64
-    { .name = "max",         .initfn = arm_max_initfn },
-#endif
 };
 
 static void arm_tcg_cpu_register_types(void)
diff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c
index 3945dc49e5e..78f819ef6ff 100644
--- a/target/arm/tcg/stubs32.c
+++ b/target/arm/tcg/stubs32.c
@@ -22,3 +22,13 @@ void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,
 {
     g_assert_not_reached();
 }
+
+void aarch64_host_initfn(Object *obj)
+{
+    g_assert_not_reached();
+}
+
+void aarch64_max_tcg_initfn(Object *obj)
+{
+    g_assert_not_reached();
+}
-- 
2.53.0

[PATCH v6 19/20] target/arm: Build cpu32-system.o as common object

[Philippe Mathieu-Daudé]

cpu32.c only contains CPU types used in 32-bit system emulation:
rename it as cpu32-system.c; always compile the file but only
register the QOM types for the 32-bit binary.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/tcg/{cpu32.c => cpu32-system.c} | 19 ++++++-------------
 target/arm/tcg/meson.build                 |  5 +----
 2 files changed, 7 insertions(+), 17 deletions(-)
 rename target/arm/tcg/{cpu32.c => cpu32-system.c} (98%)

diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32-system.c
similarity index 98%
rename from target/arm/tcg/cpu32.c
rename to target/arm/tcg/cpu32-system.c
index 8220d785f5b..51ed1f8f269 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32-system.c
@@ -1,5 +1,5 @@
 /*
- * QEMU ARM TCG-only CPUs.
+ * QEMU ARM TCG-only CPUs (not needed for the AArch64 linux-user build)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
@@ -10,18 +10,13 @@
 
 #include "qemu/osdep.h"
 #include "qemu/units.h"
+#include "qemu/target-info.h"
 #include "cpu.h"
 #include "accel/tcg/cpu-ops.h"
 #include "internals.h"
-#if !defined(CONFIG_USER_ONLY)
 #include "hw/core/boards.h"
-#endif
 #include "cpregs.h"
 
-
-/* CPU models. These are not needed for the AArch64 linux-user build. */
-#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-
 static void arm926_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -738,13 +733,11 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
 
 static void arm_tcg_cpu_register_types(void)
 {
-    size_t i;
-
-    for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
-        arm_cpu_register(&arm_tcg_cpus[i]);
+    if (target_arm()) {
+        for (size_t i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
+            arm_cpu_register(&arm_tcg_cpus[i]);
+        }
     }
 }
 
 type_init(arm_tcg_cpu_register_types)
-
-#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index f821331fbee..a6aac6deef0 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -29,10 +29,6 @@ translate32_d = [
 
 arm_stubs_ss.add(files('stubs32.c'))
 
-arm_ss.add(files(
-  'cpu32.c',
-))
-
 arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64 + files(
   'gengvec64.c',
   'translate-a64.c',
@@ -83,6 +79,7 @@ arm_common_user_system_ss.add(when: 'TARGET_AARCH64', if_true: files(
 
 arm_common_system_ss.add(files(
   'cpregs-at.c',
+  'cpu32-system.c',
   'gicv5-cpuif.c',
   'psci.c',
   'tlb_helper.c',
-- 
2.53.0

[PATCH v6 20/20] target/arm: Build cpu-max.c once

[Philippe Mathieu-Daudé]

Call TargetInfo::target_aarch64() at runtime, allowing to
remove the target-specific TARGET_AARCH64 definition and
build cpu-max.c once as common object.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/cpu-max.c   | 8 ++------
 target/arm/meson.build | 2 +-
 2 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c
index 8cf8edc6535..d38bdfcf811 100644
--- a/target/arm/cpu-max.c
+++ b/target/arm/cpu-max.c
@@ -8,6 +8,7 @@
 
 #include "qemu/osdep.h"
 #include "qemu/units.h"
+#include "qemu/target-info.h"
 #include "system/hw_accel.h"
 #include "system/kvm.h"
 #include "system/qtest.h"
@@ -190,12 +191,7 @@ void aa32_max_features(ARMCPU *cpu)
 static void cpu_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
-
-#ifdef TARGET_AARCH64
-    const bool aarch64_enabled = true;
-#else
-    const bool aarch64_enabled = false;
-#endif /* !TARGET_AARCH64 */
+    const bool aarch64_enabled = target_aarch64();
 
     if (hwaccel_enabled()) {
         assert(aarch64_enabled);
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 3e02941d0d5..9408131d178 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -9,7 +9,6 @@ arm_user_ss = ss.source_set()
 arm_common_system_ss.add(files('gdbstub.c'))
 arm_user_ss.add(files('gdbstub.c'))
 
-arm_ss.add(files('cpu-max.c'))
 arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
   'cpu64.c',
 ))
@@ -20,6 +19,7 @@ arm_common_ss.add(files(
 arm_common_user_system_ss.add(files(
   'cpregs-gcs.c',
   'cpregs-pmu.c',
+  'cpu-max.c',
   'debug_helper.c',
   'helper.c',
   'vfp_fpscr.c',
-- 
2.53.0

Re: [PATCH v6 04/20] hw/arm/aspeed: Initialize 64-bit CPU types during DeviceRealize()

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:11 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> aspeed_ast27x0.c models 2 similar SoC based on a 64-bit only
> CPU (Cortex-A35), only available in the 64-bit binary.
>
> If we build this file as common object, these SoCs become
> available in both 32 and 64-bit binaries; however when running
> the introspection test on the 32-bit binary, the init() method
> tries to init the Cortex-A35 type -- although not realizing it
> -- which is not available. This can be avoided by deferring the
> CPU type initialization to the SoC DeviceRealize step (this is
> safe because nothing uses the CPU type before, only the GIC
> access them, just after their realization).
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  hw/arm/aspeed_ast27x0.c | 7 ++-----
>  1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 87dcb82e1b0..e50125bfeec 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -418,11 +418,6 @@ static void aspeed_soc_ast2700_init(Object *obj)
>          g_assert_not_reached();
>      }
>
> -    for (i = 0; i < sc->num_cpus; i++) {
> -        object_initialize_child(obj, "cpu[*]", &a->cpu[i],
> -                                aspeed_soc_cpu_type(sc->valid_cpu_types));
> -    }
> -
>      object_initialize_child(obj, "gic", &a->gic, gicv3_class_name());
>
>      object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
> @@ -701,6 +696,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
>
>      /* CPU */
>      for (i = 0; i < sc->num_cpus; i++) {
> +        object_initialize_child(OBJECT(dev), "cpu[*]", &a->cpu[i],
> +                                aspeed_soc_cpu_type(sc->valid_cpu_types));
>          object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
>                                  aspeed_calc_affinity(i), &error_abort);
>
> --
> 2.53.0
>

Re: [PATCH v6 02/20] hw/arm/raspi: Initialize 64-bit CPU types during DeviceRealize()

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:10 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> bcm2836.c models 3 similar SoC: BCM2835, BCM2836 and BCM2837.
> The BCM2837 is a 64-bit only SoC (Cortex-A53), only available
> in the 64-bit binary.
>
> If we build this file as common object, all BCM SoCs become
> available in both 32 and 64-bit binaries; however when running
> the introspection test on the 32-bit binary, the BCM2837 init()
> method tries to init the Cortex-A53 type -- although not
> realizing it -- which is not available. This can be avoided by
> deferring the CPU type initialization to the SoC DeviceRealize
> step (this is safe because nothing uses the CPU type before,
> only the GIC access them, just after their realization).
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  hw/arm/bcm2836.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
> index ee2f44debd1..03825e69d06 100644
> --- a/hw/arm/bcm2836.c
> +++ b/hw/arm/bcm2836.c
> @@ -25,12 +25,7 @@ static void bcm283x_base_init(Object *obj)
>  {
>      BCM283XBaseState *s = BCM283X_BASE(obj);
>      BCM283XBaseClass *bc = BCM283X_BASE_GET_CLASS(obj);
> -    int n;
>
> -    for (n = 0; n < bc->core_count; n++) {
> -        object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
> -                                bc->cpu_type);
> -    }
>      if (bc->core_count > 1) {
>          qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property);
>          qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count);
> @@ -65,6 +60,11 @@ bool bcm283x_common_realize(DeviceState *dev, BCMSocPeripheralBaseState *ps,
>      BCM283XBaseClass *bc = BCM283X_BASE_GET_CLASS(dev);
>      Object *obj;
>
> +    for (int n = 0; n < bc->core_count; n++) {
> +        object_initialize_child(OBJECT(dev), "cpu[*]", &s->cpu[n].core,
> +                                bc->cpu_type);
> +    }
> +
>      /* common peripherals from bcm2835 */
>
>      obj = object_property_get_link(OBJECT(dev), "ram", &error_abort);
> --
> 2.53.0
>

Re: [PATCH v6 03/20] hw/arm/raspi: Build objects once

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:10 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Now than Raspi machines can be filtered when running a
> qemu-system-arm or qemu-system-aarch64 binary, we can
> remove the TARGET_AARCH64 #ifdef'ry and compile the
> aspeed.c file once, moving it from arm_ss[] source set
> to arm_common_ss[]. Note, we expose the TYPE_BCM2837
> and TYPE_BCM2838 types to qemu-system-arm, but they are
> not user-creatable, so not an issue.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  hw/arm/bcm2836.c   | 4 ----
>  hw/arm/raspi.c     | 4 ----
>  hw/arm/meson.build | 8 ++++++--
>  3 files changed, 6 insertions(+), 10 deletions(-)
>
> diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
> index 03825e69d06..f4ecea908bd 100644
> --- a/hw/arm/bcm2836.c
> +++ b/hw/arm/bcm2836.c
> @@ -195,7 +195,6 @@ static void bcm2836_class_init(ObjectClass *oc, const void *data)
>      dc->realize = bcm2836_realize;
>  };
>
> -#ifdef TARGET_AARCH64
>  static void bcm2837_class_init(ObjectClass *oc, const void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(oc);
> @@ -208,7 +207,6 @@ static void bcm2837_class_init(ObjectClass *oc, const void *data)
>      bc->clusterid = 0x0;
>      dc->realize = bcm2836_realize;
>  };
> -#endif
>
>  static const TypeInfo bcm283x_types[] = {
>      {
> @@ -219,12 +217,10 @@ static const TypeInfo bcm283x_types[] = {
>          .name           = TYPE_BCM2836,
>          .parent         = TYPE_BCM283X,
>          .class_init     = bcm2836_class_init,
> -#ifdef TARGET_AARCH64
>      }, {
>          .name           = TYPE_BCM2837,
>          .parent         = TYPE_BCM283X,
>          .class_init     = bcm2837_class_init,
> -#endif
>      }, {
>          .name           = TYPE_BCM283X,
>          .parent         = TYPE_BCM283X_BASE,
> diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
> index 00e4a10466a..3f99e87428c 100644
> --- a/hw/arm/raspi.c
> +++ b/hw/arm/raspi.c
> @@ -367,7 +367,6 @@ static void raspi2b_machine_class_init(ObjectClass *oc, const void *data)
>      raspi_machine_class_init(mc, rmc->board_rev);
>  };
>
> -#ifdef TARGET_AARCH64
>  static void raspi3ap_machine_class_init(ObjectClass *oc, const void *data)
>  {
>      MachineClass *mc = MACHINE_CLASS(oc);
> @@ -387,7 +386,6 @@ static void raspi3b_machine_class_init(ObjectClass *oc, const void *data)
>      rmc->board_rev = 0xa02082;
>      raspi_machine_class_init(mc, rmc->board_rev);
>  };
> -#endif /* TARGET_AARCH64 */
>
>  static const TypeInfo raspi_machine_types[] = {
>      {
> @@ -405,7 +403,6 @@ static const TypeInfo raspi_machine_types[] = {
>          .parent         = TYPE_RASPI_MACHINE,
>          .class_init     = raspi2b_machine_class_init,
>          .interfaces     = arm_machine_interfaces,
> -#ifdef TARGET_AARCH64
>      }, {
>          .name           = MACHINE_TYPE_NAME("raspi3ap"),
>          .parent         = TYPE_RASPI_MACHINE,
> @@ -416,7 +413,6 @@ static const TypeInfo raspi_machine_types[] = {
>          .parent         = TYPE_RASPI_MACHINE,
>          .class_init     = raspi3b_machine_class_init,
>          .interfaces     = aarch64_machine_interfaces,
> -#endif
>      }, {
>          .name           = TYPE_RASPI_MACHINE,
>          .parent         = TYPE_RASPI_BASE_MACHINE,
> diff --git a/hw/arm/meson.build b/hw/arm/meson.build
> index 80068f70bb9..144e4827660 100644
> --- a/hw/arm/meson.build
> +++ b/hw/arm/meson.build
> @@ -27,8 +27,12 @@ arm_common_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c'
>  arm_common_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
>  arm_common_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c', 'bananapi_m2u.c'))
>  arm_common_ss.add(when: 'CONFIG_MAX78000_SOC', if_true: files('max78000_soc.c'))
> -arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c'))
> -arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c'))
> +arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files(
> +  'bcm2836.c',
> +  'bcm2838.c',
> +  'raspi.c',
> +  'raspi4b.c'
> +))
>  arm_common_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
>  arm_common_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
>  arm_common_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
> --
> 2.53.0
>

Re: [PATCH v6 05/20] hw/arm/aspeed: Build objects once

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:11 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Commit 064f1ce95fe ("hw/arm/aspeed: Split AST2700 EVB
> machine into a separate source file for maintainability")
> remove the last TARGET_AARCH64 use.
>
> Now than Aspeed machines can be filtered when running a
> qemu-system-arm or qemu-system-aarch64 binary, we can
> compile the aspeed.c file once, moving it from arm_ss[]
> source set to arm_common_ss[].
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  hw/arm/meson.build | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/hw/arm/meson.build b/hw/arm/meson.build
> index 144e4827660..7c3d66f4378 100644
> --- a/hw/arm/meson.build
> +++ b/hw/arm/meson.build
> @@ -43,7 +43,7 @@ arm_common_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'x
>  arm_common_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'))
>  arm_common_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
>  arm_common_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
> -arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> +arm_common_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
>    'aspeed.c',
>    'aspeed_soc_common.c',
>    'aspeed_ast2400.c',
> @@ -66,8 +66,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
>    'aspeed_ast2600_gb200nvl.c',
>    'aspeed_ast2600_rainier.c',
>    'aspeed_ast10x0.c',
> -  'aspeed_ast10x0_evb.c'))
> -arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
> +  'aspeed_ast10x0_evb.c',
>    'aspeed_ast1700.c',
>    'aspeed_ast27x0.c',
>    'aspeed_ast27x0_evb.c',
> --
> 2.53.0
>

Re: [PATCH v6 06/20] hw/arm/meson: Remove now unused arm_ss[] source set

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:11 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  hw/arm/meson.build | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/hw/arm/meson.build b/hw/arm/meson.build
> index 7c3d66f4378..88e7ad1a3ed 100644
> --- a/hw/arm/meson.build
> +++ b/hw/arm/meson.build
> @@ -1,4 +1,3 @@
> -arm_ss = ss.source_set()
>  arm_common_ss = ss.source_set()
>  arm_common_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
>  arm_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
> @@ -108,5 +107,4 @@ arm_common_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
>
>  arm_common_ss.add(files('boot.c'))
>
> -hw_arch += {'arm': arm_ss}
>  hw_common_arch += {'arm': arm_common_ss}
> --
> 2.53.0
>

Re: [PATCH v6 07/20] target/arm: Introduce common system/user meson source set

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:11 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Introduce a source set common to system / user.
> No logical change intended.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  target/arm/meson.build     | 21 +++++++++--------
>  target/arm/tcg/meson.build | 48 ++++++++++++--------------------------
>  2 files changed, 26 insertions(+), 43 deletions(-)
>
> diff --git a/target/arm/meson.build b/target/arm/meson.build
> index 4723f9f170a..e56fc943bdf 100644
> --- a/target/arm/meson.build
> +++ b/target/arm/meson.build
> @@ -1,6 +1,7 @@
>  arm_ss = ss.source_set()
>  arm_common_ss = ss.source_set()
>  arm_common_system_ss = ss.source_set()
> +arm_common_user_system_ss = ss.source_set()
>  arm_system_ss = ss.source_set()
>  arm_stubs_ss = ss.source_set()
>  arm_user_ss = ss.source_set()
> @@ -16,6 +17,13 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
>  arm_common_ss.add(files(
>    'mmuidx.c',
>  ))
> +arm_common_user_system_ss.add(files(
> +  'cpregs-gcs.c',
> +  'cpregs-pmu.c',
> +  'debug_helper.c',
> +  'helper.c',
> +  'vfp_fpscr.c',
> +))
>
>  arm_common_system_ss.add(files(
>    'arm-qmp-cmds.c',
> @@ -26,11 +34,6 @@ arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c'))
>  arm_user_ss.add(files('cpu.c'))
>  arm_stubs_ss.add(files('cpu32-stubs.c'))
>  arm_user_ss.add(files(
> -  'cpregs-gcs.c',
> -  'cpregs-pmu.c',
> -  'debug_helper.c',
> -  'helper.c',
> -  'vfp_fpscr.c',
>    'el2-stubs.c',
>    'cpregs-omap-stub.c',
>  ))
> @@ -45,15 +48,10 @@ arm_common_system_ss.add(files(
>    'arch_dump.c',
>    'arm-powerctl.c',
>    'cortex-regs.c',
> -  'cpregs-gcs.c',
>    'cpregs-omap.c',
> -  'cpregs-pmu.c',
>    'cpu-irq.c',
> -  'debug_helper.c',
> -  'helper.c',
>    'machine.c',
>    'ptw.c',
> -  'vfp_fpscr.c',
>  ))
>
>  subdir('hvf')
> @@ -65,6 +63,9 @@ else
>      arm_common_system_ss.add(files('tcg-stubs.c'))
>  endif
>
> +arm_user_ss.add_all(arm_common_user_system_ss)
> +arm_common_system_ss.add_all(arm_common_user_system_ss)
> +
>  target_arch += {'arm': arm_ss}
>  target_system_arch += {'arm': arm_system_ss}
>  target_user_arch += {'arm': arm_user_ss}
> diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
> index 4fb2c15f7e0..9eeccb2adca 100644
> --- a/target/arm/tcg/meson.build
> +++ b/target/arm/tcg/meson.build
> @@ -52,59 +52,41 @@ arm_common_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c'))
>  arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c'))
>
>  arm_common_ss.add(zlib)
> -
>  arm_common_ss.add(files(
>    'arith_helper.c',
>    'crypto_helper.c',
>  ))
>
> -arm_common_system_ss.add(
> +arm_common_user_system_ss.add(
>    m_nocp_d,
>    mve_d,
>    neon_d,
>    translate32_d,
>    vfp_d,
>    files(
> -  'cpregs-at.c',
>    'debug.c',
> -  'gicv5-cpuif.c',
> -  'hflags.c',
>    'gengvec.c',
> +  'hflags.c',
>    'm_helper.c',
>    'mve_helper.c',
>    'neon_helper.c',
>    'op_helper.c',
> +  'translate.c',
> +  'translate-m-nocp.c',
> +  'translate-mve.c',
> +  'translate-neon.c',
> +  'translate-vfp.c',
> +  'vec_helper.c',
> +  'vfp_helper.c',
> +))
> +
> +arm_common_system_ss.add(files(
> +  'cpregs-at.c',
> +  'gicv5-cpuif.c',
>    'psci.c',
>    'tlb_helper.c',
>    'tlb-insns.c',
> -  'translate.c',
> -  'translate-m-nocp.c',
> -  'translate-mve.c',
> -  'translate-neon.c',
> -  'translate-vfp.c',
> -  'vec_helper.c',
> -  'vfp_helper.c',
>  ))
> -arm_user_ss.add(
> -  m_nocp_d,
> -  mve_d,
> -  neon_d,
> -  translate32_d,
> -  vfp_d,
> -  files(
> -  'debug.c',
> -  'gengvec.c',
> -  'hflags.c',
> -  'm_helper.c',
> -  'mve_helper.c',
> -  'neon_helper.c',
> -  'op_helper.c',
> +arm_user_ss.add(files(
>    'tlb_helper.c',
> -  'translate.c',
> -  'translate-m-nocp.c',
> -  'translate-mve.c',
> -  'translate-neon.c',
> -  'translate-vfp.c',
> -  'vec_helper.c',
> -  'vfp_helper.c',
>  ))
> --
> 2.53.0
>

Re: [PATCH v6 08/20] target/arm: Build gdbstub64.o as common object

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:11 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> While gdbstub64.o is already built once, build it as
> common object, reducing target-specific set in arm_ss[].
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  target/arm/meson.build | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/meson.build b/target/arm/meson.build
> index e56fc943bdf..5376be2e3bc 100644
> --- a/target/arm/meson.build
> +++ b/target/arm/meson.build
> @@ -11,7 +11,6 @@ arm_user_ss.add(files('gdbstub.c'))
>
>  arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
>    'cpu64.c',
> -  'gdbstub64.c'
>  ))
>
>  arm_common_ss.add(files(
> @@ -24,6 +23,9 @@ arm_common_user_system_ss.add(files(
>    'helper.c',
>    'vfp_fpscr.c',
>  ))
> +arm_common_user_system_ss.add(when: 'TARGET_AARCH64', if_true: files(
> +  'gdbstub64.c'
> +))
>
>  arm_common_system_ss.add(files(
>    'arm-qmp-cmds.c',
> --
> 2.53.0
>

Re: [PATCH v6 09/20] target/arm: Build cpu64.o as common object

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:11 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> While gdbstub64.o is already built once, build it as
> common object, reducing target-specific set in arm_ss[].
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

The commit message was copied from the gdbstub patch, but this patch
touches the decodetree a64 gen files

For the patch changes:

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>


>  target/arm/tcg/meson.build | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
> index 9eeccb2adca..f821331fbee 100644
> --- a/target/arm/tcg/meson.build
> +++ b/target/arm/tcg/meson.build
> @@ -27,15 +27,13 @@ translate32_d = [
>    decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']),
>  ]
>
> -arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64)
>  arm_stubs_ss.add(files('stubs32.c'))
>
>  arm_ss.add(files(
>    'cpu32.c',
>  ))
>
> -arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
> -  'cpu64.c',
> +arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64 + files(
>    'gengvec64.c',
>    'translate-a64.c',
>    'translate-sve.c',
> @@ -79,6 +77,9 @@ arm_common_user_system_ss.add(
>    'vec_helper.c',
>    'vfp_helper.c',
>  ))
> +arm_common_user_system_ss.add(when: 'TARGET_AARCH64', if_true: files(
> +  'cpu64.c',
> +))
>
>  arm_common_system_ss.add(files(
>    'cpregs-at.c',
> --
> 2.53.0
>

Re: [PATCH v6 10/20] target/arm: Restrict IDAU interface to TCG namespace

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:11 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Emphasis the IDAU interface is restricted to TCG by

Emphasis?

> moving the header under target/arm/tcg/. Move the
> definition to cpu-v7m.c which also contains v7/v8
> hardware (NVIC), keeping only CPU types in cpu32.c.
>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  include/hw/arm/armv7m.h     |  2 +-
>  include/hw/misc/tz-msc.h    |  2 +-
>  target/arm/{ => tcg}/idau.h |  4 ++--
>  hw/arm/armv7m.c             |  2 +-
>  target/arm/cpu.c            |  2 +-
>  target/arm/ptw.c            |  2 +-
>  target/arm/tcg/cpu-v7m.c    | 11 +++++++++++
>  target/arm/tcg/cpu32.c      |  8 --------
>  8 files changed, 18 insertions(+), 15 deletions(-)
>  rename target/arm/{ => tcg}/idau.h (97%)
>
> diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
> index 98ad08db036..70555962bb9 100644
> --- a/include/hw/arm/armv7m.h
> +++ b/include/hw/arm/armv7m.h
> @@ -13,7 +13,7 @@
>  #include "hw/core/sysbus.h"
>  #include "hw/intc/armv7m_nvic.h"
>  #include "hw/misc/armv7m_ras.h"
> -#include "target/arm/idau.h"
> +#include "target/arm/tcg/idau.h"
>  #include "qom/object.h"
>  #include "hw/core/clock.h"
>
> diff --git a/include/hw/misc/tz-msc.h b/include/hw/misc/tz-msc.h
> index 07112d8caa3..6cf4c6b09eb 100644
> --- a/include/hw/misc/tz-msc.h
> +++ b/include/hw/misc/tz-msc.h
> @@ -51,7 +51,7 @@
>  #define TZ_MSC_H
>
>  #include "hw/core/sysbus.h"
> -#include "target/arm/idau.h"
> +#include "target/arm/tcg/idau.h"
>  #include "qom/object.h"
>
>  #define TYPE_TZ_MSC "tz-msc"
> diff --git a/target/arm/idau.h b/target/arm/tcg/idau.h
> similarity index 97%
> rename from target/arm/idau.h
> rename to target/arm/tcg/idau.h
> index 0ef5251971d..e5736ad848d 100644
> --- a/target/arm/idau.h
> +++ b/target/arm/tcg/idau.h
> @@ -25,8 +25,8 @@
>   * connected to the CPU using a link property.
>   */
>
> -#ifndef TARGET_ARM_IDAU_H
> -#define TARGET_ARM_IDAU_H
> +#ifndef TARGET_ARM_TCG_IDAU_H
> +#define TARGET_ARM_TCG_IDAU_H
>
>  #include "qom/object.h"
>
> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
> index a29eab6c915..68a1cbd6316 100644
> --- a/hw/arm/armv7m.c
> +++ b/hw/arm/armv7m.c
> @@ -20,7 +20,7 @@
>  #include "qemu/error-report.h"
>  #include "qemu/module.h"
>  #include "qemu/log.h"
> -#include "target/arm/idau.h"
> +#include "target/arm/tcg/idau.h"
>  #include "target/arm/cpu.h"
>  #include "target/arm/cpu-features.h"
>  #include "target/arm/cpu-qom.h"
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 31e0a12a986..76f5909e902 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -24,7 +24,6 @@
>  #include "qemu/log.h"
>  #include "exec/page-vary.h"
>  #include "system/whpx.h"
> -#include "target/arm/idau.h"
>  #include "qemu/module.h"
>  #include "qapi/error.h"
>  #include "cpu.h"
> @@ -42,6 +41,7 @@
>  #include "hw/intc/arm_gicv5_stream.h"
>  #ifdef CONFIG_TCG
>  #include "hw/intc/armv7m_nvic.h"
> +#include "target/arm/tcg/idau.h"
>  #endif /* CONFIG_TCG */
>  #endif /* !CONFIG_USER_ONLY */
>  #include "system/tcg.h"
> diff --git a/target/arm/ptw.c b/target/arm/ptw.c
> index 8706dd59dd6..a4842a4b62b 100644
> --- a/target/arm/ptw.c
> +++ b/target/arm/ptw.c
> @@ -17,7 +17,7 @@
>  #include "cpu.h"
>  #include "internals.h"
>  #include "cpu-features.h"
> -#include "idau.h"
> +#include "target/arm/tcg/idau.h"
>
>  typedef struct S1Translate {
>      /*
> diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
> index dc249ce1f14..02abd831e6a 100644
> --- a/target/arm/tcg/cpu-v7m.c
> +++ b/target/arm/tcg/cpu-v7m.c
> @@ -11,6 +11,7 @@
>  #include "qemu/osdep.h"
>  #include "cpu.h"
>  #include "accel/tcg/cpu-ops.h"
> +#include "target/arm/tcg/idau.h"
>  #include "internals.h"
>
>  #if !defined(CONFIG_USER_ONLY)
> @@ -40,6 +41,16 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
>      return ret;
>  }
>
> +static const TypeInfo arm_v8m_types[] = {
> +    {
> +        .name = TYPE_IDAU_INTERFACE,
> +        .parent = TYPE_INTERFACE,
> +        .class_size = sizeof(IDAUInterfaceClass),
> +    }
> +};
> +
> +DEFINE_TYPES(arm_v8m_types)
> +
>  #endif /* !CONFIG_USER_ONLY */
>
>  static void cortex_m0_initfn(Object *obj)
> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
> index 2127d456ad6..73d21c6cf7d 100644
> --- a/target/arm/tcg/cpu32.c
> +++ b/target/arm/tcg/cpu32.c
> @@ -12,7 +12,6 @@
>  #include "cpu.h"
>  #include "accel/tcg/cpu-ops.h"
>  #include "internals.h"
> -#include "target/arm/idau.h"
>  #if !defined(CONFIG_USER_ONLY)
>  #include "hw/core/boards.h"
>  #endif
> @@ -899,17 +898,10 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
>  #endif
>  };
>
> -static const TypeInfo idau_interface_type_info = {
> -    .name = TYPE_IDAU_INTERFACE,
> -    .parent = TYPE_INTERFACE,
> -    .class_size = sizeof(IDAUInterfaceClass),
> -};
> -
>  static void arm_tcg_cpu_register_types(void)
>  {
>      size_t i;
>
> -    type_register_static(&idau_interface_type_info);
>      for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
>          arm_cpu_register(&arm_tcg_cpus[i]);
>      }
> --
> 2.53.0
>

Re: [PATCH v6 11/20] target/arm: Rename Aarch64-specific methods

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:11 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  target/arm/internals.h   |  8 ++++----
>  target/arm/cpu.c         |  8 ++++----
>  target/arm/cpu32-stubs.c |  8 ++++----
>  target/arm/cpu64.c       | 12 ++++++------
>  4 files changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index 3edc15c7b4a..00830b17248 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -1750,10 +1750,10 @@ int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg);
>  int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg);
>  int aarch64_gdb_get_tls_reg(CPUState *cs, GByteArray *buf, int reg);
>  int aarch64_gdb_set_tls_reg(CPUState *cs, uint8_t *buf, int reg);
> -void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
> -void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
> -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
> -void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
> +void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
> +void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
> +void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
> +void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
>  void aarch64_max_tcg_initfn(Object *obj);
>  void aarch64_add_pauth_properties(Object *obj);
>  void aarch64_add_sve_properties(Object *obj);
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 76f5909e902..31e1fd6cd51 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1707,25 +1707,25 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
>      Error *local_err = NULL;
>
>      if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
> -        arm_cpu_sve_finalize(cpu, &local_err);
> +        aarch64_cpu_sve_finalize(cpu, &local_err);
>          if (local_err != NULL) {
>              error_propagate(errp, local_err);
>              return;
>          }
>
> -        arm_cpu_sme_finalize(cpu, &local_err);
> +        aarch64_cpu_sme_finalize(cpu, &local_err);
>          if (local_err != NULL) {
>              error_propagate(errp, local_err);
>              return;
>          }
>
> -        arm_cpu_pauth_finalize(cpu, &local_err);
> +        aarch64_cpu_pauth_finalize(cpu, &local_err);
>          if (local_err != NULL) {
>              error_propagate(errp, local_err);
>              return;
>          }
>
> -        arm_cpu_lpa2_finalize(cpu, &local_err);
> +        aarch64_cpu_lpa2_finalize(cpu, &local_err);
>          if (local_err != NULL) {
>              error_propagate(errp, local_err);
>              return;
> diff --git a/target/arm/cpu32-stubs.c b/target/arm/cpu32-stubs.c
> index 9e50bb1b0b5..d42b1a5d6a6 100644
> --- a/target/arm/cpu32-stubs.c
> +++ b/target/arm/cpu32-stubs.c
> @@ -4,22 +4,22 @@
>  #include "target/arm/cpu.h"
>  #include "target/arm/internals.h"
>
> -void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
> +void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
>  {
>      g_assert_not_reached();
>  }
>
> -void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
> +void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
>  {
>      g_assert_not_reached();
>  }
>
> -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
> +void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
>  {
>      g_assert_not_reached();
>  }
>
> -void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
> +void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
>  {
>      g_assert_not_reached();
>  }
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index a93ad2da5ad..b38a78aac3f 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -60,7 +60,7 @@ int get_sysreg_idx(ARMSysRegs sysreg)
>
>  #undef DEF
>
> -void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
> +void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
>  {
>      /*
>       * If any vector lengths are explicitly enabled with sve<N> properties,
> @@ -121,7 +121,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
>               * Disable all SVE extensions as well. Note that some ZFR0
>               * fields are used also by SME so must not be wiped in
>               * an SME-no-SVE config. We will clear the rest in
> -             * arm_cpu_sme_finalize() if necessary.
> +             * aarch_cpu_sme_finalize() if necessary.
>               */
>              FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F64MM, 0);
>              FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F32MM, 0);
> @@ -336,7 +336,7 @@ static void cpu_arm_set_sve(Object *obj, bool value, Error **errp)
>      FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, SVE, value);
>  }
>
> -void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
> +void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
>  {
>      uint32_t vq_map = cpu->sme_vq.map;
>      uint32_t vq_init = cpu->sme_vq.init;
> @@ -408,7 +408,7 @@ static void cpu_arm_set_sme(Object *obj, bool value, Error **errp)
>      /*
>       * For now, write 0 for "off" and 1 for "on" into the PFR1 field.
>       * We will correct this value to report the right SME
> -     * level (SME vs SME2) in arm_cpu_sme_finalize() later.
> +     * level (SME vs SME2) in aarch_cpu_sme_finalize() later.
>       */
>      FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, value);
>  }
> @@ -548,7 +548,7 @@ void aarch64_add_sme_properties(Object *obj)
>  #endif
>  }
>
> -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
> +void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
>  {
>      ARMPauthFeature features = cpu_isar_feature(pauth_feature, cpu);
>      ARMISARegisters *isar = &cpu->isar;
> @@ -666,7 +666,7 @@ void aarch64_add_pauth_properties(Object *obj)
>      }
>  }
>
> -void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
> +void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
>  {
>      uint64_t t;
>
> --
> 2.53.0
>

Re: [PATCH v6 12/20] target/arm: Extract common code related to 'max' CPU

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:12 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  target/arm/cpu-max.c   | 106 +++++++++++++++++++++++++++++++++++++++++
>  target/arm/tcg/cpu32.c |  96 -------------------------------------
>  target/arm/meson.build |   1 +
>  3 files changed, 107 insertions(+), 96 deletions(-)
>  create mode 100644 target/arm/cpu-max.c
>
> diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c
> new file mode 100644
> index 00000000000..9fd48ce46e2
> --- /dev/null
> +++ b/target/arm/cpu-max.c
> @@ -0,0 +1,106 @@
> +/*
> + * QEMU ARM 'max' CPU
> + *
> + * Copyright (c) 2018 Linaro Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "target/arm/internals.h"
> +
> +/* Share AArch32 -cpu max features with AArch64. */
> +void aa32_max_features(ARMCPU *cpu)
> +{
> +    uint32_t t;
> +    ARMISARegisters *isar = &cpu->isar;
> +
> +    /* Add additional features supported by QEMU */
> +    t = GET_IDREG(isar, ID_ISAR5);
> +    t = FIELD_DP32(t, ID_ISAR5, AES, 2);          /* FEAT_PMULL */
> +    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);         /* FEAT_SHA1 */
> +    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);         /* FEAT_SHA256 */
> +    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
> +    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);          /* FEAT_RDM */
> +    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);         /* FEAT_FCMA */
> +    SET_IDREG(isar, ID_ISAR5, t);
> +
> +    t = GET_IDREG(isar, ID_ISAR6);
> +    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);        /* FEAT_JSCVT */
> +    t = FIELD_DP32(t, ID_ISAR6, DP, 1);           /* Feat_DotProd */
> +    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);          /* FEAT_FHM */
> +    t = FIELD_DP32(t, ID_ISAR6, SB, 1);           /* FEAT_SB */
> +    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);      /* FEAT_SPECRES */
> +    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);         /* FEAT_AA32BF16 */
> +    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);         /* FEAT_AA32I8MM */
> +    SET_IDREG(isar, ID_ISAR6, t);
> +
> +    t = cpu->isar.mvfr1;
> +    t = FIELD_DP32(t, MVFR1, FPHP, 3);            /* FEAT_FP16 */
> +    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);          /* FEAT_FP16 */
> +    cpu->isar.mvfr1 = t;
> +
> +    t = cpu->isar.mvfr2;
> +    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3);        /* SIMD MaxNum */
> +    t = FIELD_DP32(t, MVFR2, FPMISC, 4);          /* FP MaxNum */
> +    cpu->isar.mvfr2 = t;
> +
> +    FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2);          /* FEAT_PAN2 */
> +
> +    t = GET_IDREG(isar, ID_MMFR4);
> +    t = FIELD_DP32(t, ID_MMFR4, HPDS, 2);         /* FEAT_HPDS2 */
> +    t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
> +    t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
> +    t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
> +    t = FIELD_DP32(t, ID_MMFR4, EVT, 2);          /* FEAT_EVT */
> +    SET_IDREG(isar, ID_MMFR4, t);
> +
> +    FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2);          /* FEAT_ETS2 */
> +
> +    t = GET_IDREG(isar, ID_PFR0);
> +    t = FIELD_DP32(t, ID_PFR0, CSV2, 2);          /* FEAT_CSV2 */
> +    t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
> +    t = FIELD_DP32(t, ID_PFR0, RAS, 1);           /* FEAT_RAS */
> +    SET_IDREG(isar, ID_PFR0, t);
> +
> +    t = GET_IDREG(isar, ID_PFR2);
> +    t = FIELD_DP32(t, ID_PFR2, CSV3, 1);          /* FEAT_CSV3 */
> +    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
> +    SET_IDREG(isar, ID_PFR2, t);
> +
> +    t = GET_IDREG(isar, ID_DFR0);
> +    t = FIELD_DP32(t, ID_DFR0, COPDBG, 10);       /* FEAT_Debugv8p8 */
> +    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10);      /* FEAT_Debugv8p8 */
> +    t = FIELD_DP32(t, ID_DFR0, PERFMON, 6);       /* FEAT_PMUv3p5 */
> +    SET_IDREG(isar, ID_DFR0, t);
> +
> +    /* Debug ID registers. */
> +
> +    /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */
> +    t = 0x00008000;
> +    t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
> +    t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
> +    t = FIELD_DP32(t, DBGDIDR, VERSION, 10);      /* FEAT_Debugv8p8 */
> +    t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
> +    t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
> +    t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
> +    cpu->isar.dbgdidr = t;
> +
> +    t = 0;
> +    t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3);
> +    t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1);
> +    t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15);
> +    t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0);
> +    t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1);
> +    t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1);
> +    t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0);
> +    t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0);
> +    cpu->isar.dbgdevid = t;
> +
> +    /* Bits[31:4] are RES0. */
> +    t = 0;
> +    t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
> +    cpu->isar.dbgdevid1 = t;
> +
> +    FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1);         /* FEAT_HPMN0 */
> +}
> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
> index 73d21c6cf7d..919ed8a6cf8 100644
> --- a/target/arm/tcg/cpu32.c
> +++ b/target/arm/tcg/cpu32.c
> @@ -18,102 +18,6 @@
>  #include "cpregs.h"
>
>
> -/* Share AArch32 -cpu max features with AArch64. */
> -void aa32_max_features(ARMCPU *cpu)
> -{
> -    uint32_t t;
> -    ARMISARegisters *isar = &cpu->isar;
> -
> -    /* Add additional features supported by QEMU */
> -    t = GET_IDREG(isar, ID_ISAR5);
> -    t = FIELD_DP32(t, ID_ISAR5, AES, 2);          /* FEAT_PMULL */
> -    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);         /* FEAT_SHA1 */
> -    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);         /* FEAT_SHA256 */
> -    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
> -    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);          /* FEAT_RDM */
> -    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);         /* FEAT_FCMA */
> -    SET_IDREG(isar, ID_ISAR5, t);
> -
> -    t = GET_IDREG(isar, ID_ISAR6);
> -    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);        /* FEAT_JSCVT */
> -    t = FIELD_DP32(t, ID_ISAR6, DP, 1);           /* Feat_DotProd */
> -    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);          /* FEAT_FHM */
> -    t = FIELD_DP32(t, ID_ISAR6, SB, 1);           /* FEAT_SB */
> -    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);      /* FEAT_SPECRES */
> -    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);         /* FEAT_AA32BF16 */
> -    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);         /* FEAT_AA32I8MM */
> -    SET_IDREG(isar, ID_ISAR6, t);
> -
> -    t = cpu->isar.mvfr1;
> -    t = FIELD_DP32(t, MVFR1, FPHP, 3);            /* FEAT_FP16 */
> -    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);          /* FEAT_FP16 */
> -    cpu->isar.mvfr1 = t;
> -
> -    t = cpu->isar.mvfr2;
> -    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3);        /* SIMD MaxNum */
> -    t = FIELD_DP32(t, MVFR2, FPMISC, 4);          /* FP MaxNum */
> -    cpu->isar.mvfr2 = t;
> -
> -    FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2);          /* FEAT_PAN2 */
> -
> -    t = GET_IDREG(isar, ID_MMFR4);
> -    t = FIELD_DP32(t, ID_MMFR4, HPDS, 2);         /* FEAT_HPDS2 */
> -    t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
> -    t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
> -    t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
> -    t = FIELD_DP32(t, ID_MMFR4, EVT, 2);          /* FEAT_EVT */
> -    SET_IDREG(isar, ID_MMFR4, t);
> -
> -    FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2);          /* FEAT_ETS2 */
> -
> -    t = GET_IDREG(isar, ID_PFR0);
> -    t = FIELD_DP32(t, ID_PFR0, CSV2, 2);          /* FEAT_CSV2 */
> -    t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
> -    t = FIELD_DP32(t, ID_PFR0, RAS, 1);           /* FEAT_RAS */
> -    SET_IDREG(isar, ID_PFR0, t);
> -
> -    t = GET_IDREG(isar, ID_PFR2);
> -    t = FIELD_DP32(t, ID_PFR2, CSV3, 1);          /* FEAT_CSV3 */
> -    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
> -    SET_IDREG(isar, ID_PFR2, t);
> -
> -    t = GET_IDREG(isar, ID_DFR0);
> -    t = FIELD_DP32(t, ID_DFR0, COPDBG, 10);       /* FEAT_Debugv8p8 */
> -    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10);      /* FEAT_Debugv8p8 */
> -    t = FIELD_DP32(t, ID_DFR0, PERFMON, 6);       /* FEAT_PMUv3p5 */
> -    SET_IDREG(isar, ID_DFR0, t);
> -
> -    /* Debug ID registers. */
> -
> -    /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */
> -    t = 0x00008000;
> -    t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
> -    t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
> -    t = FIELD_DP32(t, DBGDIDR, VERSION, 10);      /* FEAT_Debugv8p8 */
> -    t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
> -    t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
> -    t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
> -    cpu->isar.dbgdidr = t;
> -
> -    t = 0;
> -    t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3);
> -    t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1);
> -    t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15);
> -    t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0);
> -    t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1);
> -    t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1);
> -    t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0);
> -    t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0);
> -    cpu->isar.dbgdevid = t;
> -
> -    /* Bits[31:4] are RES0. */
> -    t = 0;
> -    t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
> -    cpu->isar.dbgdevid1 = t;
> -
> -    FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1);         /* FEAT_HPMN0 */
> -}
> -
>  /* CPU models. These are not needed for the AArch64 linux-user build. */
>  #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
>
> diff --git a/target/arm/meson.build b/target/arm/meson.build
> index 5376be2e3bc..3e02941d0d5 100644
> --- a/target/arm/meson.build
> +++ b/target/arm/meson.build
> @@ -9,6 +9,7 @@ arm_user_ss = ss.source_set()
>  arm_common_system_ss.add(files('gdbstub.c'))
>  arm_user_ss.add(files('gdbstub.c'))
>
> +arm_ss.add(files('cpu-max.c'))
>  arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
>    'cpu64.c',
>  ))
> --
> 2.53.0
>

Re: [PATCH v6 13/20] target/arm: Use make_ccsidr(LEGACY) in 32 bit 'max' CPU type

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:12 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Commit 676624d757a ("target/arm/tcg: refine cache descriptions
> with a wrapper") added the make_ccsidr() helper. Use it. Besides
> being simpler to review, it also makes arm_max_initfn() more in
> line which aarch64_a57_initfn(), which it almost duplicates.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  target/arm/tcg/cpu32.c | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
> index 919ed8a6cf8..cf643ce43b1 100644
> --- a/target/arm/tcg/cpu32.c
> +++ b/target/arm/tcg/cpu32.c
> @@ -9,6 +9,7 @@
>   */
>
>  #include "qemu/osdep.h"
> +#include "qemu/units.h"
>  #include "cpu.h"
>  #include "accel/tcg/cpu-ops.h"
>  #include "internals.h"
> @@ -756,9 +757,12 @@ static void arm_max_initfn(Object *obj)
>      SET_IDREG(isar, ID_ISAR6, 0);
>      cpu->isar.reset_pmcr_el0 = 0x41013000;
>      SET_IDREG(isar, CLIDR, 0x0a200023);
> -    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
> -    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
> -    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
> +    /* 32KB L1 dcache */
> +    cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
> +    /* 48KB L1 icache */
> +    cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
> +    /* 2048KB L2 cache */
> +    cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
>      define_cortex_a72_a57_a53_cp_reginfo(cpu);
>
>      aa32_max_features(cpu);
> --
> 2.53.0
>

Re: [PATCH v6 14/20] target/arm: Implement DBGDEVID* registers in max AArch32 CPU

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:12 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> 32-bit ARM max CPU is a 'Cortex-A57 advertising none of the AArch64
> features'. Keep it as close as possible as the A57, by implementing
> the debug ID registers, following the changes in aarch64_a57_initfn
> added by commits 48eb3ae64b3 ("target-arm: Adjust debug ID registers
> per-CPU") and 09754ca867f ("target/arm: Implement AArch32 DBGDEVID,
> DBGDEVID1, DBGDEVID2").
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  target/arm/tcg/cpu32.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
> index cf643ce43b1..2e8afc28602 100644
> --- a/target/arm/tcg/cpu32.c
> +++ b/target/arm/tcg/cpu32.c
> @@ -755,6 +755,9 @@ static void arm_max_initfn(Object *obj)
>      SET_IDREG(isar, ID_ISAR4, 0x00011142);
>      SET_IDREG(isar, ID_ISAR5, 0x00011121);
>      SET_IDREG(isar, ID_ISAR6, 0);
> +    cpu->isar.dbgdidr = 0x3516d000;
> +    cpu->isar.dbgdevid = 0x01110f13;
> +    cpu->isar.dbgdevid1 = 0x2;
>      cpu->isar.reset_pmcr_el0 = 0x41013000;
>      SET_IDREG(isar, CLIDR, 0x0a200023);
>      /* 32KB L1 dcache */
> --
> 2.53.0
>

Re: [PATCH v6 15/20] target/arm: Only set %kvm_target when KVM is enabled

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:12 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  target/arm/cpu64.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index b38a78aac3f..7b2f09cf8ec 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -701,7 +701,9 @@ static void aarch64_a57_initfn(Object *obj)
>      set_feature(&cpu->env, ARM_FEATURE_EL2);
>      set_feature(&cpu->env, ARM_FEATURE_EL3);
>      set_feature(&cpu->env, ARM_FEATURE_PMU);
> -    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
> +    if (kvm_enabled()) {
> +        cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
> +    }
>      cpu->midr = 0x411fd070;
>      cpu->revidr = 0x00000000;
>      cpu->reset_fpsid = 0x41034070;
> --
> 2.53.0
>

Re: [PATCH v6 09/20] target/arm: Build cpu64.o as common object

[Philippe Mathieu-Daudé]

On 15/5/26 16:21, Manos Pitsidianakis wrote:
> On Fri, May 15, 2026 at 5:11 PM Philippe Mathieu-Daudé
> <philmd@linaro.org> wrote:
>>
>> While gdbstub64.o is already built once, build it as
>> common object, reducing target-specific set in arm_ss[].
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
> 
> The commit message was copied from the gdbstub patch, but this patch
> touches the decodetree a64 gen files

Indeed I should mention it in the commit description.

> 
> For the patch changes:
> 
> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
> 
> 
>>   target/arm/tcg/meson.build | 7 ++++---
>>   1 file changed, 4 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
>> index 9eeccb2adca..f821331fbee 100644
>> --- a/target/arm/tcg/meson.build
>> +++ b/target/arm/tcg/meson.build
>> @@ -27,15 +27,13 @@ translate32_d = [
>>     decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']),
>>   ]
>>
>> -arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64)
>>   arm_stubs_ss.add(files('stubs32.c'))
>>
>>   arm_ss.add(files(
>>     'cpu32.c',
>>   ))
>>
>> -arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
>> -  'cpu64.c',
>> +arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64 + files(
>>     'gengvec64.c',
>>     'translate-a64.c',
>>     'translate-sve.c',
>> @@ -79,6 +77,9 @@ arm_common_user_system_ss.add(
>>     'vec_helper.c',
>>     'vfp_helper.c',
>>   ))
>> +arm_common_user_system_ss.add(when: 'TARGET_AARCH64', if_true: files(
>> +  'cpu64.c',
>> +))
>>
>>   arm_common_system_ss.add(files(
>>     'cpregs-at.c',
>> --
>> 2.53.0
>>

Re: [PATCH v6 10/20] target/arm: Restrict IDAU interface to TCG namespace

[Philippe Mathieu-Daudé]

On 15/5/26 16:23, Manos Pitsidianakis wrote:
> On Fri, May 15, 2026 at 5:11 PM Philippe Mathieu-Daudé
> <philmd@linaro.org> wrote:
>>
>> Emphasis the IDAU interface is restricted to TCG by
> 
> Emphasis?

Emphasize!

> 
>> moving the header under target/arm/tcg/. Move the
>> definition to cpu-v7m.c which also contains v7/v8
>> hardware (NVIC), keeping only CPU types in cpu32.c.
>>
>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
> 
> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
> 
>>   include/hw/arm/armv7m.h     |  2 +-
>>   include/hw/misc/tz-msc.h    |  2 +-
>>   target/arm/{ => tcg}/idau.h |  4 ++--
>>   hw/arm/armv7m.c             |  2 +-
>>   target/arm/cpu.c            |  2 +-
>>   target/arm/ptw.c            |  2 +-
>>   target/arm/tcg/cpu-v7m.c    | 11 +++++++++++
>>   target/arm/tcg/cpu32.c      |  8 --------
>>   8 files changed, 18 insertions(+), 15 deletions(-)
>>   rename target/arm/{ => tcg}/idau.h (97%)

Re: [PATCH v6 16/20] target/arm: Factor aarch64_aa32_a57_init() out

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:12 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> In order to make the following commit easier to review,
> factor aarch64_aa32_a57_init() out of aarch64_a57_initfn()
> as a preliminary step. We only add a %aa32_only argument
> to restrict AArch64 features.
>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  target/arm/cpu64.c | 36 ++++++++++++++++++++++++------------
>  1 file changed, 24 insertions(+), 12 deletions(-)
>
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 7b2f09cf8ec..7dce17fdb20 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -686,17 +686,20 @@ void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
>      SET_IDREG(&cpu->isar, ID_AA64MMFR0, t);
>  }
>
> -static void aarch64_a57_initfn(Object *obj)
> +static void aarch64_aa32_a57_init(Object *obj, bool aa32_only)
>  {
>      ARMCPU *cpu = ARM_CPU(obj);
>      ARMISARegisters *isar = &cpu->isar;
> +    const bool aarch64_enabled = !aa32_only;
>
>      cpu->dtb_compatible = "arm,cortex-a57";
>      set_feature(&cpu->env, ARM_FEATURE_V8);
>      set_feature(&cpu->env, ARM_FEATURE_NEON);
>      set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
>      set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
> -    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> +    if (aarch64_enabled) {
> +        set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> +    }
>      set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
>      set_feature(&cpu->env, ARM_FEATURE_EL2);
>      set_feature(&cpu->env, ARM_FEATURE_EL3);
> @@ -727,10 +730,12 @@ static void aarch64_a57_initfn(Object *obj)
>      SET_IDREG(isar, ID_ISAR4, 0x00011142);
>      SET_IDREG(isar, ID_ISAR5, 0x00011121);
>      SET_IDREG(isar, ID_ISAR6, 0);
> -    SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
> -    SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
> -    SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> -    SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
> +    if (aarch64_enabled) {
> +        SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
> +        SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
> +        SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> +        SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
> +    }
>      cpu->isar.dbgdidr = 0x3516d000;
>      cpu->isar.dbgdevid = 0x01110f13;
>      cpu->isar.dbgdevid1 = 0x2;
> @@ -742,14 +747,21 @@ static void aarch64_a57_initfn(Object *obj)
>      cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
>      /* 2048KB L2 cache */
>      cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
> -    set_dczid_bs(cpu, 4); /* 64 bytes */
> -    cpu->gic_num_lrs = 4;
> -    cpu->gic_vpribits = 5;
> -    cpu->gic_vprebits = 5;
> -    cpu->gic_pribits = 5;
> +    if (aarch64_enabled) {
> +        set_dczid_bs(cpu, 4); /* 64 bytes */
> +        cpu->gic_num_lrs = 4;
> +        cpu->gic_vpribits = 5;
> +        cpu->gic_vprebits = 5;
> +        cpu->gic_pribits = 5;
> +    }
>      define_cortex_a72_a57_a53_cp_reginfo(cpu);
>  }
>
> +static void aarch64_a57_initfn(Object *obj)
> +{
> +    aarch64_aa32_a57_init(obj, false);
> +}
> +
>  static void aarch64_a53_initfn(Object *obj)
>  {
>      ARMCPU *cpu = ARM_CPU(obj);
> @@ -886,7 +898,7 @@ static void aarch64_max_initfn(Object *obj)
>      }
>
>      if (tcg_enabled() || qtest_enabled()) {
> -        aarch64_a57_initfn(obj);
> +        aarch64_aa32_a57_init(obj, false);
>      }
>
>      /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
> --
> 2.53.0
>

Re: [PATCH v6 17/20] target/arm: Re-use common aarch64_aa32_a57_init() helper

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:12 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Make aarch64_aa32_a57_init() common by exposing its prototype
> and defining it in cpu-max.c. Call it in arm_max_initfn()
> restricted to AArch32.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  target/arm/internals.h |  1 +
>  target/arm/cpu-max.c   | 74 ++++++++++++++++++++++++++++++++++++++++++
>  target/arm/cpu64.c     | 71 ----------------------------------------
>  target/arm/tcg/cpu32.c | 48 ++-------------------------
>  4 files changed, 77 insertions(+), 117 deletions(-)
>
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index 00830b17248..c95f3d63138 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -1758,6 +1758,7 @@ void aarch64_max_tcg_initfn(Object *obj);
>  void aarch64_add_pauth_properties(Object *obj);
>  void aarch64_add_sve_properties(Object *obj);
>  void aarch64_add_sme_properties(Object *obj);
> +void aarch64_aa32_a57_init(Object *obj, bool aa32_only);
>
>  /* Return true if the gdbstub is presenting an AArch64 CPU */
>  static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu)
> diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c
> index 9fd48ce46e2..6fc54ebe74e 100644
> --- a/target/arm/cpu-max.c
> +++ b/target/arm/cpu-max.c
> @@ -7,7 +7,81 @@
>   */
>
>  #include "qemu/osdep.h"
> +#include "qemu/units.h"
> +#include "system/kvm.h"
>  #include "target/arm/internals.h"
> +#include "target/arm/cpregs.h"
> +
> +void aarch64_aa32_a57_init(Object *obj, bool aa32_only)
> +{
> +    ARMCPU *cpu = ARM_CPU(obj);
> +    ARMISARegisters *isar = &cpu->isar;
> +    const bool aarch64_enabled = !aa32_only;
> +
> +    cpu->dtb_compatible = "arm,cortex-a57";
> +    set_feature(&cpu->env, ARM_FEATURE_V8);
> +    set_feature(&cpu->env, ARM_FEATURE_NEON);
> +    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> +    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
> +    if (aarch64_enabled) {
> +        set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> +    }
> +    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> +    set_feature(&cpu->env, ARM_FEATURE_EL2);
> +    set_feature(&cpu->env, ARM_FEATURE_EL3);
> +    set_feature(&cpu->env, ARM_FEATURE_PMU);
> +    if (kvm_enabled()) {
> +        cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
> +    }
> +    cpu->midr = 0x411fd070;
> +    cpu->revidr = 0x00000000;
> +    cpu->reset_fpsid = 0x41034070;
> +    cpu->isar.mvfr0 = 0x10110222;
> +    cpu->isar.mvfr1 = 0x12111111;
> +    cpu->isar.mvfr2 = 0x00000043;
> +    cpu->ctr = 0x8444c004;
> +    cpu->reset_sctlr = 0x00c50838;
> +    SET_IDREG(isar, ID_PFR0, 0x00000131);
> +    SET_IDREG(isar, ID_PFR1, 0x00011011);
> +    SET_IDREG(isar, ID_DFR0, 0x03010066);
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
> +    SET_IDREG(isar, ID_MMFR0, 0x10101105);
> +    SET_IDREG(isar, ID_MMFR1, 0x40000000);
> +    SET_IDREG(isar, ID_MMFR2, 0x01260000);
> +    SET_IDREG(isar, ID_MMFR3, 0x02102211);
> +    SET_IDREG(isar, ID_ISAR0, 0x02101110);
> +    SET_IDREG(isar, ID_ISAR1, 0x13112111);
> +    SET_IDREG(isar, ID_ISAR2, 0x21232042);
> +    SET_IDREG(isar, ID_ISAR3, 0x01112131);
> +    SET_IDREG(isar, ID_ISAR4, 0x00011142);
> +    SET_IDREG(isar, ID_ISAR5, 0x00011121);
> +    SET_IDREG(isar, ID_ISAR6, 0);
> +    if (aarch64_enabled) {
> +        SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
> +        SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
> +        SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> +        SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
> +    }
> +    cpu->isar.dbgdidr = 0x3516d000;
> +    cpu->isar.dbgdevid = 0x01110f13;
> +    cpu->isar.dbgdevid1 = 0x2;
> +    cpu->isar.reset_pmcr_el0 = 0x41013000;
> +    SET_IDREG(isar, CLIDR, 0x0a200023);
> +    /* 32KB L1 dcache */
> +    cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
> +    /* 48KB L1 icache */
> +    cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
> +    /* 2048KB L2 cache */
> +    cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
> +    if (aarch64_enabled) {
> +        set_dczid_bs(cpu, 4); /* 64 bytes */
> +        cpu->gic_num_lrs = 4;
> +        cpu->gic_vpribits = 5;
> +        cpu->gic_vprebits = 5;
> +        cpu->gic_pribits = 5;
> +    }
> +    define_cortex_a72_a57_a53_cp_reginfo(cpu);
> +}
>
>  /* Share AArch32 -cpu max features with AArch64. */
>  void aa32_max_features(ARMCPU *cpu)
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 7dce17fdb20..499d154dace 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -686,77 +686,6 @@ void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
>      SET_IDREG(&cpu->isar, ID_AA64MMFR0, t);
>  }
>
> -static void aarch64_aa32_a57_init(Object *obj, bool aa32_only)
> -{
> -    ARMCPU *cpu = ARM_CPU(obj);
> -    ARMISARegisters *isar = &cpu->isar;
> -    const bool aarch64_enabled = !aa32_only;
> -
> -    cpu->dtb_compatible = "arm,cortex-a57";
> -    set_feature(&cpu->env, ARM_FEATURE_V8);
> -    set_feature(&cpu->env, ARM_FEATURE_NEON);
> -    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> -    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
> -    if (aarch64_enabled) {
> -        set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> -    }
> -    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> -    set_feature(&cpu->env, ARM_FEATURE_EL2);
> -    set_feature(&cpu->env, ARM_FEATURE_EL3);
> -    set_feature(&cpu->env, ARM_FEATURE_PMU);
> -    if (kvm_enabled()) {
> -        cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
> -    }
> -    cpu->midr = 0x411fd070;
> -    cpu->revidr = 0x00000000;
> -    cpu->reset_fpsid = 0x41034070;
> -    cpu->isar.mvfr0 = 0x10110222;
> -    cpu->isar.mvfr1 = 0x12111111;
> -    cpu->isar.mvfr2 = 0x00000043;
> -    cpu->ctr = 0x8444c004;
> -    cpu->reset_sctlr = 0x00c50838;
> -    SET_IDREG(isar, ID_PFR0, 0x00000131);
> -    SET_IDREG(isar, ID_PFR1, 0x00011011);
> -    SET_IDREG(isar, ID_DFR0, 0x03010066);
> -    SET_IDREG(isar, ID_AFR0, 0x00000000);
> -    SET_IDREG(isar, ID_MMFR0, 0x10101105);
> -    SET_IDREG(isar, ID_MMFR1, 0x40000000);
> -    SET_IDREG(isar, ID_MMFR2, 0x01260000);
> -    SET_IDREG(isar, ID_MMFR3, 0x02102211);
> -    SET_IDREG(isar, ID_ISAR0, 0x02101110);
> -    SET_IDREG(isar, ID_ISAR1, 0x13112111);
> -    SET_IDREG(isar, ID_ISAR2, 0x21232042);
> -    SET_IDREG(isar, ID_ISAR3, 0x01112131);
> -    SET_IDREG(isar, ID_ISAR4, 0x00011142);
> -    SET_IDREG(isar, ID_ISAR5, 0x00011121);
> -    SET_IDREG(isar, ID_ISAR6, 0);
> -    if (aarch64_enabled) {
> -        SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
> -        SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
> -        SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> -        SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
> -    }
> -    cpu->isar.dbgdidr = 0x3516d000;
> -    cpu->isar.dbgdevid = 0x01110f13;
> -    cpu->isar.dbgdevid1 = 0x2;
> -    cpu->isar.reset_pmcr_el0 = 0x41013000;
> -    SET_IDREG(isar, CLIDR, 0x0a200023);
> -    /* 32KB L1 dcache */
> -    cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
> -    /* 48KB L1 icache */
> -    cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
> -    /* 2048KB L2 cache */
> -    cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
> -    if (aarch64_enabled) {
> -        set_dczid_bs(cpu, 4); /* 64 bytes */
> -        cpu->gic_num_lrs = 4;
> -        cpu->gic_vpribits = 5;
> -        cpu->gic_vprebits = 5;
> -        cpu->gic_pribits = 5;
> -    }
> -    define_cortex_a72_a57_a53_cp_reginfo(cpu);
> -}
> -
>  static void aarch64_a57_initfn(Object *obj)
>  {
>      aarch64_aa32_a57_init(obj, false);
> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
> index 2e8afc28602..a2f730451fb 100644
> --- a/target/arm/tcg/cpu32.c
> +++ b/target/arm/tcg/cpu32.c
> @@ -720,53 +720,9 @@ static void sa1110_initfn(Object *obj)
>  static void arm_max_initfn(Object *obj)
>  {
>      ARMCPU *cpu = ARM_CPU(obj);
> -    ARMISARegisters *isar = &cpu->isar;
>
> -    /* aarch64_a57_initfn, advertising none of the aarch64 features */
> -    cpu->dtb_compatible = "arm,cortex-a57";
> -    set_feature(&cpu->env, ARM_FEATURE_V8);
> -    set_feature(&cpu->env, ARM_FEATURE_NEON);
> -    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> -    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
> -    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> -    set_feature(&cpu->env, ARM_FEATURE_EL2);
> -    set_feature(&cpu->env, ARM_FEATURE_EL3);
> -    set_feature(&cpu->env, ARM_FEATURE_PMU);
> -    cpu->midr = 0x411fd070;
> -    cpu->revidr = 0x00000000;
> -    cpu->reset_fpsid = 0x41034070;
> -    cpu->isar.mvfr0 = 0x10110222;
> -    cpu->isar.mvfr1 = 0x12111111;
> -    cpu->isar.mvfr2 = 0x00000043;
> -    cpu->ctr = 0x8444c004;
> -    cpu->reset_sctlr = 0x00c50838;
> -    SET_IDREG(isar, ID_PFR0, 0x00000131);
> -    SET_IDREG(isar, ID_PFR1, 0x00011011);
> -    SET_IDREG(isar, ID_DFR0, 0x03010066);
> -    SET_IDREG(isar, ID_AFR0, 0x00000000);
> -    SET_IDREG(isar, ID_MMFR0, 0x10101105);
> -    SET_IDREG(isar, ID_MMFR1, 0x40000000);
> -    SET_IDREG(isar, ID_MMFR2, 0x01260000);
> -    SET_IDREG(isar, ID_MMFR3, 0x02102211);
> -    SET_IDREG(isar, ID_ISAR0, 0x02101110);
> -    SET_IDREG(isar, ID_ISAR1, 0x13112111);
> -    SET_IDREG(isar, ID_ISAR2, 0x21232042);
> -    SET_IDREG(isar, ID_ISAR3, 0x01112131);
> -    SET_IDREG(isar, ID_ISAR4, 0x00011142);
> -    SET_IDREG(isar, ID_ISAR5, 0x00011121);
> -    SET_IDREG(isar, ID_ISAR6, 0);
> -    cpu->isar.dbgdidr = 0x3516d000;
> -    cpu->isar.dbgdevid = 0x01110f13;
> -    cpu->isar.dbgdevid1 = 0x2;
> -    cpu->isar.reset_pmcr_el0 = 0x41013000;
> -    SET_IDREG(isar, CLIDR, 0x0a200023);
> -    /* 32KB L1 dcache */
> -    cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
> -    /* 48KB L1 icache */
> -    cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
> -    /* 2048KB L2 cache */
> -    cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
> -    define_cortex_a72_a57_a53_cp_reginfo(cpu);
> +    /* Cortex-A57 advertising none of the aarch64 features */
> +    aarch64_aa32_a57_init(obj, true);
>
>      aa32_max_features(cpu);
>
> --
> 2.53.0
>

Re: [PATCH v6 18/20] target/arm: Define 'max' CPU type in cpu-max.c

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:12 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Rather than having the 32-bit 'max' CPU type defined in
> cpu32.c and the 64-bit counter part in cpu64.c, unify the
> code in a single place in cpu-max.c. Define stubs for
> aarch64_host_initfn() and aarch64_max_tcg_initfn() in the
> 32-bit binary.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  target/arm/internals.h   |  1 +
>  target/arm/cpu-max.c     | 65 ++++++++++++++++++++++++++++++++++++++++
>  target/arm/cpu64.c       | 21 +------------
>  target/arm/tcg/cpu32.c   | 29 ------------------
>  target/arm/tcg/stubs32.c | 10 +++++++
>  5 files changed, 77 insertions(+), 49 deletions(-)
>
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index c95f3d63138..ccada1c9018 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -1759,6 +1759,7 @@ void aarch64_add_pauth_properties(Object *obj);
>  void aarch64_add_sve_properties(Object *obj);
>  void aarch64_add_sme_properties(Object *obj);
>  void aarch64_aa32_a57_init(Object *obj, bool aa32_only);
> +void aarch64_host_initfn(Object *obj);
>
>  /* Return true if the gdbstub is presenting an AArch64 CPU */
>  static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu)
> diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c
> index 6fc54ebe74e..8cf8edc6535 100644
> --- a/target/arm/cpu-max.c
> +++ b/target/arm/cpu-max.c
> @@ -8,7 +8,10 @@
>
>  #include "qemu/osdep.h"
>  #include "qemu/units.h"
> +#include "system/hw_accel.h"
>  #include "system/kvm.h"
> +#include "system/qtest.h"
> +#include "system/tcg.h"
>  #include "target/arm/internals.h"
>  #include "target/arm/cpregs.h"
>
> @@ -178,3 +181,65 @@ void aa32_max_features(ARMCPU *cpu)
>
>      FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1);         /* FEAT_HPMN0 */
>  }
> +
> +/*
> + * -cpu max: a CPU with as many features enabled as our emulation supports.
> + * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
> + * this only needs to handle 32 bits, and need not care about KVM.
> + */
> +static void cpu_max_initfn(Object *obj)
> +{
> +    ARMCPU *cpu = ARM_CPU(obj);
> +
> +#ifdef TARGET_AARCH64
> +    const bool aarch64_enabled = true;
> +#else
> +    const bool aarch64_enabled = false;
> +#endif /* !TARGET_AARCH64 */
> +
> +    if (hwaccel_enabled()) {
> +        assert(aarch64_enabled);
> +        /*
> +         * When hardware acceleration enabled, '-cpu max' is
> +         * identical to '-cpu host'
> +         */
> +        aarch64_host_initfn(obj);
> +        return;
> +    }
> +
> +    if (tcg_enabled() || qtest_enabled()) {
> +        aarch64_aa32_a57_init(obj, !aarch64_enabled);
> +    }
> +
> +    if (!aarch64_enabled) {
> +        aa32_max_features(cpu);
> +#ifdef CONFIG_USER_ONLY
> +        /*
> +         * Break with true ARMv8 and add back old-style VFP short-vector
> +         * support. Only do this for user-mode, where -cpu max is the default,
> +         * so that older v6 and v7 programs are more likely to work without
> +         * adjustment.
> +         */
> +        cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
> +#endif
> +    } else if (tcg_enabled()) {
> +        assert(aarch64_enabled);
> +        /*
> +         * '-cpu max' for TCG: we currently do this as
> +         * "A57 with extra things"
> +         */
> +        aarch64_max_tcg_initfn(obj);
> +    }
> +}
> +
> +static const ARMCPUInfo arm_max_cpu = {
> +    .name = "max",
> +    .initfn = cpu_max_initfn,
> +};
> +
> +static void arm_max_cpu_register_types(void)
> +{
> +    arm_cpu_register(&arm_max_cpu);
> +}
> +
> +type_init(arm_max_cpu_register_types)
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 499d154dace..28167355773 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -791,7 +791,7 @@ static void kvm_arm_set_cpreg_mig_tolerances(ARMCPU *cpu)
>  }
>  #endif
>
> -static void aarch64_host_initfn(Object *obj)
> +void aarch64_host_initfn(Object *obj)
>  {
>      ARMCPU *cpu = ARM_CPU(obj);
>
> @@ -818,28 +818,9 @@ static void aarch64_host_initfn(Object *obj)
>      }
>  }
>
> -static void aarch64_max_initfn(Object *obj)
> -{
> -    if (hwaccel_enabled()) {
> -        /* When hardware acceleration enabled, '-cpu max' is identical to '-cpu host' */
> -        aarch64_host_initfn(obj);
> -        return;
> -    }
> -
> -    if (tcg_enabled() || qtest_enabled()) {
> -        aarch64_aa32_a57_init(obj, false);
> -    }
> -
> -    /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
> -    if (tcg_enabled()) {
> -        aarch64_max_tcg_initfn(obj);
> -    }
> -}
> -
>  static const ARMCPUInfo aarch64_cpus[] = {
>      { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
>      { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
> -    { .name = "max",                .initfn = aarch64_max_initfn },
>  #if defined(CONFIG_KVM) || defined(CONFIG_HVF) || defined(CONFIG_WHPX)
>      { .name = "host",               .initfn = aarch64_host_initfn },
>  #endif
> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
> index a2f730451fb..8220d785f5b 100644
> --- a/target/arm/tcg/cpu32.c
> +++ b/target/arm/tcg/cpu32.c
> @@ -711,32 +711,6 @@ static void sa1110_initfn(Object *obj)
>      cpu->reset_sctlr = 0x00000070;
>  }
>
> -#ifndef TARGET_AARCH64
> -/*
> - * -cpu max: a CPU with as many features enabled as our emulation supports.
> - * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
> - * this only needs to handle 32 bits, and need not care about KVM.
> - */
> -static void arm_max_initfn(Object *obj)
> -{
> -    ARMCPU *cpu = ARM_CPU(obj);
> -
> -    /* Cortex-A57 advertising none of the aarch64 features */
> -    aarch64_aa32_a57_init(obj, true);
> -
> -    aa32_max_features(cpu);
> -
> -#ifdef CONFIG_USER_ONLY
> -    /*
> -     * Break with true ARMv8 and add back old-style VFP short-vector support.
> -     * Only do this for user-mode, where -cpu max is the default, so that
> -     * older v6 and v7 programs are more likely to work without adjustment.
> -     */
> -    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
> -#endif
> -}
> -#endif /* !TARGET_AARCH64 */
> -
>  static const ARMCPUInfo arm_tcg_cpus[] = {
>      { .name = "arm926",      .initfn = arm926_initfn },
>      { .name = "arm946",      .initfn = arm946_initfn },
> @@ -760,9 +734,6 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
>      { .name = "ti925t",      .initfn = ti925t_initfn },
>      { .name = "sa1100",      .initfn = sa1100_initfn },
>      { .name = "sa1110",      .initfn = sa1110_initfn },
> -#ifndef TARGET_AARCH64
> -    { .name = "max",         .initfn = arm_max_initfn },
> -#endif
>  };
>
>  static void arm_tcg_cpu_register_types(void)
> diff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c
> index 3945dc49e5e..78f819ef6ff 100644
> --- a/target/arm/tcg/stubs32.c
> +++ b/target/arm/tcg/stubs32.c
> @@ -22,3 +22,13 @@ void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,
>  {
>      g_assert_not_reached();
>  }
> +
> +void aarch64_host_initfn(Object *obj)
> +{
> +    g_assert_not_reached();
> +}
> +
> +void aarch64_max_tcg_initfn(Object *obj)
> +{
> +    g_assert_not_reached();
> +}
> --
> 2.53.0
>

Re: [PATCH v6 19/20] target/arm: Build cpu32-system.o as common object

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:12 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> cpu32.c only contains CPU types used in 32-bit system emulation:
> rename it as cpu32-system.c; always compile the file but only
> register the QOM types for the 32-bit binary.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>



>  target/arm/tcg/{cpu32.c => cpu32-system.c} | 19 ++++++-------------
>  target/arm/tcg/meson.build                 |  5 +----
>  2 files changed, 7 insertions(+), 17 deletions(-)
>  rename target/arm/tcg/{cpu32.c => cpu32-system.c} (98%)
>
> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32-system.c
> similarity index 98%
> rename from target/arm/tcg/cpu32.c
> rename to target/arm/tcg/cpu32-system.c
> index 8220d785f5b..51ed1f8f269 100644
> --- a/target/arm/tcg/cpu32.c
> +++ b/target/arm/tcg/cpu32-system.c
> @@ -1,5 +1,5 @@
>  /*
> - * QEMU ARM TCG-only CPUs.
> + * QEMU ARM TCG-only CPUs (not needed for the AArch64 linux-user build)
>   *
>   * Copyright (c) 2012 SUSE LINUX Products GmbH
>   *
> @@ -10,18 +10,13 @@
>
>  #include "qemu/osdep.h"
>  #include "qemu/units.h"
> +#include "qemu/target-info.h"
>  #include "cpu.h"
>  #include "accel/tcg/cpu-ops.h"
>  #include "internals.h"
> -#if !defined(CONFIG_USER_ONLY)
>  #include "hw/core/boards.h"
> -#endif
>  #include "cpregs.h"
>
> -
> -/* CPU models. These are not needed for the AArch64 linux-user build. */
> -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
> -
>  static void arm926_initfn(Object *obj)
>  {
>      ARMCPU *cpu = ARM_CPU(obj);
> @@ -738,13 +733,11 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
>
>  static void arm_tcg_cpu_register_types(void)
>  {
> -    size_t i;
> -
> -    for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
> -        arm_cpu_register(&arm_tcg_cpus[i]);
> +    if (target_arm()) {
> +        for (size_t i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
> +            arm_cpu_register(&arm_tcg_cpus[i]);
> +        }
>      }
>  }
>
>  type_init(arm_tcg_cpu_register_types)
> -
> -#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
> diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
> index f821331fbee..a6aac6deef0 100644
> --- a/target/arm/tcg/meson.build
> +++ b/target/arm/tcg/meson.build
> @@ -29,10 +29,6 @@ translate32_d = [
>
>  arm_stubs_ss.add(files('stubs32.c'))
>
> -arm_ss.add(files(
> -  'cpu32.c',
> -))
> -
>  arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64 + files(
>    'gengvec64.c',
>    'translate-a64.c',
> @@ -83,6 +79,7 @@ arm_common_user_system_ss.add(when: 'TARGET_AARCH64', if_true: files(
>
>  arm_common_system_ss.add(files(
>    'cpregs-at.c',
> +  'cpu32-system.c',
>    'gicv5-cpuif.c',
>    'psci.c',
>    'tlb_helper.c',
> --
> 2.53.0
>

Re: [PATCH v6 20/20] target/arm: Build cpu-max.c once

[Manos Pitsidianakis]

On Fri, May 15, 2026 at 5:13 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Call TargetInfo::target_aarch64() at runtime, allowing to
> remove the target-specific TARGET_AARCH64 definition and
> build cpu-max.c once as common object.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  target/arm/cpu-max.c   | 8 ++------
>  target/arm/meson.build | 2 +-
>  2 files changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c
> index 8cf8edc6535..d38bdfcf811 100644
> --- a/target/arm/cpu-max.c
> +++ b/target/arm/cpu-max.c
> @@ -8,6 +8,7 @@
>
>  #include "qemu/osdep.h"
>  #include "qemu/units.h"
> +#include "qemu/target-info.h"
>  #include "system/hw_accel.h"
>  #include "system/kvm.h"
>  #include "system/qtest.h"
> @@ -190,12 +191,7 @@ void aa32_max_features(ARMCPU *cpu)
>  static void cpu_max_initfn(Object *obj)
>  {
>      ARMCPU *cpu = ARM_CPU(obj);
> -
> -#ifdef TARGET_AARCH64
> -    const bool aarch64_enabled = true;
> -#else
> -    const bool aarch64_enabled = false;
> -#endif /* !TARGET_AARCH64 */
> +    const bool aarch64_enabled = target_aarch64();
>
>      if (hwaccel_enabled()) {
>          assert(aarch64_enabled);
> diff --git a/target/arm/meson.build b/target/arm/meson.build
> index 3e02941d0d5..9408131d178 100644
> --- a/target/arm/meson.build
> +++ b/target/arm/meson.build
> @@ -9,7 +9,6 @@ arm_user_ss = ss.source_set()
>  arm_common_system_ss.add(files('gdbstub.c'))
>  arm_user_ss.add(files('gdbstub.c'))
>
> -arm_ss.add(files('cpu-max.c'))
>  arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
>    'cpu64.c',
>  ))
> @@ -20,6 +19,7 @@ arm_common_ss.add(files(
>  arm_common_user_system_ss.add(files(
>    'cpregs-gcs.c',
>    'cpregs-pmu.c',
> +  'cpu-max.c',
>    'debug_helper.c',
>    'helper.c',
>    'vfp_fpscr.c',
> --
> 2.53.0
>

Re: [PATCH v6 04/20] hw/arm/aspeed: Initialize 64-bit CPU types during DeviceRealize()

[Cédric Le Goater]

On 5/15/26 16:10, Philippe Mathieu-Daudé wrote:
> aspeed_ast27x0.c models 2 similar SoC based on a 64-bit only
> CPU (Cortex-A35), only available in the 64-bit binary.
> 
> If we build this file as common object, these SoCs become
> available in both 32 and 64-bit binaries; however when running
> the introspection test on the 32-bit binary, the init() method
> tries to init the Cortex-A35 type -- although not realizing it
> -- which is not available. This can be avoided by deferring the
> CPU type initialization to the SoC DeviceRealize step (this is
> safe because nothing uses the CPU type before, only the GIC
> access them, just after their realization).

I understand this is a qtest workaround. Could we introduce
instead a (qtest_enabled() && 32-bit binary) helper ?

C.


> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/arm/aspeed_ast27x0.c | 7 ++-----
>   1 file changed, 2 insertions(+), 5 deletions(-)
> 
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 87dcb82e1b0..e50125bfeec 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -418,11 +418,6 @@ static void aspeed_soc_ast2700_init(Object *obj)
>           g_assert_not_reached();
>       }
>   
> -    for (i = 0; i < sc->num_cpus; i++) {
> -        object_initialize_child(obj, "cpu[*]", &a->cpu[i],
> -                                aspeed_soc_cpu_type(sc->valid_cpu_types));
> -    }
> -
>       object_initialize_child(obj, "gic", &a->gic, gicv3_class_name());
>   
>       object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
> @@ -701,6 +696,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
>   
>       /* CPU */
>       for (i = 0; i < sc->num_cpus; i++) {
> +        object_initialize_child(OBJECT(dev), "cpu[*]", &a->cpu[i],
> +                                aspeed_soc_cpu_type(sc->valid_cpu_types));
>           object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
>                                   aspeed_calc_affinity(i), &error_abort);
>   

Re: [PATCH v6 01/20] hw/arm: Build ARM/HVF GICv3 stub once

[Pierrick Bouvier]

On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote:
> Move arm_gicv3_hvf_stub.c, introduced in commit 48396ad6ce9
> ("hw/intc: arm_gicv3_hvf: save/restore Apple GIC state"), to
> the global stub_ss[] source set which holds stub files being
> built once for all binaries, instead of one time per system
> binary. This prevents symbol clash when trying to build a
> single QEMU system binary:
> 
>   clang: error: linker command failed with exit code 1 (use -v to see invocation)
>   duplicate symbol '_vmstate_gicv3_hvf' in:
>       libqemu-aarch64-softmmu.a.p/hw_intc_arm_gicv3_hvf_stub.c.o
>       libqemu-arm-softmmu.a.p/hw_intc_arm_gicv3_hvf_stub.c.o
>   ld: 1 duplicate symbols
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
> Reviewed-by: Mohamed Mediouni <mohamed@unpredictable.fr>
> ---
>  hw/intc/meson.build | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

Re: [PATCH v6 02/20] hw/arm/raspi: Initialize 64-bit CPU types during DeviceRealize()

[Pierrick Bouvier]

On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote:
> bcm2836.c models 3 similar SoC: BCM2835, BCM2836 and BCM2837.
> The BCM2837 is a 64-bit only SoC (Cortex-A53), only available
> in the 64-bit binary.
> 
> If we build this file as common object, all BCM SoCs become
> available in both 32 and 64-bit binaries; however when running
> the introspection test on the 32-bit binary, the BCM2837 init()
> method tries to init the Cortex-A53 type -- although not
> realizing it -- which is not available. This can be avoided by
> deferring the CPU type initialization to the SoC DeviceRealize
> step (this is safe because nothing uses the CPU type before,
> only the GIC access them, just after their realization).
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  hw/arm/bcm2836.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

Re: [PATCH v6 04/20] hw/arm/aspeed: Initialize 64-bit CPU types during DeviceRealize()

[Pierrick Bouvier]

On 5/15/2026 9:29 AM, Cédric Le Goater wrote:
> On 5/15/26 16:10, Philippe Mathieu-Daudé wrote:
>> aspeed_ast27x0.c models 2 similar SoC based on a 64-bit only
>> CPU (Cortex-A35), only available in the 64-bit binary.
>>
>> If we build this file as common object, these SoCs become
>> available in both 32 and 64-bit binaries; however when running
>> the introspection test on the 32-bit binary, the init() method
>> tries to init the Cortex-A35 type -- although not realizing it
>> -- which is not available. This can be avoided by deferring the
>> CPU type initialization to the SoC DeviceRealize step (this is
>> safe because nothing uses the CPU type before, only the GIC
>> access them, just after their realization).
> 
> I understand this is a qtest workaround. Could we introduce
> instead a (qtest_enabled() && 32-bit binary) helper ?
>

In general, it exposes a dependency issue in QOM type system.
In this case, we get a class depending on another one through
class_init. Moving this to realize seems like the best fix.

> C.
> 
> 
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   hw/arm/aspeed_ast27x0.c | 7 ++-----
>>   1 file changed, 2 insertions(+), 5 deletions(-)
>>
>> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
>> index 87dcb82e1b0..e50125bfeec 100644
>> --- a/hw/arm/aspeed_ast27x0.c
>> +++ b/hw/arm/aspeed_ast27x0.c
>> @@ -418,11 +418,6 @@ static void aspeed_soc_ast2700_init(Object *obj)
>>           g_assert_not_reached();
>>       }
>>   -    for (i = 0; i < sc->num_cpus; i++) {
>> -        object_initialize_child(obj, "cpu[*]", &a->cpu[i],
>> -                                aspeed_soc_cpu_type(sc-
>> >valid_cpu_types));
>> -    }
>> -
>>       object_initialize_child(obj, "gic", &a->gic, gicv3_class_name());
>>         object_initialize_child(obj, "scu", &s->scu,
>> TYPE_ASPEED_2700_SCU);
>> @@ -701,6 +696,8 @@ static void aspeed_soc_ast2700_realize(DeviceState
>> *dev, Error **errp)
>>         /* CPU */
>>       for (i = 0; i < sc->num_cpus; i++) {
>> +        object_initialize_child(OBJECT(dev), "cpu[*]", &a->cpu[i],
>> +                                aspeed_soc_cpu_type(sc-
>> >valid_cpu_types));
>>           object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
>>                                   aspeed_calc_affinity(i), &error_abort);
>>   
> 

Re: [PATCH v6 04/20] hw/arm/aspeed: Initialize 64-bit CPU types during DeviceRealize()

[Pierrick Bouvier]

On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote:
> aspeed_ast27x0.c models 2 similar SoC based on a 64-bit only
> CPU (Cortex-A35), only available in the 64-bit binary.
> 
> If we build this file as common object, these SoCs become
> available in both 32 and 64-bit binaries; however when running
> the introspection test on the 32-bit binary, the init() method
> tries to init the Cortex-A35 type -- although not realizing it
> -- which is not available. This can be avoided by deferring the
> CPU type initialization to the SoC DeviceRealize step (this is
> safe because nothing uses the CPU type before, only the GIC
> access them, just after their realization).
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  hw/arm/aspeed_ast27x0.c | 7 ++-----
>  1 file changed, 2 insertions(+), 5 deletions(-)
> 

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

Re: [PATCH v6 00/20] single-binary: Make hw/arm/ common

[Pierrick Bouvier]

On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote:
> Since v5:
> - Unify 'max' CPU type (rth, pm215)
> 
> Since v4:
> - Add DEFINE_MACHINE_WITH_INTERFACES (Zoltan)
> - Use GPtrArray for get_valid_cpu_type (Richard)
> - Define InterfaceInfo[] arrays (Richard)
> - Collect R-b tags
> 
> Since v3:
> - QAPI structure renamed as QemuTargetInfo
> - MachineClass::get_valid_cpu_types() runtime
> - target_aarch64() checking SysEmuTarget value
> - Remove CONFIG_TCG #ifdef'ry in hw/arm/
> 
> Since v2:
> - More comments from Pierrick addressed
> - Use GList to register valid CPUs list
> - Remove all TARGET_AARCH64 uses in hw/arm/
> 
> Since v1:
> - Dropped unrelated / irrelevant patches
> - Addressed Pierrick comments
> - Added R-b tag
> - Only considering machines, not CPUs.
> 
> Available here, based on my pending patch queue:
> https://gitlab.com/philmd/qemu/-/tags/single-binary-hw-arm-rfc-v5
> 
> Philippe Mathieu-Daudé (20):
>   hw/arm: Build ARM/HVF GICv3 stub once
>   hw/arm/raspi: Initialize 64-bit CPU types during DeviceRealize()
>   hw/arm/raspi: Build objects once
>   hw/arm/aspeed: Initialize 64-bit CPU types during DeviceRealize()
>   hw/arm/aspeed: Build objects once
>   hw/arm/meson: Remove now unused arm_ss[] source set
>   target/arm: Introduce common system/user meson source set
>   target/arm: Build gdbstub64.o as common object
>   target/arm: Build cpu64.o as common object
>   target/arm: Restrict IDAU interface to TCG namespace
>   target/arm: Rename Aarch64-specific methods
>   target/arm: Extract common code related to 'max' CPU
>   target/arm: Use make_ccsidr(LEGACY) in 32 bit 'max' CPU type
>   target/arm: Implement DBGDEVID* registers in max AArch32 CPU
>   target/arm: Only set %kvm_target when KVM is enabled
>   target/arm: Factor aarch64_aa32_a57_init() out
>   target/arm: Re-use common aarch64_aa32_a57_init() helper
>   target/arm: Define 'max' CPU type in cpu-max.c
>   target/arm: Build cpu32-system.o as common object
>   target/arm: Build cpu-max.c once
> 
>  include/hw/arm/armv7m.h                    |   2 +-
>  include/hw/misc/tz-msc.h                   |   2 +-
>  target/arm/internals.h                     |  10 +-
>  target/arm/{ => tcg}/idau.h                |   4 +-
>  hw/arm/armv7m.c                            |   2 +-
>  hw/arm/aspeed_ast27x0.c                    |   7 +-
>  hw/arm/bcm2836.c                           |  14 +-
>  hw/arm/raspi.c                             |   4 -
>  target/arm/cpu-max.c                       | 241 +++++++++++++++++++++
>  target/arm/cpu.c                           |  10 +-
>  target/arm/cpu32-stubs.c                   |   8 +-
>  target/arm/cpu64.c                         |  92 +-------
>  target/arm/ptw.c                           |   2 +-
>  target/arm/tcg/cpu-v7m.c                   |  11 +
>  target/arm/tcg/{cpu32.c => cpu32-system.c} | 191 +---------------
>  target/arm/tcg/stubs32.c                   |  10 +
>  hw/arm/meson.build                         |  15 +-
>  hw/intc/meson.build                        |   2 +-
>  target/arm/meson.build                     |  26 ++-
>  target/arm/tcg/meson.build                 |  60 ++---
>  20 files changed, 349 insertions(+), 364 deletions(-)
>  rename target/arm/{ => tcg}/idau.h (97%)
>  create mode 100644 target/arm/cpu-max.c
>  rename target/arm/tcg/{cpu32.c => cpu32-system.c} (80%)
> 

It seems there are some tests failing, and build failing also (on
kvm/arm with aarch64 host):
https://github.com/p-b-o/qemu-ci/actions/runs/25923481301

Regards,
Pierrick

Re: [PATCH v6 07/20] target/arm: Introduce common system/user meson source set

[Pierrick Bouvier]

On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote:
> Introduce a source set common to system / user.
> No logical change intended.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/arm/meson.build     | 21 +++++++++--------
>  target/arm/tcg/meson.build | 48 ++++++++++++--------------------------
>  2 files changed, 26 insertions(+), 43 deletions(-)
> 

It crossed my mind, and finally I kept duplication, without any real reason.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

Regards,
Pierrick

Re: [PATCH v6 08/20] target/arm: Build gdbstub64.o as common object

[Pierrick Bouvier]

On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote:
> While gdbstub64.o is already built once, build it as
> common object, reducing target-specific set in arm_ss[].
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/arm/meson.build | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

Re: [PATCH v6 09/20] target/arm: Build cpu64.o as common object

[Pierrick Bouvier]

On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote:
> While gdbstub64.o is already built once, build it as
> common object, reducing target-specific set in arm_ss[].
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/arm/tcg/meson.build | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 

With commit change as Manos mentioned:
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

Re: [PATCH v6 10/20] target/arm: Restrict IDAU interface to TCG namespace

[Pierrick Bouvier]

On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote:
> Emphasis the IDAU interface is restricted to TCG by
> moving the header under target/arm/tcg/. Move the
> definition to cpu-v7m.c which also contains v7/v8
> hardware (NVIC), keeping only CPU types in cpu32.c.
> 
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  include/hw/arm/armv7m.h     |  2 +-
>  include/hw/misc/tz-msc.h    |  2 +-
>  target/arm/{ => tcg}/idau.h |  4 ++--
>  hw/arm/armv7m.c             |  2 +-
>  target/arm/cpu.c            |  2 +-
>  target/arm/ptw.c            |  2 +-
>  target/arm/tcg/cpu-v7m.c    | 11 +++++++++++
>  target/arm/tcg/cpu32.c      |  8 --------
>  8 files changed, 18 insertions(+), 15 deletions(-)
>  rename target/arm/{ => tcg}/idau.h (97%)
> 
> diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
> index 98ad08db036..70555962bb9 100644
> --- a/include/hw/arm/armv7m.h
> +++ b/include/hw/arm/armv7m.h
> @@ -13,7 +13,7 @@
>  #include "hw/core/sysbus.h"
>  #include "hw/intc/armv7m_nvic.h"
>  #include "hw/misc/armv7m_ras.h"
> -#include "target/arm/idau.h"
> +#include "target/arm/tcg/idau.h"
>  #include "qom/object.h"
>  #include "hw/core/clock.h"
>  
> diff --git a/include/hw/misc/tz-msc.h b/include/hw/misc/tz-msc.h
> index 07112d8caa3..6cf4c6b09eb 100644
> --- a/include/hw/misc/tz-msc.h
> +++ b/include/hw/misc/tz-msc.h
> @@ -51,7 +51,7 @@
>  #define TZ_MSC_H
>  
>  #include "hw/core/sysbus.h"
> -#include "target/arm/idau.h"
> +#include "target/arm/tcg/idau.h"
>  #include "qom/object.h"
>  
>  #define TYPE_TZ_MSC "tz-msc"
> diff --git a/target/arm/idau.h b/target/arm/tcg/idau.h
> similarity index 97%
> rename from target/arm/idau.h
> rename to target/arm/tcg/idau.h
> index 0ef5251971d..e5736ad848d 100644
> --- a/target/arm/idau.h
> +++ b/target/arm/tcg/idau.h
> @@ -25,8 +25,8 @@
>   * connected to the CPU using a link property.
>   */
>  
> -#ifndef TARGET_ARM_IDAU_H
> -#define TARGET_ARM_IDAU_H
> +#ifndef TARGET_ARM_TCG_IDAU_H
> +#define TARGET_ARM_TCG_IDAU_H
>  
>  #include "qom/object.h"
>  
> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
> index a29eab6c915..68a1cbd6316 100644
> --- a/hw/arm/armv7m.c
> +++ b/hw/arm/armv7m.c
> @@ -20,7 +20,7 @@
>  #include "qemu/error-report.h"
>  #include "qemu/module.h"
>  #include "qemu/log.h"
> -#include "target/arm/idau.h"
> +#include "target/arm/tcg/idau.h"
>  #include "target/arm/cpu.h"
>  #include "target/arm/cpu-features.h"
>  #include "target/arm/cpu-qom.h"
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 31e0a12a986..76f5909e902 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -24,7 +24,6 @@
>  #include "qemu/log.h"
>  #include "exec/page-vary.h"
>  #include "system/whpx.h"
> -#include "target/arm/idau.h"
>  #include "qemu/module.h"
>  #include "qapi/error.h"
>  #include "cpu.h"
> @@ -42,6 +41,7 @@
>  #include "hw/intc/arm_gicv5_stream.h"
>  #ifdef CONFIG_TCG
>  #include "hw/intc/armv7m_nvic.h"
> +#include "target/arm/tcg/idau.h"
>  #endif /* CONFIG_TCG */
>  #endif /* !CONFIG_USER_ONLY */
>  #include "system/tcg.h"
> diff --git a/target/arm/ptw.c b/target/arm/ptw.c
> index 8706dd59dd6..a4842a4b62b 100644
> --- a/target/arm/ptw.c
> +++ b/target/arm/ptw.c
> @@ -17,7 +17,7 @@
>  #include "cpu.h"
>  #include "internals.h"
>  #include "cpu-features.h"
> -#include "idau.h"
> +#include "target/arm/tcg/idau.h"
>  
>  typedef struct S1Translate {
>      /*
> diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
> index dc249ce1f14..02abd831e6a 100644
> --- a/target/arm/tcg/cpu-v7m.c
> +++ b/target/arm/tcg/cpu-v7m.c
> @@ -11,6 +11,7 @@
>  #include "qemu/osdep.h"
>  #include "cpu.h"
>  #include "accel/tcg/cpu-ops.h"
> +#include "target/arm/tcg/idau.h"
>  #include "internals.h"
>  
>  #if !defined(CONFIG_USER_ONLY)
> @@ -40,6 +41,16 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
>      return ret;
>  }
>  
> +static const TypeInfo arm_v8m_types[] = {
> +    {
> +        .name = TYPE_IDAU_INTERFACE,
> +        .parent = TYPE_INTERFACE,
> +        .class_size = sizeof(IDAUInterfaceClass),
> +    }
> +};
> +
> +DEFINE_TYPES(arm_v8m_types)
> +
>  #endif /* !CONFIG_USER_ONLY */
>  
>  static void cortex_m0_initfn(Object *obj)
> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
> index 2127d456ad6..73d21c6cf7d 100644
> --- a/target/arm/tcg/cpu32.c
> +++ b/target/arm/tcg/cpu32.c
> @@ -12,7 +12,6 @@
>  #include "cpu.h"
>  #include "accel/tcg/cpu-ops.h"
>  #include "internals.h"
> -#include "target/arm/idau.h"
>  #if !defined(CONFIG_USER_ONLY)
>  #include "hw/core/boards.h"
>  #endif
> @@ -899,17 +898,10 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
>  #endif
>  };
>  
> -static const TypeInfo idau_interface_type_info = {
> -    .name = TYPE_IDAU_INTERFACE,
> -    .parent = TYPE_INTERFACE,
> -    .class_size = sizeof(IDAUInterfaceClass),
> -};
> -
>  static void arm_tcg_cpu_register_types(void)
>  {
>      size_t i;
>  
> -    type_register_static(&idau_interface_type_info);
>      for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
>          arm_cpu_register(&arm_tcg_cpus[i]);
>      }

That's the patch causing an issue for kvm/xen only build on aarch64 hosts.

../target/arm/cpu.c: In function ‘arm_cpu_post_init’:
../target/arm/cpu.c:1620:47: error: ‘TYPE_IDAU_INTERFACE’ undeclared
(first use in this function); did you mean ‘TYPE_INTERFACE’?
 1620 |         object_property_add_link(obj, "idau",
TYPE_IDAU_INTERFACE, &cpu->idau,
      |                                               ^~~~~~~~~~~~~~~~~~~
      |                                               TYPE_INTERFACE
../target/arm/cpu.c:1620:47: note: each undeclared identifier is
reported only once for each function it appears in

Re: [PATCH v6 12/20] target/arm: Extract common code related to 'max' CPU

[Pierrick Bouvier]

On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/arm/cpu-max.c   | 106 +++++++++++++++++++++++++++++++++++++++++
>  target/arm/tcg/cpu32.c |  96 -------------------------------------
>  target/arm/meson.build |   1 +
>  3 files changed, 107 insertions(+), 96 deletions(-)
>  create mode 100644 target/arm/cpu-max.c
> 
> diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c
> new file mode 100644
> index 00000000000..9fd48ce46e2
> --- /dev/null
> +++ b/target/arm/cpu-max.c
> @@ -0,0 +1,106 @@
> +/*
> + * QEMU ARM 'max' CPU
> + *
> + * Copyright (c) 2018 Linaro Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "target/arm/internals.h"
> +
> +/* Share AArch32 -cpu max features with AArch64. */
> +void aa32_max_features(ARMCPU *cpu)
> +{
> +    uint32_t t;
> +    ARMISARegisters *isar = &cpu->isar;
> +
> +    /* Add additional features supported by QEMU */
> +    t = GET_IDREG(isar, ID_ISAR5);
> +    t = FIELD_DP32(t, ID_ISAR5, AES, 2);          /* FEAT_PMULL */
> +    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);         /* FEAT_SHA1 */
> +    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);         /* FEAT_SHA256 */
> +    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
> +    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);          /* FEAT_RDM */
> +    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);         /* FEAT_FCMA */
> +    SET_IDREG(isar, ID_ISAR5, t);
> +
> +    t = GET_IDREG(isar, ID_ISAR6);
> +    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);        /* FEAT_JSCVT */
> +    t = FIELD_DP32(t, ID_ISAR6, DP, 1);           /* Feat_DotProd */
> +    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);          /* FEAT_FHM */
> +    t = FIELD_DP32(t, ID_ISAR6, SB, 1);           /* FEAT_SB */
> +    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);      /* FEAT_SPECRES */
> +    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);         /* FEAT_AA32BF16 */
> +    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);         /* FEAT_AA32I8MM */
> +    SET_IDREG(isar, ID_ISAR6, t);
> +
> +    t = cpu->isar.mvfr1;
> +    t = FIELD_DP32(t, MVFR1, FPHP, 3);            /* FEAT_FP16 */
> +    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);          /* FEAT_FP16 */
> +    cpu->isar.mvfr1 = t;
> +
> +    t = cpu->isar.mvfr2;
> +    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3);        /* SIMD MaxNum */
> +    t = FIELD_DP32(t, MVFR2, FPMISC, 4);          /* FP MaxNum */
> +    cpu->isar.mvfr2 = t;
> +
> +    FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2);          /* FEAT_PAN2 */
> +
> +    t = GET_IDREG(isar, ID_MMFR4);
> +    t = FIELD_DP32(t, ID_MMFR4, HPDS, 2);         /* FEAT_HPDS2 */
> +    t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
> +    t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
> +    t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
> +    t = FIELD_DP32(t, ID_MMFR4, EVT, 2);          /* FEAT_EVT */
> +    SET_IDREG(isar, ID_MMFR4, t);
> +
> +    FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2);          /* FEAT_ETS2 */
> +
> +    t = GET_IDREG(isar, ID_PFR0);
> +    t = FIELD_DP32(t, ID_PFR0, CSV2, 2);          /* FEAT_CSV2 */
> +    t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
> +    t = FIELD_DP32(t, ID_PFR0, RAS, 1);           /* FEAT_RAS */
> +    SET_IDREG(isar, ID_PFR0, t);
> +
> +    t = GET_IDREG(isar, ID_PFR2);
> +    t = FIELD_DP32(t, ID_PFR2, CSV3, 1);          /* FEAT_CSV3 */
> +    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
> +    SET_IDREG(isar, ID_PFR2, t);
> +
> +    t = GET_IDREG(isar, ID_DFR0);
> +    t = FIELD_DP32(t, ID_DFR0, COPDBG, 10);       /* FEAT_Debugv8p8 */
> +    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10);      /* FEAT_Debugv8p8 */
> +    t = FIELD_DP32(t, ID_DFR0, PERFMON, 6);       /* FEAT_PMUv3p5 */
> +    SET_IDREG(isar, ID_DFR0, t);
> +
> +    /* Debug ID registers. */
> +
> +    /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */
> +    t = 0x00008000;
> +    t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
> +    t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
> +    t = FIELD_DP32(t, DBGDIDR, VERSION, 10);      /* FEAT_Debugv8p8 */
> +    t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
> +    t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
> +    t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
> +    cpu->isar.dbgdidr = t;
> +
> +    t = 0;
> +    t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3);
> +    t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1);
> +    t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15);
> +    t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0);
> +    t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1);
> +    t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1);
> +    t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0);
> +    t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0);
> +    cpu->isar.dbgdevid = t;
> +
> +    /* Bits[31:4] are RES0. */
> +    t = 0;
> +    t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
> +    cpu->isar.dbgdevid1 = t;
> +
> +    FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1);         /* FEAT_HPMN0 */
> +}
> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
> index 73d21c6cf7d..919ed8a6cf8 100644
> --- a/target/arm/tcg/cpu32.c
> +++ b/target/arm/tcg/cpu32.c
> @@ -18,102 +18,6 @@
>  #include "cpregs.h"
>  
>  
> -/* Share AArch32 -cpu max features with AArch64. */
> -void aa32_max_features(ARMCPU *cpu)
> -{
> -    uint32_t t;
> -    ARMISARegisters *isar = &cpu->isar;
> -
> -    /* Add additional features supported by QEMU */
> -    t = GET_IDREG(isar, ID_ISAR5);
> -    t = FIELD_DP32(t, ID_ISAR5, AES, 2);          /* FEAT_PMULL */
> -    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);         /* FEAT_SHA1 */
> -    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);         /* FEAT_SHA256 */
> -    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
> -    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);          /* FEAT_RDM */
> -    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);         /* FEAT_FCMA */
> -    SET_IDREG(isar, ID_ISAR5, t);
> -
> -    t = GET_IDREG(isar, ID_ISAR6);
> -    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);        /* FEAT_JSCVT */
> -    t = FIELD_DP32(t, ID_ISAR6, DP, 1);           /* Feat_DotProd */
> -    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);          /* FEAT_FHM */
> -    t = FIELD_DP32(t, ID_ISAR6, SB, 1);           /* FEAT_SB */
> -    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);      /* FEAT_SPECRES */
> -    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);         /* FEAT_AA32BF16 */
> -    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);         /* FEAT_AA32I8MM */
> -    SET_IDREG(isar, ID_ISAR6, t);
> -
> -    t = cpu->isar.mvfr1;
> -    t = FIELD_DP32(t, MVFR1, FPHP, 3);            /* FEAT_FP16 */
> -    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);          /* FEAT_FP16 */
> -    cpu->isar.mvfr1 = t;
> -
> -    t = cpu->isar.mvfr2;
> -    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3);        /* SIMD MaxNum */
> -    t = FIELD_DP32(t, MVFR2, FPMISC, 4);          /* FP MaxNum */
> -    cpu->isar.mvfr2 = t;
> -
> -    FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2);          /* FEAT_PAN2 */
> -
> -    t = GET_IDREG(isar, ID_MMFR4);
> -    t = FIELD_DP32(t, ID_MMFR4, HPDS, 2);         /* FEAT_HPDS2 */
> -    t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
> -    t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
> -    t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
> -    t = FIELD_DP32(t, ID_MMFR4, EVT, 2);          /* FEAT_EVT */
> -    SET_IDREG(isar, ID_MMFR4, t);
> -
> -    FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2);          /* FEAT_ETS2 */
> -
> -    t = GET_IDREG(isar, ID_PFR0);
> -    t = FIELD_DP32(t, ID_PFR0, CSV2, 2);          /* FEAT_CSV2 */
> -    t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
> -    t = FIELD_DP32(t, ID_PFR0, RAS, 1);           /* FEAT_RAS */
> -    SET_IDREG(isar, ID_PFR0, t);
> -
> -    t = GET_IDREG(isar, ID_PFR2);
> -    t = FIELD_DP32(t, ID_PFR2, CSV3, 1);          /* FEAT_CSV3 */
> -    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
> -    SET_IDREG(isar, ID_PFR2, t);
> -
> -    t = GET_IDREG(isar, ID_DFR0);
> -    t = FIELD_DP32(t, ID_DFR0, COPDBG, 10);       /* FEAT_Debugv8p8 */
> -    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10);      /* FEAT_Debugv8p8 */
> -    t = FIELD_DP32(t, ID_DFR0, PERFMON, 6);       /* FEAT_PMUv3p5 */
> -    SET_IDREG(isar, ID_DFR0, t);
> -
> -    /* Debug ID registers. */
> -
> -    /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */
> -    t = 0x00008000;
> -    t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
> -    t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
> -    t = FIELD_DP32(t, DBGDIDR, VERSION, 10);      /* FEAT_Debugv8p8 */
> -    t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
> -    t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
> -    t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
> -    cpu->isar.dbgdidr = t;
> -
> -    t = 0;
> -    t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3);
> -    t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1);
> -    t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15);
> -    t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0);
> -    t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1);
> -    t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1);
> -    t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0);
> -    t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0);
> -    cpu->isar.dbgdevid = t;
> -
> -    /* Bits[31:4] are RES0. */
> -    t = 0;
> -    t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
> -    cpu->isar.dbgdevid1 = t;
> -
> -    FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1);         /* FEAT_HPMN0 */
> -}
> -
>  /* CPU models. These are not needed for the AArch64 linux-user build. */
>  #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
>  
> diff --git a/target/arm/meson.build b/target/arm/meson.build
> index 5376be2e3bc..3e02941d0d5 100644
> --- a/target/arm/meson.build
> +++ b/target/arm/meson.build
> @@ -9,6 +9,7 @@ arm_user_ss = ss.source_set()
>  arm_common_system_ss.add(files('gdbstub.c'))
>  arm_user_ss.add(files('gdbstub.c'))
>  
> +arm_ss.add(files('cpu-max.c'))
>  arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
>    'cpu64.c',
>  ))

Some bikeshedding: maybe name this cpu32-max.c for consistency?
No strong opinion though, just a feeling.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

Regards,
Pierrick

Re: [PATCH v6 13/20] target/arm: Use make_ccsidr(LEGACY) in 32 bit 'max' CPU type

[Pierrick Bouvier]

On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote:
> Commit 676624d757a ("target/arm/tcg: refine cache descriptions
> with a wrapper") added the make_ccsidr() helper. Use it. Besides
> being simpler to review, it also makes arm_max_initfn() more in
> line which aarch64_a57_initfn(), which it almost duplicates.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/arm/tcg/cpu32.c | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
> 

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

Re: [PATCH v6 14/20] target/arm: Implement DBGDEVID* registers in max AArch32 CPU

[Pierrick Bouvier]

On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote:
> 32-bit ARM max CPU is a 'Cortex-A57 advertising none of the AArch64
> features'. Keep it as close as possible as the A57, by implementing
> the debug ID registers, following the changes in aarch64_a57_initfn
> added by commits 48eb3ae64b3 ("target-arm: Adjust debug ID registers
> per-CPU") and 09754ca867f ("target/arm: Implement AArch32 DBGDEVID,
> DBGDEVID1, DBGDEVID2").
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/arm/tcg/cpu32.c | 3 +++
>  1 file changed, 3 insertions(+)
> 

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

Re: [PATCH v6 15/20] target/arm: Only set %kvm_target when KVM is enabled

[Pierrick Bouvier]

On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/arm/cpu64.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

Re: [PATCH v6 16/20] target/arm: Factor aarch64_aa32_a57_init() out

[Pierrick Bouvier]

On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote:
> In order to make the following commit easier to review,
> factor aarch64_aa32_a57_init() out of aarch64_a57_initfn()
> as a preliminary step. We only add a %aa32_only argument
> to restrict AArch64 features.
> 
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/arm/cpu64.c | 36 ++++++++++++++++++++++++------------
>  1 file changed, 24 insertions(+), 12 deletions(-)
> 

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

Re: [PATCH v6 17/20] target/arm: Re-use common aarch64_aa32_a57_init() helper

[Pierrick Bouvier]

On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote:
> Make aarch64_aa32_a57_init() common by exposing its prototype
> and defining it in cpu-max.c. Call it in arm_max_initfn()
> restricted to AArch32.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/arm/internals.h |  1 +
>  target/arm/cpu-max.c   | 74 ++++++++++++++++++++++++++++++++++++++++++
>  target/arm/cpu64.c     | 71 ----------------------------------------
>  target/arm/tcg/cpu32.c | 48 ++-------------------------
>  4 files changed, 77 insertions(+), 117 deletions(-)
> 

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

Re: [PATCH v6 12/20] target/arm: Extract common code related to 'max' CPU

[Pierrick Bouvier]

On 5/15/2026 10:10 AM, Pierrick Bouvier wrote:
> On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote:
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>  target/arm/cpu-max.c   | 106 +++++++++++++++++++++++++++++++++++++++++
>>  target/arm/tcg/cpu32.c |  96 -------------------------------------
>>  target/arm/meson.build |   1 +
>>  3 files changed, 107 insertions(+), 96 deletions(-)
>>  create mode 100644 target/arm/cpu-max.c
>>
>> diff --git a/target/arm/cpu-max.c b/target/arm/cpu-max.c
>> new file mode 100644
>> index 00000000000..9fd48ce46e2
>> --- /dev/null
>> +++ b/target/arm/cpu-max.c
>> @@ -0,0 +1,106 @@
>> +/*
>> + * QEMU ARM 'max' CPU
>> + *
>> + * Copyright (c) 2018 Linaro Ltd
>> + *
>> + * SPDX-License-Identifier: GPL-2.0-or-later
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "target/arm/internals.h"
>> +
>> +/* Share AArch32 -cpu max features with AArch64. */
>> +void aa32_max_features(ARMCPU *cpu)
>> +{
>> +    uint32_t t;
>> +    ARMISARegisters *isar = &cpu->isar;
>> +
>> +    /* Add additional features supported by QEMU */
>> +    t = GET_IDREG(isar, ID_ISAR5);
>> +    t = FIELD_DP32(t, ID_ISAR5, AES, 2);          /* FEAT_PMULL */
>> +    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);         /* FEAT_SHA1 */
>> +    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);         /* FEAT_SHA256 */
>> +    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
>> +    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);          /* FEAT_RDM */
>> +    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);         /* FEAT_FCMA */
>> +    SET_IDREG(isar, ID_ISAR5, t);
>> +
>> +    t = GET_IDREG(isar, ID_ISAR6);
>> +    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);        /* FEAT_JSCVT */
>> +    t = FIELD_DP32(t, ID_ISAR6, DP, 1);           /* Feat_DotProd */
>> +    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);          /* FEAT_FHM */
>> +    t = FIELD_DP32(t, ID_ISAR6, SB, 1);           /* FEAT_SB */
>> +    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);      /* FEAT_SPECRES */
>> +    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);         /* FEAT_AA32BF16 */
>> +    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);         /* FEAT_AA32I8MM */
>> +    SET_IDREG(isar, ID_ISAR6, t);
>> +
>> +    t = cpu->isar.mvfr1;
>> +    t = FIELD_DP32(t, MVFR1, FPHP, 3);            /* FEAT_FP16 */
>> +    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);          /* FEAT_FP16 */
>> +    cpu->isar.mvfr1 = t;
>> +
>> +    t = cpu->isar.mvfr2;
>> +    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3);        /* SIMD MaxNum */
>> +    t = FIELD_DP32(t, MVFR2, FPMISC, 4);          /* FP MaxNum */
>> +    cpu->isar.mvfr2 = t;
>> +
>> +    FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2);          /* FEAT_PAN2 */
>> +
>> +    t = GET_IDREG(isar, ID_MMFR4);
>> +    t = FIELD_DP32(t, ID_MMFR4, HPDS, 2);         /* FEAT_HPDS2 */
>> +    t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
>> +    t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
>> +    t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
>> +    t = FIELD_DP32(t, ID_MMFR4, EVT, 2);          /* FEAT_EVT */
>> +    SET_IDREG(isar, ID_MMFR4, t);
>> +
>> +    FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2);          /* FEAT_ETS2 */
>> +
>> +    t = GET_IDREG(isar, ID_PFR0);
>> +    t = FIELD_DP32(t, ID_PFR0, CSV2, 2);          /* FEAT_CSV2 */
>> +    t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
>> +    t = FIELD_DP32(t, ID_PFR0, RAS, 1);           /* FEAT_RAS */
>> +    SET_IDREG(isar, ID_PFR0, t);
>> +
>> +    t = GET_IDREG(isar, ID_PFR2);
>> +    t = FIELD_DP32(t, ID_PFR2, CSV3, 1);          /* FEAT_CSV3 */
>> +    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
>> +    SET_IDREG(isar, ID_PFR2, t);
>> +
>> +    t = GET_IDREG(isar, ID_DFR0);
>> +    t = FIELD_DP32(t, ID_DFR0, COPDBG, 10);       /* FEAT_Debugv8p8 */
>> +    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10);      /* FEAT_Debugv8p8 */
>> +    t = FIELD_DP32(t, ID_DFR0, PERFMON, 6);       /* FEAT_PMUv3p5 */
>> +    SET_IDREG(isar, ID_DFR0, t);
>> +
>> +    /* Debug ID registers. */
>> +
>> +    /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */
>> +    t = 0x00008000;
>> +    t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
>> +    t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
>> +    t = FIELD_DP32(t, DBGDIDR, VERSION, 10);      /* FEAT_Debugv8p8 */
>> +    t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
>> +    t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
>> +    t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
>> +    cpu->isar.dbgdidr = t;
>> +
>> +    t = 0;
>> +    t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3);
>> +    t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1);
>> +    t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15);
>> +    t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0);
>> +    t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1);
>> +    t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1);
>> +    t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0);
>> +    t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0);
>> +    cpu->isar.dbgdevid = t;
>> +
>> +    /* Bits[31:4] are RES0. */
>> +    t = 0;
>> +    t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
>> +    cpu->isar.dbgdevid1 = t;
>> +
>> +    FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1);         /* FEAT_HPMN0 */
>> +}
>> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
>> index 73d21c6cf7d..919ed8a6cf8 100644
>> --- a/target/arm/tcg/cpu32.c
>> +++ b/target/arm/tcg/cpu32.c
>> @@ -18,102 +18,6 @@
>>  #include "cpregs.h"
>>  
>>  
>> -/* Share AArch32 -cpu max features with AArch64. */
>> -void aa32_max_features(ARMCPU *cpu)
>> -{
>> -    uint32_t t;
>> -    ARMISARegisters *isar = &cpu->isar;
>> -
>> -    /* Add additional features supported by QEMU */
>> -    t = GET_IDREG(isar, ID_ISAR5);
>> -    t = FIELD_DP32(t, ID_ISAR5, AES, 2);          /* FEAT_PMULL */
>> -    t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);         /* FEAT_SHA1 */
>> -    t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);         /* FEAT_SHA256 */
>> -    t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
>> -    t = FIELD_DP32(t, ID_ISAR5, RDM, 1);          /* FEAT_RDM */
>> -    t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);         /* FEAT_FCMA */
>> -    SET_IDREG(isar, ID_ISAR5, t);
>> -
>> -    t = GET_IDREG(isar, ID_ISAR6);
>> -    t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);        /* FEAT_JSCVT */
>> -    t = FIELD_DP32(t, ID_ISAR6, DP, 1);           /* Feat_DotProd */
>> -    t = FIELD_DP32(t, ID_ISAR6, FHM, 1);          /* FEAT_FHM */
>> -    t = FIELD_DP32(t, ID_ISAR6, SB, 1);           /* FEAT_SB */
>> -    t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);      /* FEAT_SPECRES */
>> -    t = FIELD_DP32(t, ID_ISAR6, BF16, 1);         /* FEAT_AA32BF16 */
>> -    t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);         /* FEAT_AA32I8MM */
>> -    SET_IDREG(isar, ID_ISAR6, t);
>> -
>> -    t = cpu->isar.mvfr1;
>> -    t = FIELD_DP32(t, MVFR1, FPHP, 3);            /* FEAT_FP16 */
>> -    t = FIELD_DP32(t, MVFR1, SIMDHP, 2);          /* FEAT_FP16 */
>> -    cpu->isar.mvfr1 = t;
>> -
>> -    t = cpu->isar.mvfr2;
>> -    t = FIELD_DP32(t, MVFR2, SIMDMISC, 3);        /* SIMD MaxNum */
>> -    t = FIELD_DP32(t, MVFR2, FPMISC, 4);          /* FP MaxNum */
>> -    cpu->isar.mvfr2 = t;
>> -
>> -    FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2);          /* FEAT_PAN2 */
>> -
>> -    t = GET_IDREG(isar, ID_MMFR4);
>> -    t = FIELD_DP32(t, ID_MMFR4, HPDS, 2);         /* FEAT_HPDS2 */
>> -    t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
>> -    t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
>> -    t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
>> -    t = FIELD_DP32(t, ID_MMFR4, EVT, 2);          /* FEAT_EVT */
>> -    SET_IDREG(isar, ID_MMFR4, t);
>> -
>> -    FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2);          /* FEAT_ETS2 */
>> -
>> -    t = GET_IDREG(isar, ID_PFR0);
>> -    t = FIELD_DP32(t, ID_PFR0, CSV2, 2);          /* FEAT_CSV2 */
>> -    t = FIELD_DP32(t, ID_PFR0, DIT, 1);           /* FEAT_DIT */
>> -    t = FIELD_DP32(t, ID_PFR0, RAS, 1);           /* FEAT_RAS */
>> -    SET_IDREG(isar, ID_PFR0, t);
>> -
>> -    t = GET_IDREG(isar, ID_PFR2);
>> -    t = FIELD_DP32(t, ID_PFR2, CSV3, 1);          /* FEAT_CSV3 */
>> -    t = FIELD_DP32(t, ID_PFR2, SSBS, 1);          /* FEAT_SSBS */
>> -    SET_IDREG(isar, ID_PFR2, t);
>> -
>> -    t = GET_IDREG(isar, ID_DFR0);
>> -    t = FIELD_DP32(t, ID_DFR0, COPDBG, 10);       /* FEAT_Debugv8p8 */
>> -    t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10);      /* FEAT_Debugv8p8 */
>> -    t = FIELD_DP32(t, ID_DFR0, PERFMON, 6);       /* FEAT_PMUv3p5 */
>> -    SET_IDREG(isar, ID_DFR0, t);
>> -
>> -    /* Debug ID registers. */
>> -
>> -    /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */
>> -    t = 0x00008000;
>> -    t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
>> -    t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
>> -    t = FIELD_DP32(t, DBGDIDR, VERSION, 10);      /* FEAT_Debugv8p8 */
>> -    t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
>> -    t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
>> -    t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
>> -    cpu->isar.dbgdidr = t;
>> -
>> -    t = 0;
>> -    t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3);
>> -    t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1);
>> -    t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15);
>> -    t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0);
>> -    t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1);
>> -    t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1);
>> -    t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0);
>> -    t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0);
>> -    cpu->isar.dbgdevid = t;
>> -
>> -    /* Bits[31:4] are RES0. */
>> -    t = 0;
>> -    t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
>> -    cpu->isar.dbgdevid1 = t;
>> -
>> -    FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1);         /* FEAT_HPMN0 */
>> -}
>> -
>>  /* CPU models. These are not needed for the AArch64 linux-user build. */
>>  #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
>>  
>> diff --git a/target/arm/meson.build b/target/arm/meson.build
>> index 5376be2e3bc..3e02941d0d5 100644
>> --- a/target/arm/meson.build
>> +++ b/target/arm/meson.build
>> @@ -9,6 +9,7 @@ arm_user_ss = ss.source_set()
>>  arm_common_system_ss.add(files('gdbstub.c'))
>>  arm_user_ss.add(files('gdbstub.c'))
>>  
>> +arm_ss.add(files('cpu-max.c'))
>>  arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
>>    'cpu64.c',
>>  ))
> 
> Some bikeshedding: maybe name this cpu32-max.c for consistency?
> No strong opinion though, just a feeling.
>

Seeing patch 16/17, forget my remark above.

> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> 
> Regards,
> Pierrick

Re: [PATCH v6 19/20] target/arm: Build cpu32-system.o as common object

[Pierrick Bouvier]

On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote:
> cpu32.c only contains CPU types used in 32-bit system emulation:
> rename it as cpu32-system.c; always compile the file but only
> register the QOM types for the 32-bit binary.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/arm/tcg/{cpu32.c => cpu32-system.c} | 19 ++++++-------------
>  target/arm/tcg/meson.build                 |  5 +----
>  2 files changed, 7 insertions(+), 17 deletions(-)
>  rename target/arm/tcg/{cpu32.c => cpu32-system.c} (98%)
> 

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

Re: [PATCH v6 20/20] target/arm: Build cpu-max.c once

[Pierrick Bouvier]

On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote:
> Call TargetInfo::target_aarch64() at runtime, allowing to
> remove the target-specific TARGET_AARCH64 definition and
> build cpu-max.c once as common object.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/arm/cpu-max.c   | 8 ++------
>  target/arm/meson.build | 2 +-
>  2 files changed, 3 insertions(+), 7 deletions(-)
> 

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

Re: [PATCH v6 04/20] hw/arm/aspeed: Initialize 64-bit CPU types during DeviceRealize()

[Cédric Le Goater]

On 5/15/26 19:00, Pierrick Bouvier wrote:
> On 5/15/2026 9:29 AM, Cédric Le Goater wrote:
>> On 5/15/26 16:10, Philippe Mathieu-Daudé wrote:
>>> aspeed_ast27x0.c models 2 similar SoC based on a 64-bit only
>>> CPU (Cortex-A35), only available in the 64-bit binary.
>>>
>>> If we build this file as common object, these SoCs become
>>> available in both 32 and 64-bit binaries; however when running
>>> the introspection test on the 32-bit binary, the init() method
>>> tries to init the Cortex-A35 type -- although not realizing it
>>> -- which is not available. This can be avoided by deferring the
>>> CPU type initialization to the SoC DeviceRealize step (this is
>>> safe because nothing uses the CPU type before, only the GIC
>>> access them, just after their realization).
>>
>> I understand this is a qtest workaround. Could we introduce
>> instead a (qtest_enabled() && 32-bit binary) helper ?
>>
> 
> In general, it exposes a dependency issue in QOM type system.
> In this case, we get a class depending on another one through
> class_init. Moving this to realize seems like the best fix.

My feeling is that this goes against the best modeling practices
we have tried to put in place over the last decade.

C.

Re: [PATCH v6 04/20] hw/arm/aspeed: Initialize 64-bit CPU types during DeviceRealize()

[Pierrick Bouvier]

On 5/15/2026 10:18 AM, Cédric Le Goater wrote:
> On 5/15/26 19:00, Pierrick Bouvier wrote:
>> On 5/15/2026 9:29 AM, Cédric Le Goater wrote:
>>> On 5/15/26 16:10, Philippe Mathieu-Daudé wrote:
>>>> aspeed_ast27x0.c models 2 similar SoC based on a 64-bit only
>>>> CPU (Cortex-A35), only available in the 64-bit binary.
>>>>
>>>> If we build this file as common object, these SoCs become
>>>> available in both 32 and 64-bit binaries; however when running
>>>> the introspection test on the 32-bit binary, the init() method
>>>> tries to init the Cortex-A35 type -- although not realizing it
>>>> -- which is not available. This can be avoided by deferring the
>>>> CPU type initialization to the SoC DeviceRealize step (this is
>>>> safe because nothing uses the CPU type before, only the GIC
>>>> access them, just after their realization).
>>>
>>> I understand this is a qtest workaround. Could we introduce
>>> instead a (qtest_enabled() && 32-bit binary) helper ?
>>>
>>
>> In general, it exposes a dependency issue in QOM type system.
>> In this case, we get a class depending on another one through
>> class_init. Moving this to realize seems like the best fix.
> 
> My feeling is that this goes against the best modeling practices
> we have tried to put in place over the last decade.
>

In this case, adding the workaround you suggested might be the best
approach indeed.

> C.
> 

Re: [PATCH v6 18/20] target/arm: Define 'max' CPU type in cpu-max.c

[Pierrick Bouvier]

On 5/15/2026 7:10 AM, Philippe Mathieu-Daudé wrote:
> Rather than having the 32-bit 'max' CPU type defined in
> cpu32.c and the 64-bit counter part in cpu64.c, unify the
> code in a single place in cpu-max.c. Define stubs for
> aarch64_host_initfn() and aarch64_max_tcg_initfn() in the
> 32-bit binary.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/arm/internals.h   |  1 +
>  target/arm/cpu-max.c     | 65 ++++++++++++++++++++++++++++++++++++++++
>  target/arm/cpu64.c       | 21 +------------
>  target/arm/tcg/cpu32.c   | 29 ------------------
>  target/arm/tcg/stubs32.c | 10 +++++++
>  5 files changed, 77 insertions(+), 49 deletions(-)
> 

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

Re: [PATCH v6 04/20] hw/arm/aspeed: Initialize 64-bit CPU types during DeviceRealize()

[Cédric Le Goater]

On 5/15/26 19:22, Pierrick Bouvier wrote:
> On 5/15/2026 10:18 AM, Cédric Le Goater wrote:
>> On 5/15/26 19:00, Pierrick Bouvier wrote:
>>> On 5/15/2026 9:29 AM, Cédric Le Goater wrote:
>>>> On 5/15/26 16:10, Philippe Mathieu-Daudé wrote:
>>>>> aspeed_ast27x0.c models 2 similar SoC based on a 64-bit only
>>>>> CPU (Cortex-A35), only available in the 64-bit binary.
>>>>>
>>>>> If we build this file as common object, these SoCs become
>>>>> available in both 32 and 64-bit binaries; however when running
>>>>> the introspection test on the 32-bit binary, the init() method
>>>>> tries to init the Cortex-A35 type -- although not realizing it
>>>>> -- which is not available. This can be avoided by deferring the
>>>>> CPU type initialization to the SoC DeviceRealize step (this is
>>>>> safe because nothing uses the CPU type before, only the GIC
>>>>> access them, just after their realization).
>>>>
>>>> I understand this is a qtest workaround. Could we introduce
>>>> instead a (qtest_enabled() && 32-bit binary) helper ?
>>>>
>>>
>>> In general, it exposes a dependency issue in QOM type system.
>>> In this case, we get a class depending on another one through
>>> class_init. Moving this to realize seems like the best fix.
>>
>> My feeling is that this goes against the best modeling practices
>> we have tried to put in place over the last decade.
>>
> 
> In this case, adding the workaround you suggested might be the best
> approach indeed.


Well, if we want to make progress, let's at least add a comment
for better fix later.

C.