[PATCH 0/3] More SI power management and PLL fixes

[PATCH 0/3] More SI power management and PLL fixes

[Timur Kristóf]

This series has a few minor patches to address some SI issues.

When a 4K 60Hz display is connected to Tahiti or Pitcairn
there is a slight flickering near the bottom of the display.
Disabling MCLK switching fixes that.
(Other SI parts are likely affected too, but I didn't test
them thoroughly enough to say.)

When enabling ASPM on Zen 4 with Tahiti and Oland,
there are random hangs when the GPU usage is low.
Disabling ASPM fixes that.
At the moment I don't know if this is a platform-specific or
GPU-specific issue and I don't think we can reasonably
determine that without spending more time than we have.
(Other SI parts may be affected, but I didn't test them
for a long enough time to judge that.)

Finally, there is a DC patch to change the minimum PLL
dividers to the same value as the legacy non-DC display code.
This doesn't fix any visible issue but I think it's still
good to have just in case.

Timur Kristóf (3):
  drm/amd/pm: Disable MCLK switching on SI at high pixel clocks
  drm/amd: Disable ASPM on SI
  drm/amd/display: Set stricter clock dividers on DCE 6-10

 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c            | 7 +++++++
 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +++++++
 drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c            | 5 +++++
 3 files changed, 19 insertions(+)

-- 
2.51.0

[PATCH 1/3] drm/amd/pm: Disable MCLK switching on SI at high pixel clocks

[Timur Kristóf]

On various SI GPUs, a flickering can be observed near the bottom
edge of the screen when using a single 4K 60Hz monitor over DP.
Disabling MCLK switching works around this problem.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index cf9932e68055..3a9522c17fee 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
@@ -3500,6 +3500,11 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
 	 * for these GPUs to calculate bandwidth requirements.
 	 */
 	if (high_pixelclock_count) {
+		/* Work around flickering lines at the bottom edge
+		 * of the screen when using a single 4K 60Hz monitor.
+		 */
+		disable_mclk_switching = true;
+
 		/* On Oland, we observe some flickering when two 4K 60Hz
 		 * displays are connected, possibly because voltage is too low.
 		 * Raise the voltage by requiring a higher SCLK.
-- 
2.51.0

Re: [PATCH 1/3] drm/amd/pm: Disable MCLK switching on SI at high pixel clocks

[Alex Deucher]

On Fri, Sep 26, 2025 at 2:26 PM Timur Kristóf <timur.kristof@gmail.com> wrote:
>
> On various SI GPUs, a flickering can be observed near the bottom
> edge of the screen when using a single 4K 60Hz monitor over DP.
> Disabling MCLK switching works around this problem.
>
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> index cf9932e68055..3a9522c17fee 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> @@ -3500,6 +3500,11 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
>          * for these GPUs to calculate bandwidth requirements.
>          */
>         if (high_pixelclock_count) {
> +               /* Work around flickering lines at the bottom edge
> +                * of the screen when using a single 4K 60Hz monitor.
> +                */
> +               disable_mclk_switching = true;
> +
>                 /* On Oland, we observe some flickering when two 4K 60Hz
>                  * displays are connected, possibly because voltage is too low.
>                  * Raise the voltage by requiring a higher SCLK.
> --
> 2.51.0
>

[PATCH 2/3] drm/amd: Disable ASPM on SI

[Timur Kristóf]

Enabling ASPM causes randoms hangs on Tahiti and Oland on Zen4.
It's unclear if this is a platform-specific or GPU-specific issue.
Disable ASPM on SI for the time being.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a77000c2e0bb..279b6912be2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1882,6 +1882,13 @@ static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device
 
 static bool amdgpu_device_aspm_support_quirk(struct amdgpu_device *adev)
 {
+	/* Enabling ASPM causes randoms hangs on Tahiti and Oland on Zen4.
+	 * It's unclear if this is a platform-specific or GPU-specific issue.
+	 * Disable ASPM on SI for the time being.
+	 */
+	if (adev->family == AMDGPU_FAMILY_SI)
+		return true;
+
 #if IS_ENABLED(CONFIG_X86)
 	struct cpuinfo_x86 *c = &cpu_data(0);
 
-- 
2.51.0

Re: [PATCH 2/3] drm/amd: Disable ASPM on SI

[Alex Deucher]

On Fri, Sep 26, 2025 at 2:44 PM Timur Kristóf <timur.kristof@gmail.com> wrote:
>
> Enabling ASPM causes randoms hangs on Tahiti and Oland on Zen4.
> It's unclear if this is a platform-specific or GPU-specific issue.
> Disable ASPM on SI for the time being.
>
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Will pick up patches 1 and 2 today.

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index a77000c2e0bb..279b6912be2a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1882,6 +1882,13 @@ static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device
>
>  static bool amdgpu_device_aspm_support_quirk(struct amdgpu_device *adev)
>  {
> +       /* Enabling ASPM causes randoms hangs on Tahiti and Oland on Zen4.
> +        * It's unclear if this is a platform-specific or GPU-specific issue.
> +        * Disable ASPM on SI for the time being.
> +        */
> +       if (adev->family == AMDGPU_FAMILY_SI)
> +               return true;
> +
>  #if IS_ENABLED(CONFIG_X86)
>         struct cpuinfo_x86 *c = &cpu_data(0);
>
> --
> 2.51.0
>

[PATCH 3/3] drm/amd/display: Set stricter clock dividers on DCE 6-10

[Timur Kristóf]

Set stricter dividers to stabilize the PLL's feedback loop.
In practice, the actual output isn't exactly the target
clock, but slowly oscillates around it. This makes it
more stable.

The values here are taken from the non-DC code.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index b4f5b4a6331a..00f25e2ee081 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -1700,6 +1700,13 @@ bool dce110_clk_src_construct(
 			clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
 	calc_pll_cs_init_data.min_pll_ref_divider =	1;
 	calc_pll_cs_init_data.max_pll_ref_divider =	clk_src->cs_mask->PLL_REF_DIV;
+
+	if (ctx->dce_version <= DCE_VERSION_10_0) {
+		/* Set stricter dividers to stabilize the PLL's feedback loop on old HW. */
+		calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 2;
+		calc_pll_cs_init_data.min_pll_ref_divider = 2;
+	}
+
 	/* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
 	calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz =	0;
 	/* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
-- 
2.51.0

Re: [PATCH 3/3] drm/amd/display: Set stricter clock dividers on DCE 6-10

[Christian König]

On 26.09.25 20:26, Timur Kristóf wrote:
> Set stricter dividers to stabilize the PLL's feedback loop.
> In practice, the actual output isn't exactly the target
> clock, but slowly oscillates around it. This makes it
> more stable.
> 
> The values here are taken from the non-DC code.

There are also a bunch of other restrictions which need to be kept in mind.

For example what is the minimum feedback divider value the DC code uses?

We once had a longer discussion with the PLL HW engineers to get this working because at least the display code we used as reference back then got it wrong.

Regards,
Christian.

> 
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
>  drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> index b4f5b4a6331a..00f25e2ee081 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> @@ -1700,6 +1700,13 @@ bool dce110_clk_src_construct(
>  			clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
>  	calc_pll_cs_init_data.min_pll_ref_divider =	1;
>  	calc_pll_cs_init_data.max_pll_ref_divider =	clk_src->cs_mask->PLL_REF_DIV;
> +
> +	if (ctx->dce_version <= DCE_VERSION_10_0) {
> +		/* Set stricter dividers to stabilize the PLL's feedback loop on old HW. */
> +		calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 2;
> +		calc_pll_cs_init_data.min_pll_ref_divider = 2;
> +	}
> +
>  	/* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
>  	calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz =	0;
>  	/* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/

Re: [PATCH 3/3] drm/amd/display: Set stricter clock dividers on DCE 6-10

[timur.kristof]

On Sun, 2025-09-28 at 16:14 +0200, Christian König wrote:
> 
> 
> On 26.09.25 20:26, Timur Kristóf wrote:
> > Set stricter dividers to stabilize the PLL's feedback loop.
> > In practice, the actual output isn't exactly the target
> > clock, but slowly oscillates around it. This makes it
> > more stable.
> > 
> > The values here are taken from the non-DC code.
> 
> There are also a bunch of other restrictions which need to be kept in
> mind.
> 
> For example what is the minimum feedback divider value the DC code
> uses?

As far as I see DC doesn't have minimum / maximum limits for the
feedback divider right now, though I can add that in a future patch if
necessary.

> 
> We once had a longer discussion with the PLL HW engineers to get this
> working because at least the display code we used as reference back
> then got it wrong.

After this series is reviewed, I can look through the other
restrictions in the amdgpu_atombios_get_clock_info function and write
another patch series to add those restrictions to DC.

> 
> > ---
> >  drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> > b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> > index b4f5b4a6331a..00f25e2ee081 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> > @@ -1700,6 +1700,13 @@ bool dce110_clk_src_construct(
> >  			clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
> >  	calc_pll_cs_init_data.min_pll_ref_divider =	1;
> >  	calc_pll_cs_init_data.max_pll_ref_divider =	clk_src-
> > >cs_mask->PLL_REF_DIV;
> > +
> > +	if (ctx->dce_version <= DCE_VERSION_10_0) {
> > +		/* Set stricter dividers to stabilize the PLL's
> > feedback loop on old HW. */
> > +		calc_pll_cs_init_data.min_pix_clk_pll_post_divider
> > = 2;
> > +		calc_pll_cs_init_data.min_pll_ref_divider = 2;
> > +	}
> > +
> >  	/* when 0 use minInputPxlClkPLLFrequencyInKHz from
> > firmwareInfo*/
> >  	calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_
> > khz =	0;
> >  	/* when 0 use maxInputPxlClkPLLFrequencyInKHz from
> > firmwareInfo*/

Re: [PATCH 3/3] drm/amd/display: Set stricter clock dividers on DCE 6-10

[Alex Deucher]

On Sun, Sep 28, 2025 at 7:39 PM <timur.kristof@gmail.com> wrote:
>
> On Sun, 2025-09-28 at 16:14 +0200, Christian König wrote:
> >
> >
> > On 26.09.25 20:26, Timur Kristóf wrote:
> > > Set stricter dividers to stabilize the PLL's feedback loop.
> > > In practice, the actual output isn't exactly the target
> > > clock, but slowly oscillates around it. This makes it
> > > more stable.
> > >
> > > The values here are taken from the non-DC code.
> >
> > There are also a bunch of other restrictions which need to be kept in
> > mind.
> >
> > For example what is the minimum feedback divider value the DC code
> > uses?
>
> As far as I see DC doesn't have minimum / maximum limits for the
> feedback divider right now, though I can add that in a future patch if
> necessary.
>
> >
> > We once had a longer discussion with the PLL HW engineers to get this
> > working because at least the display code we used as reference back
> > then got it wrong.
>
> After this series is reviewed, I can look through the other
> restrictions in the amdgpu_atombios_get_clock_info function and write
> another patch series to add those restrictions to DC.
>

The PPLL limits from radeon and the non-DC code were based on the PLL
registers, i.e., what the hardware limit in the register was.  I'm not
sure what the practical limits really are per se.  I.e., if the whole
range is really usable or not.  I would tend to defer to DC.

Alex

> >
> > > ---
> > >  drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +++++++
> > >  1 file changed, 7 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> > > b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> > > index b4f5b4a6331a..00f25e2ee081 100644
> > > --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> > > +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> > > @@ -1700,6 +1700,13 @@ bool dce110_clk_src_construct(
> > >                     clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
> > >     calc_pll_cs_init_data.min_pll_ref_divider =     1;
> > >     calc_pll_cs_init_data.max_pll_ref_divider =     clk_src-
> > > >cs_mask->PLL_REF_DIV;
> > > +
> > > +   if (ctx->dce_version <= DCE_VERSION_10_0) {
> > > +           /* Set stricter dividers to stabilize the PLL's
> > > feedback loop on old HW. */
> > > +           calc_pll_cs_init_data.min_pix_clk_pll_post_divider
> > > = 2;
> > > +           calc_pll_cs_init_data.min_pll_ref_divider = 2;
> > > +   }
> > > +
> > >     /* when 0 use minInputPxlClkPLLFrequencyInKHz from
> > > firmwareInfo*/
> > >     calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_
> > > khz =       0;
> > >     /* when 0 use maxInputPxlClkPLLFrequencyInKHz from
> > > firmwareInfo*/

Re: [PATCH 3/3] drm/amd/display: Set stricter clock dividers on DCE 6-10

[Timur Kristóf]

On 10/9/25 21:38, Alex Deucher wrote:
> On Sun, Sep 28, 2025 at 7:39 PM <timur.kristof@gmail.com> wrote:
>>
>> On Sun, 2025-09-28 at 16:14 +0200, Christian König wrote:
>>>
>>>
>>> On 26.09.25 20:26, Timur Kristóf wrote:
>>>> Set stricter dividers to stabilize the PLL's feedback loop.
>>>> In practice, the actual output isn't exactly the target
>>>> clock, but slowly oscillates around it. This makes it
>>>> more stable.
>>>>
>>>> The values here are taken from the non-DC code.
>>>
>>> There are also a bunch of other restrictions which need to be kept in
>>> mind.
>>>
>>> For example what is the minimum feedback divider value the DC code
>>> uses?
>>
>> As far as I see DC doesn't have minimum / maximum limits for the
>> feedback divider right now, though I can add that in a future patch if
>> necessary.
>>
>>>
>>> We once had a longer discussion with the PLL HW engineers to get this
>>> working because at least the display code we used as reference back
>>> then got it wrong.
>>
>> After this series is reviewed, I can look through the other
>> restrictions in the amdgpu_atombios_get_clock_info function and write
>> another patch series to add those restrictions to DC.
>>
> 
> The PPLL limits from radeon and the non-DC code were based on the PLL
> registers, i.e., what the hardware limit in the register was.  I'm not
> sure what the practical limits really are per se.  I.e., if the whole
> range is really usable or not.  I would tend to defer to DC.
> 
> Alex

Hi Alex,

I'll leave it up to your judgement if you want to include this patch.
I just wrote this for the sake of consistency with the non-DC code but 
the patch actually doesn't fix any actual bugs for me.

It is is based on information I found in the non-DC code, in the 
amdgpu_atombios_get_clock_info function. Maybe the PLL limits in this 
function were meant for even older GPUs and are not relevant to SI/CIK?

Best regards,
Timur


> 
>>>
>>>> ---
>>>>   drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +++++++
>>>>   1 file changed, 7 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>>>> b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>>>> index b4f5b4a6331a..00f25e2ee081 100644
>>>> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>>>> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>>>> @@ -1700,6 +1700,13 @@ bool dce110_clk_src_construct(
>>>>                      clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
>>>>      calc_pll_cs_init_data.min_pll_ref_divider =     1;
>>>>      calc_pll_cs_init_data.max_pll_ref_divider =     clk_src-
>>>>> cs_mask->PLL_REF_DIV;
>>>> +
>>>> +   if (ctx->dce_version <= DCE_VERSION_10_0) {
>>>> +           /* Set stricter dividers to stabilize the PLL's
>>>> feedback loop on old HW. */
>>>> +           calc_pll_cs_init_data.min_pix_clk_pll_post_divider
>>>> = 2;
>>>> +           calc_pll_cs_init_data.min_pll_ref_divider = 2;
>>>> +   }
>>>> +
>>>>      /* when 0 use minInputPxlClkPLLFrequencyInKHz from
>>>> firmwareInfo*/
>>>>      calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_
>>>> khz =       0;
>>>>      /* when 0 use maxInputPxlClkPLLFrequencyInKHz from
>>>> firmwareInfo*/

Re: [PATCH 3/3] drm/amd/display: Set stricter clock dividers on DCE 6-10

[Christian König]

On 13.10.25 08:15, Timur Kristóf wrote:
> On 10/9/25 21:38, Alex Deucher wrote:
>> On Sun, Sep 28, 2025 at 7:39 PM <timur.kristof@gmail.com> wrote:
>>>
>>> On Sun, 2025-09-28 at 16:14 +0200, Christian König wrote:
>>>>
>>>>
>>>> On 26.09.25 20:26, Timur Kristóf wrote:
>>>>> Set stricter dividers to stabilize the PLL's feedback loop.
>>>>> In practice, the actual output isn't exactly the target
>>>>> clock, but slowly oscillates around it. This makes it
>>>>> more stable.
>>>>>
>>>>> The values here are taken from the non-DC code.
>>>>
>>>> There are also a bunch of other restrictions which need to be kept in
>>>> mind.
>>>>
>>>> For example what is the minimum feedback divider value the DC code
>>>> uses?
>>>
>>> As far as I see DC doesn't have minimum / maximum limits for the
>>> feedback divider right now, though I can add that in a future patch if
>>> necessary.
>>>
>>>>
>>>> We once had a longer discussion with the PLL HW engineers to get this
>>>> working because at least the display code we used as reference back
>>>> then got it wrong.
>>>
>>> After this series is reviewed, I can look through the other
>>> restrictions in the amdgpu_atombios_get_clock_info function and write
>>> another patch series to add those restrictions to DC.
>>>
>>
>> The PPLL limits from radeon and the non-DC code were based on the PLL
>> registers, i.e., what the hardware limit in the register was.  I'm not
>> sure what the practical limits really are per se.  I.e., if the whole
>> range is really usable or not.  I would tend to defer to DC.
>>
>> Alex
> 
> Hi Alex,
> 
> I'll leave it up to your judgement if you want to include this patch.
> I just wrote this for the sake of consistency with the non-DC code but the patch actually doesn't fix any actual bugs for me.
> 
> It is is based on information I found in the non-DC code, in the amdgpu_atombios_get_clock_info function. Maybe the PLL limits in this function were meant for even older GPUs and are not relevant to SI/CIK?

The DC and even the atombios tables got the clock divider ranges quite wrong sometimes. For example as far as I know the 1/10th handling for the feedback divider minimum was never correct in those.

But I'm not sure where the ref and post divider minimums came from of hand.

Regards,
Christian.

> 
> Best regards,
> Timur
> 
> 
>>
>>>>
>>>>> ---
>>>>>   drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +++++++
>>>>>   1 file changed, 7 insertions(+)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>>>>> b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>>>>> index b4f5b4a6331a..00f25e2ee081 100644
>>>>> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>>>>> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>>>>> @@ -1700,6 +1700,13 @@ bool dce110_clk_src_construct(
>>>>>                      clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
>>>>>      calc_pll_cs_init_data.min_pll_ref_divider =     1;
>>>>>      calc_pll_cs_init_data.max_pll_ref_divider =     clk_src-
>>>>>> cs_mask->PLL_REF_DIV;
>>>>> +
>>>>> +   if (ctx->dce_version <= DCE_VERSION_10_0) {
>>>>> +           /* Set stricter dividers to stabilize the PLL's
>>>>> feedback loop on old HW. */
>>>>> +           calc_pll_cs_init_data.min_pix_clk_pll_post_divider
>>>>> = 2;
>>>>> +           calc_pll_cs_init_data.min_pll_ref_divider = 2;
>>>>> +   }
>>>>> +
>>>>>      /* when 0 use minInputPxlClkPLLFrequencyInKHz from
>>>>> firmwareInfo*/
>>>>>      calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_
>>>>> khz =       0;
>>>>>      /* when 0 use maxInputPxlClkPLLFrequencyInKHz from
>>>>> firmwareInfo*/
>