[PATCH 00/13] Some refactor, rewrite and fixes for OA tests

[PATCH 00/13] Some refactor, rewrite and fixes for OA tests

[Umesh Nerlige Ramappa]

Some refactor, rewrite and fixes for OA tests. Added some tuning
parameters to control execution on slower platforms.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Umesh Nerlige Ramappa (13):
  tests/intel/xe_oa: Use static for global variables
  tests/intel/xe_oa: Drop unused macro
  tests/intel/xe_oa: Rename oa_exp_1_millisec to oa_exponent_default
  tests/intel/xe_oa: Use default exponent for some tests
  tests/intel/xe_oa: Use same render copy width and height across tests
  tests/intel/xe_oa: Rewrite the polling small buf test
  tests/intel/xe_oa: Simplify the buffer-fill test
  tests/intel/xe_oa: Use default buffer size for non-zero reason
  tests/intel/xe_oa: Test oa buffer sizes
  tests/intel/xe_oa: Rewrite enable-disable test
  tests/intel/xe_oa: Enable unprivileged-single-ctx-counters and fix it
  tests/intel/xe_oa: Fix mmio_trigger_reports testing
  tests/intel/xe_oa: Set boundaries for OA exponent test

 tests/intel/xe_oa.c | 571 ++++++++++++++++----------------------------
 1 file changed, 205 insertions(+), 366 deletions(-)

-- 
2.34.1

[PATCH 01/13] tests/intel/xe_oa: Use static for global variables

[Umesh Nerlige Ramappa]

Use static for mmio_data and hwe.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 0242fd594..3274d472d 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -296,12 +296,12 @@ static int pm_fd = -1;
 static int stream_fd = -1;
 static uint32_t devid;
 
-struct drm_xe_engine_class_instance default_hwe;
+static struct drm_xe_engine_class_instance default_hwe;
 
 static struct intel_xe_perf *intel_xe_perf;
 static uint64_t oa_exp_1_millisec;
 static size_t default_oa_buffer_size;
-struct intel_mmio_data mmio_data;
+static struct intel_mmio_data mmio_data;
 static igt_render_copyfunc_t render_copy;
 
 static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
-- 
2.34.1

Re: [PATCH 01/13] tests/intel/xe_oa: Use static for global variables

[Dixit, Ashutosh]

On Fri, 14 Feb 2025 17:06:16 -0800, Umesh Nerlige Ramappa wrote:
>
> Use static for mmio_data and hwe.
>

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/intel/xe_oa.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> index 0242fd594..3274d472d 100644
> --- a/tests/intel/xe_oa.c
> +++ b/tests/intel/xe_oa.c
> @@ -296,12 +296,12 @@ static int pm_fd = -1;
>  static int stream_fd = -1;
>  static uint32_t devid;
>
> -struct drm_xe_engine_class_instance default_hwe;
> +static struct drm_xe_engine_class_instance default_hwe;
>
>  static struct intel_xe_perf *intel_xe_perf;
>  static uint64_t oa_exp_1_millisec;
>  static size_t default_oa_buffer_size;
> -struct intel_mmio_data mmio_data;
> +static struct intel_mmio_data mmio_data;
>  static igt_render_copyfunc_t render_copy;
>
>  static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
> --
> 2.34.1
>

[PATCH 02/13] tests/intel/xe_oa: Drop unused macro

[Umesh Nerlige Ramappa]

Drop unused for helper

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 3274d472d..9c74315df 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -4788,13 +4788,6 @@ static const char *xe_engine_class_name(uint32_t engine_class)
 		igt_dynamic_f("%s-%d-%s", xe_engine_class_name(hwe->engine_class), \
 			      hwe->engine_instance, str)
 
-#define __for_one_render_engine_0(hwe) \
-	xe_for_each_engine(drm_fd, hwe) \
-		if (hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER) \
-			break; \
-	for_each_if(hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER) \
-		igt_dynamic_f("rcs-%d", hwe->engine_instance)
-
 #define __for_one_render_engine(hwe)	      \
 	for (int m = 0, done = 0; !done; m++) \
 		for_each_if(m < xe_number_engines(drm_fd) && \
-- 
2.34.1

Re: [PATCH 02/13] tests/intel/xe_oa: Drop unused macro

[Dixit, Ashutosh]

On Fri, 14 Feb 2025 17:06:17 -0800, Umesh Nerlige Ramappa wrote:
>
> Drop unused for helper

I don't remember why I left this in, probably wanted to save the way the
macro was written. Anyway, we can get it out of git if we need it:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>


>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/intel/xe_oa.c | 7 -------
>  1 file changed, 7 deletions(-)
>
> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> index 3274d472d..9c74315df 100644
> --- a/tests/intel/xe_oa.c
> +++ b/tests/intel/xe_oa.c
> @@ -4788,13 +4788,6 @@ static const char *xe_engine_class_name(uint32_t engine_class)
>		igt_dynamic_f("%s-%d-%s", xe_engine_class_name(hwe->engine_class), \
>			      hwe->engine_instance, str)
>
> -#define __for_one_render_engine_0(hwe) \
> -	xe_for_each_engine(drm_fd, hwe) \
> -		if (hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER) \
> -			break; \
> -	for_each_if(hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER) \
> -		igt_dynamic_f("rcs-%d", hwe->engine_instance)
> -
>  #define __for_one_render_engine(hwe)	      \
>	for (int m = 0, done = 0; !done; m++) \
>		for_each_if(m < xe_number_engines(drm_fd) && \
> --
> 2.34.1
>

[PATCH 03/13] tests/intel/xe_oa: Rename oa_exp_1_millisec to oa_exponent_default

[Umesh Nerlige Ramappa]

Rename the global exponent to default so it can be used in different
modes.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 9c74315df..e7d6ac5af 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -299,7 +299,7 @@ static uint32_t devid;
 static struct drm_xe_engine_class_instance default_hwe;
 
 static struct intel_xe_perf *intel_xe_perf;
-static uint64_t oa_exp_1_millisec;
+static uint64_t oa_exponent_default;
 static size_t default_oa_buffer_size;
 static struct intel_mmio_data mmio_data;
 static igt_render_copyfunc_t render_copy;
@@ -514,7 +514,7 @@ static size_t get_default_oa_buffer_size(int fd)
 		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 	};
 	struct intel_xe_oa_open_prop param = {
 		.num_properties = ARRAY_SIZE(properties) / 2,
@@ -1089,7 +1089,7 @@ init_sys_info(void)
 
 	intel_xe_perf_load_perf_configs(intel_xe_perf, drm_fd);
 
-	oa_exp_1_millisec = max_oa_exponent_for_period_lte(1000000);
+	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
 
 	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
 	igt_debug("default_oa_buffer_size: %zu\n", default_oa_buffer_size);
@@ -1114,7 +1114,7 @@ static void test_system_wide_paranoid(void)
 			/* OA unit configuration */
 			DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
 			DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
-			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		};
 		struct intel_xe_oa_open_prop param = {
 			.num_properties = ARRAY_SIZE(properties) / 2,
@@ -1140,7 +1140,7 @@ static void test_system_wide_paranoid(void)
 			/* OA unit configuration */
 			DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
 			DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
-			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		};
 		struct intel_xe_oa_open_prop param = {
 			.num_properties = ARRAY_SIZE(properties) / 2,
@@ -1174,7 +1174,7 @@ static void test_invalid_oa_metric_set_id(void)
 
 		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, UINT64_MAX,
 	};
 	struct intel_xe_oa_open_prop param = {
@@ -1211,7 +1211,7 @@ static void test_invalid_oa_format_id(void)
 
 		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, UINT64_MAX, /* No __ff() here */
 	};
 	struct intel_xe_oa_open_prop param = {
@@ -1246,7 +1246,7 @@ static void test_missing_sample_flags(void)
 
 		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
 	};
 	struct intel_xe_oa_open_prop param = {
@@ -1536,7 +1536,7 @@ static void test_oa_formats(const struct drm_xe_engine_class_instance *hwe)
 		igt_debug("Checking OA format %s\n", format.name);
 
 		open_and_read_2_oa_reports(i,
-					   oa_exp_1_millisec,
+					   oa_exponent_default,
 					   oa_report0,
 					   oa_report1,
 					   false, /* timer reports only */
@@ -3420,7 +3420,7 @@ test_rc6_disable(void)
 		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 	};
 	struct intel_xe_oa_open_prop param = {
 		.num_properties = ARRAY_SIZE(properties) / 2,
@@ -3648,7 +3648,7 @@ test_create_destroy_userspace_config(void)
 		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET
 	};
@@ -3948,7 +3948,7 @@ static void test_oa_regs_whitelist(const struct drm_xe_engine_class_instance *hw
 		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 	};
 	struct intel_xe_oa_open_prop param = {
 		.num_properties = sizeof(properties) / 16,
@@ -4154,7 +4154,7 @@ test_oa_unit_exclusive_stream(bool exponent)
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, 0,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(0),
 		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, 0,
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 	};
 	struct intel_xe_oa_open_prop param = {
 		.num_properties = ARRAY_SIZE(properties) / 2,
@@ -4216,7 +4216,7 @@ test_oa_unit_exclusive_stream(bool exponent)
 		properties[7] = __ff(test_set->perf_oa_format);
 		properties[9] = hwe->engine_instance;
 		properties[10] = DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT;
-		properties[11] = oa_exp_1_millisec;
+		properties[11] = oa_exponent_default;
 		intel_xe_perf_ioctl_err(drm_fd, DRM_XE_OBSERVATION_OP_STREAM_OPEN, &param, EBUSY);
 
 		/* case 2: concurrent access to non-OAG unit should fail */
@@ -4374,7 +4374,7 @@ static void map_oa_buffer_forked_access(const struct drm_xe_engine_class_instanc
 static void mmap_wait_for_periodic_reports(void *oa_vaddr, uint32_t n,
 					   const struct drm_xe_engine_class_instance *hwe)
 {
-	uint32_t period_us = oa_exponent_to_ns(oa_exp_1_millisec) / 1000;
+	uint32_t period_us = oa_exponent_to_ns(oa_exponent_default) / 1000;
 	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
 	uint64_t fmt = test_set->perf_oa_format;
 	uint32_t num_periodic_reports = 0;
@@ -4440,7 +4440,7 @@ static void closed_fd_and_unmapped_access(const struct drm_xe_engine_class_insta
 		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 	};
 	struct intel_xe_oa_open_prop param = {
 		.num_properties = ARRAY_SIZE(properties) / 2,
@@ -4487,7 +4487,7 @@ static void test_mapped_oa_buffer(map_oa_buffer_test_t test_with_fd_open,
 		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
 	};
 	struct intel_xe_oa_open_prop param = {
-- 
2.34.1

Re: [PATCH 03/13] tests/intel/xe_oa: Rename oa_exp_1_millisec to oa_exponent_default

[Dixit, Ashutosh]

On Fri, 14 Feb 2025 17:06:18 -0800, Umesh Nerlige Ramappa wrote:
>
> Rename the global exponent to default so it can be used in different
> modes.

Please see discussion on this patch on the CI series here:

https://patchwork.freedesktop.org/series/145042/

>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/intel/xe_oa.c | 34 +++++++++++++++++-----------------
>  1 file changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> index 9c74315df..e7d6ac5af 100644
> --- a/tests/intel/xe_oa.c
> +++ b/tests/intel/xe_oa.c
> @@ -299,7 +299,7 @@ static uint32_t devid;
>  static struct drm_xe_engine_class_instance default_hwe;
>
>  static struct intel_xe_perf *intel_xe_perf;
> -static uint64_t oa_exp_1_millisec;
> +static uint64_t oa_exponent_default;
>  static size_t default_oa_buffer_size;
>  static struct intel_mmio_data mmio_data;
>  static igt_render_copyfunc_t render_copy;
> @@ -514,7 +514,7 @@ static size_t get_default_oa_buffer_size(int fd)
>		/* OA unit configuration */
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>	};
>	struct intel_xe_oa_open_prop param = {
>		.num_properties = ARRAY_SIZE(properties) / 2,
> @@ -1089,7 +1089,7 @@ init_sys_info(void)
>
>	intel_xe_perf_load_perf_configs(intel_xe_perf, drm_fd);
>
> -	oa_exp_1_millisec = max_oa_exponent_for_period_lte(1000000);
> +	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
>
>	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
>	igt_debug("default_oa_buffer_size: %zu\n", default_oa_buffer_size);
> @@ -1114,7 +1114,7 @@ static void test_system_wide_paranoid(void)
>			/* OA unit configuration */
>			DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
>			DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> -			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> +			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>		};
>		struct intel_xe_oa_open_prop param = {
>			.num_properties = ARRAY_SIZE(properties) / 2,
> @@ -1140,7 +1140,7 @@ static void test_system_wide_paranoid(void)
>			/* OA unit configuration */
>			DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
>			DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> -			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> +			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>		};
>		struct intel_xe_oa_open_prop param = {
>			.num_properties = ARRAY_SIZE(properties) / 2,
> @@ -1174,7 +1174,7 @@ static void test_invalid_oa_metric_set_id(void)
>
>		/* OA unit configuration */
>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, UINT64_MAX,
>	};
>	struct intel_xe_oa_open_prop param = {
> @@ -1211,7 +1211,7 @@ static void test_invalid_oa_format_id(void)
>
>		/* OA unit configuration */
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>		DRM_XE_OA_PROPERTY_OA_FORMAT, UINT64_MAX, /* No __ff() here */
>	};
>	struct intel_xe_oa_open_prop param = {
> @@ -1246,7 +1246,7 @@ static void test_missing_sample_flags(void)
>
>		/* OA unit configuration */
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
>	};
>	struct intel_xe_oa_open_prop param = {
> @@ -1536,7 +1536,7 @@ static void test_oa_formats(const struct drm_xe_engine_class_instance *hwe)
>		igt_debug("Checking OA format %s\n", format.name);
>
>		open_and_read_2_oa_reports(i,
> -					   oa_exp_1_millisec,
> +					   oa_exponent_default,
>					   oa_report0,
>					   oa_report1,
>					   false, /* timer reports only */
> @@ -3420,7 +3420,7 @@ test_rc6_disable(void)
>		/* OA unit configuration */
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>	};
>	struct intel_xe_oa_open_prop param = {
>		.num_properties = ARRAY_SIZE(properties) / 2,
> @@ -3648,7 +3648,7 @@ test_create_destroy_userspace_config(void)
>		/* OA unit configuration */
>		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET
>	};
> @@ -3948,7 +3948,7 @@ static void test_oa_regs_whitelist(const struct drm_xe_engine_class_instance *hw
>		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>	};
>	struct intel_xe_oa_open_prop param = {
>		.num_properties = sizeof(properties) / 16,
> @@ -4154,7 +4154,7 @@ test_oa_unit_exclusive_stream(bool exponent)
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, 0,
>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(0),
>		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, 0,
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>	};
>	struct intel_xe_oa_open_prop param = {
>		.num_properties = ARRAY_SIZE(properties) / 2,
> @@ -4216,7 +4216,7 @@ test_oa_unit_exclusive_stream(bool exponent)
>		properties[7] = __ff(test_set->perf_oa_format);
>		properties[9] = hwe->engine_instance;
>		properties[10] = DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT;
> -		properties[11] = oa_exp_1_millisec;
> +		properties[11] = oa_exponent_default;
>		intel_xe_perf_ioctl_err(drm_fd, DRM_XE_OBSERVATION_OP_STREAM_OPEN, &param, EBUSY);
>
>		/* case 2: concurrent access to non-OAG unit should fail */
> @@ -4374,7 +4374,7 @@ static void map_oa_buffer_forked_access(const struct drm_xe_engine_class_instanc
>  static void mmap_wait_for_periodic_reports(void *oa_vaddr, uint32_t n,
>					   const struct drm_xe_engine_class_instance *hwe)
>  {
> -	uint32_t period_us = oa_exponent_to_ns(oa_exp_1_millisec) / 1000;
> +	uint32_t period_us = oa_exponent_to_ns(oa_exponent_default) / 1000;
>	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
>	uint64_t fmt = test_set->perf_oa_format;
>	uint32_t num_periodic_reports = 0;
> @@ -4440,7 +4440,7 @@ static void closed_fd_and_unmapped_access(const struct drm_xe_engine_class_insta
>		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>	};
>	struct intel_xe_oa_open_prop param = {
>		.num_properties = ARRAY_SIZE(properties) / 2,
> @@ -4487,7 +4487,7 @@ static void test_mapped_oa_buffer(map_oa_buffer_test_t test_with_fd_open,
>		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
>	};
>	struct intel_xe_oa_open_prop param = {
> --
> 2.34.1
>

Re: [PATCH 03/13] tests/intel/xe_oa: Rename oa_exp_1_millisec to oa_exponent_default

[Dixit, Ashutosh]

On Fri, 21 Feb 2025 18:42:31 -0800, Dixit, Ashutosh wrote:
>
> On Fri, 14 Feb 2025 17:06:18 -0800, Umesh Nerlige Ramappa wrote:
> >
> > Rename the global exponent to default so it can be used in different
> > modes.
>
> Please see discussion on this patch on the CI series here:
>
> https://patchwork.freedesktop.org/series/145042/


This is that discussion:

> > > My suggestion here would be to (a) either rename this to
> > > oa_exponent_default_1ms, or alternatively, (b) to rename the period
> > > argument of max_oa_exponent_for_period_lte() to period_ns. So it's clear
> > > from the code, without having to guess, what the value of the default
> > > exponent is.
> >
> > So, the idea is to set this default to a smaller value like 1000 ns for
> > simulation, so that it gets applied to all the tests, hence not using any
> > specific values in the name. Thoughts?
>
> Then let's do (b).

After doing this:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>



>
> >
> > Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> > ---
> >  tests/intel/xe_oa.c | 34 +++++++++++++++++-----------------
> >  1 file changed, 17 insertions(+), 17 deletions(-)
> >
> > diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> > index 9c74315df..e7d6ac5af 100644
> > --- a/tests/intel/xe_oa.c
> > +++ b/tests/intel/xe_oa.c
> > @@ -299,7 +299,7 @@ static uint32_t devid;
> >  static struct drm_xe_engine_class_instance default_hwe;
> >
> >  static struct intel_xe_perf *intel_xe_perf;
> > -static uint64_t oa_exp_1_millisec;
> > +static uint64_t oa_exponent_default;
> >  static size_t default_oa_buffer_size;
> >  static struct intel_mmio_data mmio_data;
> >  static igt_render_copyfunc_t render_copy;
> > @@ -514,7 +514,7 @@ static size_t get_default_oa_buffer_size(int fd)
> >		/* OA unit configuration */
> >		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
> >		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> > -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> > +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >	};
> >	struct intel_xe_oa_open_prop param = {
> >		.num_properties = ARRAY_SIZE(properties) / 2,
> > @@ -1089,7 +1089,7 @@ init_sys_info(void)
> >
> >	intel_xe_perf_load_perf_configs(intel_xe_perf, drm_fd);
> >
> > -	oa_exp_1_millisec = max_oa_exponent_for_period_lte(1000000);
> > +	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
> >
> >	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
> >	igt_debug("default_oa_buffer_size: %zu\n", default_oa_buffer_size);
> > @@ -1114,7 +1114,7 @@ static void test_system_wide_paranoid(void)
> >			/* OA unit configuration */
> >			DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
> >			DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> > -			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> > +			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >		};
> >		struct intel_xe_oa_open_prop param = {
> >			.num_properties = ARRAY_SIZE(properties) / 2,
> > @@ -1140,7 +1140,7 @@ static void test_system_wide_paranoid(void)
> >			/* OA unit configuration */
> >			DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
> >			DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> > -			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> > +			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >		};
> >		struct intel_xe_oa_open_prop param = {
> >			.num_properties = ARRAY_SIZE(properties) / 2,
> > @@ -1174,7 +1174,7 @@ static void test_invalid_oa_metric_set_id(void)
> >
> >		/* OA unit configuration */
> >		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> > -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> > +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >		DRM_XE_OA_PROPERTY_OA_METRIC_SET, UINT64_MAX,
> >	};
> >	struct intel_xe_oa_open_prop param = {
> > @@ -1211,7 +1211,7 @@ static void test_invalid_oa_format_id(void)
> >
> >		/* OA unit configuration */
> >		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
> > -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> > +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >		DRM_XE_OA_PROPERTY_OA_FORMAT, UINT64_MAX, /* No __ff() here */
> >	};
> >	struct intel_xe_oa_open_prop param = {
> > @@ -1246,7 +1246,7 @@ static void test_missing_sample_flags(void)
> >
> >		/* OA unit configuration */
> >		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
> > -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> > +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> >	};
> >	struct intel_xe_oa_open_prop param = {
> > @@ -1536,7 +1536,7 @@ static void test_oa_formats(const struct drm_xe_engine_class_instance *hwe)
> >		igt_debug("Checking OA format %s\n", format.name);
> >
> >		open_and_read_2_oa_reports(i,
> > -					   oa_exp_1_millisec,
> > +					   oa_exponent_default,
> >					   oa_report0,
> >					   oa_report1,
> >					   false, /* timer reports only */
> > @@ -3420,7 +3420,7 @@ test_rc6_disable(void)
> >		/* OA unit configuration */
> >		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
> >		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> > -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> > +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >	};
> >	struct intel_xe_oa_open_prop param = {
> >		.num_properties = ARRAY_SIZE(properties) / 2,
> > @@ -3648,7 +3648,7 @@ test_create_destroy_userspace_config(void)
> >		/* OA unit configuration */
> >		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
> >		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> > -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> > +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
> >		DRM_XE_OA_PROPERTY_OA_METRIC_SET
> >	};
> > @@ -3948,7 +3948,7 @@ static void test_oa_regs_whitelist(const struct drm_xe_engine_class_instance *hw
> >		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
> >		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
> >		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
> > -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> > +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >	};
> >	struct intel_xe_oa_open_prop param = {
> >		.num_properties = sizeof(properties) / 16,
> > @@ -4154,7 +4154,7 @@ test_oa_unit_exclusive_stream(bool exponent)
> >		DRM_XE_OA_PROPERTY_OA_METRIC_SET, 0,
> >		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(0),
> >		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, 0,
> > -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> > +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >	};
> >	struct intel_xe_oa_open_prop param = {
> >		.num_properties = ARRAY_SIZE(properties) / 2,
> > @@ -4216,7 +4216,7 @@ test_oa_unit_exclusive_stream(bool exponent)
> >		properties[7] = __ff(test_set->perf_oa_format);
> >		properties[9] = hwe->engine_instance;
> >		properties[10] = DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT;
> > -		properties[11] = oa_exp_1_millisec;
> > +		properties[11] = oa_exponent_default;
> >		intel_xe_perf_ioctl_err(drm_fd, DRM_XE_OBSERVATION_OP_STREAM_OPEN, &param, EBUSY);
> >
> >		/* case 2: concurrent access to non-OAG unit should fail */
> > @@ -4374,7 +4374,7 @@ static void map_oa_buffer_forked_access(const struct drm_xe_engine_class_instanc
> >  static void mmap_wait_for_periodic_reports(void *oa_vaddr, uint32_t n,
> >					   const struct drm_xe_engine_class_instance *hwe)
> >  {
> > -	uint32_t period_us = oa_exponent_to_ns(oa_exp_1_millisec) / 1000;
> > +	uint32_t period_us = oa_exponent_to_ns(oa_exponent_default) / 1000;
> >	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
> >	uint64_t fmt = test_set->perf_oa_format;
> >	uint32_t num_periodic_reports = 0;
> > @@ -4440,7 +4440,7 @@ static void closed_fd_and_unmapped_access(const struct drm_xe_engine_class_insta
> >		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
> >		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
> >		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> > -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> > +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >	};
> >	struct intel_xe_oa_open_prop param = {
> >		.num_properties = ARRAY_SIZE(properties) / 2,
> > @@ -4487,7 +4487,7 @@ static void test_mapped_oa_buffer(map_oa_buffer_test_t test_with_fd_open,
> >		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
> >		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
> >		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
> > -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exp_1_millisec,
> > +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
> >	};
> >	struct intel_xe_oa_open_prop param = {
> > --
> > 2.34.1
> >

[PATCH 04/13] tests/intel/xe_oa: Use default exponent for some tests

[Umesh Nerlige Ramappa]

Use the default exponent for below tests:

oa-tlb-validate
short-reads
stress-open-close
mmio-triggered-reports

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index e7d6ac5af..7e40e9257 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -2316,7 +2316,6 @@ num_valid_reports_captured(struct intel_xe_oa_open_prop *param,
 static void
 test_oa_tlb_invalidate(const struct drm_xe_engine_class_instance *hwe)
 {
-	int oa_exponent = max_oa_exponent_for_period_lte(30000000);
 	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
 	uint64_t properties[] = {
 		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
@@ -2324,7 +2323,7 @@ test_oa_tlb_invalidate(const struct drm_xe_engine_class_instance *hwe)
 
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
 		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
 	};
@@ -2342,14 +2341,14 @@ test_oa_tlb_invalidate(const struct drm_xe_engine_class_instance *hwe)
 	 */
 	duration = 5LL * NSEC_PER_SEC;
 	num_reports1 = num_valid_reports_captured(&param, &duration, test_set->perf_oa_format);
-	num_expected_reports = duration / oa_exponent_to_ns(oa_exponent);
+	num_expected_reports = duration / oa_exponent_to_ns(oa_exponent_default);
 	igt_debug("expected num reports = %d\n", num_expected_reports);
 	igt_debug("actual num reports = %d\n", num_reports1);
 	igt_assert(num_reports1 > 0.95 * num_expected_reports);
 
 	duration = 5LL * NSEC_PER_SEC;
 	num_reports2 = num_valid_reports_captured(&param, &duration, test_set->perf_oa_format);
-	num_expected_reports = duration / oa_exponent_to_ns(oa_exponent);
+	num_expected_reports = duration / oa_exponent_to_ns(oa_exponent_default);
 	igt_debug("expected num reports = %d\n", num_expected_reports);
 	igt_debug("actual num reports = %d\n", num_reports2);
 	igt_assert(num_reports2 > 0.95 * num_expected_reports);
@@ -2738,7 +2737,6 @@ test_enable_disable(const struct drm_xe_engine_class_instance *hwe)
 static void
 test_short_reads(void)
 {
-	int oa_exponent = max_oa_exponent_for_period_lte(5000);
 	uint64_t properties[] = {
 		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
 
@@ -2748,7 +2746,7 @@ test_short_reads(void)
 		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 	};
 	struct intel_xe_oa_open_prop param = {
 		.num_properties = ARRAY_SIZE(properties) / 2,
@@ -3464,7 +3462,6 @@ test_stress_open_close(const struct drm_xe_engine_class_instance *hwe)
 	load_helper_run(HIGH);
 
 	igt_until_timeout(2) {
-		int oa_exponent = 5; /* 5 micro seconds */
 		uint64_t properties[] = {
 			DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
 
@@ -3476,7 +3473,7 @@ test_stress_open_close(const struct drm_xe_engine_class_instance *hwe)
 			/* OA unit configuration */
 			DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
 			DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
-			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 			DRM_XE_OA_PROPERTY_OA_DISABLED, true,
 			DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
 		};
@@ -3990,12 +3987,11 @@ static void
 __test_mmio_triggered_reports(struct drm_xe_engine_class_instance *hwe)
 {
 	struct intel_xe_perf_metric_set *test_set = default_test_set;
-	int oa_exponent = max_oa_exponent_for_period_lte(2 * NSEC_PER_SEC);
 	uint64_t properties[] = {
 		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
 	};
 	struct intel_xe_oa_open_prop param = {
-- 
2.34.1

Re: [PATCH 04/13] tests/intel/xe_oa: Use default exponent for some tests

[Dixit, Ashutosh]

On Fri, 14 Feb 2025 17:06:19 -0800, Umesh Nerlige Ramappa wrote:
>
> Use the default exponent for below tests:
>
> oa-tlb-validate
> short-reads
> stress-open-close
> mmio-triggered-reports

Please see discussion on this patch in the CI series here:

https://patchwork.freedesktop.org/series/145042/


>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/intel/xe_oa.c | 16 ++++++----------
>  1 file changed, 6 insertions(+), 10 deletions(-)
>
> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> index e7d6ac5af..7e40e9257 100644
> --- a/tests/intel/xe_oa.c
> +++ b/tests/intel/xe_oa.c
> @@ -2316,7 +2316,6 @@ num_valid_reports_captured(struct intel_xe_oa_open_prop *param,
>  static void
>  test_oa_tlb_invalidate(const struct drm_xe_engine_class_instance *hwe)
>  {
> -	int oa_exponent = max_oa_exponent_for_period_lte(30000000);
>	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
>	uint64_t properties[] = {
>		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
> @@ -2324,7 +2323,7 @@ test_oa_tlb_invalidate(const struct drm_xe_engine_class_instance *hwe)
>
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
>		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
>	};
> @@ -2342,14 +2341,14 @@ test_oa_tlb_invalidate(const struct drm_xe_engine_class_instance *hwe)
>	 */
>	duration = 5LL * NSEC_PER_SEC;
>	num_reports1 = num_valid_reports_captured(&param, &duration, test_set->perf_oa_format);
> -	num_expected_reports = duration / oa_exponent_to_ns(oa_exponent);
> +	num_expected_reports = duration / oa_exponent_to_ns(oa_exponent_default);
>	igt_debug("expected num reports = %d\n", num_expected_reports);
>	igt_debug("actual num reports = %d\n", num_reports1);
>	igt_assert(num_reports1 > 0.95 * num_expected_reports);
>
>	duration = 5LL * NSEC_PER_SEC;
>	num_reports2 = num_valid_reports_captured(&param, &duration, test_set->perf_oa_format);
> -	num_expected_reports = duration / oa_exponent_to_ns(oa_exponent);
> +	num_expected_reports = duration / oa_exponent_to_ns(oa_exponent_default);
>	igt_debug("expected num reports = %d\n", num_expected_reports);
>	igt_debug("actual num reports = %d\n", num_reports2);
>	igt_assert(num_reports2 > 0.95 * num_expected_reports);
> @@ -2738,7 +2737,6 @@ test_enable_disable(const struct drm_xe_engine_class_instance *hwe)
>  static void
>  test_short_reads(void)
>  {
> -	int oa_exponent = max_oa_exponent_for_period_lte(5000);
>	uint64_t properties[] = {
>		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
>
> @@ -2748,7 +2746,7 @@ test_short_reads(void)
>		/* OA unit configuration */
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>	};
>	struct intel_xe_oa_open_prop param = {
>		.num_properties = ARRAY_SIZE(properties) / 2,
> @@ -3464,7 +3462,6 @@ test_stress_open_close(const struct drm_xe_engine_class_instance *hwe)
>	load_helper_run(HIGH);
>
>	igt_until_timeout(2) {
> -		int oa_exponent = 5; /* 5 micro seconds */
>		uint64_t properties[] = {
>			DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
>
> @@ -3476,7 +3473,7 @@ test_stress_open_close(const struct drm_xe_engine_class_instance *hwe)
>			/* OA unit configuration */
>			DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
>			DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
> -			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
> +			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>			DRM_XE_OA_PROPERTY_OA_DISABLED, true,
>			DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
>		};
> @@ -3990,12 +3987,11 @@ static void
>  __test_mmio_triggered_reports(struct drm_xe_engine_class_instance *hwe)
>  {
>	struct intel_xe_perf_metric_set *test_set = default_test_set;
> -	int oa_exponent = max_oa_exponent_for_period_lte(2 * NSEC_PER_SEC);
>	uint64_t properties[] = {
>		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
>	};
>	struct intel_xe_oa_open_prop param = {
> --
> 2.34.1
>

Re: [PATCH 04/13] tests/intel/xe_oa: Use default exponent for some tests

[Dixit, Ashutosh]

On Fri, 21 Feb 2025 18:43:01 -0800, Dixit, Ashutosh wrote:
>
> On Fri, 14 Feb 2025 17:06:19 -0800, Umesh Nerlige Ramappa wrote:
> >
> > Use the default exponent for below tests:
> >
> > oa-tlb-validate
> > short-reads
> > stress-open-close
> > mmio-triggered-reports
>
> Please see discussion on this patch in the CI series here:
>
> https://patchwork.freedesktop.org/series/145042/

This is that discussion:

> >> > Why? Let's add a reason in the commit message, for all the patches, even
> >> > if, in this case, it might be "because it doesn't matter what exponent is
> >> > used".
> >>
> >> That's open for discussion in this review. My reasoning:
> >>
> >> Other than the stress-open-close, none of the other tests actually depend
> >> on the oa exponent, so we might as well use one value everywhere.
> >
> > Yeah that's what I thought.
> >
> >>
> >> >
> >> > Because these tests were ported from i915 I myself don't quite understand
> >> > why some of these tests do what the do. So it will help if we could
> >> > document why we are making the changes we are making, and, when needed,
> >> > what the effect of the changes is going to be.
> >>
> >> There is one patch on top of this series which should adjust the exponent
> >> value for all tests so that they run quickly on simulation.  Maybe I should
> >> post the v2 with that patch so the context is clear, otherwise, I agree
> >> that the reason for these changes is unclear.
> >
> > Either way, or just state on the patch something like: "this would allow
> > these tests to run in a reasonable time on slower platforms".
>
> will do
> >
> > Oops, should have commented on the original series, but ended up commenting
> > on the CI series :/
>
> Either should be fine. Both series are identical except that the CI one
> forces 128MB buffer-size test and also runs on DG2.

Just fix up the commit message to include the "why":

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>



>
>
> >
> > Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> > ---
> >  tests/intel/xe_oa.c | 16 ++++++----------
> >  1 file changed, 6 insertions(+), 10 deletions(-)
> >
> > diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> > index e7d6ac5af..7e40e9257 100644
> > --- a/tests/intel/xe_oa.c
> > +++ b/tests/intel/xe_oa.c
> > @@ -2316,7 +2316,6 @@ num_valid_reports_captured(struct intel_xe_oa_open_prop *param,
> >  static void
> >  test_oa_tlb_invalidate(const struct drm_xe_engine_class_instance *hwe)
> >  {
> > -	int oa_exponent = max_oa_exponent_for_period_lte(30000000);
> >	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
> >	uint64_t properties[] = {
> >		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
> > @@ -2324,7 +2323,7 @@ test_oa_tlb_invalidate(const struct drm_xe_engine_class_instance *hwe)
> >
> >		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
> >		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
> > -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
> > +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
> >		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
> >	};
> > @@ -2342,14 +2341,14 @@ test_oa_tlb_invalidate(const struct drm_xe_engine_class_instance *hwe)
> >	 */
> >	duration = 5LL * NSEC_PER_SEC;
> >	num_reports1 = num_valid_reports_captured(&param, &duration, test_set->perf_oa_format);
> > -	num_expected_reports = duration / oa_exponent_to_ns(oa_exponent);
> > +	num_expected_reports = duration / oa_exponent_to_ns(oa_exponent_default);
> >	igt_debug("expected num reports = %d\n", num_expected_reports);
> >	igt_debug("actual num reports = %d\n", num_reports1);
> >	igt_assert(num_reports1 > 0.95 * num_expected_reports);
> >
> >	duration = 5LL * NSEC_PER_SEC;
> >	num_reports2 = num_valid_reports_captured(&param, &duration, test_set->perf_oa_format);
> > -	num_expected_reports = duration / oa_exponent_to_ns(oa_exponent);
> > +	num_expected_reports = duration / oa_exponent_to_ns(oa_exponent_default);
> >	igt_debug("expected num reports = %d\n", num_expected_reports);
> >	igt_debug("actual num reports = %d\n", num_reports2);
> >	igt_assert(num_reports2 > 0.95 * num_expected_reports);
> > @@ -2738,7 +2737,6 @@ test_enable_disable(const struct drm_xe_engine_class_instance *hwe)
> >  static void
> >  test_short_reads(void)
> >  {
> > -	int oa_exponent = max_oa_exponent_for_period_lte(5000);
> >	uint64_t properties[] = {
> >		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
> >
> > @@ -2748,7 +2746,7 @@ test_short_reads(void)
> >		/* OA unit configuration */
> >		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
> >		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> > -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
> > +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >	};
> >	struct intel_xe_oa_open_prop param = {
> >		.num_properties = ARRAY_SIZE(properties) / 2,
> > @@ -3464,7 +3462,6 @@ test_stress_open_close(const struct drm_xe_engine_class_instance *hwe)
> >	load_helper_run(HIGH);
> >
> >	igt_until_timeout(2) {
> > -		int oa_exponent = 5; /* 5 micro seconds */
> >		uint64_t properties[] = {
> >			DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
> >
> > @@ -3476,7 +3473,7 @@ test_stress_open_close(const struct drm_xe_engine_class_instance *hwe)
> >			/* OA unit configuration */
> >			DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
> >			DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
> > -			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
> > +			DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >			DRM_XE_OA_PROPERTY_OA_DISABLED, true,
> >			DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
> >		};
> > @@ -3990,12 +3987,11 @@ static void
> >  __test_mmio_triggered_reports(struct drm_xe_engine_class_instance *hwe)
> >  {
> >	struct intel_xe_perf_metric_set *test_set = default_test_set;
> > -	int oa_exponent = max_oa_exponent_for_period_lte(2 * NSEC_PER_SEC);
> >	uint64_t properties[] = {
> >		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
> >		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
> >		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
> > -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
> > +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
> >	};
> >	struct intel_xe_oa_open_prop param = {
> > --
> > 2.34.1
> >

[PATCH 05/13] tests/intel/xe_oa: Use same render copy width and height across tests

[Umesh Nerlige Ramappa]

Use the same width and height for render copy frame across tests.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 39 +++++++++++++++++++--------------------
 1 file changed, 19 insertions(+), 20 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 7e40e9257..aaf92308a 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -303,6 +303,7 @@ static uint64_t oa_exponent_default;
 static size_t default_oa_buffer_size;
 static struct intel_mmio_data mmio_data;
 static igt_render_copyfunc_t render_copy;
+static uint32_t rc_width, rc_height;
 
 static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
 {
@@ -1089,6 +1090,8 @@ init_sys_info(void)
 
 	intel_xe_perf_load_perf_configs(intel_xe_perf, drm_fd);
 
+	rc_width = 1920;
+	rc_height = 1080;
 	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
 
 	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
@@ -1608,7 +1611,7 @@ static void load_helper_run(enum load load)
 
 		while (!lh.exit) {
 			render_copy(lh.ibb,
-				    &lh.src, 0, 0, 1920, 1080,
+				    &lh.src, 0, 0, rc_width, rc_height,
 				    &lh.dst, 0, 0);
 
 			intel_bb_sync(lh.ibb);
@@ -1645,8 +1648,8 @@ static void load_helper_init(void)
 
 	lh.ibb = intel_bb_create_with_context(drm_fd, lh.context_id, lh.vm, NULL, BATCH_SZ);
 
-	scratch_buf_init(lh.bops, &lh.dst, 1920, 1080, 0);
-	scratch_buf_init(lh.bops, &lh.src, 1920, 1080, 0);
+	scratch_buf_init(lh.bops, &lh.dst, rc_width, rc_height, 0);
+	scratch_buf_init(lh.bops, &lh.src, rc_width, rc_height, 0);
 }
 
 static void load_helper_fini(void)
@@ -3112,8 +3115,6 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	uint64_t delta_ts64, delta_oa32;
 	uint64_t delta_ts64_ns, delta_oa32_ns;
 	uint64_t delta_delta;
-	int width = 800;
-	int height = 600;
 #define INVALID_CTX_ID 0xffffffff
 	uint32_t ctx0_id = INVALID_CTX_ID;
 	uint32_t ctx1_id = INVALID_CTX_ID;
@@ -3125,8 +3126,8 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	bops = buf_ops_create(drm_fd);
 
 	for (int i = 0; i < ARRAY_SIZE(src); i++) {
-		scratch_buf_init(bops, &src[i], width, height, 0xff0000ff);
-		scratch_buf_init(bops, &dst[i], width, height, 0x00ff00ff);
+		scratch_buf_init(bops, &src[i], rc_width, rc_height, 0xff0000ff);
+		scratch_buf_init(bops, &dst[i], rc_width, rc_height, 0x00ff00ff);
 	}
 
 	vm = xe_vm_create(drm_fd, 0, 0);
@@ -3139,7 +3140,7 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 
 	/* Submit some early, unmeasured, work to the context we want */
 	render_copy(ibb0,
-		    &src[0], 0, 0, width, height,
+		    &src[0], 0, 0, rc_width, rc_height,
 		    &dst[0], 0, 0);
 
 	/* Initialize the context parameter to the perf open ioctl here */
@@ -3175,7 +3176,7 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 
 	/* This is the work/context that is measured for counter increments */
 	render_copy(ibb0,
-		    &src[0], 0, 0, width, height,
+		    &src[0], 0, 0, rc_width, rc_height,
 		    &dst[0], 0, 0);
 	intel_bb_flush_render(ibb0);
 
@@ -3200,11 +3201,11 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	 * context1
 	 */
 	render_copy(ibb1,
-		    &src[1], 0, 0, width, height,
+		    &src[1], 0, 0, rc_width, rc_height,
 		    &dst[1], 0, 0);
 
 	render_copy(ibb1,
-		    &src[2], 0, 0, width, height,
+		    &src[2], 0, 0, rc_width, rc_height,
 		    &dst[2], 0, 0);
 	intel_bb_flush_render(ibb1);
 
@@ -3325,7 +3326,7 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	igt_debug("n samples written = %"PRIu64"/%"PRIu64" (%ix%i)\n",
 		  accumulator.deltas[2 + 21],
 		  accumulator.deltas[2 + 26],
-		  width, height);
+		  rc_width, rc_height);
 	accumulator_print(&accumulator, "filtered");
 
 	/* Verify that the work actually happened by comparing the src
@@ -3334,7 +3335,7 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	buf_map(drm_fd, &src[0], false);
 	buf_map(drm_fd, &dst[0], false);
 
-	ret = memcmp(src[0].ptr, dst[0].ptr, 4 * width * height);
+	ret = memcmp(src[0].ptr, dst[0].ptr, 4 * rc_width * rc_height);
 	intel_buf_unmap(&src[0]);
 	intel_buf_unmap(&dst[0]);
 
@@ -3350,9 +3351,9 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	/* Check that this test passed. The test measures the number of 2x2
 	 * samples written to the render target using the counter A26. For
 	 * OAR, this counter will only have increments relevant to this specific
-	 * context. The value equals the width * height of the rendered work.
+	 * context. The value equals the rc_width * rc_height of the rendered work.
 	 */
-	igt_assert_eq(accumulator.deltas[2 + 26], width * height);
+	igt_assert_eq(accumulator.deltas[2 + 26], rc_width * rc_height);
 
  skip_check:
 	/* Clean up */
@@ -4006,8 +4007,6 @@ __test_mmio_triggered_reports(struct drm_xe_engine_class_instance *hwe)
 	struct buf_ops *bops;
 	struct intel_bb *ibb;
 	uint32_t context, vm;
-	int height = 600;
-	int width = 800;
 	uint8_t *buf;
 
 	bops = buf_ops_create(drm_fd);
@@ -4019,8 +4018,8 @@ __test_mmio_triggered_reports(struct drm_xe_engine_class_instance *hwe)
 	memset(dst_buf->ptr, 0, 4096);
 	intel_buf_unmap(dst_buf);
 
-	scratch_buf_init(bops, &src, width, height, 0xff0000ff);
-	scratch_buf_init(bops, &dst, width, height, 0x00ff00ff);
+	scratch_buf_init(bops, &src, rc_width, rc_height, 0xff0000ff);
+	scratch_buf_init(bops, &dst, rc_width, rc_height, 0x00ff00ff);
 
 	vm = xe_vm_create(drm_fd, 0, 0);
 	context = xe_exec_queue_create(drm_fd, vm, hwe, 0);
@@ -4039,7 +4038,7 @@ __test_mmio_triggered_reports(struct drm_xe_engine_class_instance *hwe)
 
 	if (render_copy)
 		render_copy(ibb,
-			    &src, 0, 0, width, height,
+			    &src, 0, 0, rc_width, rc_height,
 			    &dst, 0, 0);
 
 	emit_mmio_triggered_report(ibb, 0xc0ffee22);
-- 
2.34.1

Re: [PATCH 05/13] tests/intel/xe_oa: Use same render copy width and height across tests

[Dixit, Ashutosh]

On Fri, 14 Feb 2025 17:06:20 -0800, Umesh Nerlige Ramappa wrote:
>
> Use the same width and height for render copy frame across tests.

Use the same width and height for render copy frame to make execution times
uniform across tests.

>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/intel/xe_oa.c | 39 +++++++++++++++++++--------------------
>  1 file changed, 19 insertions(+), 20 deletions(-)
>
> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> index 7e40e9257..aaf92308a 100644
> --- a/tests/intel/xe_oa.c
> +++ b/tests/intel/xe_oa.c
> @@ -303,6 +303,7 @@ static uint64_t oa_exponent_default;
>  static size_t default_oa_buffer_size;
>  static struct intel_mmio_data mmio_data;
>  static igt_render_copyfunc_t render_copy;
> +static uint32_t rc_width, rc_height;
>
>  static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
>  {
> @@ -1089,6 +1090,8 @@ init_sys_info(void)
>
>	intel_xe_perf_load_perf_configs(intel_xe_perf, drm_fd);
>
> +	rc_width = 1920;
> +	rc_height = 1080;

If this increases the execution time for the tests, we could go with the
smaller 800x600 size?

But otherwise this is:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>


>	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
>
>	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
> @@ -1608,7 +1611,7 @@ static void load_helper_run(enum load load)
>
>		while (!lh.exit) {
>			render_copy(lh.ibb,
> -				    &lh.src, 0, 0, 1920, 1080,
> +				    &lh.src, 0, 0, rc_width, rc_height,
>				    &lh.dst, 0, 0);
>
>			intel_bb_sync(lh.ibb);
> @@ -1645,8 +1648,8 @@ static void load_helper_init(void)
>
>	lh.ibb = intel_bb_create_with_context(drm_fd, lh.context_id, lh.vm, NULL, BATCH_SZ);
>
> -	scratch_buf_init(lh.bops, &lh.dst, 1920, 1080, 0);
> -	scratch_buf_init(lh.bops, &lh.src, 1920, 1080, 0);
> +	scratch_buf_init(lh.bops, &lh.dst, rc_width, rc_height, 0);
> +	scratch_buf_init(lh.bops, &lh.src, rc_width, rc_height, 0);
>  }
>
>  static void load_helper_fini(void)
> @@ -3112,8 +3115,6 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
>	uint64_t delta_ts64, delta_oa32;
>	uint64_t delta_ts64_ns, delta_oa32_ns;
>	uint64_t delta_delta;
> -	int width = 800;
> -	int height = 600;
>  #define INVALID_CTX_ID 0xffffffff
>	uint32_t ctx0_id = INVALID_CTX_ID;
>	uint32_t ctx1_id = INVALID_CTX_ID;
> @@ -3125,8 +3126,8 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
>	bops = buf_ops_create(drm_fd);
>
>	for (int i = 0; i < ARRAY_SIZE(src); i++) {
> -		scratch_buf_init(bops, &src[i], width, height, 0xff0000ff);
> -		scratch_buf_init(bops, &dst[i], width, height, 0x00ff00ff);
> +		scratch_buf_init(bops, &src[i], rc_width, rc_height, 0xff0000ff);
> +		scratch_buf_init(bops, &dst[i], rc_width, rc_height, 0x00ff00ff);
>	}
>
>	vm = xe_vm_create(drm_fd, 0, 0);
> @@ -3139,7 +3140,7 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
>
>	/* Submit some early, unmeasured, work to the context we want */
>	render_copy(ibb0,
> -		    &src[0], 0, 0, width, height,
> +		    &src[0], 0, 0, rc_width, rc_height,
>		    &dst[0], 0, 0);
>
>	/* Initialize the context parameter to the perf open ioctl here */
> @@ -3175,7 +3176,7 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
>
>	/* This is the work/context that is measured for counter increments */
>	render_copy(ibb0,
> -		    &src[0], 0, 0, width, height,
> +		    &src[0], 0, 0, rc_width, rc_height,
>		    &dst[0], 0, 0);
>	intel_bb_flush_render(ibb0);
>
> @@ -3200,11 +3201,11 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
>	 * context1
>	 */
>	render_copy(ibb1,
> -		    &src[1], 0, 0, width, height,
> +		    &src[1], 0, 0, rc_width, rc_height,
>		    &dst[1], 0, 0);
>
>	render_copy(ibb1,
> -		    &src[2], 0, 0, width, height,
> +		    &src[2], 0, 0, rc_width, rc_height,
>		    &dst[2], 0, 0);
>	intel_bb_flush_render(ibb1);
>
> @@ -3325,7 +3326,7 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
>	igt_debug("n samples written = %"PRIu64"/%"PRIu64" (%ix%i)\n",
>		  accumulator.deltas[2 + 21],
>		  accumulator.deltas[2 + 26],
> -		  width, height);
> +		  rc_width, rc_height);
>	accumulator_print(&accumulator, "filtered");
>
>	/* Verify that the work actually happened by comparing the src
> @@ -3334,7 +3335,7 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
>	buf_map(drm_fd, &src[0], false);
>	buf_map(drm_fd, &dst[0], false);
>
> -	ret = memcmp(src[0].ptr, dst[0].ptr, 4 * width * height);
> +	ret = memcmp(src[0].ptr, dst[0].ptr, 4 * rc_width * rc_height);
>	intel_buf_unmap(&src[0]);
>	intel_buf_unmap(&dst[0]);
>
> @@ -3350,9 +3351,9 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
>	/* Check that this test passed. The test measures the number of 2x2
>	 * samples written to the render target using the counter A26. For
>	 * OAR, this counter will only have increments relevant to this specific
> -	 * context. The value equals the width * height of the rendered work.
> +	 * context. The value equals the rc_width * rc_height of the rendered work.
>	 */
> -	igt_assert_eq(accumulator.deltas[2 + 26], width * height);
> +	igt_assert_eq(accumulator.deltas[2 + 26], rc_width * rc_height);
>
>   skip_check:
>	/* Clean up */
> @@ -4006,8 +4007,6 @@ __test_mmio_triggered_reports(struct drm_xe_engine_class_instance *hwe)
>	struct buf_ops *bops;
>	struct intel_bb *ibb;
>	uint32_t context, vm;
> -	int height = 600;
> -	int width = 800;
>	uint8_t *buf;
>
>	bops = buf_ops_create(drm_fd);
> @@ -4019,8 +4018,8 @@ __test_mmio_triggered_reports(struct drm_xe_engine_class_instance *hwe)
>	memset(dst_buf->ptr, 0, 4096);
>	intel_buf_unmap(dst_buf);
>
> -	scratch_buf_init(bops, &src, width, height, 0xff0000ff);
> -	scratch_buf_init(bops, &dst, width, height, 0x00ff00ff);
> +	scratch_buf_init(bops, &src, rc_width, rc_height, 0xff0000ff);
> +	scratch_buf_init(bops, &dst, rc_width, rc_height, 0x00ff00ff);
>
>	vm = xe_vm_create(drm_fd, 0, 0);
>	context = xe_exec_queue_create(drm_fd, vm, hwe, 0);
> @@ -4039,7 +4038,7 @@ __test_mmio_triggered_reports(struct drm_xe_engine_class_instance *hwe)
>
>	if (render_copy)
>		render_copy(ibb,
> -			    &src, 0, 0, width, height,
> +			    &src, 0, 0, rc_width, rc_height,
>			    &dst, 0, 0);
>
>	emit_mmio_triggered_report(ibb, 0xc0ffee22);
> --
> 2.34.1
>

[PATCH 06/13] tests/intel/xe_oa: Rewrite the polling small buf test

[Umesh Nerlige Ramappa]

Use mmio reads as a side-channel to determine if reports are available
and ensure that poll will return with POLLIN set. Then provide a small
buffer to force ENOSPC error. Then poll with a timeout of 0 to check if
POLLIN is still set.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 64 +++++++++++++++++++++++++--------------------
 1 file changed, 35 insertions(+), 29 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index aaf92308a..5792ffec2 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -2216,7 +2216,6 @@ static void test_polling(uint64_t requested_oa_period,
  */
 static void test_polling_small_buf(void)
 {
-	int oa_exponent = max_oa_exponent_for_period_lte(40 * 1000); /* 40us */
 	uint64_t properties[] = {
 		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
 
@@ -2226,50 +2225,57 @@ static void test_polling_small_buf(void)
 		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
 	};
 	struct intel_xe_oa_open_prop param = {
 		.num_properties = ARRAY_SIZE(properties) / 2,
 		.properties_ptr = to_user_pointer(properties),
 	};
-	uint32_t test_duration = 80 * 1000 * 1000;
-	int sample_size = get_oa_format(default_test_set->perf_oa_format).size;
-	int n_expected_reports = test_duration / oa_exponent_to_ns(oa_exponent);
-	int n_expect_read_bytes = n_expected_reports * sample_size;
-	struct timespec ts = {};
-	int n_bytes_read = 0;
-	uint32_t n_polls = 0;
+	int report_size = get_oa_format(default_test_set->perf_oa_format).size;
+	u32 oa_tail, prev_tail;
+	struct pollfd pollfd;
+	uint8_t buf[10];
+	int ret, i = 0;
+
+	intel_register_access_init(&mmio_data,
+				   igt_device_get_pci_device(drm_fd), 0);
 
 	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
 	set_fd_flags(stream_fd, O_CLOEXEC | O_NONBLOCK);
-	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
-
-	while (igt_nsec_elapsed(&ts) < test_duration) {
-		struct pollfd pollfd = { .fd = stream_fd, .events = POLLIN };
 
-		ppoll(&pollfd, 1, NULL, NULL);
-		if (pollfd.revents & POLLIN) {
-			uint8_t buf[1024];
-			int ret;
+#define OAG_OATAILPTR	(0xdb04)
+	/* Save the current tail */
+	prev_tail = oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
 
-			ret = read(stream_fd, buf, sizeof(buf));
-			if (ret >= 0)
-				n_bytes_read += ret;
-		}
+	/* Kickstart the capture */
+	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
 
-		n_polls++;
+	/* Wait for 5 reports */
+	while ((oa_tail - prev_tail) < (5 * report_size)) {
+		usleep(1000);
+		oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
+		if (i++ > 10)
+			break;
 	}
 
-	igt_info("Read %d expected %d (%.2f%% of the expected number), polls=%u\n",
-		 n_bytes_read, n_expect_read_bytes,
-		 n_bytes_read * 100.0f / n_expect_read_bytes,
-		 n_polls);
+	intel_register_access_fini(&mmio_data);
 
-	__perf_close(stream_fd);
+	/* Just read one report and expect ENOSPC */
+	pollfd.fd = stream_fd;
+	pollfd.events = POLLIN;
+	poll(&pollfd, 1, 1000);
+	igt_assert(pollfd.revents & POLLIN);
+	errno = 0;
+	ret = read(stream_fd, buf, sizeof(buf));
+	igt_assert_eq(ret, -1);
+	igt_assert_eq(errno, ENOSPC);
 
-	igt_assert(abs(n_expect_read_bytes - n_bytes_read) <
-		   0.20 * n_expect_read_bytes);
+	/* Poll with 0 timeout and expect POLLIN flag to be set */
+	poll(&pollfd, 1, 0);
+	igt_assert(pollfd.revents & POLLIN);
+
+	__perf_close(stream_fd);
 }
 
 static int
-- 
2.34.1

Re: [PATCH 06/13] tests/intel/xe_oa: Rewrite the polling small buf test

[Dixit, Ashutosh]

On Tue, 18 Feb 2025 12:28:04 -0800, Umesh Nerlige Ramappa wrote:
>

Hi Umesh,

> Use mmio reads as a side-channel to determine if reports are available
> and ensure that poll will return with POLLIN set. Then provide a small
> buffer to force ENOSPC error. Then poll with a timeout of 0 to check if
> POLLIN is still set.

Will need a reason for doing this here. But see below.

>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/intel/xe_oa.c | 64 +++++++++++++++++++++++++--------------------
>  1 file changed, 35 insertions(+), 29 deletions(-)
>
> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> index aaf92308a..5792ffec2 100644
> --- a/tests/intel/xe_oa.c
> +++ b/tests/intel/xe_oa.c
> @@ -2216,7 +2216,6 @@ static void test_polling(uint64_t requested_oa_period,
>   */
>  static void test_polling_small_buf(void)
>  {
> -	int oa_exponent = max_oa_exponent_for_period_lte(40 * 1000); /* 40us */
>	uint64_t properties[] = {
>		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
>
> @@ -2226,50 +2225,57 @@ static void test_polling_small_buf(void)
>		/* OA unit configuration */
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
>	};
>	struct intel_xe_oa_open_prop param = {
>		.num_properties = ARRAY_SIZE(properties) / 2,
>		.properties_ptr = to_user_pointer(properties),
>	};
> -	uint32_t test_duration = 80 * 1000 * 1000;
> -	int sample_size = get_oa_format(default_test_set->perf_oa_format).size;
> -	int n_expected_reports = test_duration / oa_exponent_to_ns(oa_exponent);
> -	int n_expect_read_bytes = n_expected_reports * sample_size;
> -	struct timespec ts = {};
> -	int n_bytes_read = 0;
> -	uint32_t n_polls = 0;
> +	int report_size = get_oa_format(default_test_set->perf_oa_format).size;
> +	u32 oa_tail, prev_tail;
> +	struct pollfd pollfd;
> +	uint8_t buf[10];
> +	int ret, i = 0;
> +
> +	intel_register_access_init(&mmio_data,
> +				   igt_device_get_pci_device(drm_fd), 0);
>
>	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
>	set_fd_flags(stream_fd, O_CLOEXEC | O_NONBLOCK);
> -	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
> -
> -	while (igt_nsec_elapsed(&ts) < test_duration) {
> -		struct pollfd pollfd = { .fd = stream_fd, .events = POLLIN };
>
> -		ppoll(&pollfd, 1, NULL, NULL);
> -		if (pollfd.revents & POLLIN) {
> -			uint8_t buf[1024];
> -			int ret;
> +#define OAG_OATAILPTR	(0xdb04)
> +	/* Save the current tail */
> +	prev_tail = oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
>
> -			ret = read(stream_fd, buf, sizeof(buf));
> -			if (ret >= 0)
> -				n_bytes_read += ret;
> -		}
> +	/* Kickstart the capture */
> +	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
>
> -		n_polls++;
> +	/* Wait for 5 reports */

Wait for 5 reports or 10 ms ?


> +	while ((oa_tail - prev_tail) < (5 * report_size)) {
> +		usleep(1000);
> +		oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
> +		if (i++ > 10)

So on slow platforms we might not get any reports in 10 ms? The idea here
should be to not have any timing dependence? So if we want to wait for 5
reports, just wait for 5 reports?

We tried doing this for the mmap OA buffer: see
mmap_wait_for_periodic_reports(), the function waits indefinitely.

So if this is done I am not sure if the intel_register_read() approach is
needed (but I didn't think of doing that :). But I guess we can use it to
see when there are N reports available.

Longer term it would be nice to have a centralized function
wait_for_n_reports(int n) or something like that which different tests can
use.

> +			break;
>	}
>
> -	igt_info("Read %d expected %d (%.2f%% of the expected number), polls=%u\n",
> -		 n_bytes_read, n_expect_read_bytes,
> -		 n_bytes_read * 100.0f / n_expect_read_bytes,
> -		 n_polls);
> +	intel_register_access_fini(&mmio_data);
>
> -	__perf_close(stream_fd);
> +	/* Just read one report and expect ENOSPC */
> +	pollfd.fd = stream_fd;
> +	pollfd.events = POLLIN;
> +	poll(&pollfd, 1, 1000);
> +	igt_assert(pollfd.revents & POLLIN);

Is the assumption here that the kernel timer is firing every 5 ms (so if
we've waited for 10 ms POLLIN must be set since the timer is firing every 5
ms)? I am not sure if that 5 ms is uapi. Or is it? Actually I was thinking
of changing that 5 ms time or changing the timer to a delayed work.

> +	errno = 0;
> +	ret = read(stream_fd, buf, sizeof(buf));
> +	igt_assert_eq(ret, -1);
> +	igt_assert_eq(errno, ENOSPC);

This part looks ok, it's uapi.

>
> -	igt_assert(abs(n_expect_read_bytes - n_bytes_read) <
> -		   0.20 * n_expect_read_bytes);
> +	/* Poll with 0 timeout and expect POLLIN flag to be set */
> +	poll(&pollfd, 1, 0);
> +	igt_assert(pollfd.revents & POLLIN);
> +
> +	__perf_close(stream_fd);

How about just reading N reports using a small buffer for this test,
however long it takes? N can 5 or 10.

Thanks.
--
Ashutosh

Re: [PATCH 06/13] tests/intel/xe_oa: Rewrite the polling small buf test

[Dixit, Ashutosh]

On Mon, 24 Feb 2025 14:56:05 -0800, Umesh Nerlige Ramappa wrote:
>
> On Mon, Feb 24, 2025 at 12:11:37PM -0800, Dixit, Ashutosh wrote:
> > On Tue, 18 Feb 2025 12:28:04 -0800, Umesh Nerlige Ramappa wrote:
> >>
> >
> > Hi Umesh,
> >
> >> Use mmio reads as a side-channel to determine if reports are available
> >> and ensure that poll will return with POLLIN set. Then provide a small
> >> buffer to force ENOSPC error. Then poll with a timeout of 0 to check if
> >> POLLIN is still set.
> >
> > Will need a reason for doing this here. But see below.
> >
> >>
> >> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> >> ---
> >>  tests/intel/xe_oa.c | 64 +++++++++++++++++++++++++--------------------
> >>  1 file changed, 35 insertions(+), 29 deletions(-)
> >>
> >> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> >> index aaf92308a..5792ffec2 100644
> >> --- a/tests/intel/xe_oa.c
> >> +++ b/tests/intel/xe_oa.c
> >> @@ -2216,7 +2216,6 @@ static void test_polling(uint64_t requested_oa_period,
> >>   */
> >>  static void test_polling_small_buf(void)
> >>  {
> >> -	int oa_exponent = max_oa_exponent_for_period_lte(40 * 1000); /* 40us */
> >>	uint64_t properties[] = {
> >>		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
> >>
> >> @@ -2226,50 +2225,57 @@ static void test_polling_small_buf(void)
> >>		/* OA unit configuration */
> >>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
> >>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> >> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
> >> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >>		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
> >>	};
> >>	struct intel_xe_oa_open_prop param = {
> >>		.num_properties = ARRAY_SIZE(properties) / 2,
> >>		.properties_ptr = to_user_pointer(properties),
> >>	};
> >> -	uint32_t test_duration = 80 * 1000 * 1000;
> >> -	int sample_size = get_oa_format(default_test_set->perf_oa_format).size;
> >> -	int n_expected_reports = test_duration / oa_exponent_to_ns(oa_exponent);
> >> -	int n_expect_read_bytes = n_expected_reports * sample_size;
> >> -	struct timespec ts = {};
> >> -	int n_bytes_read = 0;
> >> -	uint32_t n_polls = 0;
> >> +	int report_size = get_oa_format(default_test_set->perf_oa_format).size;
> >> +	u32 oa_tail, prev_tail;
> >> +	struct pollfd pollfd;
> >> +	uint8_t buf[10];
> >> +	int ret, i = 0;
> >> +
> >> +	intel_register_access_init(&mmio_data,
> >> +				   igt_device_get_pci_device(drm_fd), 0);
> >>
> >>	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
> >>	set_fd_flags(stream_fd, O_CLOEXEC | O_NONBLOCK);
> >> -	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
> >> -
> >> -	while (igt_nsec_elapsed(&ts) < test_duration) {
> >> -		struct pollfd pollfd = { .fd = stream_fd, .events = POLLIN };
> >>
> >> -		ppoll(&pollfd, 1, NULL, NULL);
> >> -		if (pollfd.revents & POLLIN) {
> >> -			uint8_t buf[1024];
> >> -			int ret;
> >> +#define OAG_OATAILPTR	(0xdb04)
> >> +	/* Save the current tail */
> >> +	prev_tail = oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
> >>
> >> -			ret = read(stream_fd, buf, sizeof(buf));
> >> -			if (ret >= 0)
> >> -				n_bytes_read += ret;
> >> -		}
> >> +	/* Kickstart the capture */
> >> +	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
> >>
> >> -		n_polls++;
> >> +	/* Wait for 5 reports */
> >
> > Wait for 5 reports or 10 ms ?
> >
> >
> >> +	while ((oa_tail - prev_tail) < (5 * report_size)) {
> >> +		usleep(1000);
> >> +		oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
> >> +		if (i++ > 10)
> >
> > So on slow platforms we might not get any reports in 10 ms? The idea here
> > should be to not have any timing dependence? So if we want to wait for 5
> > reports, just wait for 5 reports?
>
> Oh, I think the loop was stuck while debugging something, so had added a
> counter to bail out in 10 iterations. I will remove that. We only need to
> wait for 5 reports.

Ok.

>
> >
> > We tried doing this for the mmap OA buffer: see
> > mmap_wait_for_periodic_reports(), the function waits indefinitely.
>
> You mean this:
>
> while (num_periodic_reports < n) {
>	usleep(4 * n * period_us);
>	num_periodic_reports = 0;
>	for (reports = (uint32_t *)oa_vaddr;
>	     reports[0] && oa_timestamp(reports, fmt) && oa_report_is_periodic(reports);
>	     reports += get_oa_format(fmt).size) {
>		num_periodic_reports++;
>	}
> }
>
> Well.. if your reports start coming in fast enough, then you would just
> spin in the inner for loop. Maybe break the inner for loop when
> num_periodic_reports >= n;

Ok, but I was just pointing out that this sort of code is beginning to get
in. Sai Teja did this.

>
> >
> > So if this is done I am not sure if the intel_register_read() approach is
> > needed (but I didn't think of doing that :). But I guess we can use it to
> > see when there are N reports available.
> >
> > Longer term it would be nice to have a centralized function
> > wait_for_n_reports(int n) or something like that which different tests can
> > use.
>
> Agree, except that some tests will read the actual reports, while others
> just want to take a peek at how many reports are available without reading
> them. Since mmap is also a feature under test, I took the easier
> approach. We can always refine it if we find something better.

Can have similar peek_for_n_reports(n), which would have to use your
register read method.

>
> >
> >> +			break;
> >>	}
> >>
> >> -	igt_info("Read %d expected %d (%.2f%% of the expected number), polls=%u\n",
> >> -		 n_bytes_read, n_expect_read_bytes,
> >> -		 n_bytes_read * 100.0f / n_expect_read_bytes,
> >> -		 n_polls);
> >> +	intel_register_access_fini(&mmio_data);
> >>
> >> -	__perf_close(stream_fd);
> >> +	/* Just read one report and expect ENOSPC */
> >> +	pollfd.fd = stream_fd;
> >> +	pollfd.events = POLLIN;
> >> +	poll(&pollfd, 1, 1000);
> >> +	igt_assert(pollfd.revents & POLLIN);
> >
> > Is the assumption here that the kernel timer is firing every 5 ms (so if
> > we've waited for 10 ms POLLIN must be set since the timer is firing every 5
> > ms)? I am not sure if that 5 ms is uapi. Or is it? Actually I was thinking
> > of changing that 5 ms time or changing the timer to a delayed work.
>
> But here I am waiting 1000ms in the poll above. That should be sufficient
> for POLLIN  to be set. If not, we could set the timeout to a large value (a
> few seconds).

Oh ok, sorry I missed the 1000 ms.

>
> >
> >> +	errno = 0;
> >> +	ret = read(stream_fd, buf, sizeof(buf));
> >> +	igt_assert_eq(ret, -1);
> >> +	igt_assert_eq(errno, ENOSPC);
> >
> > This part looks ok, it's uapi.
> >
>
> Note:
> ENOSPC is returned only if the buffer is small enough that not even one
> report will fit in. Initially I had a 600 byte buffer, but I did not get
> ENOSPC. Instead I got 576 in ret which I think is the correct behavior.

OK.

> >>
> >> -	igt_assert(abs(n_expect_read_bytes - n_bytes_read) <
> >> -		   0.20 * n_expect_read_bytes);
> >> +	/* Poll with 0 timeout and expect POLLIN flag to be set */
> >> +	poll(&pollfd, 1, 0);
> >> +	igt_assert(pollfd.revents & POLLIN);
> >> +
> >> +	__perf_close(stream_fd);
> >
> > How about just reading N reports using a small buffer for this test,
> > however long it takes? N can 5 or 10.
>
> Not sure I understand. You mean at this stage of the test, read 5/10
> reports? OR just alter the entire test somehow to do something different?
>
> I thought the test was specifically testing that POLLIN is still set after
> an ENOSPC error, so I have written it for that case alone. The 0 timeout
> will bypass the wait in the poll so that we only get the state of POLLIN.

The original test, as I see it, seems to be just doing a lot of regular
reads with a small buffer (1K instead of 16 MB say).

But what you are doing here is also probably ok/better than the
original. Let me think some more about it.

Thanks.
--
Ashutosh

Re: [PATCH 06/13] tests/intel/xe_oa: Rewrite the polling small buf test

[Umesh Nerlige Ramappa]

On Mon, Feb 24, 2025 at 08:26:56PM -0800, Dixit, Ashutosh wrote:
>On Mon, 24 Feb 2025 14:56:05 -0800, Umesh Nerlige Ramappa wrote:
>>
>> On Mon, Feb 24, 2025 at 12:11:37PM -0800, Dixit, Ashutosh wrote:
>> > On Tue, 18 Feb 2025 12:28:04 -0800, Umesh Nerlige Ramappa wrote:
>> >>
>> >
>> > Hi Umesh,
>> >
>> >> Use mmio reads as a side-channel to determine if reports are available
>> >> and ensure that poll will return with POLLIN set. Then provide a small
>> >> buffer to force ENOSPC error. Then poll with a timeout of 0 to check if
>> >> POLLIN is still set.
>> >
>> > Will need a reason for doing this here. But see below.
>> >
>> >>
>> >> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> >> ---
>> >>  tests/intel/xe_oa.c | 64 +++++++++++++++++++++++++--------------------
>> >>  1 file changed, 35 insertions(+), 29 deletions(-)
>> >>
>> >> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
>> >> index aaf92308a..5792ffec2 100644
>> >> --- a/tests/intel/xe_oa.c
>> >> +++ b/tests/intel/xe_oa.c
>> >> @@ -2216,7 +2216,6 @@ static void test_polling(uint64_t requested_oa_period,
>> >>   */
>> >>  static void test_polling_small_buf(void)
>> >>  {
>> >> -	int oa_exponent = max_oa_exponent_for_period_lte(40 * 1000); /* 40us */
>> >>	uint64_t properties[] = {
>> >>		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
>> >>
>> >> @@ -2226,50 +2225,57 @@ static void test_polling_small_buf(void)
>> >>		/* OA unit configuration */
>> >>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
>> >>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
>> >> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
>> >> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>> >>		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
>> >>	};
>> >>	struct intel_xe_oa_open_prop param = {
>> >>		.num_properties = ARRAY_SIZE(properties) / 2,
>> >>		.properties_ptr = to_user_pointer(properties),
>> >>	};
>> >> -	uint32_t test_duration = 80 * 1000 * 1000;
>> >> -	int sample_size = get_oa_format(default_test_set->perf_oa_format).size;
>> >> -	int n_expected_reports = test_duration / oa_exponent_to_ns(oa_exponent);
>> >> -	int n_expect_read_bytes = n_expected_reports * sample_size;
>> >> -	struct timespec ts = {};
>> >> -	int n_bytes_read = 0;
>> >> -	uint32_t n_polls = 0;
>> >> +	int report_size = get_oa_format(default_test_set->perf_oa_format).size;
>> >> +	u32 oa_tail, prev_tail;
>> >> +	struct pollfd pollfd;
>> >> +	uint8_t buf[10];
>> >> +	int ret, i = 0;
>> >> +
>> >> +	intel_register_access_init(&mmio_data,
>> >> +				   igt_device_get_pci_device(drm_fd), 0);
>> >>
>> >>	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
>> >>	set_fd_flags(stream_fd, O_CLOEXEC | O_NONBLOCK);
>> >> -	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
>> >> -
>> >> -	while (igt_nsec_elapsed(&ts) < test_duration) {
>> >> -		struct pollfd pollfd = { .fd = stream_fd, .events = POLLIN };
>> >>
>> >> -		ppoll(&pollfd, 1, NULL, NULL);
>> >> -		if (pollfd.revents & POLLIN) {
>> >> -			uint8_t buf[1024];
>> >> -			int ret;
>> >> +#define OAG_OATAILPTR	(0xdb04)
>> >> +	/* Save the current tail */
>> >> +	prev_tail = oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
>> >>
>> >> -			ret = read(stream_fd, buf, sizeof(buf));
>> >> -			if (ret >= 0)
>> >> -				n_bytes_read += ret;
>> >> -		}
>> >> +	/* Kickstart the capture */
>> >> +	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
>> >>
>> >> -		n_polls++;
>> >> +	/* Wait for 5 reports */
>> >
>> > Wait for 5 reports or 10 ms ?
>> >
>> >
>> >> +	while ((oa_tail - prev_tail) < (5 * report_size)) {
>> >> +		usleep(1000);
>> >> +		oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
>> >> +		if (i++ > 10)
>> >
>> > So on slow platforms we might not get any reports in 10 ms? The idea here
>> > should be to not have any timing dependence? So if we want to wait for 5
>> > reports, just wait for 5 reports?
>>
>> Oh, I think the loop was stuck while debugging something, so had added a
>> counter to bail out in 10 iterations. I will remove that. We only need to
>> wait for 5 reports.
>
>Ok.
>
>>
>> >
>> > We tried doing this for the mmap OA buffer: see
>> > mmap_wait_for_periodic_reports(), the function waits indefinitely.
>>
>> You mean this:
>>
>> while (num_periodic_reports < n) {
>>	usleep(4 * n * period_us);
>>	num_periodic_reports = 0;
>>	for (reports = (uint32_t *)oa_vaddr;
>>	     reports[0] && oa_timestamp(reports, fmt) && oa_report_is_periodic(reports);
>>	     reports += get_oa_format(fmt).size) {
>>		num_periodic_reports++;
>>	}
>> }
>>
>> Well.. if your reports start coming in fast enough, then you would just
>> spin in the inner for loop. Maybe break the inner for loop when
>> num_periodic_reports >= n;
>
>Ok, but I was just pointing out that this sort of code is beginning to get
>in. Sai Teja did this.
>
>>
>> >
>> > So if this is done I am not sure if the intel_register_read() approach is
>> > needed (but I didn't think of doing that :). But I guess we can use it to
>> > see when there are N reports available.
>> >
>> > Longer term it would be nice to have a centralized function
>> > wait_for_n_reports(int n) or something like that which different tests can
>> > use.
>>
>> Agree, except that some tests will read the actual reports, while others
>> just want to take a peek at how many reports are available without reading
>> them. Since mmap is also a feature under test, I took the easier
>> approach. We can always refine it if we find something better.
>
>Can have similar peek_for_n_reports(n), which would have to use your
>register read method.
>
>>
>> >
>> >> +			break;
>> >>	}
>> >>
>> >> -	igt_info("Read %d expected %d (%.2f%% of the expected number), polls=%u\n",
>> >> -		 n_bytes_read, n_expect_read_bytes,
>> >> -		 n_bytes_read * 100.0f / n_expect_read_bytes,
>> >> -		 n_polls);
>> >> +	intel_register_access_fini(&mmio_data);
>> >>
>> >> -	__perf_close(stream_fd);
>> >> +	/* Just read one report and expect ENOSPC */
>> >> +	pollfd.fd = stream_fd;
>> >> +	pollfd.events = POLLIN;
>> >> +	poll(&pollfd, 1, 1000);
>> >> +	igt_assert(pollfd.revents & POLLIN);
>> >
>> > Is the assumption here that the kernel timer is firing every 5 ms (so if
>> > we've waited for 10 ms POLLIN must be set since the timer is firing every 5
>> > ms)? I am not sure if that 5 ms is uapi. Or is it? Actually I was thinking
>> > of changing that 5 ms time or changing the timer to a delayed work.
>>
>> But here I am waiting 1000ms in the poll above. That should be sufficient
>> for POLLIN  to be set. If not, we could set the timeout to a large value (a
>> few seconds).
>
>Oh ok, sorry I missed the 1000 ms.
>
>>
>> >
>> >> +	errno = 0;
>> >> +	ret = read(stream_fd, buf, sizeof(buf));
>> >> +	igt_assert_eq(ret, -1);
>> >> +	igt_assert_eq(errno, ENOSPC);
>> >
>> > This part looks ok, it's uapi.
>> >
>>
>> Note:
>> ENOSPC is returned only if the buffer is small enough that not even one
>> report will fit in. Initially I had a 600 byte buffer, but I did not get
>> ENOSPC. Instead I got 576 in ret which I think is the correct behavior.
>
>OK.
>
>> >>
>> >> -	igt_assert(abs(n_expect_read_bytes - n_bytes_read) <
>> >> -		   0.20 * n_expect_read_bytes);
>> >> +	/* Poll with 0 timeout and expect POLLIN flag to be set */
>> >> +	poll(&pollfd, 1, 0);
>> >> +	igt_assert(pollfd.revents & POLLIN);
>> >> +
>> >> +	__perf_close(stream_fd);
>> >
>> > How about just reading N reports using a small buffer for this test,
>> > however long it takes? N can 5 or 10.
>>
>> Not sure I understand. You mean at this stage of the test, read 5/10
>> reports? OR just alter the entire test somehow to do something different?
>>
>> I thought the test was specifically testing that POLLIN is still set after
>> an ENOSPC error, so I have written it for that case alone. The 0 timeout
>> will bypass the wait in the poll so that we only get the state of POLLIN.
>
>The original test, as I see it, seems to be just doing a lot of regular
>reads with a small buffer (1K instead of 16 MB say).
>
>But what you are doing here is also probably ok/better than the
>original. Let me think some more about it.

Just a heads up, I think prev_tail should be read after oa_stream is 
enabled, because BUFFER/TAIL/HEAD is configured on enable. Maybe I will 
read the prev_tail after enabling OA or something like that.

In the long run, I might just use the whitelisted TAIL reg to do that, 
so that it's part of the uapi and will hopefully work the way I want it 
to. Right now taking the path of least resistance..

Thanks,
Umesh
>
>Thanks.
>--
>Ashutosh

Re: [PATCH 06/13] tests/intel/xe_oa: Rewrite the polling small buf test

[Dixit, Ashutosh]

On Tue, 25 Feb 2025 14:51:39 -0800, Umesh Nerlige Ramappa wrote:
>

Hi Umesh,

> On Mon, Feb 24, 2025 at 08:26:56PM -0800, Dixit, Ashutosh wrote:
> > On Mon, 24 Feb 2025 14:56:05 -0800, Umesh Nerlige Ramappa wrote:
> >>
> >> On Mon, Feb 24, 2025 at 12:11:37PM -0800, Dixit, Ashutosh wrote:
> >> > On Tue, 18 Feb 2025 12:28:04 -0800, Umesh Nerlige Ramappa wrote:
> >> >>
> >> >
> >> >> Use mmio reads as a side-channel to determine if reports are available
> >> >> and ensure that poll will return with POLLIN set. Then provide a small
> >> >> buffer to force ENOSPC error. Then poll with a timeout of 0 to check if
> >> >> POLLIN is still set.
> >> >
> >> > Will need a reason for doing this here. But see below.
> >> >
> >> >>
> >> >> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> >> >> ---
> >> >>  tests/intel/xe_oa.c | 64 +++++++++++++++++++++++++--------------------
> >> >>  1 file changed, 35 insertions(+), 29 deletions(-)
> >> >>
> >> >> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> >> >> index aaf92308a..5792ffec2 100644
> >> >> --- a/tests/intel/xe_oa.c
> >> >> +++ b/tests/intel/xe_oa.c
> >> >> @@ -2216,7 +2216,6 @@ static void test_polling(uint64_t requested_oa_period,
> >> >>   */
> >> >>  static void test_polling_small_buf(void)
> >> >>  {
> >> >> -	int oa_exponent = max_oa_exponent_for_period_lte(40 * 1000); /* 40us */
> >> >>	uint64_t properties[] = {
> >> >>		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
> >> >>
> >> >> @@ -2226,50 +2225,57 @@ static void test_polling_small_buf(void)
> >> >>		/* OA unit configuration */
> >> >>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, default_test_set->perf_oa_metrics_set,
> >> >>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(default_test_set->perf_oa_format),
> >> >> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
> >> >> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >> >>		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
> >> >>	};
> >> >>	struct intel_xe_oa_open_prop param = {
> >> >>		.num_properties = ARRAY_SIZE(properties) / 2,
> >> >>		.properties_ptr = to_user_pointer(properties),
> >> >>	};
> >> >> -	uint32_t test_duration = 80 * 1000 * 1000;
> >> >> -	int sample_size = get_oa_format(default_test_set->perf_oa_format).size;
> >> >> -	int n_expected_reports = test_duration / oa_exponent_to_ns(oa_exponent);
> >> >> -	int n_expect_read_bytes = n_expected_reports * sample_size;
> >> >> -	struct timespec ts = {};
> >> >> -	int n_bytes_read = 0;
> >> >> -	uint32_t n_polls = 0;
> >> >> +	int report_size = get_oa_format(default_test_set->perf_oa_format).size;
> >> >> +	u32 oa_tail, prev_tail;
> >> >> +	struct pollfd pollfd;
> >> >> +	uint8_t buf[10];
> >> >> +	int ret, i = 0;
> >> >> +
> >> >> +	intel_register_access_init(&mmio_data,
> >> >> +				   igt_device_get_pci_device(drm_fd), 0);
> >> >>
> >> >>	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
> >> >>	set_fd_flags(stream_fd, O_CLOEXEC | O_NONBLOCK);
> >> >> -	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
> >> >> -
> >> >> -	while (igt_nsec_elapsed(&ts) < test_duration) {
> >> >> -		struct pollfd pollfd = { .fd = stream_fd, .events = POLLIN };
> >> >>
> >> >> -		ppoll(&pollfd, 1, NULL, NULL);
> >> >> -		if (pollfd.revents & POLLIN) {
> >> >> -			uint8_t buf[1024];
> >> >> -			int ret;
> >> >> +#define OAG_OATAILPTR	(0xdb04)
> >> >> +	/* Save the current tail */
> >> >> +	prev_tail = oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
> >> >>
> >> >> -			ret = read(stream_fd, buf, sizeof(buf));
> >> >> -			if (ret >= 0)
> >> >> -				n_bytes_read += ret;
> >> >> -		}
> >> >> +	/* Kickstart the capture */
> >> >> +	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
> >> >>
> >> >> -		n_polls++;
> >> >> +	/* Wait for 5 reports */
> >> >
> >> > Wait for 5 reports or 10 ms ?
> >> >
> >> >
> >> >> +	while ((oa_tail - prev_tail) < (5 * report_size)) {
> >> >> +		usleep(1000);
> >> >> +		oa_tail = intel_register_read(&mmio_data, OAG_OATAILPTR);
> >> >> +		if (i++ > 10)
> >> >
> >> > So on slow platforms we might not get any reports in 10 ms? The idea here
> >> > should be to not have any timing dependence? So if we want to wait for 5
> >> > reports, just wait for 5 reports?
> >>
> >> Oh, I think the loop was stuck while debugging something, so had added a
> >> counter to bail out in 10 iterations. I will remove that. We only need to
> >> wait for 5 reports.
> >
> > Ok.
> >
> >>
> >> >
> >> > We tried doing this for the mmap OA buffer: see
> >> > mmap_wait_for_periodic_reports(), the function waits indefinitely.
> >>
> >> You mean this:
> >>
> >> while (num_periodic_reports < n) {
> >>	usleep(4 * n * period_us);
> >>	num_periodic_reports = 0;
> >>	for (reports = (uint32_t *)oa_vaddr;
> >>	     reports[0] && oa_timestamp(reports, fmt) && oa_report_is_periodic(reports);
> >>	     reports += get_oa_format(fmt).size) {
> >>		num_periodic_reports++;
> >>	}
> >> }
> >>
> >> Well.. if your reports start coming in fast enough, then you would just
> >> spin in the inner for loop. Maybe break the inner for loop when
> >> num_periodic_reports >= n;
> >
> > Ok, but I was just pointing out that this sort of code is beginning to get
> > in. Sai Teja did this.
> >
> >>
> >> >
> >> > So if this is done I am not sure if the intel_register_read() approach is
> >> > needed (but I didn't think of doing that :). But I guess we can use it to
> >> > see when there are N reports available.
> >> >
> >> > Longer term it would be nice to have a centralized function
> >> > wait_for_n_reports(int n) or something like that which different tests can
> >> > use.
> >>
> >> Agree, except that some tests will read the actual reports, while others
> >> just want to take a peek at how many reports are available without reading
> >> them. Since mmap is also a feature under test, I took the easier
> >> approach. We can always refine it if we find something better.
> >
> > Can have similar peek_for_n_reports(n), which would have to use your
> > register read method.
> >
> >>
> >> >
> >> >> +			break;
> >> >>	}
> >> >>
> >> >> -	igt_info("Read %d expected %d (%.2f%% of the expected number), polls=%u\n",
> >> >> -		 n_bytes_read, n_expect_read_bytes,
> >> >> -		 n_bytes_read * 100.0f / n_expect_read_bytes,
> >> >> -		 n_polls);
> >> >> +	intel_register_access_fini(&mmio_data);
> >> >>
> >> >> -	__perf_close(stream_fd);
> >> >> +	/* Just read one report and expect ENOSPC */
> >> >> +	pollfd.fd = stream_fd;
> >> >> +	pollfd.events = POLLIN;
> >> >> +	poll(&pollfd, 1, 1000);
> >> >> +	igt_assert(pollfd.revents & POLLIN);
> >> >
> >> > Is the assumption here that the kernel timer is firing every 5 ms (so if
> >> > we've waited for 10 ms POLLIN must be set since the timer is firing every 5
> >> > ms)? I am not sure if that 5 ms is uapi. Or is it? Actually I was thinking
> >> > of changing that 5 ms time or changing the timer to a delayed work.
> >>
> >> But here I am waiting 1000ms in the poll above. That should be sufficient
> >> for POLLIN  to be set. If not, we could set the timeout to a large value (a
> >> few seconds).
> >
> > Oh ok, sorry I missed the 1000 ms.
> >
> >>
> >> >
> >> >> +	errno = 0;
> >> >> +	ret = read(stream_fd, buf, sizeof(buf));
> >> >> +	igt_assert_eq(ret, -1);
> >> >> +	igt_assert_eq(errno, ENOSPC);
> >> >
> >> > This part looks ok, it's uapi.
> >> >
> >>
> >> Note:
> >> ENOSPC is returned only if the buffer is small enough that not even one
> >> report will fit in. Initially I had a 600 byte buffer, but I did not get
> >> ENOSPC. Instead I got 576 in ret which I think is the correct behavior.
> >
> > OK.
> >
> >> >>
> >> >> -	igt_assert(abs(n_expect_read_bytes - n_bytes_read) <
> >> >> -		   0.20 * n_expect_read_bytes);
> >> >> +	/* Poll with 0 timeout and expect POLLIN flag to be set */
> >> >> +	poll(&pollfd, 1, 0);
> >> >> +	igt_assert(pollfd.revents & POLLIN);
> >> >> +
> >> >> +	__perf_close(stream_fd);
> >> >
> >> > How about just reading N reports using a small buffer for this test,
> >> > however long it takes? N can 5 or 10.
> >>
> >> Not sure I understand. You mean at this stage of the test, read 5/10
> >> reports? OR just alter the entire test somehow to do something different?
> >>
> >> I thought the test was specifically testing that POLLIN is still set after
> >> an ENOSPC error, so I have written it for that case alone. The 0 timeout
> >> will bypass the wait in the poll so that we only get the state of POLLIN.
> >
> > The original test, as I see it, seems to be just doing a lot of regular
> > reads with a small buffer (1K instead of 16 MB say).
> >
> > But what you are doing here is also probably ok/better than the
> > original. Let me think some more about it.
>
> Just a heads up, I think prev_tail should be read after oa_stream is
> enabled, because BUFFER/TAIL/HEAD is configured on enable. Maybe I will
> read the prev_tail after enabling OA or something like that.
>
> In the long run, I might just use the whitelisted TAIL reg to do that, so
> that it's part of the uapi and will hopefully work the way I want it
> to. Right now taking the path of least resistance..

Let's go with this approach, I think it's pretty good. We can see later if
we can think of anything better.

Also, as we were discussing, maybe instead of using  mmio read's to detect
presence of data, we can just use DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS?

Thanks.
--
Ashutosh

[PATCH 07/13] tests/intel/xe_oa: Simplify the buffer-fill test

[Umesh Nerlige Ramappa]

We only want to test that the BUFFER OVERFLOW status is set when we do
not read the OA stream data in time. To do so, keeping reading zero
bytes of data until you hit a buffer overflow.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 135 +++++++++-----------------------------------
 1 file changed, 26 insertions(+), 109 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 5792ffec2..fc03b74af 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -304,6 +304,7 @@ static size_t default_oa_buffer_size;
 static struct intel_mmio_data mmio_data;
 static igt_render_copyfunc_t render_copy;
 static uint32_t rc_width, rc_height;
+static uint32_t buffer_fill_size;
 
 static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
 {
@@ -1092,6 +1093,7 @@ init_sys_info(void)
 
 	rc_width = 1920;
 	rc_height = 1080;
+	buffer_fill_size = SZ_16M;
 	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
 
 	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
@@ -2370,11 +2372,7 @@ test_oa_tlb_invalidate(const struct drm_xe_engine_class_instance *hwe)
 static void
 test_buffer_fill(const struct drm_xe_engine_class_instance *hwe)
 {
-	/* ~5 micro second period */
-	int oa_exponent = max_oa_exponent_for_period_lte(5000);
-	uint64_t oa_period = oa_exponent_to_ns(oa_exponent);
 	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
-	uint64_t fmt = test_set->perf_oa_format;
 	uint64_t properties[] = {
 		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
 
@@ -2383,126 +2381,45 @@ test_buffer_fill(const struct drm_xe_engine_class_instance *hwe)
 
 		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
-		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
+		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
+		DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE, buffer_fill_size,
 	};
 	struct intel_xe_oa_open_prop param = {
 		.num_properties = ARRAY_SIZE(properties) / 2,
 		.properties_ptr = to_user_pointer(properties),
 	};
-	size_t report_size = get_oa_format(fmt).size;
-	int buf_size = 65536 * report_size;
-	uint8_t *buf = malloc(buf_size);
-	int len;
-	int n_full_oa_reports = default_oa_buffer_size / report_size;
-	uint64_t fill_duration = n_full_oa_reports * oa_period;
-	uint32_t *last_periodic_report = malloc(report_size);
+	uint64_t oa_period = oa_exponent_to_ns(oa_exponent_default);
+	char *buf = malloc(1024);
+	bool overflow_seen;
 	u32 oa_status;
+	int len;
 
-	igt_assert(fill_duration < 1000000000);
-
+	igt_debug("oa_period %s\n", pretty_print_oa_period(oa_period));
 	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
         set_fd_flags(stream_fd, O_CLOEXEC);
 
-	for (int i = 0; i < 5; i++) {
-		bool overflow_seen;
-		uint32_t n_periodic_reports;
-		uint32_t first_timestamp = 0, last_timestamp = 0;
-
-		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
-
-		nanosleep(&(struct timespec){ .tv_sec = 0,
-					      .tv_nsec = fill_duration * 1.25 },
-			  NULL);
-again:
-		oa_status = 0;
-		while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == EINTR)
-			;
-
-		if (errno == EIO) {
-			oa_status = get_stream_status(stream_fd);
-			igt_debug("oa_status %#x\n", oa_status);
-			overflow_seen = oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW;
-			igt_assert_eq(overflow_seen, true);
-			goto again;
-		}
-		igt_assert_neq(len, -1);
-
-		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_DISABLE, 0);
-
-		igt_debug("fill_duration = %"PRIu64"ns, oa_exponent = %u\n",
-			  fill_duration, oa_exponent);
-
-		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
-
-		nanosleep(&(struct timespec){ .tv_sec = 0,
-					.tv_nsec = fill_duration / 2 },
-			NULL);
-
-		n_periodic_reports = 0;
-
-		/* Because of the race condition between notification of new
-		 * reports and reports landing in memory, we need to rely on
-		 * timestamps to figure whether we've read enough of them.
-		 */
-		while (((last_timestamp - first_timestamp) * oa_period) < (fill_duration / 2)) {
-
-			igt_debug("dts=%u elapsed=%"PRIu64" duration=%"PRIu64"\n",
-				  last_timestamp - first_timestamp,
-				  (last_timestamp - first_timestamp) * oa_period,
-				  fill_duration / 2);
-again_1:
-			oa_status = 0;
-			while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == EINTR)
-				;
-			if (errno == EIO) {
-				oa_status = get_stream_status(stream_fd);
-				igt_debug("oa_status %#x\n", oa_status);
-				igt_assert(!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW));
-				goto again_1;
-			}
-			igt_assert_neq(len, -1);
-
-			for (int offset = 0; offset < len; offset += report_size) {
-				uint32_t *report = (void *) (buf + offset);
-
-				igt_debug(" > report ts=%"PRIu64""
-					  " ts_delta_last_periodic=%"PRIu64" is_timer=%i ctx_id=%8x nb_periodic=%u\n",
-					  oa_timestamp(report, fmt),
-					  n_periodic_reports > 0 ?  oa_timestamp_delta(report, last_periodic_report, fmt) : 0,
-					  oa_report_is_periodic(report),
-					  oa_report_get_ctx_id(report),
-					  n_periodic_reports);
-
-				if (first_timestamp == 0)
-					first_timestamp = oa_timestamp(report, fmt);
-				last_timestamp = oa_timestamp(report, fmt);
-
-				if (oa_report_is_periodic(report)) {
-					memcpy(last_periodic_report, report, report_size);
-					n_periodic_reports++;
-				}
-			}
-		}
-
-		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_DISABLE, 0);
-
-		igt_debug("first ts = %u, last ts = %u\n", first_timestamp, last_timestamp);
+	/* OA buffer is disable, we do not expect any error status */
+	oa_status = get_stream_status(stream_fd);
+	overflow_seen = !!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW);
+	igt_assert_eq(overflow_seen, 0);
 
-		igt_debug("%f < %zu < %f\n",
-			  report_size * n_full_oa_reports * 0.45,
-			  n_periodic_reports * report_size,
-			  report_size * n_full_oa_reports * 0.55);
+	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
 
-		igt_assert(n_periodic_reports * report_size >
-			   report_size * n_full_oa_reports * 0.45);
-		igt_assert(n_periodic_reports * report_size <
-			   report_size * n_full_oa_reports * 0.55);
+	errno = 0;
+	/* Read 0 bytes repeatedly until you see an EIO */
+	while ((len = read(stream_fd, buf, 0)) == -1 && (errno == EINTR || errno == ENOSPC)) {
+		usleep(100);
 	}
+	igt_assert_eq(len, -1);
+	igt_assert_eq(errno, EIO);
 
-	free(last_periodic_report);
-	free(buf);
+	/* Ensure buffer overflowed */
+	oa_status = get_stream_status(stream_fd);
+	overflow_seen = !!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW);
+	igt_assert(overflow_seen);
 
 	__perf_close(stream_fd);
 }
-- 
2.34.1

Re: [PATCH 07/13] tests/intel/xe_oa: Simplify the buffer-fill test

[Dixit, Ashutosh]

On Tue, 18 Feb 2025 12:28:05 -0800, Umesh Nerlige Ramappa wrote:
>
> We only want to test that the BUFFER OVERFLOW status is set when we do
> not read the OA stream data in time. To do so, keeping reading zero
> bytes of data until you hit a buffer overflow.

The approach in this patch is great!

>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/intel/xe_oa.c | 135 +++++++++-----------------------------------
>  1 file changed, 26 insertions(+), 109 deletions(-)
>
> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> index 5792ffec2..fc03b74af 100644
> --- a/tests/intel/xe_oa.c
> +++ b/tests/intel/xe_oa.c
> @@ -304,6 +304,7 @@ static size_t default_oa_buffer_size;
>  static struct intel_mmio_data mmio_data;
>  static igt_render_copyfunc_t render_copy;
>  static uint32_t rc_width, rc_height;
> +static uint32_t buffer_fill_size;

I am assuming these globals will be changed for slow platforms?

>
>  static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
>  {
> @@ -1092,6 +1093,7 @@ init_sys_info(void)
>
>	rc_width = 1920;
>	rc_height = 1080;
> +	buffer_fill_size = SZ_16M;
>	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
>
>	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
> @@ -2370,11 +2372,7 @@ test_oa_tlb_invalidate(const struct drm_xe_engine_class_instance *hwe)
>  static void
>  test_buffer_fill(const struct drm_xe_engine_class_instance *hwe)

There is this comment above this line:

Description: Test filling, wraparound and overflow of OA buffer

I think we should drop "wraparound", since this test never tested the
wraparound of the OA buffer, it just tested overflow.

To test wraparound I was using non-zero-reason.

>  {
> -	/* ~5 micro second period */
> -	int oa_exponent = max_oa_exponent_for_period_lte(5000);
> -	uint64_t oa_period = oa_exponent_to_ns(oa_exponent);
>	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
> -	uint64_t fmt = test_set->perf_oa_format;
>	uint64_t properties[] = {
>		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
>
> @@ -2383,126 +2381,45 @@ test_buffer_fill(const struct drm_xe_engine_class_instance *hwe)
>
>		/* OA unit configuration */
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
> -		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt),
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
> +		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
> +		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
> +		DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE, buffer_fill_size,
>	};
>	struct intel_xe_oa_open_prop param = {
>		.num_properties = ARRAY_SIZE(properties) / 2,
>		.properties_ptr = to_user_pointer(properties),
>	};
> -	size_t report_size = get_oa_format(fmt).size;
> -	int buf_size = 65536 * report_size;
> -	uint8_t *buf = malloc(buf_size);
> -	int len;
> -	int n_full_oa_reports = default_oa_buffer_size / report_size;
> -	uint64_t fill_duration = n_full_oa_reports * oa_period;
> -	uint32_t *last_periodic_report = malloc(report_size);
> +	uint64_t oa_period = oa_exponent_to_ns(oa_exponent_default);
> +	char *buf = malloc(1024);
> +	bool overflow_seen;
>	u32 oa_status;
> +	int len;
>
> -	igt_assert(fill_duration < 1000000000);
> -
> +	igt_debug("oa_period %s\n", pretty_print_oa_period(oa_period));
>	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
>          set_fd_flags(stream_fd, O_CLOEXEC);
>
> -	for (int i = 0; i < 5; i++) {
> -		bool overflow_seen;
> -		uint32_t n_periodic_reports;
> -		uint32_t first_timestamp = 0, last_timestamp = 0;
> -
> -		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
> -
> -		nanosleep(&(struct timespec){ .tv_sec = 0,
> -					      .tv_nsec = fill_duration * 1.25 },
> -			  NULL);
> -again:
> -		oa_status = 0;
> -		while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == EINTR)
> -			;
> -
> -		if (errno == EIO) {
> -			oa_status = get_stream_status(stream_fd);
> -			igt_debug("oa_status %#x\n", oa_status);
> -			overflow_seen = oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW;
> -			igt_assert_eq(overflow_seen, true);
> -			goto again;
> -		}
> -		igt_assert_neq(len, -1);
> -
> -		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_DISABLE, 0);
> -
> -		igt_debug("fill_duration = %"PRIu64"ns, oa_exponent = %u\n",
> -			  fill_duration, oa_exponent);
> -
> -		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
> -
> -		nanosleep(&(struct timespec){ .tv_sec = 0,
> -					.tv_nsec = fill_duration / 2 },
> -			NULL);
> -
> -		n_periodic_reports = 0;
> -
> -		/* Because of the race condition between notification of new
> -		 * reports and reports landing in memory, we need to rely on
> -		 * timestamps to figure whether we've read enough of them.
> -		 */
> -		while (((last_timestamp - first_timestamp) * oa_period) < (fill_duration / 2)) {
> -
> -			igt_debug("dts=%u elapsed=%"PRIu64" duration=%"PRIu64"\n",
> -				  last_timestamp - first_timestamp,
> -				  (last_timestamp - first_timestamp) * oa_period,
> -				  fill_duration / 2);
> -again_1:
> -			oa_status = 0;
> -			while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == EINTR)
> -				;
> -			if (errno == EIO) {
> -				oa_status = get_stream_status(stream_fd);
> -				igt_debug("oa_status %#x\n", oa_status);
> -				igt_assert(!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW));
> -				goto again_1;
> -			}
> -			igt_assert_neq(len, -1);
> -
> -			for (int offset = 0; offset < len; offset += report_size) {
> -				uint32_t *report = (void *) (buf + offset);
> -
> -				igt_debug(" > report ts=%"PRIu64""
> -					  " ts_delta_last_periodic=%"PRIu64" is_timer=%i ctx_id=%8x nb_periodic=%u\n",
> -					  oa_timestamp(report, fmt),
> -					  n_periodic_reports > 0 ?  oa_timestamp_delta(report, last_periodic_report, fmt) : 0,
> -					  oa_report_is_periodic(report),
> -					  oa_report_get_ctx_id(report),
> -					  n_periodic_reports);
> -
> -				if (first_timestamp == 0)
> -					first_timestamp = oa_timestamp(report, fmt);
> -				last_timestamp = oa_timestamp(report, fmt);
> -
> -				if (oa_report_is_periodic(report)) {
> -					memcpy(last_periodic_report, report, report_size);
> -					n_periodic_reports++;
> -				}
> -			}
> -		}
> -
> -		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_DISABLE, 0);
> -
> -		igt_debug("first ts = %u, last ts = %u\n", first_timestamp, last_timestamp);
> +	/* OA buffer is disable, we do not expect any error status */

disabled

> +	oa_status = get_stream_status(stream_fd);
> +	overflow_seen = !!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW);

Don't need !!

> +	igt_assert_eq(overflow_seen, 0);
>
> -		igt_debug("%f < %zu < %f\n",
> -			  report_size * n_full_oa_reports * 0.45,
> -			  n_periodic_reports * report_size,
> -			  report_size * n_full_oa_reports * 0.55);
> +	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
>
> -		igt_assert(n_periodic_reports * report_size >
> -			   report_size * n_full_oa_reports * 0.45);
> -		igt_assert(n_periodic_reports * report_size <
> -			   report_size * n_full_oa_reports * 0.55);
> +	errno = 0;
> +	/* Read 0 bytes repeatedly until you see an EIO */
> +	while ((len = read(stream_fd, buf, 0)) == -1 && (errno == EINTR || errno == ENOSPC)) {
> +		usleep(100);
>	}
> +	igt_assert_eq(len, -1);
> +	igt_assert_eq(errno, EIO);
>
> -	free(last_periodic_report);
> -	free(buf);
> +	/* Ensure buffer overflowed */
> +	oa_status = get_stream_status(stream_fd);
> +	overflow_seen = !!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW);

Don't need !!

> +	igt_assert(overflow_seen);

Also I am wondering if we disabled the stream now using
DRM_XE_OBSERVATION_IOCTL_DISABLE, would it clear the overflow status? But
anyway the test is good as is.

>
>	__perf_close(stream_fd);
>  }

Apart from the above nits, this is:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

[PATCH 08/13] tests/intel/xe_oa: Use default buffer size for non-zero reason

[Umesh Nerlige Ramappa]

Use a default buffer size for non-zero-reason for and strip
out testing buffer size in the same test.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 14 ++++----------
 1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index fc03b74af..03d223df4 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -2447,7 +2447,7 @@ test_non_zero_reason(const struct drm_xe_engine_class_instance *hwe, size_t oa_b
 		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt),
 		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
 		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
-		DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE, oa_buffer_size,
+		DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE, oa_buffer_size ?: buffer_fill_size
 	};
 	struct intel_xe_oa_open_prop param = {
 		.num_properties = ARRAY_SIZE(properties) / 2,
@@ -4805,15 +4805,9 @@ igt_main
 		__for_one_hwe_in_oag(hwe)
 			test_buffer_fill(hwe);
 
-	igt_subtest_with_dynamic("non-zero-reason") {
-		if (oau->capabilities & DRM_XE_OA_CAPS_OA_BUFFER_SIZE) {
-			__for_one_hwe_in_oag_w_arg(hwe, "16M")
-				test_non_zero_reason(hwe, SZ_16M);
-		} else {
-			__for_one_hwe_in_oag_w_arg(hwe, "default")
-				test_non_zero_reason(hwe, 0);
-		}
-	}
+	igt_subtest_with_dynamic("non-zero-reason")
+		__for_one_hwe_in_oag(hwe)
+			test_non_zero_reason(hwe, 0);
 
 	igt_subtest("disabled-read-error")
 		test_disabled_read_error();
-- 
2.34.1

Re: [PATCH 08/13] tests/intel/xe_oa: Use default buffer size for non-zero reason

[Dixit, Ashutosh]

On Fri, 14 Feb 2025 17:06:23 -0800, Umesh Nerlige Ramappa wrote:
>
> Use a default buffer size for non-zero-reason for and strip
> out testing buffer size in the same test.

OK, this is cleaner:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/intel/xe_oa.c | 14 ++++----------
>  1 file changed, 4 insertions(+), 10 deletions(-)
>
> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> index fc03b74af..03d223df4 100644
> --- a/tests/intel/xe_oa.c
> +++ b/tests/intel/xe_oa.c
> @@ -2447,7 +2447,7 @@ test_non_zero_reason(const struct drm_xe_engine_class_instance *hwe, size_t oa_b
>		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt),
>		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
>		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
> -		DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE, oa_buffer_size,
> +		DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE, oa_buffer_size ?: buffer_fill_size
>	};
>	struct intel_xe_oa_open_prop param = {
>		.num_properties = ARRAY_SIZE(properties) / 2,
> @@ -4805,15 +4805,9 @@ igt_main
>		__for_one_hwe_in_oag(hwe)
>			test_buffer_fill(hwe);
>
> -	igt_subtest_with_dynamic("non-zero-reason") {
> -		if (oau->capabilities & DRM_XE_OA_CAPS_OA_BUFFER_SIZE) {
> -			__for_one_hwe_in_oag_w_arg(hwe, "16M")
> -				test_non_zero_reason(hwe, SZ_16M);
> -		} else {
> -			__for_one_hwe_in_oag_w_arg(hwe, "default")
> -				test_non_zero_reason(hwe, 0);
> -		}
> -	}
> +	igt_subtest_with_dynamic("non-zero-reason")
> +		__for_one_hwe_in_oag(hwe)
> +			test_non_zero_reason(hwe, 0);
>
>	igt_subtest("disabled-read-error")
>		test_disabled_read_error();
> --
> 2.34.1
>

[PATCH 09/13] tests/intel/xe_oa: Test oa buffer sizes

[Umesh Nerlige Ramappa]

Introduce oa buffer size test separately. Pick a random valid buffer
size for the test.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index 03d223df4..ee87b7338 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -93,6 +93,23 @@ struct accumulator {
 	uint64_t deltas[MAX_RAW_OA_COUNTERS];
 };
 
+struct oa_buf_size {
+	char name[12];
+	uint32_t size;
+} buf_sizes[] = {
+	{ "128K", SZ_128K },
+	{ "256K", SZ_256K },
+	{ "512K", SZ_512K },
+	{ "1M", SZ_1M },
+	{ "2M", SZ_2M },
+	{ "4M", SZ_4M },
+	{ "8M", SZ_8M },
+	{ "16M", SZ_16M },
+	{ "32M", SZ_32M },
+	{ "64M", SZ_64M },
+	{ "128M", SZ_128M },
+};
+
 /* OA unit types */
 enum {
 	OAG,
@@ -305,6 +322,7 @@ static struct intel_mmio_data mmio_data;
 static igt_render_copyfunc_t render_copy;
 static uint32_t rc_width, rc_height;
 static uint32_t buffer_fill_size;
+static uint32_t num_buf_sizes;
 
 static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
 {
@@ -1094,6 +1112,7 @@ init_sys_info(void)
 	rc_width = 1920;
 	rc_height = 1080;
 	buffer_fill_size = SZ_16M;
+	num_buf_sizes = ARRAY_SIZE(buf_sizes);
 	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
 
 	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
@@ -4805,6 +4824,17 @@ igt_main
 		__for_one_hwe_in_oag(hwe)
 			test_buffer_fill(hwe);
 
+	/**
+	 * SUBTEST: buffer-size
+	 * Description: Test various OA buffer sizes
+	 */
+	igt_subtest_with_dynamic("buffer-size") {
+		long k = random() % num_buf_sizes;
+
+		__for_one_hwe_in_oag_w_arg(hwe, buf_sizes[k].name)
+			test_non_zero_reason(hwe, buf_sizes[k].size);
+	}
+
 	igt_subtest_with_dynamic("non-zero-reason")
 		__for_one_hwe_in_oag(hwe)
 			test_non_zero_reason(hwe, 0);
-- 
2.34.1

Re: [PATCH 09/13] tests/intel/xe_oa: Test oa buffer sizes

[Dixit, Ashutosh]

On Fri, 14 Feb 2025 17:06:24 -0800, Umesh Nerlige Ramappa wrote:
>
> Introduce oa buffer size test separately. Pick a random valid buffer
> size for the test.
>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/intel/xe_oa.c | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
>
> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> index 03d223df4..ee87b7338 100644
> --- a/tests/intel/xe_oa.c
> +++ b/tests/intel/xe_oa.c
> @@ -93,6 +93,23 @@ struct accumulator {
>	uint64_t deltas[MAX_RAW_OA_COUNTERS];
>  };
>
> +struct oa_buf_size {
> +	char name[12];
> +	uint32_t size;
> +} buf_sizes[] = {
> +	{ "128K", SZ_128K },
> +	{ "256K", SZ_256K },
> +	{ "512K", SZ_512K },
> +	{ "1M", SZ_1M },
> +	{ "2M", SZ_2M },
> +	{ "4M", SZ_4M },
> +	{ "8M", SZ_8M },
> +	{ "16M", SZ_16M },
> +	{ "32M", SZ_32M },
> +	{ "64M", SZ_64M },
> +	{ "128M", SZ_128M },

Would you have the running time for these? Hopefully not too huge for the
large buffer sizes, even if we are running just one of them? And what about
slower platforms?

That was the reason we restricted OA buffer size to just 16 M.

This is what I measured here:

https://patchwork.freedesktop.org/patch/627269/?series=142128&rev=1

	$ sudo ./build/tests/xe_oa --r oa-buffer-size
	IGT-Version: 1.29-g724fd0b79 (x86_64) (Linux: 6.12.0-rc4+ x86_64)
	Using IGT_SRANDOM=1733459091 for randomisation
	Opened device: /dev/dri/card0
	Starting subtest: oa-buffer-size
	Starting dynamic subtest: 8MB
	Dynamic subtest 8MB: SUCCESS (0.403s)
	Starting dynamic subtest: 32MB
	Dynamic subtest 32MB: SUCCESS (1.595s)
	Starting dynamic subtest: 128MB
	Dynamic subtest 128MB: SUCCESS (6.326s)
	Subtest oa-buffer-size: SUCCESS (8.324s)

> +};
> +
>  /* OA unit types */
>  enum {
>	OAG,
> @@ -305,6 +322,7 @@ static struct intel_mmio_data mmio_data;
>  static igt_render_copyfunc_t render_copy;
>  static uint32_t rc_width, rc_height;
>  static uint32_t buffer_fill_size;
> +static uint32_t num_buf_sizes;
>
>  static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
>  {
> @@ -1094,6 +1112,7 @@ init_sys_info(void)
>	rc_width = 1920;
>	rc_height = 1080;
>	buffer_fill_size = SZ_16M;
> +	num_buf_sizes = ARRAY_SIZE(buf_sizes);
>	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
>
>	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
> @@ -4805,6 +4824,17 @@ igt_main
>		__for_one_hwe_in_oag(hwe)
>			test_buffer_fill(hwe);
>
> +	/**
> +	 * SUBTEST: buffer-size
> +	 * Description: Test various OA buffer sizes
> +	 */
> +	igt_subtest_with_dynamic("buffer-size") {
> +		long k = random() % num_buf_sizes;
> +
> +		__for_one_hwe_in_oag_w_arg(hwe, buf_sizes[k].name)
> +			test_non_zero_reason(hwe, buf_sizes[k].size);
> +	}
> +
>	igt_subtest_with_dynamic("non-zero-reason")
>		__for_one_hwe_in_oag(hwe)
>			test_non_zero_reason(hwe, 0);
> --
> 2.34.1
>

Re: [PATCH 09/13] tests/intel/xe_oa: Test oa buffer sizes

[Dixit, Ashutosh]

On Tue, 18 Feb 2025 10:34:53 -0800, Dixit, Ashutosh wrote:
>
> On Fri, 14 Feb 2025 17:06:24 -0800, Umesh Nerlige Ramappa wrote:
> >
> > Introduce oa buffer size test separately. Pick a random valid buffer
> > size for the test.
> >
> > Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> > ---
> >  tests/intel/xe_oa.c | 30 ++++++++++++++++++++++++++++++
> >  1 file changed, 30 insertions(+)
> >
> > diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> > index 03d223df4..ee87b7338 100644
> > --- a/tests/intel/xe_oa.c
> > +++ b/tests/intel/xe_oa.c
> > @@ -93,6 +93,23 @@ struct accumulator {
> >	uint64_t deltas[MAX_RAW_OA_COUNTERS];
> >  };
> >
> > +struct oa_buf_size {
> > +	char name[12];
> > +	uint32_t size;
> > +} buf_sizes[] = {
> > +	{ "128K", SZ_128K },
> > +	{ "256K", SZ_256K },
> > +	{ "512K", SZ_512K },
> > +	{ "1M", SZ_1M },
> > +	{ "2M", SZ_2M },
> > +	{ "4M", SZ_4M },
> > +	{ "8M", SZ_8M },
> > +	{ "16M", SZ_16M },
> > +	{ "32M", SZ_32M },
> > +	{ "64M", SZ_64M },
> > +	{ "128M", SZ_128M },
>
> Would you have the running time for these? Hopefully not too huge for the
> large buffer sizes, even if we are running just one of them? And what about
> slower platforms?
>
> That was the reason we restricted OA buffer size to just 16 M.
>
> This is what I measured here:
>
> https://patchwork.freedesktop.org/patch/627269/?series=142128&rev=1
>
>	$ sudo ./build/tests/xe_oa --r oa-buffer-size
>	IGT-Version: 1.29-g724fd0b79 (x86_64) (Linux: 6.12.0-rc4+ x86_64)
>	Using IGT_SRANDOM=1733459091 for randomisation
>	Opened device: /dev/dri/card0
>	Starting subtest: oa-buffer-size
>	Starting dynamic subtest: 8MB
>	Dynamic subtest 8MB: SUCCESS (0.403s)
>	Starting dynamic subtest: 32MB
>	Dynamic subtest 32MB: SUCCESS (1.595s)
>	Starting dynamic subtest: 128MB
>	Dynamic subtest 128MB: SUCCESS (6.326s)
>	Subtest oa-buffer-size: SUCCESS (8.324s)

Also iirc the 32 MB size kept failing because of the reason being zero HW
bug:

https://patchwork.freedesktop.org/patch/632685/?series=142128&rev=2


>
> > +};
> > +
> >  /* OA unit types */
> >  enum {
> >	OAG,
> > @@ -305,6 +322,7 @@ static struct intel_mmio_data mmio_data;
> >  static igt_render_copyfunc_t render_copy;
> >  static uint32_t rc_width, rc_height;
> >  static uint32_t buffer_fill_size;
> > +static uint32_t num_buf_sizes;
> >
> >  static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
> >  {
> > @@ -1094,6 +1112,7 @@ init_sys_info(void)
> >	rc_width = 1920;
> >	rc_height = 1080;
> >	buffer_fill_size = SZ_16M;
> > +	num_buf_sizes = ARRAY_SIZE(buf_sizes);
> >	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
> >
> >	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
> > @@ -4805,6 +4824,17 @@ igt_main
> >		__for_one_hwe_in_oag(hwe)
> >			test_buffer_fill(hwe);
> >
> > +	/**
> > +	 * SUBTEST: buffer-size
> > +	 * Description: Test various OA buffer sizes
> > +	 */
> > +	igt_subtest_with_dynamic("buffer-size") {
> > +		long k = random() % num_buf_sizes;
> > +
> > +		__for_one_hwe_in_oag_w_arg(hwe, buf_sizes[k].name)
> > +			test_non_zero_reason(hwe, buf_sizes[k].size);
> > +	}
> > +
> >	igt_subtest_with_dynamic("non-zero-reason")
> >		__for_one_hwe_in_oag(hwe)
> >			test_non_zero_reason(hwe, 0);
> > --
> > 2.34.1
> >

Re: [PATCH 09/13] tests/intel/xe_oa: Test oa buffer sizes

[Umesh Nerlige Ramappa]

On Tue, Feb 18, 2025 at 10:34:53AM -0800, Dixit, Ashutosh wrote:
>On Fri, 14 Feb 2025 17:06:24 -0800, Umesh Nerlige Ramappa wrote:
>>
>> Introduce oa buffer size test separately. Pick a random valid buffer
>> size for the test.
>>
>> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> ---
>>  tests/intel/xe_oa.c | 30 ++++++++++++++++++++++++++++++
>>  1 file changed, 30 insertions(+)
>>
>> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
>> index 03d223df4..ee87b7338 100644
>> --- a/tests/intel/xe_oa.c
>> +++ b/tests/intel/xe_oa.c
>> @@ -93,6 +93,23 @@ struct accumulator {
>>	uint64_t deltas[MAX_RAW_OA_COUNTERS];
>>  };
>>
>> +struct oa_buf_size {
>> +	char name[12];
>> +	uint32_t size;
>> +} buf_sizes[] = {
>> +	{ "128K", SZ_128K },
>> +	{ "256K", SZ_256K },
>> +	{ "512K", SZ_512K },
>> +	{ "1M", SZ_1M },
>> +	{ "2M", SZ_2M },
>> +	{ "4M", SZ_4M },
>> +	{ "8M", SZ_8M },
>> +	{ "16M", SZ_16M },
>> +	{ "32M", SZ_32M },
>> +	{ "64M", SZ_64M },
>> +	{ "128M", SZ_128M },
>
>Would you have the running time for these? Hopefully not too huge for the
>large buffer sizes, even if we are running just one of them? And what about
>slower platforms?
>
>That was the reason we restricted OA buffer size to just 16 M.
>
>This is what I measured here:
>
>https://patchwork.freedesktop.org/patch/627269/?series=142128&rev=1
>
>	$ sudo ./build/tests/xe_oa --r oa-buffer-size
>	IGT-Version: 1.29-g724fd0b79 (x86_64) (Linux: 6.12.0-rc4+ x86_64)
>	Using IGT_SRANDOM=1733459091 for randomisation
>	Opened device: /dev/dri/card0
>	Starting subtest: oa-buffer-size
>	Starting dynamic subtest: 8MB
>	Dynamic subtest 8MB: SUCCESS (0.403s)
>	Starting dynamic subtest: 32MB
>	Dynamic subtest 32MB: SUCCESS (1.595s)
>	Starting dynamic subtest: 128MB
>	Dynamic subtest 128MB: SUCCESS (6.326s)
>	Subtest oa-buffer-size: SUCCESS (8.324s)

I can run 128MB and see how long it takes. I guess I didn't hit the 
larger buffers on random runs.  Technically around 30 seconds for 128MB 
buffer with 20us period and a 256 byte report. If report is 576 bytes, 
then 13 seconds. As long as it falls within the IGT timeout period, we 
should be good.

Thanks,
Umesh


>
>> +};
>> +
>>  /* OA unit types */
>>  enum {
>>	OAG,
>> @@ -305,6 +322,7 @@ static struct intel_mmio_data mmio_data;
>>  static igt_render_copyfunc_t render_copy;
>>  static uint32_t rc_width, rc_height;
>>  static uint32_t buffer_fill_size;
>> +static uint32_t num_buf_sizes;
>>
>>  static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
>>  {
>> @@ -1094,6 +1112,7 @@ init_sys_info(void)
>>	rc_width = 1920;
>>	rc_height = 1080;
>>	buffer_fill_size = SZ_16M;
>> +	num_buf_sizes = ARRAY_SIZE(buf_sizes);
>>	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
>>
>>	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
>> @@ -4805,6 +4824,17 @@ igt_main
>>		__for_one_hwe_in_oag(hwe)
>>			test_buffer_fill(hwe);
>>
>> +	/**
>> +	 * SUBTEST: buffer-size
>> +	 * Description: Test various OA buffer sizes
>> +	 */
>> +	igt_subtest_with_dynamic("buffer-size") {
>> +		long k = random() % num_buf_sizes;
>> +
>> +		__for_one_hwe_in_oag_w_arg(hwe, buf_sizes[k].name)
>> +			test_non_zero_reason(hwe, buf_sizes[k].size);
>> +	}
>> +
>>	igt_subtest_with_dynamic("non-zero-reason")
>>		__for_one_hwe_in_oag(hwe)
>>			test_non_zero_reason(hwe, 0);
>> --
>> 2.34.1
>>

Re: [PATCH 09/13] tests/intel/xe_oa: Test oa buffer sizes

[Dixit, Ashutosh]

On Tue, 18 Feb 2025 10:44:54 -0800, Umesh Nerlige Ramappa wrote:
>

Hi Umesh,

> On Tue, Feb 18, 2025 at 10:34:53AM -0800, Dixit, Ashutosh wrote:
> > On Fri, 14 Feb 2025 17:06:24 -0800, Umesh Nerlige Ramappa wrote:
> >>
> >> Introduce oa buffer size test separately. Pick a random valid buffer
> >> size for the test.
> >>
> >> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> >> ---
> >>  tests/intel/xe_oa.c | 30 ++++++++++++++++++++++++++++++
> >>  1 file changed, 30 insertions(+)
> >>
> >> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> >> index 03d223df4..ee87b7338 100644
> >> --- a/tests/intel/xe_oa.c
> >> +++ b/tests/intel/xe_oa.c
> >> @@ -93,6 +93,23 @@ struct accumulator {
> >>	uint64_t deltas[MAX_RAW_OA_COUNTERS];
> >>  };
> >>
> >> +struct oa_buf_size {
> >> +	char name[12];
> >> +	uint32_t size;
> >> +} buf_sizes[] = {
> >> +	{ "128K", SZ_128K },
> >> +	{ "256K", SZ_256K },
> >> +	{ "512K", SZ_512K },
> >> +	{ "1M", SZ_1M },
> >> +	{ "2M", SZ_2M },
> >> +	{ "4M", SZ_4M },
> >> +	{ "8M", SZ_8M },
> >> +	{ "16M", SZ_16M },
> >> +	{ "32M", SZ_32M },
> >> +	{ "64M", SZ_64M },
> >> +	{ "128M", SZ_128M },
> >
> > Would you have the running time for these? Hopefully not too huge for the
> > large buffer sizes, even if we are running just one of them? And what about
> > slower platforms?
> >
> > That was the reason we restricted OA buffer size to just 16 M.
> >
> > This is what I measured here:
> >
> > https://patchwork.freedesktop.org/patch/627269/?series=142128&rev=1
> >
> >	$ sudo ./build/tests/xe_oa --r oa-buffer-size
> >	IGT-Version: 1.29-g724fd0b79 (x86_64) (Linux: 6.12.0-rc4+ x86_64)
> >	Using IGT_SRANDOM=1733459091 for randomisation
> >	Opened device: /dev/dri/card0
> >	Starting subtest: oa-buffer-size
> >	Starting dynamic subtest: 8MB
> >	Dynamic subtest 8MB: SUCCESS (0.403s)
> >	Starting dynamic subtest: 32MB
> >	Dynamic subtest 32MB: SUCCESS (1.595s)
> >	Starting dynamic subtest: 128MB
> >	Dynamic subtest 128MB: SUCCESS (6.326s)
> >	Subtest oa-buffer-size: SUCCESS (8.324s)
>
> I can run 128MB and see how long it takes. I guess I didn't hit the larger
> buffers on random runs.  Technically around 30 seconds for 128MB buffer
> with 20us period and a 256 byte report. If report is 576 bytes, then 13
> seconds. As long as it falls within the IGT timeout period, we should be
> good.

To do a quick regression test I frequently just run the OA tests locally
with:

	sudo ./build/tests/xe_oa

So I don't care how long CI takes to run the tests, but for me I want the
each test to finish in ~3 seconds tops.

Though in this case, on LNL:

	$ sudo ./build/tests/xe_oa --r buffer-size
	IGT-Version: 1.30-g71d723c60 (x86_64) (Linux: 6.13.0+ x86_64)
	Using IGT_SRANDOM=1740181681 for randomisation
	Opened device: /dev/dri/card0
	Starting subtest: buffer-size
	Starting dynamic subtest: ccs-0-128M
	Dynamic subtest ccs-0-128M: SUCCESS (2.959s)
	Subtest buffer-size: SUCCESS (2.959s)

This seems to meet the 3 seconds criteria so it's ok.

The big outlier is this one:

	$ sudo ./build/tests/xe_oa --r buffer-fill
	IGT-Version: 1.30-g71d723c60 (x86_64) (Linux: 6.13.0+ x86_64)
	Using IGT_SRANDOM=1740182998 for randomisation
	Opened device: /dev/dri/card0
	Starting subtest: buffer-fill
	Starting dynamic subtest: ccs-0
	Dynamic subtest ccs-0: SUCCESS (24.869s)
	Subtest buffer-fill: SUCCESS (24.869s)

which is definitely not ok and would need a respin.

Anyway I should have other comments on the patches too, so wait for my
review comments before posting a new revision.

Thanks.
--
Ashutosh


>
> >
> >> +};
> >> +
> >>  /* OA unit types */
> >>  enum {
> >>	OAG,
> >> @@ -305,6 +322,7 @@ static struct intel_mmio_data mmio_data;
> >>  static igt_render_copyfunc_t render_copy;
> >>  static uint32_t rc_width, rc_height;
> >>  static uint32_t buffer_fill_size;
> >> +static uint32_t num_buf_sizes;
> >>
> >>  static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
> >>  {
> >> @@ -1094,6 +1112,7 @@ init_sys_info(void)
> >>	rc_width = 1920;
> >>	rc_height = 1080;
> >>	buffer_fill_size = SZ_16M;
> >> +	num_buf_sizes = ARRAY_SIZE(buf_sizes);
> >>	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
> >>
> >>	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
> >> @@ -4805,6 +4824,17 @@ igt_main
> >>		__for_one_hwe_in_oag(hwe)
> >>			test_buffer_fill(hwe);
> >>
> >> +	/**
> >> +	 * SUBTEST: buffer-size
> >> +	 * Description: Test various OA buffer sizes
> >> +	 */
> >> +	igt_subtest_with_dynamic("buffer-size") {
> >> +		long k = random() % num_buf_sizes;
> >> +
> >> +		__for_one_hwe_in_oag_w_arg(hwe, buf_sizes[k].name)
> >> +			test_non_zero_reason(hwe, buf_sizes[k].size);
> >> +	}
> >> +
> >>	igt_subtest_with_dynamic("non-zero-reason")
> >>		__for_one_hwe_in_oag(hwe)
> >>			test_non_zero_reason(hwe, 0);
> >> --
> >> 2.34.1
> >>

Re: [PATCH 09/13] tests/intel/xe_oa: Test oa buffer sizes

[Umesh Nerlige Ramappa]

On Fri, Feb 21, 2025 at 04:13:31PM -0800, Dixit, Ashutosh wrote:
>On Tue, 18 Feb 2025 10:44:54 -0800, Umesh Nerlige Ramappa wrote:
>>
>
>Hi Umesh,
>
>> On Tue, Feb 18, 2025 at 10:34:53AM -0800, Dixit, Ashutosh wrote:
>> > On Fri, 14 Feb 2025 17:06:24 -0800, Umesh Nerlige Ramappa wrote:
>> >>
>> >> Introduce oa buffer size test separately. Pick a random valid buffer
>> >> size for the test.
>> >>
>> >> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> >> ---
>> >>  tests/intel/xe_oa.c | 30 ++++++++++++++++++++++++++++++
>> >>  1 file changed, 30 insertions(+)
>> >>
>> >> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
>> >> index 03d223df4..ee87b7338 100644
>> >> --- a/tests/intel/xe_oa.c
>> >> +++ b/tests/intel/xe_oa.c
>> >> @@ -93,6 +93,23 @@ struct accumulator {
>> >>	uint64_t deltas[MAX_RAW_OA_COUNTERS];
>> >>  };
>> >>
>> >> +struct oa_buf_size {
>> >> +	char name[12];
>> >> +	uint32_t size;
>> >> +} buf_sizes[] = {
>> >> +	{ "128K", SZ_128K },
>> >> +	{ "256K", SZ_256K },
>> >> +	{ "512K", SZ_512K },
>> >> +	{ "1M", SZ_1M },
>> >> +	{ "2M", SZ_2M },
>> >> +	{ "4M", SZ_4M },
>> >> +	{ "8M", SZ_8M },
>> >> +	{ "16M", SZ_16M },
>> >> +	{ "32M", SZ_32M },
>> >> +	{ "64M", SZ_64M },
>> >> +	{ "128M", SZ_128M },
>> >
>> > Would you have the running time for these? Hopefully not too huge for the
>> > large buffer sizes, even if we are running just one of them? And what about
>> > slower platforms?
>> >
>> > That was the reason we restricted OA buffer size to just 16 M.
>> >
>> > This is what I measured here:
>> >
>> > https://patchwork.freedesktop.org/patch/627269/?series=142128&rev=1
>> >
>> >	$ sudo ./build/tests/xe_oa --r oa-buffer-size
>> >	IGT-Version: 1.29-g724fd0b79 (x86_64) (Linux: 6.12.0-rc4+ x86_64)
>> >	Using IGT_SRANDOM=1733459091 for randomisation
>> >	Opened device: /dev/dri/card0
>> >	Starting subtest: oa-buffer-size
>> >	Starting dynamic subtest: 8MB
>> >	Dynamic subtest 8MB: SUCCESS (0.403s)
>> >	Starting dynamic subtest: 32MB
>> >	Dynamic subtest 32MB: SUCCESS (1.595s)
>> >	Starting dynamic subtest: 128MB
>> >	Dynamic subtest 128MB: SUCCESS (6.326s)
>> >	Subtest oa-buffer-size: SUCCESS (8.324s)
>>
>> I can run 128MB and see how long it takes. I guess I didn't hit the larger
>> buffers on random runs.  Technically around 30 seconds for 128MB buffer
>> with 20us period and a 256 byte report. If report is 576 bytes, then 13
>> seconds. As long as it falls within the IGT timeout period, we should be
>> good.
>
>To do a quick regression test I frequently just run the OA tests locally
>with:
>
>	sudo ./build/tests/xe_oa
>
>So I don't care how long CI takes to run the tests, but for me I want the
>each test to finish in ~3 seconds tops.
>
>Though in this case, on LNL:
>
>	$ sudo ./build/tests/xe_oa --r buffer-size
>	IGT-Version: 1.30-g71d723c60 (x86_64) (Linux: 6.13.0+ x86_64)
>	Using IGT_SRANDOM=1740181681 for randomisation
>	Opened device: /dev/dri/card0
>	Starting subtest: buffer-size
>	Starting dynamic subtest: ccs-0-128M
>	Dynamic subtest ccs-0-128M: SUCCESS (2.959s)
>	Subtest buffer-size: SUCCESS (2.959s)
>
>This seems to meet the 3 seconds criteria so it's ok.
>
>The big outlier is this one:
>
>	$ sudo ./build/tests/xe_oa --r buffer-fill
>	IGT-Version: 1.30-g71d723c60 (x86_64) (Linux: 6.13.0+ x86_64)
>	Using IGT_SRANDOM=1740182998 for randomisation
>	Opened device: /dev/dri/card0
>	Starting subtest: buffer-fill
>	Starting dynamic subtest: ccs-0
>	Dynamic subtest ccs-0: SUCCESS (24.869s)
>	Subtest buffer-fill: SUCCESS (24.869s)
>
>which is definitely not ok and would need a respin.

ok, it looks like for Xe you have reduced the test times drastically. I 
did not consider that. I was just focusing on making the tests uniform 
in terms of the exponent used.

Maybe I will just use the simulation exponent (1000ns) for the tests 
that need to run fast so their implementation stays the same.

Thanks,
Umesh

>
>Anyway I should have other comments on the patches too, so wait for my
>review comments before posting a new revision.
>
>Thanks.
>--
>Ashutosh
>
>
>>
>> >
>> >> +};
>> >> +
>> >>  /* OA unit types */
>> >>  enum {
>> >>	OAG,
>> >> @@ -305,6 +322,7 @@ static struct intel_mmio_data mmio_data;
>> >>  static igt_render_copyfunc_t render_copy;
>> >>  static uint32_t rc_width, rc_height;
>> >>  static uint32_t buffer_fill_size;
>> >> +static uint32_t num_buf_sizes;
>> >>
>> >>  static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
>> >>  {
>> >> @@ -1094,6 +1112,7 @@ init_sys_info(void)
>> >>	rc_width = 1920;
>> >>	rc_height = 1080;
>> >>	buffer_fill_size = SZ_16M;
>> >> +	num_buf_sizes = ARRAY_SIZE(buf_sizes);
>> >>	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
>> >>
>> >>	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
>> >> @@ -4805,6 +4824,17 @@ igt_main
>> >>		__for_one_hwe_in_oag(hwe)
>> >>			test_buffer_fill(hwe);
>> >>
>> >> +	/**
>> >> +	 * SUBTEST: buffer-size
>> >> +	 * Description: Test various OA buffer sizes
>> >> +	 */
>> >> +	igt_subtest_with_dynamic("buffer-size") {
>> >> +		long k = random() % num_buf_sizes;
>> >> +
>> >> +		__for_one_hwe_in_oag_w_arg(hwe, buf_sizes[k].name)
>> >> +			test_non_zero_reason(hwe, buf_sizes[k].size);
>> >> +	}
>> >> +
>> >>	igt_subtest_with_dynamic("non-zero-reason")
>> >>		__for_one_hwe_in_oag(hwe)
>> >>			test_non_zero_reason(hwe, 0);
>> >> --
>> >> 2.34.1
>> >>

Re: [PATCH 09/13] tests/intel/xe_oa: Test oa buffer sizes

[Dixit, Ashutosh]

On Fri, 14 Feb 2025 17:06:24 -0800, Umesh Nerlige Ramappa wrote:
>
> Introduce oa buffer size test separately. Pick a random valid buffer
> size for the test.

As discussed, all execution times are under 3 seconds, so ok. Or, to be
safe we could trim 64 M and 128 M sizes from the array.

Either case this is:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/intel/xe_oa.c | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
>
> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> index 03d223df4..ee87b7338 100644
> --- a/tests/intel/xe_oa.c
> +++ b/tests/intel/xe_oa.c
> @@ -93,6 +93,23 @@ struct accumulator {
>	uint64_t deltas[MAX_RAW_OA_COUNTERS];
>  };
>
> +struct oa_buf_size {
> +	char name[12];
> +	uint32_t size;
> +} buf_sizes[] = {
> +	{ "128K", SZ_128K },
> +	{ "256K", SZ_256K },
> +	{ "512K", SZ_512K },
> +	{ "1M", SZ_1M },
> +	{ "2M", SZ_2M },
> +	{ "4M", SZ_4M },
> +	{ "8M", SZ_8M },
> +	{ "16M", SZ_16M },
> +	{ "32M", SZ_32M },
> +	{ "64M", SZ_64M },
> +	{ "128M", SZ_128M },
> +};
> +
>  /* OA unit types */
>  enum {
>	OAG,
> @@ -305,6 +322,7 @@ static struct intel_mmio_data mmio_data;
>  static igt_render_copyfunc_t render_copy;
>  static uint32_t rc_width, rc_height;
>  static uint32_t buffer_fill_size;
> +static uint32_t num_buf_sizes;
>
>  static struct intel_xe_perf_metric_set *metric_set(const struct drm_xe_engine_class_instance *hwe)
>  {
> @@ -1094,6 +1112,7 @@ init_sys_info(void)
>	rc_width = 1920;
>	rc_height = 1080;
>	buffer_fill_size = SZ_16M;
> +	num_buf_sizes = ARRAY_SIZE(buf_sizes);
>	oa_exponent_default = max_oa_exponent_for_period_lte(1000000);
>
>	default_oa_buffer_size = get_default_oa_buffer_size(drm_fd);
> @@ -4805,6 +4824,17 @@ igt_main
>		__for_one_hwe_in_oag(hwe)
>			test_buffer_fill(hwe);
>
> +	/**
> +	 * SUBTEST: buffer-size
> +	 * Description: Test various OA buffer sizes
> +	 */
> +	igt_subtest_with_dynamic("buffer-size") {
> +		long k = random() % num_buf_sizes;
> +
> +		__for_one_hwe_in_oag_w_arg(hwe, buf_sizes[k].name)
> +			test_non_zero_reason(hwe, buf_sizes[k].size);
> +	}
> +
>	igt_subtest_with_dynamic("non-zero-reason")
>		__for_one_hwe_in_oag(hwe)
>			test_non_zero_reason(hwe, 0);
> --
> 2.34.1
>

[PATCH 10/13] tests/intel/xe_oa: Rewrite enable-disable test

[Umesh Nerlige Ramappa]

Keep it simple and just check if enable/disable is working correctly
using mmio.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 129 +++++---------------------------------------
 1 file changed, 13 insertions(+), 116 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index ee87b7338..c6c1c2358 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -2534,21 +2534,13 @@ test_non_zero_reason(const struct drm_xe_engine_class_instance *hwe, size_t oa_b
 static void
 test_enable_disable(const struct drm_xe_engine_class_instance *hwe)
 {
-	/* ~5 micro second period */
-	int oa_exponent = max_oa_exponent_for_period_lte(5000);
-	uint64_t oa_period = oa_exponent_to_ns(oa_exponent);
 	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
-	uint64_t fmt = test_set->perf_oa_format;
 	uint64_t properties[] = {
 		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
-
-		/* Include OA reports in samples */
 		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
-
-		/* OA unit configuration */
 		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
-		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt),
-		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
+		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
+		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
 		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
 		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
 	};
@@ -2556,123 +2548,28 @@ test_enable_disable(const struct drm_xe_engine_class_instance *hwe)
 		.num_properties = ARRAY_SIZE(properties) / 2,
 		.properties_ptr = to_user_pointer(properties),
 	};
-	size_t report_size = get_oa_format(fmt).size;
-	int buf_size = 65536 * report_size;
-	uint8_t *buf = malloc(buf_size);
-	int n_full_oa_reports = default_oa_buffer_size / report_size;
-	uint64_t fill_duration = n_full_oa_reports * oa_period;
-	uint32_t *last_periodic_report = malloc(report_size);
-
-	load_helper_init();
-	load_helper_run(HIGH);
+	u32 oacontrol;
 
 	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
         set_fd_flags(stream_fd, O_CLOEXEC);
 
-	for (int i = 0; i < 5; i++) {
-		int len;
-		uint32_t n_periodic_reports;
-		uint64_t first_timestamp = 0, last_timestamp = 0;
-		u32 oa_status;
-
-		/* Giving enough time for an overflow might help catch whether
-		 * the OA unit has been enabled even if the driver might at
-		 * least avoid copying reports while disabled.
-		 */
-		nanosleep(&(struct timespec){ .tv_sec = 0,
-					      .tv_nsec = fill_duration * 1.25 },
-			  NULL);
-
-		while ((len = read(stream_fd, buf, buf_size)) == -1 &&
-		       (errno == EINTR || errno == EIO))
-			;
-
-		igt_assert_eq(len, -1);
-		igt_assert_eq(errno, EINVAL);
-
-		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
+#define OAG_OACONTROL	(0xdaf4)
+#define  OAG_OACONTROL_OA_COUNTER_ENABLE	(1 << 0)
 
-		nanosleep(&(struct timespec){ .tv_sec = 0,
-					      .tv_nsec = fill_duration / 2 },
-			NULL);
-
-		n_periodic_reports = 0;
-
-		/* Because of the race condition between notification of new
-		 * reports and reports landing in memory, we need to rely on
-		 * timestamps to figure whether we've read enough of them.
-		 */
-		while (((last_timestamp - first_timestamp) * oa_period) < (fill_duration / 2)) {
-
-			while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == EINTR)
-				;
-			if (errno == EIO) {
-				oa_status = get_stream_status(stream_fd);
-				igt_debug("oa_status %#x\n", oa_status);
-				igt_assert(!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW));
-				continue;
-			}
-			igt_assert_neq(len, -1);
-
-			for (int offset = 0; offset < len; offset += report_size) {
-				uint32_t *report = (void *) (buf + offset);
-
-				if (first_timestamp == 0)
-					first_timestamp = oa_timestamp(report, fmt);
-				last_timestamp = oa_timestamp(report, fmt);
-
-				igt_debug(" > report ts=%"PRIx64""
-					  " ts_delta_last_periodic=%s%"PRIu64""
-					  " is_timer=%i ctx_id=0x%8x\n",
-					  oa_timestamp(report, fmt),
-					  oa_report_is_periodic(report) ? " " : "*",
-					  n_periodic_reports > 0 ?  oa_timestamp_delta(report, last_periodic_report, fmt) : 0,
-					  oa_report_is_periodic(report),
-					  oa_report_get_ctx_id(report));
-
-				if (oa_report_is_periodic(report)) {
-					memcpy(last_periodic_report, report, report_size);
-
-					/* We want to measure only the periodic reports,
-					 * ctx-switch might inflate the content of the
-					 * buffer and skew or measurement.
-					 */
-					n_periodic_reports++;
-				}
-			}
-		}
-
-		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_DISABLE, 0);
-
-		igt_debug("first ts = %"PRIu64", last ts = %"PRIu64"\n", first_timestamp, last_timestamp);
-
-		igt_debug("%f < %zu < %f\n",
-			  report_size * n_full_oa_reports * 0.45,
-			  n_periodic_reports * report_size,
-			  report_size * n_full_oa_reports * 0.55);
-
-		igt_assert((n_periodic_reports * report_size) >
-			   (report_size * n_full_oa_reports * 0.45));
-		igt_assert((n_periodic_reports * report_size) <
-			   report_size * n_full_oa_reports * 0.55);
+	intel_register_access_init(&mmio_data,
+				   igt_device_get_pci_device(drm_fd), 0);
 
+	oacontrol = intel_register_read(&mmio_data, OAG_OACONTROL);
+	igt_assert_eq(oacontrol & OAG_OACONTROL_OA_COUNTER_ENABLE, 0);
 
-		/* It's considered an error to read a stream while it's disabled
-		 * since it would block indefinitely...
-		 */
-		len = read(stream_fd, buf, buf_size);
+	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
 
-		igt_assert_eq(len, -1);
-		igt_assert_eq(errno, EINVAL);
-	}
+	oacontrol = intel_register_read(&mmio_data, OAG_OACONTROL);
 
-	free(last_periodic_report);
-	free(buf);
+	igt_assert_eq(oacontrol & OAG_OACONTROL_OA_COUNTER_ENABLE, 1);
 
+	intel_register_access_fini(&mmio_data);
 	__perf_close(stream_fd);
-
-	load_helper_stop();
-	load_helper_fini();
 }
 
 /**
-- 
2.34.1

Re: [PATCH 10/13] tests/intel/xe_oa: Rewrite enable-disable test

[Dixit, Ashutosh]

On Fri, 14 Feb 2025 17:06:25 -0800, Umesh Nerlige Ramappa wrote:
>
> Keep it simple and just check if enable/disable is working correctly
> using mmio.
>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/intel/xe_oa.c | 129 +++++---------------------------------------
>  1 file changed, 13 insertions(+), 116 deletions(-)
>
> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> index ee87b7338..c6c1c2358 100644
> --- a/tests/intel/xe_oa.c
> +++ b/tests/intel/xe_oa.c
> @@ -2534,21 +2534,13 @@ test_non_zero_reason(const struct drm_xe_engine_class_instance *hwe, size_t oa_b
>  static void
>  test_enable_disable(const struct drm_xe_engine_class_instance *hwe)
>  {
> -	/* ~5 micro second period */
> -	int oa_exponent = max_oa_exponent_for_period_lte(5000);
> -	uint64_t oa_period = oa_exponent_to_ns(oa_exponent);
>	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
> -	uint64_t fmt = test_set->perf_oa_format;
>	uint64_t properties[] = {
>		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
> -
> -		/* Include OA reports in samples */
>		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
> -
> -		/* OA unit configuration */
>		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
> -		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt),
> -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
> +		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
> +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
>		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
>	};
> @@ -2556,123 +2548,28 @@ test_enable_disable(const struct drm_xe_engine_class_instance *hwe)
>		.num_properties = ARRAY_SIZE(properties) / 2,
>		.properties_ptr = to_user_pointer(properties),
>	};
> -	size_t report_size = get_oa_format(fmt).size;
> -	int buf_size = 65536 * report_size;
> -	uint8_t *buf = malloc(buf_size);
> -	int n_full_oa_reports = default_oa_buffer_size / report_size;
> -	uint64_t fill_duration = n_full_oa_reports * oa_period;
> -	uint32_t *last_periodic_report = malloc(report_size);
> -
> -	load_helper_init();
> -	load_helper_run(HIGH);
> +	u32 oacontrol;
>
>	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
>          set_fd_flags(stream_fd, O_CLOEXEC);
>
> -	for (int i = 0; i < 5; i++) {
> -		int len;
> -		uint32_t n_periodic_reports;
> -		uint64_t first_timestamp = 0, last_timestamp = 0;
> -		u32 oa_status;
> -
> -		/* Giving enough time for an overflow might help catch whether
> -		 * the OA unit has been enabled even if the driver might at
> -		 * least avoid copying reports while disabled.
> -		 */
> -		nanosleep(&(struct timespec){ .tv_sec = 0,
> -					      .tv_nsec = fill_duration * 1.25 },
> -			  NULL);
> -
> -		while ((len = read(stream_fd, buf, buf_size)) == -1 &&
> -		       (errno == EINTR || errno == EIO))
> -			;
> -
> -		igt_assert_eq(len, -1);
> -		igt_assert_eq(errno, EINVAL);
> -
> -		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
> +#define OAG_OACONTROL	(0xdaf4)
> +#define  OAG_OACONTROL_OA_COUNTER_ENABLE	(1 << 0)
>
> -		nanosleep(&(struct timespec){ .tv_sec = 0,
> -					      .tv_nsec = fill_duration / 2 },
> -			NULL);
> -
> -		n_periodic_reports = 0;
> -
> -		/* Because of the race condition between notification of new
> -		 * reports and reports landing in memory, we need to rely on
> -		 * timestamps to figure whether we've read enough of them.
> -		 */
> -		while (((last_timestamp - first_timestamp) * oa_period) < (fill_duration / 2)) {
> -
> -			while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == EINTR)
> -				;
> -			if (errno == EIO) {
> -				oa_status = get_stream_status(stream_fd);
> -				igt_debug("oa_status %#x\n", oa_status);
> -				igt_assert(!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW));
> -				continue;
> -			}
> -			igt_assert_neq(len, -1);
> -
> -			for (int offset = 0; offset < len; offset += report_size) {
> -				uint32_t *report = (void *) (buf + offset);
> -
> -				if (first_timestamp == 0)
> -					first_timestamp = oa_timestamp(report, fmt);
> -				last_timestamp = oa_timestamp(report, fmt);
> -
> -				igt_debug(" > report ts=%"PRIx64""
> -					  " ts_delta_last_periodic=%s%"PRIu64""
> -					  " is_timer=%i ctx_id=0x%8x\n",
> -					  oa_timestamp(report, fmt),
> -					  oa_report_is_periodic(report) ? " " : "*",
> -					  n_periodic_reports > 0 ?  oa_timestamp_delta(report, last_periodic_report, fmt) : 0,
> -					  oa_report_is_periodic(report),
> -					  oa_report_get_ctx_id(report));
> -
> -				if (oa_report_is_periodic(report)) {
> -					memcpy(last_periodic_report, report, report_size);
> -
> -					/* We want to measure only the periodic reports,
> -					 * ctx-switch might inflate the content of the
> -					 * buffer and skew or measurement.
> -					 */
> -					n_periodic_reports++;
> -				}
> -			}
> -		}
> -
> -		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_DISABLE, 0);
> -
> -		igt_debug("first ts = %"PRIu64", last ts = %"PRIu64"\n", first_timestamp, last_timestamp);
> -
> -		igt_debug("%f < %zu < %f\n",
> -			  report_size * n_full_oa_reports * 0.45,
> -			  n_periodic_reports * report_size,
> -			  report_size * n_full_oa_reports * 0.55);
> -
> -		igt_assert((n_periodic_reports * report_size) >
> -			   (report_size * n_full_oa_reports * 0.45));
> -		igt_assert((n_periodic_reports * report_size) <
> -			   report_size * n_full_oa_reports * 0.55);
> +	intel_register_access_init(&mmio_data,
> +				   igt_device_get_pci_device(drm_fd), 0);
>
> +	oacontrol = intel_register_read(&mmio_data, OAG_OACONTROL);
> +	igt_assert_eq(oacontrol & OAG_OACONTROL_OA_COUNTER_ENABLE, 0);
>
> -		/* It's considered an error to read a stream while it's disabled
> -		 * since it would block indefinitely...
> -		 */
> -		len = read(stream_fd, buf, buf_size);
> +	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
>
> -		igt_assert_eq(len, -1);
> -		igt_assert_eq(errno, EINVAL);
> -	}
> +	oacontrol = intel_register_read(&mmio_data, OAG_OACONTROL);
>
> -	free(last_periodic_report);
> -	free(buf);
> +	igt_assert_eq(oacontrol & OAG_OACONTROL_OA_COUNTER_ENABLE, 1);
>
> +	intel_register_access_fini(&mmio_data);
>	__perf_close(stream_fd);
> -
> -	load_helper_stop();
> -	load_helper_fini();

The sync tests actually change the config on an open OA stream. However
they do it without disable-enable. We could add disable-enable there, but
still those tests only check for the syncs to signal. And the syncs signal
after a delay after the OA config is applied, not when disable/enable
completes, so those tests wouldn't check for enable/disable.

At least here we have some basic testing of enable disable. So this is:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

Re: [PATCH 10/13] tests/intel/xe_oa: Rewrite enable-disable test

[Dixit, Ashutosh]

On Mon, 24 Feb 2025 16:30:19 -0800, Dixit, Ashutosh wrote:
>
> On Fri, 14 Feb 2025 17:06:25 -0800, Umesh Nerlige Ramappa wrote:
> >
> > Keep it simple and just check if enable/disable is working correctly
> > using mmio.
> >
> > Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> > ---
> >  tests/intel/xe_oa.c | 129 +++++---------------------------------------
> >  1 file changed, 13 insertions(+), 116 deletions(-)
> >
> > diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> > index ee87b7338..c6c1c2358 100644
> > --- a/tests/intel/xe_oa.c
> > +++ b/tests/intel/xe_oa.c
> > @@ -2534,21 +2534,13 @@ test_non_zero_reason(const struct drm_xe_engine_class_instance *hwe, size_t oa_b
> >  static void
> >  test_enable_disable(const struct drm_xe_engine_class_instance *hwe)
> >  {
> > -	/* ~5 micro second period */
> > -	int oa_exponent = max_oa_exponent_for_period_lte(5000);
> > -	uint64_t oa_period = oa_exponent_to_ns(oa_exponent);
> >	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
> > -	uint64_t fmt = test_set->perf_oa_format;
> >	uint64_t properties[] = {
> >		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
> > -
> > -		/* Include OA reports in samples */
> >		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
> > -
> > -		/* OA unit configuration */
> >		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
> > -		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt),
> > -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
> > +		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
> > +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
> >		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
> >		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
> >	};
> > @@ -2556,123 +2548,28 @@ test_enable_disable(const struct drm_xe_engine_class_instance *hwe)
> >		.num_properties = ARRAY_SIZE(properties) / 2,
> >		.properties_ptr = to_user_pointer(properties),
> >	};
> > -	size_t report_size = get_oa_format(fmt).size;
> > -	int buf_size = 65536 * report_size;
> > -	uint8_t *buf = malloc(buf_size);
> > -	int n_full_oa_reports = default_oa_buffer_size / report_size;
> > -	uint64_t fill_duration = n_full_oa_reports * oa_period;
> > -	uint32_t *last_periodic_report = malloc(report_size);
> > -
> > -	load_helper_init();
> > -	load_helper_run(HIGH);
> > +	u32 oacontrol;
> >
> >	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
> >          set_fd_flags(stream_fd, O_CLOEXEC);
> >
> > -	for (int i = 0; i < 5; i++) {
> > -		int len;
> > -		uint32_t n_periodic_reports;
> > -		uint64_t first_timestamp = 0, last_timestamp = 0;
> > -		u32 oa_status;
> > -
> > -		/* Giving enough time for an overflow might help catch whether
> > -		 * the OA unit has been enabled even if the driver might at
> > -		 * least avoid copying reports while disabled.
> > -		 */
> > -		nanosleep(&(struct timespec){ .tv_sec = 0,
> > -					      .tv_nsec = fill_duration * 1.25 },
> > -			  NULL);
> > -
> > -		while ((len = read(stream_fd, buf, buf_size)) == -1 &&
> > -		       (errno == EINTR || errno == EIO))
> > -			;
> > -
> > -		igt_assert_eq(len, -1);
> > -		igt_assert_eq(errno, EINVAL);
> > -
> > -		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
> > +#define OAG_OACONTROL	(0xdaf4)
> > +#define  OAG_OACONTROL_OA_COUNTER_ENABLE	(1 << 0)
> >
> > -		nanosleep(&(struct timespec){ .tv_sec = 0,
> > -					      .tv_nsec = fill_duration / 2 },
> > -			NULL);
> > -
> > -		n_periodic_reports = 0;
> > -
> > -		/* Because of the race condition between notification of new
> > -		 * reports and reports landing in memory, we need to rely on
> > -		 * timestamps to figure whether we've read enough of them.
> > -		 */
> > -		while (((last_timestamp - first_timestamp) * oa_period) < (fill_duration / 2)) {
> > -
> > -			while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == EINTR)
> > -				;
> > -			if (errno == EIO) {
> > -				oa_status = get_stream_status(stream_fd);
> > -				igt_debug("oa_status %#x\n", oa_status);
> > -				igt_assert(!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW));
> > -				continue;
> > -			}
> > -			igt_assert_neq(len, -1);
> > -
> > -			for (int offset = 0; offset < len; offset += report_size) {
> > -				uint32_t *report = (void *) (buf + offset);
> > -
> > -				if (first_timestamp == 0)
> > -					first_timestamp = oa_timestamp(report, fmt);
> > -				last_timestamp = oa_timestamp(report, fmt);
> > -
> > -				igt_debug(" > report ts=%"PRIx64""
> > -					  " ts_delta_last_periodic=%s%"PRIu64""
> > -					  " is_timer=%i ctx_id=0x%8x\n",
> > -					  oa_timestamp(report, fmt),
> > -					  oa_report_is_periodic(report) ? " " : "*",
> > -					  n_periodic_reports > 0 ?  oa_timestamp_delta(report, last_periodic_report, fmt) : 0,
> > -					  oa_report_is_periodic(report),
> > -					  oa_report_get_ctx_id(report));
> > -
> > -				if (oa_report_is_periodic(report)) {
> > -					memcpy(last_periodic_report, report, report_size);
> > -
> > -					/* We want to measure only the periodic reports,
> > -					 * ctx-switch might inflate the content of the
> > -					 * buffer and skew or measurement.
> > -					 */
> > -					n_periodic_reports++;
> > -				}
> > -			}
> > -		}
> > -
> > -		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_DISABLE, 0);
> > -
> > -		igt_debug("first ts = %"PRIu64", last ts = %"PRIu64"\n", first_timestamp, last_timestamp);
> > -
> > -		igt_debug("%f < %zu < %f\n",
> > -			  report_size * n_full_oa_reports * 0.45,
> > -			  n_periodic_reports * report_size,
> > -			  report_size * n_full_oa_reports * 0.55);
> > -
> > -		igt_assert((n_periodic_reports * report_size) >
> > -			   (report_size * n_full_oa_reports * 0.45));
> > -		igt_assert((n_periodic_reports * report_size) <
> > -			   report_size * n_full_oa_reports * 0.55);
> > +	intel_register_access_init(&mmio_data,
> > +				   igt_device_get_pci_device(drm_fd), 0);
> >
> > +	oacontrol = intel_register_read(&mmio_data, OAG_OACONTROL);
> > +	igt_assert_eq(oacontrol & OAG_OACONTROL_OA_COUNTER_ENABLE, 0);
> >
> > -		/* It's considered an error to read a stream while it's disabled
> > -		 * since it would block indefinitely...
> > -		 */
> > -		len = read(stream_fd, buf, buf_size);
> > +	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
> >
> > -		igt_assert_eq(len, -1);
> > -		igt_assert_eq(errno, EINVAL);
> > -	}
> > +	oacontrol = intel_register_read(&mmio_data, OAG_OACONTROL);
> >
> > -	free(last_periodic_report);
> > -	free(buf);
> > +	igt_assert_eq(oacontrol & OAG_OACONTROL_OA_COUNTER_ENABLE, 1);
> >
> > +	intel_register_access_fini(&mmio_data);
> >	__perf_close(stream_fd);
> > -
> > -	load_helper_stop();
> > -	load_helper_fini();
>
> The sync tests actually change the config on an open OA stream. However
> they do it without disable-enable. We could add disable-enable there, but
> still those tests only check for the syncs to signal. And the syncs signal
> after a delay after the OA config is applied, not when disable/enable
> completes, so those tests wouldn't check for enable/disable.
>
> At least here we have some basic testing of enable disable. So this is:
>
> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

Actually, I want to question the "wisdom" of bypassing the uapi and
verifying something by this sideband method or direct register reads,
clever though that method is.

So for example, another way to simplify this test is:

1. Disable the stream and check that read() returns -EINVAL
2. Re-enable the stream and read() a single report

So why not do just that?

Fine we verify the register bit here, but the uapi is more than the
register bit. Verifying the uapi as indicated above verifies that
re-enabling the stream actually returns valid data, which is more than the
register bit and of which the register bit is a subset.

So not sure.

Thanks.
--
Ashutosh

Re: [PATCH 10/13] tests/intel/xe_oa: Rewrite enable-disable test

[Umesh Nerlige Ramappa]

On Mon, Feb 24, 2025 at 06:54:42PM -0800, Dixit, Ashutosh wrote:
>On Mon, 24 Feb 2025 16:30:19 -0800, Dixit, Ashutosh wrote:
>>
>> On Fri, 14 Feb 2025 17:06:25 -0800, Umesh Nerlige Ramappa wrote:
>> >
>> > Keep it simple and just check if enable/disable is working correctly
>> > using mmio.
>> >
>> > Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> > ---
>> >  tests/intel/xe_oa.c | 129 +++++---------------------------------------
>> >  1 file changed, 13 insertions(+), 116 deletions(-)
>> >
>> > diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
>> > index ee87b7338..c6c1c2358 100644
>> > --- a/tests/intel/xe_oa.c
>> > +++ b/tests/intel/xe_oa.c
>> > @@ -2534,21 +2534,13 @@ test_non_zero_reason(const struct drm_xe_engine_class_instance *hwe, size_t oa_b
>> >  static void
>> >  test_enable_disable(const struct drm_xe_engine_class_instance *hwe)
>> >  {
>> > -	/* ~5 micro second period */
>> > -	int oa_exponent = max_oa_exponent_for_period_lte(5000);
>> > -	uint64_t oa_period = oa_exponent_to_ns(oa_exponent);
>> >	struct intel_xe_perf_metric_set *test_set = metric_set(hwe);
>> > -	uint64_t fmt = test_set->perf_oa_format;
>> >	uint64_t properties[] = {
>> >		DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
>> > -
>> > -		/* Include OA reports in samples */
>> >		DRM_XE_OA_PROPERTY_SAMPLE_OA, true,
>> > -
>> > -		/* OA unit configuration */
>> >		DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set,
>> > -		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt),
>> > -		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent,
>> > +		DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(test_set->perf_oa_format),
>> > +		DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, oa_exponent_default,
>> >		DRM_XE_OA_PROPERTY_OA_DISABLED, true,
>> >		DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance,
>> >	};
>> > @@ -2556,123 +2548,28 @@ test_enable_disable(const struct drm_xe_engine_class_instance *hwe)
>> >		.num_properties = ARRAY_SIZE(properties) / 2,
>> >		.properties_ptr = to_user_pointer(properties),
>> >	};
>> > -	size_t report_size = get_oa_format(fmt).size;
>> > -	int buf_size = 65536 * report_size;
>> > -	uint8_t *buf = malloc(buf_size);
>> > -	int n_full_oa_reports = default_oa_buffer_size / report_size;
>> > -	uint64_t fill_duration = n_full_oa_reports * oa_period;
>> > -	uint32_t *last_periodic_report = malloc(report_size);
>> > -
>> > -	load_helper_init();
>> > -	load_helper_run(HIGH);
>> > +	u32 oacontrol;
>> >
>> >	stream_fd = __perf_open(drm_fd, &param, true /* prevent_pm */);
>> >          set_fd_flags(stream_fd, O_CLOEXEC);
>> >
>> > -	for (int i = 0; i < 5; i++) {
>> > -		int len;
>> > -		uint32_t n_periodic_reports;
>> > -		uint64_t first_timestamp = 0, last_timestamp = 0;
>> > -		u32 oa_status;
>> > -
>> > -		/* Giving enough time for an overflow might help catch whether
>> > -		 * the OA unit has been enabled even if the driver might at
>> > -		 * least avoid copying reports while disabled.
>> > -		 */
>> > -		nanosleep(&(struct timespec){ .tv_sec = 0,
>> > -					      .tv_nsec = fill_duration * 1.25 },
>> > -			  NULL);
>> > -
>> > -		while ((len = read(stream_fd, buf, buf_size)) == -1 &&
>> > -		       (errno == EINTR || errno == EIO))
>> > -			;
>> > -
>> > -		igt_assert_eq(len, -1);
>> > -		igt_assert_eq(errno, EINVAL);
>> > -
>> > -		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
>> > +#define OAG_OACONTROL	(0xdaf4)
>> > +#define  OAG_OACONTROL_OA_COUNTER_ENABLE	(1 << 0)
>> >
>> > -		nanosleep(&(struct timespec){ .tv_sec = 0,
>> > -					      .tv_nsec = fill_duration / 2 },
>> > -			NULL);
>> > -
>> > -		n_periodic_reports = 0;
>> > -
>> > -		/* Because of the race condition between notification of new
>> > -		 * reports and reports landing in memory, we need to rely on
>> > -		 * timestamps to figure whether we've read enough of them.
>> > -		 */
>> > -		while (((last_timestamp - first_timestamp) * oa_period) < (fill_duration / 2)) {
>> > -
>> > -			while ((len = read(stream_fd, buf, buf_size)) == -1 && errno == EINTR)
>> > -				;
>> > -			if (errno == EIO) {
>> > -				oa_status = get_stream_status(stream_fd);
>> > -				igt_debug("oa_status %#x\n", oa_status);
>> > -				igt_assert(!(oa_status & DRM_XE_OASTATUS_BUFFER_OVERFLOW));
>> > -				continue;
>> > -			}
>> > -			igt_assert_neq(len, -1);
>> > -
>> > -			for (int offset = 0; offset < len; offset += report_size) {
>> > -				uint32_t *report = (void *) (buf + offset);
>> > -
>> > -				if (first_timestamp == 0)
>> > -					first_timestamp = oa_timestamp(report, fmt);
>> > -				last_timestamp = oa_timestamp(report, fmt);
>> > -
>> > -				igt_debug(" > report ts=%"PRIx64""
>> > -					  " ts_delta_last_periodic=%s%"PRIu64""
>> > -					  " is_timer=%i ctx_id=0x%8x\n",
>> > -					  oa_timestamp(report, fmt),
>> > -					  oa_report_is_periodic(report) ? " " : "*",
>> > -					  n_periodic_reports > 0 ?  oa_timestamp_delta(report, last_periodic_report, fmt) : 0,
>> > -					  oa_report_is_periodic(report),
>> > -					  oa_report_get_ctx_id(report));
>> > -
>> > -				if (oa_report_is_periodic(report)) {
>> > -					memcpy(last_periodic_report, report, report_size);
>> > -
>> > -					/* We want to measure only the periodic reports,
>> > -					 * ctx-switch might inflate the content of the
>> > -					 * buffer and skew or measurement.
>> > -					 */
>> > -					n_periodic_reports++;
>> > -				}
>> > -			}
>> > -		}
>> > -
>> > -		do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_DISABLE, 0);
>> > -
>> > -		igt_debug("first ts = %"PRIu64", last ts = %"PRIu64"\n", first_timestamp, last_timestamp);
>> > -
>> > -		igt_debug("%f < %zu < %f\n",
>> > -			  report_size * n_full_oa_reports * 0.45,
>> > -			  n_periodic_reports * report_size,
>> > -			  report_size * n_full_oa_reports * 0.55);
>> > -
>> > -		igt_assert((n_periodic_reports * report_size) >
>> > -			   (report_size * n_full_oa_reports * 0.45));
>> > -		igt_assert((n_periodic_reports * report_size) <
>> > -			   report_size * n_full_oa_reports * 0.55);
>> > +	intel_register_access_init(&mmio_data,
>> > +				   igt_device_get_pci_device(drm_fd), 0);
>> >
>> > +	oacontrol = intel_register_read(&mmio_data, OAG_OACONTROL);
>> > +	igt_assert_eq(oacontrol & OAG_OACONTROL_OA_COUNTER_ENABLE, 0);
>> >
>> > -		/* It's considered an error to read a stream while it's disabled
>> > -		 * since it would block indefinitely...
>> > -		 */
>> > -		len = read(stream_fd, buf, buf_size);
>> > +	do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0);
>> >
>> > -		igt_assert_eq(len, -1);
>> > -		igt_assert_eq(errno, EINVAL);
>> > -	}
>> > +	oacontrol = intel_register_read(&mmio_data, OAG_OACONTROL);
>> >
>> > -	free(last_periodic_report);
>> > -	free(buf);
>> > +	igt_assert_eq(oacontrol & OAG_OACONTROL_OA_COUNTER_ENABLE, 1);
>> >
>> > +	intel_register_access_fini(&mmio_data);
>> >	__perf_close(stream_fd);
>> > -
>> > -	load_helper_stop();
>> > -	load_helper_fini();
>>
>> The sync tests actually change the config on an open OA stream. However
>> they do it without disable-enable. We could add disable-enable there, but
>> still those tests only check for the syncs to signal. And the syncs signal
>> after a delay after the OA config is applied, not when disable/enable
>> completes, so those tests wouldn't check for enable/disable.
>>
>> At least here we have some basic testing of enable disable. So this is:
>>
>> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>
>Actually, I want to question the "wisdom" of bypassing the uapi and
>verifying something by this sideband method or direct register reads,
>clever though that method is.

Since this use case is privileged, I thought I might as well check stuff 
using mmio compared to cooking up complex logic to do so. Also the logic 
needs to be simple enough to run quickly on all platforms.

>
>So for example, another way to simplify this test is:
>
>1. Disable the stream and check that read() returns -EINVAL
>2. Re-enable the stream and read() a single report
>
>So why not do just that?

Sure, I did not think of that. Looks like EINVAL is also returned in 
read if stream->sample is not set, but since our test already sets 
sample, we should be good with that. I can change this test to do that 
since anyways, this is only testing basic stuff now (see below).

>
>Fine we verify the register bit here, but the uapi is more than the
>register bit. Verifying the uapi as indicated above verifies that
>re-enabling the stream actually returns valid data, which is more than the
>register bit and of which the register bit is a subset.

There's more to actually verify in this test, but the uapi itself does 
not allow that - i.e. check that enable would have reset the OA buffer 
tail/head/status etc. Sometimes users use it to restart the capture.

For now, I have kept it to bare minimum. We can add additional coverage 
in this as we test more stuff.

Thanks,
Umesh

>
>So not sure.
>
>Thanks.
>--
>Ashutosh

[PATCH 11/13] tests/intel/xe_oa: Enable unprivileged-single-ctx-counters and fix it

[Umesh Nerlige Ramappa]

unprivileged-single-ctx-counters was hardcoded for a format size of 256
bytes. Fix it up for generic format size.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 93 +++++++++++++++++++++++----------------------
 1 file changed, 48 insertions(+), 45 deletions(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index c6c1c2358..ff1b873d5 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -2961,6 +2961,16 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	struct accumulator accumulator = {
 		.format = fmt
 	};
+	uint32_t ctx_id_offset, counter_offset, dst_buf_size;
+	struct oa_format format = get_oa_format(fmt);
+
+	if (format.report_hdr_64bit) {
+		ctx_id_offset = 4;
+		counter_offset = 8;
+	} else {
+		ctx_id_offset = 2;
+		counter_offset = 4;
+	}
 
 	bops = buf_ops_create(drm_fd);
 
@@ -2989,25 +2999,29 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	stream_fd = __perf_open(drm_fd, &param, false);
         set_fd_flags(stream_fd, O_CLOEXEC);
 
-	dst_buf = intel_buf_create(bops, 4096, 1, 8, 64,
+#define FOUR_REPORTS (4 * format.size)
+#define BO_REPORT_OFFSET(_r) (_r * format.size)
+
+#define FOUR_TIMESTAMPS (4 * 8)
+#define BO_TIMESTAMP_OFFSET(_r) (FOUR_REPORTS + (_r * 8))
+
+	dst_buf_size = FOUR_REPORTS + FOUR_TIMESTAMPS;
+	dst_buf = intel_buf_create(bops, dst_buf_size, 1, 8, 64,
 				   I915_TILING_NONE,
 				   I915_COMPRESSION_NONE);
 
 	/* Set write domain to cpu briefly to fill the buffer with 80s */
 	buf_map(drm_fd, dst_buf, true /* write enable */);
-	memset(dst_buf->ptr, 0x80, 2048);
-	memset((uint8_t *) dst_buf->ptr + 2048, 0, 2048);
+	memset(dst_buf->ptr, 0, dst_buf_size);
+	memset(dst_buf->ptr, 0x80, FOUR_REPORTS);
 	intel_buf_unmap(dst_buf);
 
 	/* Submit an mi-rpc to context0 before measurable work */
-#define BO_TIMESTAMP_OFFSET0 1024
-#define BO_REPORT_OFFSET0 0
-#define BO_REPORT_ID0 0xdeadbeef
 	emit_stall_timestamp_and_rpc(ibb0,
 				     dst_buf,
-				     BO_TIMESTAMP_OFFSET0,
-				     BO_REPORT_OFFSET0,
-				     BO_REPORT_ID0);
+				     BO_TIMESTAMP_OFFSET(0),
+				     BO_REPORT_OFFSET(0),
+				     0xdeadbeef);
 	intel_bb_flush_render(ibb0);
 
 	/* Remove intel_buf from ibb0 added implicitly in rendercopy */
@@ -3025,14 +3039,11 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	 * all zeroes, since the counters will only increment for the
 	 * context passed to perf open ioctl
 	 */
-#define BO_TIMESTAMP_OFFSET2 1040
-#define BO_REPORT_OFFSET2 512
-#define BO_REPORT_ID2 0x00c0ffee
 	emit_stall_timestamp_and_rpc(ibb1,
 				     dst_buf,
-				     BO_TIMESTAMP_OFFSET2,
-				     BO_REPORT_OFFSET2,
-				     BO_REPORT_ID2);
+				     BO_TIMESTAMP_OFFSET(2),
+				     BO_REPORT_OFFSET(2),
+				     0x00c0ffee);
 	intel_bb_flush_render(ibb1);
 
 	/* Submit two copies on the other context to avoid a false
@@ -3049,28 +3060,22 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	intel_bb_flush_render(ibb1);
 
 	/* Submit an mi-rpc to context1 after all work */
-#define BO_TIMESTAMP_OFFSET3 1048
-#define BO_REPORT_OFFSET3 768
-#define BO_REPORT_ID3 0x01c0ffee
 	emit_stall_timestamp_and_rpc(ibb1,
 				     dst_buf,
-				     BO_TIMESTAMP_OFFSET3,
-				     BO_REPORT_OFFSET3,
-				     BO_REPORT_ID3);
+				     BO_TIMESTAMP_OFFSET(3),
+				     BO_REPORT_OFFSET(3),
+				     0x01c0ffee);
 	intel_bb_flush_render(ibb1);
 
 	/* Remove intel_buf from ibb1 added implicitly in rendercopy */
 	intel_bb_remove_intel_buf(ibb1, dst_buf);
 
 	/* Submit an mi-rpc to context0 after all measurable work */
-#define BO_TIMESTAMP_OFFSET1 1032
-#define BO_REPORT_OFFSET1 256
-#define BO_REPORT_ID1 0xbeefbeef
 	emit_stall_timestamp_and_rpc(ibb0,
 				     dst_buf,
-				     BO_TIMESTAMP_OFFSET1,
-				     BO_REPORT_OFFSET1,
-				     BO_REPORT_ID1);
+				     BO_TIMESTAMP_OFFSET(1),
+				     BO_REPORT_OFFSET(1),
+				     0xbeefbeef);
 	intel_bb_flush_render(ibb0);
 	intel_bb_sync(ibb0);
 	intel_bb_sync(ibb1);
@@ -3090,33 +3095,32 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	report0_32 = dst_buf->ptr;
 	igt_assert_eq(report0_32[0], 0xdeadbeef);
 	igt_assert(oa_timestamp(report0_32, fmt));
-	ctx0_id = report0_32[2];
+	ctx0_id = report0_32[ctx_id_offset];
 	igt_debug("MI_RPC(start) CTX ID: %u\n", ctx0_id);
-	dump_report(report0_32, 64, "report0_32");
+	dump_report(report0_32, format.size / 4, "report0_32");
 
-	report1_32 = report0_32 + 64;
+	report1_32 = report0_32 + format.size / 4;
 	igt_assert_eq(report1_32[0], 0xbeefbeef);
 	igt_assert(oa_timestamp(report1_32, fmt));
-	ctx1_id = report1_32[2];
+	ctx1_id = report1_32[ctx_id_offset];
 	igt_debug("CTX ID1: %u\n", ctx1_id);
-	dump_report(report1_32, 64, "report1_32");
+	dump_report(report1_32, format.size / 4, "report1_32");
 
 	/* Verify that counters in context1 are all zeroes */
-	report2_32 = report0_32 + 128;
+	report2_32 = report1_32 + format.size / 4;
 	igt_assert_eq(report2_32[0], 0x00c0ffee);
 	igt_assert(oa_timestamp(report2_32, fmt));
-	dump_report(report2_32, 64, "report2_32");
-	igt_assert_eq(0, memcmp(&report2_32[4],
-				(uint8_t *) dst_buf->ptr + 2048,
-				240));
+	dump_report(report2_32, format.size / 4, "report2_32");
 
-	report3_32 = report0_32 + 192;
+	report3_32 = report2_32 + format.size / 4;
 	igt_assert_eq(report3_32[0], 0x01c0ffee);
 	igt_assert(oa_timestamp(report3_32, fmt));
-	dump_report(report3_32, 64, "report3_32");
-	igt_assert_eq(0, memcmp(&report3_32[4],
-				(uint8_t *) dst_buf->ptr + 2048,
-				240));
+	dump_report(report3_32, format.size / 4, "report3_32");
+
+	for (int k = counter_offset; k < format.size / 4; k++) {
+		igt_assert_f(report2_32[k] == 0, "Failed counter %d check\n", k);
+		igt_assert_f(report3_32[k] == 0, "Failed counter %d check\n", k);
+	}
 
 	/* Accumulate deltas for counters - A0, A21 and A26 */
 	memset(accumulator.deltas, 0, sizeof(accumulator.deltas));
@@ -3135,8 +3139,8 @@ static void single_ctx_helper(struct drm_xe_engine_class_instance *hwe)
 	 * the OA report timestamps should be almost identical but
 	 * allow a 500 nanoseconds margin.
 	 */
-	timestamp0_64 = *(uint64_t *)(((uint8_t *)dst_buf->ptr) + BO_TIMESTAMP_OFFSET0);
-	timestamp1_64 = *(uint64_t *)(((uint8_t *)dst_buf->ptr) + BO_TIMESTAMP_OFFSET1);
+	timestamp0_64 = *(uint64_t *)(((uint8_t *)dst_buf->ptr) + BO_TIMESTAMP_OFFSET(0));
+	timestamp1_64 = *(uint64_t *)(((uint8_t *)dst_buf->ptr) + BO_TIMESTAMP_OFFSET(1));
 
 	igt_debug("ts_timestamp64 0 = %"PRIu64"\n", timestamp0_64);
 	igt_debug("ts_timestamp64 1 = %"PRIu64"\n", timestamp1_64);
@@ -4781,7 +4785,6 @@ igt_main
 
 		igt_subtest_with_dynamic("unprivileged-single-ctx-counters") {
 			igt_require_f(render_copy, "no render-copy function\n");
-			igt_require(intel_graphics_ver(devid) < IP_VER(20, 0));
 			__for_one_render_engine(hwe)
 				test_single_ctx_render_target_writes_a_counter(hwe);
 		}
-- 
2.34.1

Re: [PATCH 11/13] tests/intel/xe_oa: Enable unprivileged-single-ctx-counters and fix it

[Dixit, Ashutosh]

On Fri, 14 Feb 2025 17:06:26 -0800, Umesh Nerlige Ramappa wrote:
>
> unprivileged-single-ctx-counters was hardcoded for a format size of 256
> bytes. Fix it up for generic format size.

Great to see this working, thanks for fixing this :)

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

[PATCH 12/13] tests/intel/xe_oa: Fix mmio_trigger_reports testing

[Umesh Nerlige Ramappa]

The MI_STORE command needs modification to set the right amount of dwords. While
at it, set the default exponent and add a render_copy check.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index ff1b873d5..d44832a8a 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -3688,7 +3688,7 @@ emit_oa_reg_read(struct intel_bb *ibb, struct intel_buf *dst, uint32_t offset,
 {
 	intel_bb_add_intel_buf(ibb, dst, true);
 
-	intel_bb_out(ibb, MI_STORE_REGISTER_MEM | 2);
+	intel_bb_out(ibb, MI_STORE_REGISTER_MEM_GEN8);
 	intel_bb_out(ibb, reg);
 	intel_bb_emit_reloc(ibb, dst->handle,
 			    I915_GEM_DOMAIN_INSTRUCTION,
-- 
2.34.1

Re: [PATCH 12/13] tests/intel/xe_oa: Fix mmio_trigger_reports testing

[Dixit, Ashutosh]

On Fri, 14 Feb 2025 17:06:27 -0800, Umesh Nerlige Ramappa wrote:
>
> The MI_STORE command needs modification to set the right amount of dwords. While
> at it, set the default exponent and add a render_copy check.

What is the second sentence here referring to, please fix:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/intel/xe_oa.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> index ff1b873d5..d44832a8a 100644
> --- a/tests/intel/xe_oa.c
> +++ b/tests/intel/xe_oa.c
> @@ -3688,7 +3688,7 @@ emit_oa_reg_read(struct intel_bb *ibb, struct intel_buf *dst, uint32_t offset,
>  {
>	intel_bb_add_intel_buf(ibb, dst, true);
>
> -	intel_bb_out(ibb, MI_STORE_REGISTER_MEM | 2);
> +	intel_bb_out(ibb, MI_STORE_REGISTER_MEM_GEN8);
>	intel_bb_out(ibb, reg);
>	intel_bb_emit_reloc(ibb, dst->handle,
>			    I915_GEM_DOMAIN_INSTRUCTION,
> --
> 2.34.1
>

[PATCH 13/13] tests/intel/xe_oa: Set boundaries for OA exponent test

[Umesh Nerlige Ramappa]

Define min and max oa exponents for the oa exponent test

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/intel/xe_oa.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
index d44832a8a..22ff3f20d 100644
--- a/tests/intel/xe_oa.c
+++ b/tests/intel/xe_oa.c
@@ -321,6 +321,8 @@ static size_t default_oa_buffer_size;
 static struct intel_mmio_data mmio_data;
 static igt_render_copyfunc_t render_copy;
 static uint32_t rc_width, rc_height;
+static uint32_t max_oa_exponent;
+static uint32_t min_oa_exponent;
 static uint32_t buffer_fill_size;
 static uint32_t num_buf_sizes;
 
@@ -1109,6 +1111,8 @@ init_sys_info(void)
 
 	intel_xe_perf_load_perf_configs(intel_xe_perf, drm_fd);
 
+	min_oa_exponent = 5;
+	max_oa_exponent = 20;
 	rc_width = 1920;
 	rc_height = 1080;
 	buffer_fill_size = SZ_16M;
@@ -1710,7 +1714,7 @@ static void test_oa_exponents(const struct drm_xe_engine_class_instance *hwe)
 	 * test can fail due to buffer overflows if it wasn't possible to
 	 * keep up, so we don't start from an exponent of zero...
 	 */
-	for (int exponent = 5; exponent < 20; exponent++) {
+	for (int exponent = min_oa_exponent; exponent < max_oa_exponent; exponent++) {
 		uint64_t properties[] = {
 			DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
 
-- 
2.34.1

Re: [PATCH 13/13] tests/intel/xe_oa: Set boundaries for OA exponent test

[Dixit, Ashutosh]

On Fri, 14 Feb 2025 17:06:28 -0800, Umesh Nerlige Ramappa wrote:
>
> Define min and max oa exponents for the oa exponent test

so that they can be set differently on slow platforms.

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/intel/xe_oa.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
> index d44832a8a..22ff3f20d 100644
> --- a/tests/intel/xe_oa.c
> +++ b/tests/intel/xe_oa.c
> @@ -321,6 +321,8 @@ static size_t default_oa_buffer_size;
>  static struct intel_mmio_data mmio_data;
>  static igt_render_copyfunc_t render_copy;
>  static uint32_t rc_width, rc_height;
> +static uint32_t max_oa_exponent;
> +static uint32_t min_oa_exponent;
>  static uint32_t buffer_fill_size;
>  static uint32_t num_buf_sizes;
>
> @@ -1109,6 +1111,8 @@ init_sys_info(void)
>
>	intel_xe_perf_load_perf_configs(intel_xe_perf, drm_fd);
>
> +	min_oa_exponent = 5;
> +	max_oa_exponent = 20;
>	rc_width = 1920;
>	rc_height = 1080;
>	buffer_fill_size = SZ_16M;
> @@ -1710,7 +1714,7 @@ static void test_oa_exponents(const struct drm_xe_engine_class_instance *hwe)
>	 * test can fail due to buffer overflows if it wasn't possible to
>	 * keep up, so we don't start from an exponent of zero...
>	 */
> -	for (int exponent = 5; exponent < 20; exponent++) {
> +	for (int exponent = min_oa_exponent; exponent < max_oa_exponent; exponent++) {
>		uint64_t properties[] = {
>			DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0,
>
> --
> 2.34.1
>

✓ Xe.CI.BAT: success for Some refactor, rewrite and fixes for OA tests

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 978 bytes --]

== Series Details ==

Series: Some refactor, rewrite and fixes for OA tests
URL   : https://patchwork.freedesktop.org/series/144916/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_8230_BAT -> XEIGTPW_12607_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (8 -> 8)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_8230 -> IGTPW_12607
  * Linux: xe-2665-57457d93f156d8b4bdff8d138127d81b8f97d8c9 -> xe-2669-cbd747025a1ef985e1ebfa040aa0da4a5d77aacd

  IGTPW_12607: 12607
  IGT_8230: 8230
  xe-2665-57457d93f156d8b4bdff8d138127d81b8f97d8c9: 57457d93f156d8b4bdff8d138127d81b8f97d8c9
  xe-2669-cbd747025a1ef985e1ebfa040aa0da4a5d77aacd: cbd747025a1ef985e1ebfa040aa0da4a5d77aacd

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/index.html

[-- Attachment #2: Type: text/html, Size: 1537 bytes --]

✗ i915.CI.BAT: failure for Some refactor, rewrite and fixes for OA tests

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6393 bytes --]

== Series Details ==

Series: Some refactor, rewrite and fixes for OA tests
URL   : https://patchwork.freedesktop.org/series/144916/
State : failure

== Summary ==

CI Bug Log - changes from IGT_8230 -> IGTPW_12607
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_12607 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_12607, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12607/index.html

Participating hosts (42 -> 41)
------------------------------

  Additional (1): bat-twl-1 
  Missing    (2): fi-snb-2520m bat-twl-2 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_12607:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live:
    - bat-adlp-6:         [PASS][1] -> [ABORT][2] +1 other test abort
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8230/bat-adlp-6/igt@i915_selftest@live.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12607/bat-adlp-6/igt@i915_selftest@live.html

  
Known issues
------------

  Here are the changes found in IGTPW_12607 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - bat-twl-1:          NOTRUN -> [SKIP][3] ([i915#9318])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12607/bat-twl-1/igt@debugfs_test@basic-hwmon.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - bat-twl-1:          NOTRUN -> [SKIP][4] ([i915#10213] / [i915#11671]) +3 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12607/bat-twl-1/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
    - bat-twl-1:          NOTRUN -> [SKIP][5] ([i915#11031])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12607/bat-twl-1/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-twl-1:          NOTRUN -> [SKIP][6] ([i915#10209] / [i915#11681])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12607/bat-twl-1/igt@i915_pm_rps@basic-api.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-twl-1:          NOTRUN -> [SKIP][7] ([i915#11030] / [i915#11731]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12607/bat-twl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - bat-twl-1:          NOTRUN -> [SKIP][8] ([i915#9886])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12607/bat-twl-1/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-twl-1:          NOTRUN -> [SKIP][9] ([i915#11032])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12607/bat-twl-1/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-twl-1:          NOTRUN -> [SKIP][10] ([i915#8809])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12607/bat-twl-1/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-read:
    - bat-twl-1:          NOTRUN -> [SKIP][11] ([i915#10212] / [i915#3708])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12607/bat-twl-1/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@basic-read:
    - bat-twl-1:          NOTRUN -> [SKIP][12] ([i915#10214] / [i915#3708])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12607/bat-twl-1/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@basic-write:
    - bat-twl-1:          NOTRUN -> [SKIP][13] ([i915#10216] / [i915#3708])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12607/bat-twl-1/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-2:         [DMESG-FAIL][14] ([i915#12061]) -> [PASS][15] +1 other test pass
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8230/bat-arlh-2/igt@i915_selftest@live@workarounds.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12607/bat-arlh-2/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-6:         [DMESG-FAIL][16] ([i915#12061]) -> [PASS][17] +1 other test pass
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8230/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12607/bat-mtlp-6/igt@i915_selftest@live@workarounds.html

  
  [i915#10209]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10209
  [i915#10212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10212
  [i915#10213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10213
  [i915#10214]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10214
  [i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
  [i915#11030]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11030
  [i915#11031]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11031
  [i915#11032]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11032
  [i915#11671]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11671
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#11731]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11731
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
  [i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
  [i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_8230 -> IGTPW_12607
  * Linux: CI_DRM_16134 -> CI_DRM_16138

  CI-20190529: 20190529
  CI_DRM_16134: 57457d93f156d8b4bdff8d138127d81b8f97d8c9 @ git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_16138: cbd747025a1ef985e1ebfa040aa0da4a5d77aacd @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_12607: 12607
  IGT_8230: 8230

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12607/index.html

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Re: ✗ i915.CI.BAT: failure for Some refactor, rewrite and fixes for OA tests

[Umesh Nerlige Ramappa]

On Sat, Feb 15, 2025 at 02:23:37AM +0000, Patchwork wrote:
>   Patch Details
>
>   Series:  Some refactor, rewrite and fixes for OA tests
>   URL:     [1]https://patchwork.freedesktop.org/series/144916/
>   State:   failure
>   Details: [2]https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12607/index.html
>
>               CI Bug Log - changes from IGT_8230 -> IGTPW_12607
>
>Summary
>
>   FAILURE
>
>   Serious unknown changes coming with IGTPW_12607 absolutely need to be
>   verified manually.
>
>   If you think the reported changes have nothing to do with the changes
>   introduced in IGTPW_12607, please notify your bug team
>   (I915-ci-infra@lists.freedesktop.org) to allow them
>   to document this new failure mode, which will reduce false positives in
>   CI.
>
>   External URL:
>   https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_12607/index.html
>
>Participating hosts (42 -> 41)
>
>   Additional (1): bat-twl-1
>   Missing (2): fi-snb-2520m bat-twl-2
>
>Possible new issues
>
>   Here are the unknown changes that may have been introduced in IGTPW_12607:
>
>  IGT changes
>
>    Possible regressions
>
>     * igt@i915_selftest@live:
>
>          * bat-adlp-6: [3]PASS -> [4]ABORT +1 other test abort

Unrelated since this series is strictly touching OA tests only.

Umesh
>
>Known issues

✗ Xe.CI.Full: failure for Some refactor, rewrite and fixes for OA tests

[Patchwork]

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== Series Details ==

Series: Some refactor, rewrite and fixes for OA tests
URL   : https://patchwork.freedesktop.org/series/144916/
State : failure

== Summary ==

CI Bug Log - changes from XEIGT_8230_full -> XEIGTPW_12607_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with XEIGTPW_12607_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in XEIGTPW_12607_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_12607_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][1]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html

  * {igt@xe_oa@buffer-size} (NEW):
    - shard-dg2-set2:     NOTRUN -> [SKIP][2]
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@xe_oa@buffer-size.html

  
#### Warnings ####

  * igt@xe_pm@s4-vm-bind-prefetch:
    - shard-lnl:          [ABORT][3] ([Intel XE#4268]) -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-lnl-2/igt@xe_pm@s4-vm-bind-prefetch.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-2/igt@xe_pm@s4-vm-bind-prefetch.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_pipe_stress@stress-xrgb8888-ytiled}:
    - shard-bmg:          NOTRUN -> [SKIP][5]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][6]
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html
    - shard-lnl:          NOTRUN -> [SKIP][7]
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-3/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  
New tests
---------

  New tests have been introduced between XEIGT_8230_full and XEIGTPW_12607_full:

### New IGT tests (4) ###

  * igt@xe_oa@buffer-size:
    - Statuses : 2 pass(s) 1 skip(s)
    - Exec time: [0.0, 2.86] s

  * igt@xe_oa@buffer-size@ccs-0-16m:
    - Statuses : 1 pass(s)
    - Exec time: [2.80] s

  * igt@xe_oa@buffer-size@rcs-0-2m:
    - Statuses : 1 pass(s)
    - Exec time: [2.86] s

  * igt@xe_oa@unprivileged-single-ctx-counters@rcs-0:
    - Statuses : 2 pass(s)
    - Exec time: [0.07, 0.08] s

  

Known issues
------------

  Here are the changes found in XEIGTPW_12607_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@hotreplug-lateclose:
    - shard-lnl:          NOTRUN -> [ABORT][8] ([Intel XE#3914])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-3/igt@core_hotunplug@hotreplug-lateclose.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#3157])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-6/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-bmg:          [PASS][10] -> [FAIL][11] ([Intel XE#827]) +1 other test fail
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-5/igt@kms_async_flips@alternate-sync-async-flip.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-5/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-atomic:
    - shard-lnl:          [PASS][12] -> [FAIL][13] ([Intel XE#3719] / [Intel XE#911]) +3 other tests fail
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-lnl-6/igt@kms_async_flips@async-flip-with-page-flip-events-atomic.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-3/igt@kms_async_flips@async-flip-with-page-flip-events-atomic.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-b-dp-4-4-rc-ccs-cc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#3767]) +7 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-463/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-b-dp-4-4-rc-ccs-cc.html

  * igt@kms_async_flips@invalid-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#873])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-5/igt@kms_async_flips@invalid-async-flip.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][16] ([Intel XE#873])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-434/igt@kms_async_flips@invalid-async-flip.html
    - shard-lnl:          NOTRUN -> [SKIP][17] ([Intel XE#873])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-3/igt@kms_async_flips@invalid-async-flip.html

  * igt@kms_atomic_transition@plane-all-modeset-transition:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#3279])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-3/igt@kms_atomic_transition@plane-all-modeset-transition.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#3658])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][20] ([Intel XE#1407]) +8 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2327]) +7 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][22] ([Intel XE#316]) +7 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-434/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#607])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][24] ([Intel XE#607])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-434/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#1477])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-8/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#1124]) +11 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][27] ([Intel XE#1124]) +12 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-463/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#1124]) +8 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          [PASS][29] -> [SKIP][30] ([Intel XE#2314] / [Intel XE#2894])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-7/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#2314] / [Intel XE#2894]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#2191])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-4/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][33] ([Intel XE#2191]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#1512]) +1 other test skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-4/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-3-displays-1920x1080p:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#367])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-8/igt@kms_bw@linear-tiling-3-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-3-displays-3840x2160p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][36] ([Intel XE#367]) +2 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@kms_bw@linear-tiling-3-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-4-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#367]) +2 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#2669]) +7 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-7/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-a-edp-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][39] ([Intel XE#2907])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-466/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][40] ([Intel XE#3442])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#3433]) +3 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-7/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#3432])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs.html
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#3432])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-5/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#2887]) +17 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-2/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][45] ([Intel XE#787]) +174 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-434/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][46] ([Intel XE#455] / [Intel XE#787]) +42 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-466/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#2887]) +17 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs.html

  * igt@kms_chamelium_audio@hdmi-audio-edid:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#2252]) +11 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_chamelium_audio@hdmi-audio-edid.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#2325]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_chamelium_color@ctm-red-to-blue.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][50] ([Intel XE#306]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_chamelium_color@ctm-red-to-blue.html
    - shard-lnl:          NOTRUN -> [SKIP][51] ([Intel XE#306]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-8/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
    - shard-dg2-set2:     NOTRUN -> [SKIP][52] ([Intel XE#373]) +11 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html

  * igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#373]) +11 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-5/igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode.html

  * igt@kms_color@ctm-0-75@pipe-d-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][54] ([Intel XE#4172]) +23 other tests dmesg-warn
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_color@ctm-0-75@pipe-d-hdmi-a-3.html

  * igt@kms_content_protection@legacy:
    - shard-bmg:          NOTRUN -> [DMESG-FAIL][55] ([Intel XE#4172]) +1 other test dmesg-fail
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-7/igt@kms_content_protection@legacy.html
    - shard-dg2-set2:     NOTRUN -> [DMESG-FAIL][56] ([Intel XE#1033]) +1 other test dmesg-fail
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@kms_content_protection@legacy.html
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#3278]) +1 other test skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-4/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@lic-type-0:
    - shard-dg2-set2:     NOTRUN -> [FAIL][58] ([Intel XE#1178])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-463/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][59] ([Intel XE#3304])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-463/igt@kms_content_protection@lic-type-0@pipe-a-dp-4.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#2320]) +4 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-7/igt@kms_cursor_crc@cursor-random-32x32.html
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#1424]) +4 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-5/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][62] -> [SKIP][63] ([Intel XE#2291]) +2 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-1/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
    - shard-lnl:          NOTRUN -> [SKIP][64] ([Intel XE#309]) +3 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-4/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-dg2-set2:     [PASS][65] -> [SKIP][66] ([Intel XE#309]) +5 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-433/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-legacy:
    - shard-bmg:          NOTRUN -> [SKIP][67] ([Intel XE#2291]) +2 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-dg2-set2:     NOTRUN -> [SKIP][68] ([Intel XE#323])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-466/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#323])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#2286])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dsc@dsc-basic:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#2244])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-7/igt@kms_dsc@dsc-basic.html
    - shard-lnl:          NOTRUN -> [SKIP][72] ([Intel XE#2244])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-7/igt@kms_dsc@dsc-basic.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#776])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-5/igt@kms_fbcon_fbt@psr-suspend.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][74] ([Intel XE#776])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@psr1:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#2374])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_feature_discovery@psr1.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][76] ([Intel XE#1135])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-flip-vs-panning-interruptible:
    - shard-bmg:          [PASS][77] -> [DMESG-WARN][78] ([Intel XE#2955])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-7/igt@kms_flip@2x-flip-vs-panning-interruptible.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_flip@2x-flip-vs-panning-interruptible.html
    - shard-dg2-set2:     [PASS][79] -> [SKIP][80] ([Intel XE#310]) +1 other test skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-432/igt@kms_flip@2x-flip-vs-panning-interruptible.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_flip@2x-flip-vs-panning-interruptible.html

  * igt@kms_flip@2x-flip-vs-panning-interruptible@cd-dp2-hdmi-a3:
    - shard-bmg:          [PASS][81] -> [DMESG-WARN][82] ([Intel XE#4172]) +41 other tests dmesg-warn
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-7/igt@kms_flip@2x-flip-vs-panning-interruptible@cd-dp2-hdmi-a3.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_flip@2x-flip-vs-panning-interruptible@cd-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-panning-vs-hang:
    - shard-bmg:          NOTRUN -> [SKIP][83] ([Intel XE#2316])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_flip@2x-flip-vs-panning-vs-hang.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][84] ([Intel XE#1421]) +5 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-6/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
    - shard-bmg:          NOTRUN -> [DMESG-WARN][85] ([Intel XE#2955])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-5/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][86] ([Intel XE#2955])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-466/igt@kms_flip@2x-flip-vs-suspend-interruptible.html

  * igt@kms_flip@2x-plain-flip:
    - shard-bmg:          [PASS][87] -> [SKIP][88] ([Intel XE#2316]) +4 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-7/igt@kms_flip@2x-plain-flip.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-dg2-set2:     NOTRUN -> [SKIP][89] ([Intel XE#310]) +2 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html

  * igt@kms_flip@busy-flip:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][90] ([Intel XE#1033]) +29 other tests dmesg-warn
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@kms_flip@busy-flip.html

  * igt@kms_flip@flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-dg2-set2:     [PASS][91] -> [DMESG-WARN][92] ([Intel XE#2955]) +1 other test dmesg-warn
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-464/igt@kms_flip@flip-vs-dpms-off-vs-modeset-interruptible.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-463/igt@kms_flip@flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@plain-flip-ts-check:
    - shard-bmg:          NOTRUN -> [FAIL][93] ([Intel XE#2882]) +2 other tests fail
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-5/igt@kms_flip@plain-flip-ts-check.html

  * igt@kms_flip@plain-flip-ts-check@a-hdmi-a6:
    - shard-dg2-set2:     NOTRUN -> [FAIL][94] ([Intel XE#886]) +1 other test fail
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-466/igt@kms_flip@plain-flip-ts-check@a-hdmi-a6.html

  * igt@kms_flip@plain-flip-ts-check@b-edp1:
    - shard-lnl:          NOTRUN -> [FAIL][95] ([Intel XE#886]) +2 other tests fail
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-6/igt@kms_flip@plain-flip-ts-check@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][96] ([Intel XE#1397]) +1 other test skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-8/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][97] ([Intel XE#2293] / [Intel XE#2380]) +3 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][98] ([Intel XE#1397] / [Intel XE#1745]) +1 other test skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-4/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][99] ([Intel XE#455]) +22 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-466/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
    - shard-lnl:          NOTRUN -> [SKIP][100] ([Intel XE#1401] / [Intel XE#1745]) +3 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][101] ([Intel XE#1401]) +3 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][102] ([Intel XE#2293]) +3 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_force_connector_basic@force-connector-state:
    - shard-lnl:          NOTRUN -> [SKIP][103] ([Intel XE#352])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-3/igt@kms_force_connector_basic@force-connector-state.html

  * igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][104] ([Intel XE#2311]) +29 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][105] ([Intel XE#651]) +16 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-6/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     [PASS][106] -> [SKIP][107] ([Intel XE#656]) +6 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][108] ([Intel XE#2312]) +10 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][109] ([Intel XE#4141]) +14 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc:
    - shard-dg2-set2:     [PASS][110] -> [DMESG-WARN][111] ([Intel XE#1033]) +42 other tests dmesg-warn
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-463/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][112] ([Intel XE#651]) +31 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][113] ([Intel XE#656]) +11 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][114] ([Intel XE#2313]) +24 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
    - shard-dg2-set2:     NOTRUN -> [SKIP][115] ([Intel XE#653]) +24 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][116] ([Intel XE#656]) +47 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-lnl:          NOTRUN -> [SKIP][117] ([Intel XE#1470] / [Intel XE#2853])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-5/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][118] ([Intel XE#2934])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-5/igt@kms_joiner@basic-force-ultra-joiner.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][119] ([Intel XE#2925])
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@kms_joiner@basic-force-ultra-joiner.html
    - shard-lnl:          NOTRUN -> [SKIP][120] ([Intel XE#2934])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-7/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][121] ([Intel XE#346])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-5/igt@kms_joiner@invalid-modeset-big-joiner.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][122] ([Intel XE#346])
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-bmg:          NOTRUN -> [SKIP][123] ([Intel XE#2486])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-5/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256:
    - shard-dg2-set2:     NOTRUN -> [FAIL][124] ([Intel XE#616]) +3 other tests fail
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-bmg:          NOTRUN -> [SKIP][125] ([Intel XE#2493])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_plane_multiple@tiling-yf.html
    - shard-lnl:          NOTRUN -> [SKIP][126] ([Intel XE#2493])
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-4/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-lnl:          NOTRUN -> [SKIP][127] ([Intel XE#3307])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-7/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][128] ([Intel XE#4212]) +1 other test dmesg-warn
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-6.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-c:
    - shard-lnl:          NOTRUN -> [SKIP][129] ([Intel XE#2763]) +23 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-3/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-c.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][130] ([Intel XE#2763] / [Intel XE#455]) +7 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-466/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-b:
    - shard-dg2-set2:     NOTRUN -> [SKIP][131] ([Intel XE#2763]) +11 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-466/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-b.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d:
    - shard-bmg:          NOTRUN -> [SKIP][132] ([Intel XE#2763]) +14 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d.html

  * igt@kms_pm_backlight@fade:
    - shard-bmg:          NOTRUN -> [SKIP][133] ([Intel XE#870]) +1 other test skip
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-5/igt@kms_pm_backlight@fade.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][134] ([Intel XE#870]) +1 other test skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_pm_backlight@fade.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-bmg:          NOTRUN -> [SKIP][135] ([Intel XE#2391])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_pm_dc@dc3co-vpb-simulation.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][136] ([Intel XE#1122]) +1 other test skip
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-434/igt@kms_pm_dc@dc3co-vpb-simulation.html
    - shard-lnl:          NOTRUN -> [SKIP][137] ([Intel XE#736])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-3/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-dg2-set2:     NOTRUN -> [SKIP][138] ([Intel XE#3309])
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-dg2-set2:     [PASS][139] -> [SKIP][140] ([Intel XE#836])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-466/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][141] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836]) +1 other test skip
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][142] ([Intel XE#1489]) +8 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html
    - shard-lnl:          NOTRUN -> [SKIP][143] ([Intel XE#2893]) +2 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-2/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          NOTRUN -> [SKIP][144] ([Intel XE#1489]) +8 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-7/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-bmg:          NOTRUN -> [SKIP][145] ([Intel XE#2387])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-7/igt@kms_psr2_su@page_flip-p010.html
    - shard-lnl:          NOTRUN -> [SKIP][146] ([Intel XE#1128])
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-3/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-psr-sprite-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][147] ([Intel XE#2850] / [Intel XE#929]) +18 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_psr@fbc-psr-sprite-render.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move:
    - shard-bmg:          NOTRUN -> [SKIP][148] ([Intel XE#2234] / [Intel XE#2850]) +15 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-7/igt@kms_psr@fbc-psr2-cursor-plane-move.html

  * igt@kms_psr@pr-no-drrs:
    - shard-lnl:          NOTRUN -> [SKIP][149] ([Intel XE#1406]) +6 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-8/igt@kms_psr@pr-no-drrs.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][150] ([Intel XE#3414]) +2 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-bmg:          NOTRUN -> [SKIP][151] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-7/igt@kms_rotation_crc@primary-rotation-90.html
    - shard-lnl:          NOTRUN -> [SKIP][152] ([Intel XE#3414] / [Intel XE#3904]) +2 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-8/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_scaling_modes@scaling-mode-none:
    - shard-bmg:          NOTRUN -> [SKIP][153] ([Intel XE#2413])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_scaling_modes@scaling-mode-none.html
    - shard-lnl:          NOTRUN -> [SKIP][154] ([Intel XE#2413] / [Intel XE#374])
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-5/igt@kms_scaling_modes@scaling-mode-none.html

  * igt@kms_scaling_modes@scaling-mode-none@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][155] ([Intel XE#374]) +2 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-5/igt@kms_scaling_modes@scaling-mode-none@pipe-a-edp-1.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-bmg:          [PASS][156] -> [SKIP][157] ([Intel XE#1435])
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-1/igt@kms_setmode@clone-exclusive-crtc.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_setmode@invalid-clone-exclusive-crtc:
    - shard-bmg:          NOTRUN -> [SKIP][158] ([Intel XE#1435])
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_setmode@invalid-clone-exclusive-crtc.html
    - shard-lnl:          NOTRUN -> [SKIP][159] ([Intel XE#1435]) +1 other test skip
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-5/igt@kms_setmode@invalid-clone-exclusive-crtc.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          NOTRUN -> [SKIP][160] ([Intel XE#2426])
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][161] ([Intel XE#362])
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_tiled_display@basic-test-pattern.html
    - shard-lnl:          NOTRUN -> [SKIP][162] ([Intel XE#362])
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-2/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-dg2-set2:     NOTRUN -> [SKIP][163] ([Intel XE#330])
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_tv_load_detect@load-detect.html
    - shard-lnl:          NOTRUN -> [SKIP][164] ([Intel XE#330])
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-5/igt@kms_tv_load_detect@load-detect.html
    - shard-bmg:          NOTRUN -> [SKIP][165] ([Intel XE#2450])
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [FAIL][166] ([Intel XE#899]) +3 other tests fail
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-6/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html

  * igt@xe_compute@ccs-mode-compute-kernel:
    - shard-lnl:          NOTRUN -> [SKIP][167] ([Intel XE#1447])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-3/igt@xe_compute@ccs-mode-compute-kernel.html

  * igt@xe_eudebug@basic-close:
    - shard-dg2-set2:     NOTRUN -> [SKIP][168] ([Intel XE#2905]) +11 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-463/igt@xe_eudebug@basic-close.html

  * igt@xe_eudebug@basic-vm-bind-discovery:
    - shard-bmg:          NOTRUN -> [SKIP][169] ([Intel XE#2905]) +12 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-7/igt@xe_eudebug@basic-vm-bind-discovery.html

  * igt@xe_eudebug@discovery-empty-clients:
    - shard-lnl:          NOTRUN -> [SKIP][170] ([Intel XE#2905]) +14 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-7/igt@xe_eudebug@discovery-empty-clients.html

  * igt@xe_eudebug@discovery-race-sigint:
    - shard-dg2-set2:     NOTRUN -> [SKIP][171] ([Intel XE#4259])
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-463/igt@xe_eudebug@discovery-race-sigint.html

  * igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-reopen:
    - shard-lnl:          NOTRUN -> [SKIP][172] ([Intel XE#688]) +5 other tests skip
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-7/igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-reopen.html

  * igt@xe_exec_basic@multigpu-once-null-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][173] ([Intel XE#2322]) +10 other tests skip
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@xe_exec_basic@multigpu-once-null-rebind.html

  * igt@xe_exec_basic@multigpu-once-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][174] ([Intel XE#1392]) +10 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-5/igt@xe_exec_basic@multigpu-once-userptr-invalidate.html

  * igt@xe_exec_fault_mode@many-execqueues-userptr-imm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][175] ([Intel XE#288]) +25 other tests skip
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-463/igt@xe_exec_fault_mode@many-execqueues-userptr-imm.html

  * igt@xe_exec_mix_modes@exec-simple-batch-store-lr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][176] ([Intel XE#2360]) +2 other tests skip
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@xe_exec_mix_modes@exec-simple-batch-store-lr.html

  * igt@xe_live_ktest@xe_migrate:
    - shard-lnl:          NOTRUN -> [SKIP][177] ([Intel XE#1192])
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-6/igt@xe_live_ktest@xe_migrate.html

  * igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit:
    - shard-dg2-set2:     NOTRUN -> [SKIP][178] ([Intel XE#2229])
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html

  * igt@xe_mmap@small-bar:
    - shard-lnl:          NOTRUN -> [SKIP][179] ([Intel XE#512])
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-2/igt@xe_mmap@small-bar.html

  * igt@xe_mmap@vram:
    - shard-lnl:          NOTRUN -> [SKIP][180] ([Intel XE#1416])
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-5/igt@xe_mmap@vram.html

  * igt@xe_module_load@force-load:
    - shard-bmg:          NOTRUN -> [SKIP][181] ([Intel XE#2457])
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@xe_module_load@force-load.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][182] ([Intel XE#378])
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-434/igt@xe_module_load@force-load.html
    - shard-lnl:          NOTRUN -> [SKIP][183] ([Intel XE#378])
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-3/igt@xe_module_load@force-load.html

  * igt@xe_oa@non-privileged-map-oa-buffer:
    - shard-dg2-set2:     NOTRUN -> [SKIP][184] ([Intel XE#2541] / [Intel XE#3573]) +6 other tests skip
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@xe_oa@non-privileged-map-oa-buffer.html

  * igt@xe_pat@display-vs-wb-transient:
    - shard-dg2-set2:     NOTRUN -> [SKIP][185] ([Intel XE#1337])
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@xe_pat@display-vs-wb-transient.html

  * igt@xe_pm@d3cold-mocs:
    - shard-bmg:          NOTRUN -> [SKIP][186] ([Intel XE#2284])
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@xe_pm@d3cold-mocs.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][187] ([Intel XE#2284])
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-434/igt@xe_pm@d3cold-mocs.html
    - shard-lnl:          NOTRUN -> [SKIP][188] ([Intel XE#2284])
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-4/igt@xe_pm@d3cold-mocs.html

  * igt@xe_pm@d3cold-multiple-execs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][189] ([Intel XE#2284] / [Intel XE#366])
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@xe_pm@d3cold-multiple-execs.html

  * igt@xe_pm@s3-basic:
    - shard-bmg:          [PASS][190] -> [DMESG-WARN][191] ([Intel XE#4172] / [Intel XE#569])
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-4/igt@xe_pm@s3-basic.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-5/igt@xe_pm@s3-basic.html
    - shard-dg2-set2:     [PASS][192] -> [DMESG-WARN][193] ([Intel XE#1033] / [Intel XE#569])
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-433/igt@xe_pm@s3-basic.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@xe_pm@s3-basic.html

  * igt@xe_pm@s3-multiple-execs:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][194] ([Intel XE#1033] / [Intel XE#569])
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@xe_pm@s3-multiple-execs.html

  * igt@xe_query@multigpu-query-invalid-extension:
    - shard-bmg:          NOTRUN -> [SKIP][195] ([Intel XE#944]) +1 other test skip
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-7/igt@xe_query@multigpu-query-invalid-extension.html

  * igt@xe_query@multigpu-query-topology:
    - shard-dg2-set2:     NOTRUN -> [SKIP][196] ([Intel XE#944]) +1 other test skip
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-434/igt@xe_query@multigpu-query-topology.html
    - shard-lnl:          NOTRUN -> [SKIP][197] ([Intel XE#944]) +1 other test skip
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-8/igt@xe_query@multigpu-query-topology.html

  * igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling:
    - shard-bmg:          NOTRUN -> [SKIP][198] ([Intel XE#4130]) +1 other test skip
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][199] ([Intel XE#4130])
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html
    - shard-lnl:          NOTRUN -> [SKIP][200] ([Intel XE#4130])
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-4/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html

  * igt@xe_sriov_flr@flr-vf1-clear:
    - shard-dg2-set2:     NOTRUN -> [SKIP][201] ([Intel XE#3342])
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-434/igt@xe_sriov_flr@flr-vf1-clear.html

  * igt@xe_wedged@wedged-mode-toggle:
    - shard-dg2-set2:     NOTRUN -> [ABORT][202] ([Intel XE#3075] / [Intel XE#3084])
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-434/igt@xe_wedged@wedged-mode-toggle.html

  
#### Possible fixes ####

  * igt@kms_async_flips@alternate-sync-async-flip-atomic:
    - shard-bmg:          [FAIL][203] ([Intel XE#3701] / [Intel XE#3718] / [Intel XE#827]) -> [PASS][204]
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-5/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_async_flips@alternate-sync-async-flip-atomic.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-d-dp-2:
    - shard-bmg:          [FAIL][205] ([Intel XE#3746] / [Intel XE#827]) -> [PASS][206]
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-5/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-d-dp-2.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-d-dp-2.html

  * igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
    - shard-bmg:          [SKIP][207] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][208]
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-7/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][209] ([Intel XE#1727] / [Intel XE#3124] / [Intel XE#4010]) -> [PASS][210]
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
    - shard-bmg:          [SKIP][211] ([Intel XE#2291]) -> [PASS][212]
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-4/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-7/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-dg2-set2:     [SKIP][213] ([Intel XE#309]) -> [PASS][214]
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-464/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
    - shard-dg2-set2:     [SKIP][215] ([Intel XE#310]) -> [PASS][216] +1 other test pass
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-464/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-466/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-bmg:          [SKIP][217] ([Intel XE#2316]) -> [PASS][218] +2 other tests pass
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-4/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-5/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@basic-flip-vs-dpms:
    - shard-dg2-set2:     [DMESG-WARN][219] ([Intel XE#2955]) -> [PASS][220] +1 other test pass
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-433/igt@kms_flip@basic-flip-vs-dpms.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@kms_flip@basic-flip-vs-dpms.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank:
    - shard-lnl:          [FAIL][221] ([Intel XE#886]) -> [PASS][222] +2 other tests pass
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-lnl-2/igt@kms_flip@flip-vs-absolute-wf_vblank.html
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-3/igt@kms_flip@flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a6:
    - shard-dg2-set2:     [FAIL][223] ([Intel XE#301]) -> [PASS][224] +4 other tests pass
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-464/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a6.html
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-434/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a6.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-dg2-set2:     [DMESG-WARN][225] ([Intel XE#1033] / [Intel XE#2955]) -> [PASS][226]
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-433/igt@kms_flip@flip-vs-suspend-interruptible.html
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-434/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-bmg:          [DMESG-WARN][227] -> [PASS][228]
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-5/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
    - shard-dg2-set2:     [DMESG-WARN][229] -> [PASS][230]
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-463/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-dg2-set2:     [SKIP][231] ([Intel XE#656]) -> [PASS][232] +4 other tests pass
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_pipe_crc_basic@disable-crc-after-crtc:
    - shard-bmg:          [DMESG-WARN][233] ([Intel XE#4172]) -> [PASS][234] +28 other tests pass
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-7/igt@kms_pipe_crc_basic@disable-crc-after-crtc.html
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-7/igt@kms_pipe_crc_basic@disable-crc-after-crtc.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
    - shard-bmg:          [INCOMPLETE][235] ([Intel XE#3663] / [Intel XE#4016]) -> [PASS][236]
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-4/igt@kms_pipe_crc_basic@suspend-read-crc.html
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_pipe_crc_basic@suspend-read-crc.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-2:
    - shard-bmg:          [INCOMPLETE][237] ([Intel XE#3663]) -> [PASS][238]
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-4/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-2.html
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-2.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-dg2-set2:     [SKIP][239] ([Intel XE#836]) -> [PASS][240]
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-464/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-463/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_psr@psr2-sprite-plane-onoff:
    - shard-lnl:          [FAIL][241] ([Intel XE#3924]) -> [PASS][242] +1 other test pass
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-lnl-6/igt@kms_psr@psr2-sprite-plane-onoff.html
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-4/igt@kms_psr@psr2-sprite-plane-onoff.html

  * igt@kms_vblank@query-busy-hang@pipe-d-dp-4:
    - shard-dg2-set2:     [DMESG-WARN][243] ([Intel XE#1033]) -> [PASS][244] +37 other tests pass
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-466/igt@kms_vblank@query-busy-hang@pipe-d-dp-4.html
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-463/igt@kms_vblank@query-busy-hang@pipe-d-dp-4.html

  * igt@xe_evict@evict-large-multi-vm:
    - shard-dg2-set2:     [DMESG-WARN][245] ([Intel XE#1033] / [Intel XE#1473]) -> [PASS][246] +2 other tests pass
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-463/igt@xe_evict@evict-large-multi-vm.html
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@xe_evict@evict-large-multi-vm.html

  * igt@xe_exec_basic@multigpu-no-exec-null-defer-bind:
    - shard-dg2-set2:     [SKIP][247] ([Intel XE#1392]) -> [PASS][248] +4 other tests pass
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-null-defer-bind.html
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-463/igt@xe_exec_basic@multigpu-no-exec-null-defer-bind.html

  * igt@xe_exec_fault_mode@once-userptr-invalidate-race-prefetch:
    - shard-lnl:          [FAIL][249] -> [PASS][250]
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-lnl-4/igt@xe_exec_fault_mode@once-userptr-invalidate-race-prefetch.html
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-8/igt@xe_exec_fault_mode@once-userptr-invalidate-race-prefetch.html

  * igt@xe_module_load@many-reload:
    - shard-dg2-set2:     [INCOMPLETE][251] -> [PASS][252]
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-432/igt@xe_module_load@many-reload.html
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-463/igt@xe_module_load@many-reload.html

  * igt@xe_oa@unprivileged-single-ctx-counters:
    - shard-bmg:          [SKIP][253] ([Intel XE#2248]) -> [PASS][254]
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-1/igt@xe_oa@unprivileged-single-ctx-counters.html
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@xe_oa@unprivileged-single-ctx-counters.html
    - shard-lnl:          [SKIP][255] ([Intel XE#2248]) -> [PASS][256]
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-lnl-6/igt@xe_oa@unprivileged-single-ctx-counters.html
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-lnl-4/igt@xe_oa@unprivileged-single-ctx-counters.html

  * igt@xe_pm@s3-d3hot-basic-exec:
    - shard-bmg:          [DMESG-WARN][257] ([Intel XE#4172] / [Intel XE#569]) -> [PASS][258]
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-7/igt@xe_pm@s3-d3hot-basic-exec.html
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-5/igt@xe_pm@s3-d3hot-basic-exec.html
    - shard-dg2-set2:     [DMESG-WARN][259] ([Intel XE#1033] / [Intel XE#569]) -> [PASS][260]
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-434/igt@xe_pm@s3-d3hot-basic-exec.html
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@xe_pm@s3-d3hot-basic-exec.html

  
#### Warnings ####

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][261] ([Intel XE#787]) -> [SKIP][262] ([Intel XE#455] / [Intel XE#787]) +5 other tests skip
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-463/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-6.html
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][263] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][264] ([Intel XE#787]) +2 other tests skip
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-6.html
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-6.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2-set2:     [FAIL][265] ([Intel XE#1178]) -> [SKIP][266] ([Intel XE#455])
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-432/igt@kms_content_protection@atomic-dpms.html
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@srm:
    - shard-bmg:          [FAIL][267] ([Intel XE#1178]) -> [DMESG-FAIL][268] ([Intel XE#4172]) +1 other test dmesg-fail
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-5/igt@kms_content_protection@srm.html
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_content_protection@srm.html

  * igt@kms_content_protection@srm@pipe-a-dp-4:
    - shard-dg2-set2:     [FAIL][269] ([Intel XE#1178]) -> [DMESG-FAIL][270] ([Intel XE#1033]) +1 other test dmesg-fail
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-463/igt@kms_content_protection@srm@pipe-a-dp-4.html
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-463/igt@kms_content_protection@srm@pipe-a-dp-4.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
    - shard-dg2-set2:     [DMESG-WARN][271] ([Intel XE#1033]) -> [SKIP][272] ([Intel XE#309])
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-432/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
    - shard-bmg:          [DMESG-WARN][273] ([Intel XE#4172]) -> [SKIP][274] ([Intel XE#2291])
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
    - shard-dg2-set2:     [DMESG-WARN][275] ([Intel XE#1033]) -> [SKIP][276] ([Intel XE#310])
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-432/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-dg2-set2:     [FAIL][277] ([Intel XE#301]) -> [SKIP][278] ([Intel XE#310])
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-466/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
    - shard-dg2-set2:     [SKIP][279] ([Intel XE#310]) -> [DMESG-WARN][280] ([Intel XE#1033])
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-464/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][281] ([Intel XE#2312]) -> [SKIP][282] ([Intel XE#2311]) +10 other tests skip
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render:
    - shard-dg2-set2:     [SKIP][283] ([Intel XE#651]) -> [SKIP][284] ([Intel XE#656]) +14 other tests skip
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render.html
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][285] ([Intel XE#2312]) -> [SKIP][286] ([Intel XE#4141]) +5 other tests skip
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][287] ([Intel XE#4141]) -> [SKIP][288] ([Intel XE#2312]) +2 other tests skip
   [287]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
   [288]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-blt:
    - shard-bmg:          [SKIP][289] ([Intel XE#2311]) -> [SKIP][290] ([Intel XE#2312]) +14 other tests skip
   [289]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-blt.html
   [290]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt:
    - shard-dg2-set2:     [SKIP][291] ([Intel XE#656]) -> [SKIP][292] ([Intel XE#651]) +5 other tests skip
   [291]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt.html
   [292]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw:
    - shard-bmg:          [SKIP][293] ([Intel XE#2312]) -> [SKIP][294] ([Intel XE#2313]) +6 other tests skip
   [293]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html
   [294]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][295] ([Intel XE#2313]) -> [SKIP][296] ([Intel XE#2312]) +8 other tests skip
   [295]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
   [296]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
    - shard-dg2-set2:     [SKIP][297] ([Intel XE#656]) -> [SKIP][298] ([Intel XE#653]) +6 other tests skip
   [297]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html
   [298]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render:
    - shard-dg2-set2:     [SKIP][299] ([Intel XE#653]) -> [SKIP][300] ([Intel XE#656]) +9 other tests skip
   [299]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-466/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render.html
   [300]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][301] ([Intel XE#2426]) -> [SKIP][302] ([Intel XE#2509])
   [301]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [302]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
    - shard-dg2-set2:     [SKIP][303] ([Intel XE#1500]) -> [SKIP][304] ([Intel XE#362])
   [303]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-433/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [304]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_pm@s4-mocs:
    - shard-dg2-set2:     [ABORT][305] ([Intel XE#1033] / [Intel XE#4268]) -> [ABORT][306] ([Intel XE#4268])
   [305]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8230/shard-dg2-433/igt@xe_pm@s4-mocs.html
   [306]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/shard-dg2-464/igt@xe_pm@s4-mocs.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1033]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1033
  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192
  [Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1416
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1447
  [Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470
  [Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473
  [Intel XE#1477]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1477
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
  [Intel XE#1512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1512
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2248]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2248
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
  [Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2391
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2450]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2450
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2486
  [Intel XE#2493]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2493
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2853]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2853
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
  [Intel XE#2934]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2934
  [Intel XE#2955]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2955
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#3075]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3075
  [Intel XE#3084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3084
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3157]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3157
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3278]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3278
  [Intel XE#3279]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3279
  [Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3307
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3433]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3433
  [Intel XE#3442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3442
  [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
  [Intel XE#352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/352
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#3663]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3663
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3701
  [Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
  [Intel XE#3719]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3719
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/374
  [Intel XE#3746]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3746
  [Intel XE#3767]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3767
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#3914]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3914
  [Intel XE#3924]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3924
  [Intel XE#4010]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4010
  [Intel XE#4016]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4016
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4172]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4172
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4259]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4259
  [Intel XE#4268]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4268
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/512
  [Intel XE#569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/569
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#736]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/736
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#827]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/827
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#873]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/873
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
  [Intel XE#911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/911
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * IGT: IGT_8230 -> IGTPW_12607
  * Linux: xe-2665-57457d93f156d8b4bdff8d138127d81b8f97d8c9 -> xe-2669-cbd747025a1ef985e1ebfa040aa0da4a5d77aacd

  IGTPW_12607: 12607
  IGT_8230: 8230
  xe-2665-57457d93f156d8b4bdff8d138127d81b8f97d8c9: 57457d93f156d8b4bdff8d138127d81b8f97d8c9
  xe-2669-cbd747025a1ef985e1ebfa040aa0da4a5d77aacd: cbd747025a1ef985e1ebfa040aa0da4a5d77aacd

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/index.html

[-- Attachment #2: Type: text/html, Size: 97281 bytes --]

Re: ✗ Xe.CI.Full: failure for Some refactor, rewrite and fixes for OA tests

[Umesh Nerlige Ramappa]

Hi Ashutosh,

On Sun, Feb 16, 2025 at 08:05:52AM +0000, Patchwork wrote:
>   Patch Details
>
>   Series:  Some refactor, rewrite and fixes for OA tests
>   URL:     [1]https://patchwork.freedesktop.org/series/144916/
>   State:   failure
>   Details: [2]https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_12607/index.html
>
>        CI Bug Log - changes from XEIGT_8230_full -> XEIGTPW_12607_full
>
>Summary
>
>   FAILURE
>
>   Serious unknown changes coming with XEIGTPW_12607_full absolutely need to
>   be
>   verified manually.
>
>   If you think the reported changes have nothing to do with the changes
>   introduced in XEIGTPW_12607_full, please notify your bug team
>   (I915-ci-infra@lists.freedesktop.org) to allow them
>   to document this new failure mode, which will reduce false positives in
>   CI.
>
>Participating hosts (4 -> 4)
>
>   No changes in participating hosts
>
>Possible new issues
>
>   Here are the unknown changes that may have been introduced in
>   XEIGTPW_12607_full:
>
>  IGT changes
>
>    Possible regressions
>
>     * igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset:
>
>          * shard-bmg: NOTRUN -> [3]DMESG-WARN
>
>     * {igt@xe_oa@buffer-size} (NEW):
>
>          * shard-dg2-set2: NOTRUN -> [4]SKIP

Should we enable OA tests for dg2 as well? Your call. If not, then this 
is just an expected skip.

Thanks,
Umesh
>
>    Warnings
>
>     * igt@xe_pm@s4-vm-bind-prefetch:
>
>          * shard-lnl: [5]ABORT ([6]Intel XE#4268) -> [7]ABORT
>
>    Suppressed
>
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
>
>     * {igt@kms_pipe_stress@stress-xrgb8888-ytiled}:
>
>          * shard-bmg: NOTRUN -> [8]SKIP
>          * shard-dg2-set2: NOTRUN -> [9]SKIP
>          * shard-lnl: NOTRUN -> [10]SKIP
>
>New tests
>
>   New tests have been introduced between XEIGT_8230_full and
>   XEIGTPW_12607_full:
>
>  New IGT tests (4)
>
>     * igt@xe_oa@buffer-size:
>
>          * Statuses : 2 pass(s) 1 skip(s)
>          * Exec time: [0.0, 2.86] s
>
>     * igt@xe_oa@buffer-size@ccs-0-16m:
>
>          * Statuses : 1 pass(s)
>          * Exec time: [2.80] s
>
>     * igt@xe_oa@buffer-size@rcs-0-2m:
>
>          * Statuses : 1 pass(s)
>          * Exec time: [2.86] s
>
>     * igt@xe_oa@unprivileged-single-ctx-counters@rcs-0:
>
>          * Statuses : 2 pass(s)
>          * Exec time: [0.07, 0.08] s
>
>Known issues

Re: ✗ Xe.CI.Full: failure for Some refactor, rewrite and fixes for OA tests

[Dixit, Ashutosh]

On Tue, 18 Feb 2025 10:38:11 -0800, Umesh Nerlige Ramappa wrote:
>
> Hi Ashutosh,
> >  IGT changes
> >
> >    Possible regressions
> >
> >     * igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset:
> >
> >          * shard-bmg: NOTRUN -> [3]DMESG-WARN
> >
> >     * {igt@xe_oa@buffer-size} (NEW):
> >
> >          * shard-dg2-set2: NOTRUN -> [4]SKIP
>
> Should we enable OA tests for dg2 as well? Your call. If not, then this is
> just an expected skip.

Not till all tests are fixed and timing heuristics are gone. Don't want to
deal with a bunch of Xe1 failures.