[PATCH 1/4] drm/i915: read current freq from Punit on VLV

[PATCH 1/4] drm/i915: read current freq from Punit on VLV

[Jesse Barnes]

Instead of returning the cached value, which is just what the kernel
requested.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_sysfs.c |    9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index ca00df2..c0d7875 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -212,10 +212,13 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
 	int ret;
 
 	mutex_lock(&dev_priv->rps.hw_lock);
-	if (IS_VALLEYVIEW(dev_priv->dev))
-		ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay);
-	else
+	if (IS_VALLEYVIEW(dev_priv->dev)) {
+		u32 freq;
+		valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &freq);
+		ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff);
+	} else {
 		ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
+	}
 	mutex_unlock(&dev_priv->rps.hw_lock);
 
 	return snprintf(buf, PAGE_SIZE, "%d\n", ret);
-- 
1.7.10.4

[PATCH 2/4] drm/i915: go back to switch for VLV mem freq detection v2

[Jesse Barnes]

Both the docs and the existing code were wrong.  So fix both and use a
switch statement like we do elsewhere to make things simple & clear.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_pm.c |   13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0f4b46e..556b989 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2902,7 +2902,18 @@ static void valleyview_enable_rps(struct drm_device *dev)
 		   GEN7_RC_CTL_TO_MODE);
 
 	valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
-	dev_priv->mem_freq = 800 + (266 * (val >> 6) & 3);
+	switch ((val >> 6) & 3) {
+	case 0:
+	case 1:
+		dev_priv->mem_freq = 800;
+		break;
+	case 2:
+		dev_priv->mem_freq = 1066;
+		break;
+	case 3:
+		dev_priv->mem_freq = 1333;
+		break;
+	}
 	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
 
 	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
-- 
1.7.10.4

[PATCH 3/4] drm/i915: set proper DPIO post divider for VGA on VLV v4

[Jesse Barnes]

Supposedly we should use the DAC divider for <300MHz pixel clocks, but as
that doesn't actually work as well as the high freq divider here in
practice, just use the high freq divider all the time.

v2: remove unconditional write (Jesse)
    check for pixel rate properly (Jesse)
v3: give up, the DAC divider apparently doesn't work, and low res modes
    work ok (Jesse)
    remove debug msg (Jesse)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |   11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6504337..59c2114 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4425,10 +4425,13 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
 	mdiv |= ((bestn << DPIO_N_SHIFT));
 	mdiv |= (1 << DPIO_K_SHIFT);
-	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
-	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
-	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
-		mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
+
+	/*
+	 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
+	 * but we don't support that).
+	 * Note: don't use the DAC post divider as it seems unstable.
+	 */
+	mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
 	intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
 
 	mdiv |= DPIO_ENABLE_CALIBRATION;
-- 
1.7.10.4

[PATCH 4/4] drm/i915: BIOS and power context stolen mem handling for VLV

[Jesse Barnes]

But we need to get the right stolen base and make pre-allocated objects
for BIOS stuff so we don't clobber it.  If the BIOS hasn't allocated a
power context, we allocate one here too, from stolen space as required
by the docs.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.h        |    2 +
 drivers/gpu/drm/i915/i915_gem_stolen.c |   78 +++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h        |    1 +
 3 files changed, 80 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3ac71db..5e9ea36 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1055,6 +1055,8 @@ typedef struct drm_i915_private {
 
 	struct i915_gpu_error gpu_error;
 
+	struct drm_i915_gem_object *vlv_pctx;
+
 	/* list of fbdev register on this device */
 	struct intel_fbdev *fbdev;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 67d3510..c06056a 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -62,7 +62,10 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
 	 * its value of TOLUD.
 	 */
 	base = 0;
-	if (INTEL_INFO(dev)->gen >= 6) {
+	if (IS_VALLEYVIEW(dev)) {
+		pci_read_config_dword(pdev, 0x5c, &base);
+		base &= ((1<<19) - 1);
+	} if (INTEL_INFO(dev)->gen >= 6) {
 		/* Read Base Data of Stolen Memory Register (BDSM) directly.
 		 * Note that there is also a MCHBAR miror at 0x1080c0 or
 		 * we could use device 2:0x5c instead.
@@ -172,14 +175,82 @@ void i915_gem_stolen_cleanup_compression(struct drm_device *dev)
 	dev_priv->cfb_size = 0;
 }
 
+static void valleyview_setup_pctx(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *pctx;
+	unsigned long pctx_paddr;
+	u32 pcbr;
+	int pctx_size = 24*1024;
+
+	pcbr = I915_READ(VLV_PCBR);
+	if (pcbr) {
+		/* BIOS set it up already, grab the pre-alloc'd space */
+		int pcbr_offset;
+
+		pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
+		pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
+								      pcbr_offset,
+								      pcbr_offset,
+								      pctx_size);
+		/* We don't need to track it since we don't own it */
+		return;
+	}
+
+	/*
+	 * From the Gunit register HAS:
+	 * The Gfx driver is expected to program this register and ensure
+	 * proper allocation within Gfx stolen memory.  For example, this
+	 * register should be programmed such than the PCBR range does not
+	 * overlap with other ranges, such as the frame buffer, protected
+	 * memory, or any other relevant ranges.
+	 */
+	pctx = i915_gem_object_create_stolen(dev, pctx_size);
+	if (!pctx) {
+		DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
+		return;
+	}
+
+	dev_priv->vlv_pctx = pctx;
+	pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
+	I915_WRITE(VLV_PCBR, pctx_paddr);
+}
+
+static void valleyview_cleanup_pctx(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	if (!dev_priv->vlv_pctx)
+		return;
+
+	i915_gem_object_release_stolen(dev_priv->vlv_pctx);
+	I915_WRITE(VLV_PCBR, 0);
+}
+
 void i915_gem_cleanup_stolen(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	i915_gem_stolen_cleanup_compression(dev);
+	if (IS_VALLEYVIEW(dev))
+		valleyview_cleanup_pctx(dev);
 	drm_mm_takedown(&dev_priv->mm.stolen);
 }
 
+/* On VLV make sure we create pre-alloc'd objects for BIOS bits */
+static void valleyview_init_bios_stolen(struct drm_i915_private *dev_priv)
+{
+	struct drm_i915_gem_object *bios_stolen;
+	int bios_offset;
+
+	/* Top 1M of stolen space is used by firmware */
+	bios_offset = dev_priv->gtt.stolen_size - 1024*1024;
+	bios_stolen = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
+								     bios_offset,
+								     bios_offset,
+								     1024*1024);
+}
+
 int i915_gem_init_stolen(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -194,6 +265,11 @@ int i915_gem_init_stolen(struct drm_device *dev)
 	/* Basic memrange allocator for stolen space */
 	drm_mm_init(&dev_priv->mm.stolen, 0, dev_priv->gtt.stolen_size);
 
+	if (IS_VALLEYVIEW(dev)) {
+		valleyview_init_bios_stolen(dev_priv);
+		valleyview_setup_pctx(dev);
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b5d87bd..1cc43ce 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -700,6 +700,7 @@
 #define VLV_IIR		(VLV_DISPLAY_BASE + 0x20a4)
 #define VLV_IMR		(VLV_DISPLAY_BASE + 0x20a8)
 #define VLV_ISR		(VLV_DISPLAY_BASE + 0x20ac)
+#define VLV_PCBR	(VLV_DISPLAY_BASE + 0x2120)
 #define   I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)
 #define   I915_DISPLAY_PORT_INTERRUPT			(1<<17)
 #define   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT	(1<<15)
-- 
1.7.10.4

Re: [PATCH 2/4] drm/i915: go back to switch for VLV mem freq detection v2

[Ben Widawsky]

On Thu, May 02, 2013 at 10:48:08AM -0700, Jesse Barnes wrote:
> Both the docs and the existing code were wrong.  So fix both and use a
> switch statement like we do elsewhere to make things simple & clear.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_pm.c |   13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0f4b46e..556b989 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2902,7 +2902,18 @@ static void valleyview_enable_rps(struct drm_device *dev)
>  		   GEN7_RC_CTL_TO_MODE);
>  
>  	valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
> -	dev_priv->mem_freq = 800 + (266 * (val >> 6) & 3);
> +	switch ((val >> 6) & 3) {
> +	case 0:
> +	case 1:
> +		dev_priv->mem_freq = 800;
> +		break;
> +	case 2:
> +		dev_priv->mem_freq = 1066;
> +		break;
> +	case 3:
> +		dev_priv->mem_freq = 1333;
> +		break;
> +	}
>  	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
>  
>  	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");

The code does what the author wants it to, but I don't have the doc that
says this:
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

Since I've set up a precedent of providing what I think are better
options:
freq_lut[] = {800, 800, 1066, 1333};
freq_lut[(val >> 6) & 3];

[really ugly one-liner redacted]

-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 4/4] drm/i915: BIOS and power context stolen mem handling for VLV

[Ben Widawsky]

On Thu, May 02, 2013 at 10:48:10AM -0700, Jesse Barnes wrote:
> But we need to get the right stolen base and make pre-allocated objects
> for BIOS stuff so we don't clobber it.  If the BIOS hasn't allocated a
> power context, we allocate one here too, from stolen space as required
> by the docs.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.h        |    2 +
>  drivers/gpu/drm/i915/i915_gem_stolen.c |   78 +++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/i915_reg.h        |    1 +
>  3 files changed, 80 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3ac71db..5e9ea36 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1055,6 +1055,8 @@ typedef struct drm_i915_private {
>  
>  	struct i915_gpu_error gpu_error;
>  
> +	struct drm_i915_gem_object *vlv_pctx;
> +
>  	/* list of fbdev register on this device */
>  	struct intel_fbdev *fbdev;
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index 67d3510..c06056a 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -62,7 +62,10 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
>  	 * its value of TOLUD.
>  	 */
>  	base = 0;
> -	if (INTEL_INFO(dev)->gen >= 6) {
> +	if (IS_VALLEYVIEW(dev)) {
> +		pci_read_config_dword(pdev, 0x5c, &base);
> +		base &= ((1<<19) - 1);
> +	} if (INTEL_INFO(dev)->gen >= 6) {

else if

>  		/* Read Base Data of Stolen Memory Register (BDSM) directly.
>  		 * Note that there is also a MCHBAR miror at 0x1080c0 or
>  		 * we could use device 2:0x5c instead.
> @@ -172,14 +175,82 @@ void i915_gem_stolen_cleanup_compression(struct drm_device *dev)
>  	dev_priv->cfb_size = 0;
>  }
>  
> +static void valleyview_setup_pctx(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_i915_gem_object *pctx;
> +	unsigned long pctx_paddr;
> +	u32 pcbr;
> +	int pctx_size = 24*1024;
> +
> +	pcbr = I915_READ(VLV_PCBR);
> +	if (pcbr) {
> +		/* BIOS set it up already, grab the pre-alloc'd space */
> +		int pcbr_offset;
> +
> +		pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
s/4095/PAGE_MASK?
> +		pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
> +								      pcbr_offset,
> +								      pcbr_offset,
> +								      pctx_size);

Can you remind me how we can get away with the assumption that gtt
offset has a 1:1 mapping with the stolen offset?

> +		/* We don't need to track it since we don't own it */
> +		return;
> +	}
> +
> +	/*
> +	 * From the Gunit register HAS:
> +	 * The Gfx driver is expected to program this register and ensure
> +	 * proper allocation within Gfx stolen memory.  For example, this
> +	 * register should be programmed such than the PCBR range does not
> +	 * overlap with other ranges, such as the frame buffer, protected
> +	 * memory, or any other relevant ranges.
> +	 */
> +	pctx = i915_gem_object_create_stolen(dev, pctx_size);
> +	if (!pctx) {
> +		DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
> +		return;
> +	}
> +
> +	dev_priv->vlv_pctx = pctx;
> +	pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
> +	I915_WRITE(VLV_PCBR, pctx_paddr);

Does the powerctx need to be reinitialized after GPU reset?

> +}

> +
> +static void valleyview_cleanup_pctx(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	if (!dev_priv->vlv_pctx)
> +		return;
> +
> +	i915_gem_object_release_stolen(dev_priv->vlv_pctx);
> +	I915_WRITE(VLV_PCBR, 0);
> +}
> +
>  void i915_gem_cleanup_stolen(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	i915_gem_stolen_cleanup_compression(dev);
> +	if (IS_VALLEYVIEW(dev))
> +		valleyview_cleanup_pctx(dev);
>  	drm_mm_takedown(&dev_priv->mm.stolen);
>  }
>  
> +/* On VLV make sure we create pre-alloc'd objects for BIOS bits */
> +static void valleyview_init_bios_stolen(struct drm_i915_private *dev_priv)
> +{
> +	struct drm_i915_gem_object *bios_stolen;
> +	int bios_offset;
> +
> +	/* Top 1M of stolen space is used by firmware */
> +	bios_offset = dev_priv->gtt.stolen_size - 1024*1024;
> +	bios_stolen = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
> +								     bios_offset,
> +								     bios_offset,
> +								     1024*1024);
> +}
> +
>  int i915_gem_init_stolen(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -194,6 +265,11 @@ int i915_gem_init_stolen(struct drm_device *dev)
>  	/* Basic memrange allocator for stolen space */
>  	drm_mm_init(&dev_priv->mm.stolen, 0, dev_priv->gtt.stolen_size);

I think you should chop off the 1MB here instead of making a stolen
object which we don't want to use or touch
>  
> +	if (IS_VALLEYVIEW(dev)) {
> +		valleyview_init_bios_stolen(dev_priv);
> +		valleyview_setup_pctx(dev);
       drm_mm_init(&dev_priv->mm.stolen, 0, dev_priv->gtt.stolen_size - 1K); 
} else {
        drm_mm_init(&dev_priv->mm.stolen, 0, dev_priv->gtt.stolen_size);
}
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b5d87bd..1cc43ce 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -700,6 +700,7 @@
>  #define VLV_IIR		(VLV_DISPLAY_BASE + 0x20a4)
>  #define VLV_IMR		(VLV_DISPLAY_BASE + 0x20a8)
>  #define VLV_ISR		(VLV_DISPLAY_BASE + 0x20ac)
> +#define VLV_PCBR	(VLV_DISPLAY_BASE + 0x2120)
>  #define   I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)
>  #define   I915_DISPLAY_PORT_INTERRUPT			(1<<17)
>  #define   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT	(1<<15)
> -- 
> 1.7.10.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 2/4] drm/i915: go back to switch for VLV mem freq detection v2

[Daniel Vetter]

On Fri, May 03, 2013 at 10:52:11AM -0700, Ben Widawsky wrote:
> On Thu, May 02, 2013 at 10:48:08AM -0700, Jesse Barnes wrote:
> > Both the docs and the existing code were wrong.  So fix both and use a
> > switch statement like we do elsewhere to make things simple & clear.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c |   13 ++++++++++++-
> >  1 file changed, 12 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 0f4b46e..556b989 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -2902,7 +2902,18 @@ static void valleyview_enable_rps(struct drm_device *dev)
> >  		   GEN7_RC_CTL_TO_MODE);
> >  
> >  	valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
> > -	dev_priv->mem_freq = 800 + (266 * (val >> 6) & 3);
> > +	switch ((val >> 6) & 3) {
> > +	case 0:
> > +	case 1:
> > +		dev_priv->mem_freq = 800;
> > +		break;
> > +	case 2:
> > +		dev_priv->mem_freq = 1066;
> > +		break;
> > +	case 3:
> > +		dev_priv->mem_freq = 1333;
> > +		break;
> > +	}
> >  	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
> >  
> >  	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
> 
> The code does what the author wants it to, but I don't have the doc that
> says this:
> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

First two patches of this series are merged to dinq, thanks.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 3/4] drm/i915: set proper DPIO post divider for VGA on VLV v4

[Kenneth Graunke]

On 05/02/2013 10:48 AM, Jesse Barnes wrote:
> Supposedly we should use the DAC divider for <300MHz pixel clocks, but as
> that doesn't actually work as well as the high freq divider here in
> practice, just use the high freq divider all the time.
>
> v2: remove unconditional write (Jesse)
>      check for pixel rate properly (Jesse)
> v3: give up, the DAC divider apparently doesn't work, and low res modes
>      work ok (Jesse)
>      remove debug msg (Jesse)
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

VGA is broken with today's drm-intel-next-queued (3a2128bcac1ae). 
Applying this patch fixes it.  Thanks!

Tested-by: Kenneth Graunke <kenneth@whitecape.org>

> ---
>   drivers/gpu/drm/i915/intel_display.c |   11 +++++++----
>   1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6504337..59c2114 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4425,10 +4425,13 @@ static void vlv_update_pll(struct intel_crtc *crtc)
>   	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
>   	mdiv |= ((bestn << DPIO_N_SHIFT));
>   	mdiv |= (1 << DPIO_K_SHIFT);
> -	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
> -	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
> -	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
> -		mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
> +
> +	/*
> +	 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
> +	 * but we don't support that).
> +	 * Note: don't use the DAC post divider as it seems unstable.
> +	 */
> +	mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
>   	intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
>
>   	mdiv |= DPIO_ENABLE_CALIBRATION;
>

Re: [PATCH 3/4] drm/i915: set proper DPIO post divider for VGA on VLV v4

[Daniel Vetter]

On Mon, May 06, 2013 at 10:52:36AM -0700, Kenneth Graunke wrote:
> On 05/02/2013 10:48 AM, Jesse Barnes wrote:
> >Supposedly we should use the DAC divider for <300MHz pixel clocks, but as
> >that doesn't actually work as well as the high freq divider here in
> >practice, just use the high freq divider all the time.
> >
> >v2: remove unconditional write (Jesse)
> >     check for pixel rate properly (Jesse)
> >v3: give up, the DAC divider apparently doesn't work, and low res modes
> >     work ok (Jesse)
> >     remove debug msg (Jesse)
> >
> >Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> VGA is broken with today's drm-intel-next-queued (3a2128bcac1ae).
> Applying this patch fixes it.  Thanks!
> 
> Tested-by: Kenneth Graunke <kenneth@whitecape.org>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch