From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [CI v13 15/17] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
Date: Wed, 28 Nov 2018 12:26:26 -0800 [thread overview]
Message-ID: <20181128202628.20238-15-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20181128202628.20238-1-manasi.d.navare@intel.com>
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased. (r-b Manasi)
v4: Use fec crtc state, before setting FEC_READY
bit. (Anusha)
v5: Move to intel_ddi.c
- Make the function static (Anusha)
v6: Dont pass state as a separate argument (Ville)
v7: (From Manasi)
* Correct the debug print (Ville)
Cc: dri-devel@lists.freedesktop.org
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6533624226a7..4c74bbe1cf73 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3102,6 +3102,16 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
I915_WRITE(MG_DP_MODE(port, 1), ln1);
}
+static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ if (!crtc_state->fec_enable)
+ return;
+
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
+ DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
+}
+
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
@@ -3142,6 +3152,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
true);
+ intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
--
2.19.1
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next prev parent reply other threads:[~2018-11-28 20:23 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-28 20:26 [CI v13 01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-28 20:26 ` [CI v13 02/17] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-11-28 21:36 ` [PATCH v14 " Manasi Navare
2018-11-28 20:26 ` [CI v13 03/17] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-11-28 20:26 ` [CI v13 04/17] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-11-29 19:38 ` [CI v15 " Manasi Navare
2018-11-28 20:26 ` [CI v13 05/17] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-11-28 20:26 ` [CI v13 06/17] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-11-28 20:26 ` [CI v13 07/17] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-11-28 20:26 ` [CI v13 08/17] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-11-28 20:26 ` [CI v13 09/17] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-11-28 20:26 ` [CI v13 10/17] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-11-28 20:26 ` [CI v13 11/17] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-11-28 20:26 ` [CI v13 12/17] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-11-28 20:26 ` [CI v13 13/17] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-11-28 20:26 ` [CI v13 14/17] i915/dp/fec: Add fec_enable to the crtc state Manasi Navare
2018-11-28 20:26 ` Manasi Navare [this message]
2018-11-28 20:26 ` [CI v13 16/17] i915/dp/fec: Configure the Forward Error Correction bits Manasi Navare
2018-11-28 20:26 ` [CI v13 17/17] drm/i915/fec: Disable FEC state Manasi Navare
2018-11-28 21:01 ` ✗ Fi.CI.BAT: failure for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Patchwork
2018-11-28 22:59 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev2) Patchwork
2018-11-28 23:06 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-28 23:15 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-29 10:29 ` ✓ Fi.CI.IGT: " Patchwork
2018-11-29 19:50 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev3) Patchwork
2018-11-29 19:56 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-29 20:08 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-29 20:52 ` [CI v13 01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-30 12:52 ` ✗ Fi.CI.IGT: failure for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev3) Patchwork
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